1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /* FW writes status value to the OUT buffer at offset 00H */ 17 #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status) 18 /* FW writes syndrome value to the OUT buffer at offset 04H */ 19 #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome) 20 21 #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1)) 22 23 #define DEVX_DRV_LOG(level, out, reason, param, value) \ 24 do { \ 25 /* \ 26 * Some (old) GCC compilers like 7.5.0 and aarch64 GCC 7.1-2017.08 \ 27 * do not expand correctly when the macro invoked when the `param` \ 28 * is `NULL`. \ 29 * Use `local_param` to avoid direct `NULL` expansion. \ 30 */ \ 31 const char *local_param = (const char *)param; \ 32 \ 33 rte_errno = errno; \ 34 if (!local_param) { \ 35 DRV_LOG(level, \ 36 "DevX %s failed errno=%d status=%#x syndrome=%#x", \ 37 (reason), errno, MLX5_FW_STATUS((out)), \ 38 MLX5_FW_SYNDROME((out))); \ 39 } else { \ 40 DRV_LOG(level, \ 41 "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x",\ 42 (reason), local_param, (value), errno, \ 43 MLX5_FW_STATUS((out)), MLX5_FW_SYNDROME((out))); \ 44 } \ 45 } while (0) 46 47 static void * 48 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, 49 int *err, uint32_t flags) 50 { 51 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); 52 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); 53 int rc; 54 55 memset(in, 0, size_in); 56 memset(out, 0, size_out); 57 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 58 MLX5_SET(query_hca_cap_in, in, op_mod, flags); 59 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); 60 if (rc || MLX5_FW_STATUS(out)) { 61 DEVX_DRV_LOG(ERR, out, "HCA capabilities", "func", flags >> 1); 62 if (err) 63 *err = MLX5_DEVX_ERR_RC(rc); 64 return NULL; 65 } 66 if (err) 67 *err = 0; 68 return MLX5_ADDR_OF(query_hca_cap_out, out, capability); 69 } 70 71 /** 72 * Perform read access to the registers. Reads data from register 73 * and writes ones to the specified buffer. 74 * 75 * @param[in] ctx 76 * Context returned from mlx5 open_device() glue function. 77 * @param[in] reg_id 78 * Register identifier according to the PRM. 79 * @param[in] arg 80 * Register access auxiliary parameter according to the PRM. 81 * @param[out] data 82 * Pointer to the buffer to store read data. 83 * @param[in] dw_cnt 84 * Buffer size in double words. 85 * 86 * @return 87 * 0 on success, a negative value otherwise. 88 */ 89 int 90 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 91 uint32_t *data, uint32_t dw_cnt) 92 { 93 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 94 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 95 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 96 int rc; 97 98 MLX5_ASSERT(data && dw_cnt); 99 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 100 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 101 DRV_LOG(ERR, "Not enough buffer for register read data"); 102 return -1; 103 } 104 MLX5_SET(access_register_in, in, opcode, 105 MLX5_CMD_OP_ACCESS_REGISTER_USER); 106 MLX5_SET(access_register_in, in, op_mod, 107 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 108 MLX5_SET(access_register_in, in, register_id, reg_id); 109 MLX5_SET(access_register_in, in, argument, arg); 110 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 111 MLX5_ST_SZ_BYTES(access_register_out) + 112 sizeof(uint32_t) * dw_cnt); 113 if (rc || MLX5_FW_STATUS(out)) { 114 DEVX_DRV_LOG(DEBUG, out, "read access", "NIC register", reg_id); 115 return MLX5_DEVX_ERR_RC(rc); 116 } 117 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 118 dw_cnt * sizeof(uint32_t)); 119 return 0; 120 } 121 122 /** 123 * Perform write access to the registers. 124 * 125 * @param[in] ctx 126 * Context returned from mlx5 open_device() glue function. 127 * @param[in] reg_id 128 * Register identifier according to the PRM. 129 * @param[in] arg 130 * Register access auxiliary parameter according to the PRM. 131 * @param[out] data 132 * Pointer to the buffer containing data to write. 133 * @param[in] dw_cnt 134 * Buffer size in double words (32bit units). 135 * 136 * @return 137 * 0 on success, a negative value otherwise. 138 */ 139 int 140 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 141 uint32_t *data, uint32_t dw_cnt) 142 { 143 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 144 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 145 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 146 int rc; 147 void *ptr; 148 149 MLX5_ASSERT(data && dw_cnt); 150 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 151 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 152 DRV_LOG(ERR, "Data to write exceeds max size"); 153 return -1; 154 } 155 MLX5_SET(access_register_in, in, opcode, 156 MLX5_CMD_OP_ACCESS_REGISTER_USER); 157 MLX5_SET(access_register_in, in, op_mod, 158 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 159 MLX5_SET(access_register_in, in, register_id, reg_id); 160 MLX5_SET(access_register_in, in, argument, arg); 161 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 162 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 163 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 164 if (rc || MLX5_FW_STATUS(out)) { 165 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 166 return MLX5_DEVX_ERR_RC(rc); 167 } 168 rc = mlx5_glue->devx_general_cmd(ctx, in, 169 MLX5_ST_SZ_BYTES(access_register_in) + 170 dw_cnt * sizeof(uint32_t), 171 out, sizeof(out)); 172 if (rc || MLX5_FW_STATUS(out)) { 173 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 174 return MLX5_DEVX_ERR_RC(rc); 175 } 176 return 0; 177 } 178 179 struct mlx5_devx_obj * 180 mlx5_devx_cmd_flow_counter_alloc_general(void *ctx, 181 struct mlx5_devx_counter_attr *attr) 182 { 183 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 184 0, SOCKET_ID_ANY); 185 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 186 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 187 188 if (!dcs) { 189 rte_errno = ENOMEM; 190 return NULL; 191 } 192 MLX5_SET(alloc_flow_counter_in, in, opcode, 193 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 194 if (attr->bulk_log_max_alloc) 195 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk_log_size, 196 attr->flow_counter_bulk_log_size); 197 else 198 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, 199 attr->bulk_n_128); 200 if (attr->pd_valid) 201 MLX5_SET(alloc_flow_counter_in, in, pd, attr->pd); 202 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 203 sizeof(in), out, sizeof(out)); 204 if (!dcs->obj) { 205 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 206 rte_errno = errno; 207 mlx5_free(dcs); 208 return NULL; 209 } 210 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 211 return dcs; 212 } 213 214 /** 215 * Allocate flow counters via devx interface. 216 * 217 * @param[in] ctx 218 * Context returned from mlx5 open_device() glue function. 219 * @param dcs 220 * Pointer to counters properties structure to be filled by the routine. 221 * @param bulk_n_128 222 * Bulk counter numbers in 128 counters units. 223 * 224 * @return 225 * Pointer to counter object on success, a negative value otherwise and 226 * rte_errno is set. 227 */ 228 struct mlx5_devx_obj * 229 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 230 { 231 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 232 0, SOCKET_ID_ANY); 233 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 234 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 235 236 if (!dcs) { 237 rte_errno = ENOMEM; 238 return NULL; 239 } 240 MLX5_SET(alloc_flow_counter_in, in, opcode, 241 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 242 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 243 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 244 sizeof(in), out, sizeof(out)); 245 if (!dcs->obj) { 246 DEVX_DRV_LOG(ERR, out, "allocate counters", NULL, 0); 247 mlx5_free(dcs); 248 return NULL; 249 } 250 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 251 return dcs; 252 } 253 254 /** 255 * Query flow counters values. 256 * 257 * @param[in] dcs 258 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 259 * @param[in] clear 260 * Whether hardware should clear the counters after the query or not. 261 * @param[in] n_counters 262 * 0 in case of 1 counter to read, otherwise the counter number to read. 263 * @param pkts 264 * The number of packets that matched the flow. 265 * @param bytes 266 * The number of bytes that matched the flow. 267 * @param mkey 268 * The mkey key for batch query. 269 * @param addr 270 * The address in the mkey range for batch query. 271 * @param cmd_comp 272 * The completion object for asynchronous batch query. 273 * @param async_id 274 * The ID to be returned in the asynchronous batch query response. 275 * 276 * @return 277 * 0 on success, a negative value otherwise. 278 */ 279 int 280 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 281 int clear, uint32_t n_counters, 282 uint64_t *pkts, uint64_t *bytes, 283 uint32_t mkey, void *addr, 284 void *cmd_comp, 285 uint64_t async_id) 286 { 287 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 288 MLX5_ST_SZ_BYTES(traffic_counter); 289 uint32_t out[out_len]; 290 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 291 void *stats; 292 int rc; 293 294 MLX5_SET(query_flow_counter_in, in, opcode, 295 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 296 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 297 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 298 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 299 300 if (n_counters) { 301 MLX5_SET(query_flow_counter_in, in, num_of_counters, 302 n_counters); 303 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 304 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 305 MLX5_SET64(query_flow_counter_in, in, address, 306 (uint64_t)(uintptr_t)addr); 307 } 308 if (!cmd_comp) 309 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 310 out_len); 311 else 312 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 313 out_len, async_id, 314 cmd_comp); 315 if (rc) { 316 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 317 rte_errno = rc; 318 return -rc; 319 } 320 if (!n_counters) { 321 stats = MLX5_ADDR_OF(query_flow_counter_out, 322 out, flow_statistics); 323 *pkts = MLX5_GET64(traffic_counter, stats, packets); 324 *bytes = MLX5_GET64(traffic_counter, stats, octets); 325 } 326 return 0; 327 } 328 329 /** 330 * Create a new mkey. 331 * 332 * @param[in] ctx 333 * Context returned from mlx5 open_device() glue function. 334 * @param[in] attr 335 * Attributes of the requested mkey. 336 * 337 * @return 338 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 339 * is set. 340 */ 341 struct mlx5_devx_obj * 342 mlx5_devx_cmd_mkey_create(void *ctx, 343 struct mlx5_devx_mkey_attr *attr) 344 { 345 struct mlx5_klm *klm_array = attr->klm_array; 346 int klm_num = attr->klm_num; 347 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 348 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 349 uint32_t in[in_size_dw]; 350 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 351 void *mkc; 352 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 353 0, SOCKET_ID_ANY); 354 size_t pgsize; 355 uint32_t translation_size; 356 357 if (!mkey) { 358 rte_errno = ENOMEM; 359 return NULL; 360 } 361 memset(in, 0, in_size_dw * 4); 362 pgsize = rte_mem_page_size(); 363 if (pgsize == (size_t)-1) { 364 mlx5_free(mkey); 365 DRV_LOG(ERR, "Failed to get page size"); 366 rte_errno = ENOMEM; 367 return NULL; 368 } 369 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 370 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 371 if (klm_num > 0) { 372 int i; 373 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 374 klm_pas_mtt); 375 translation_size = RTE_ALIGN(klm_num, 4); 376 for (i = 0; i < klm_num; i++) { 377 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 378 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 379 MLX5_SET64(klm, klm, address, klm_array[i].address); 380 klm += MLX5_ST_SZ_BYTES(klm); 381 } 382 for (; i < (int)translation_size; i++) { 383 MLX5_SET(klm, klm, mkey, 0x0); 384 MLX5_SET64(klm, klm, address, 0x0); 385 klm += MLX5_ST_SZ_BYTES(klm); 386 } 387 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 388 MLX5_MKC_ACCESS_MODE_KLM_FBS : 389 MLX5_MKC_ACCESS_MODE_KLM); 390 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 391 } else { 392 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 393 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 394 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 395 } 396 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 397 translation_size); 398 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 399 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 400 MLX5_SET(mkc, mkc, lw, 0x1); 401 MLX5_SET(mkc, mkc, lr, 0x1); 402 if (attr->set_remote_rw) { 403 MLX5_SET(mkc, mkc, rw, 0x1); 404 MLX5_SET(mkc, mkc, rr, 0x1); 405 } 406 MLX5_SET(mkc, mkc, qpn, 0xffffff); 407 MLX5_SET(mkc, mkc, pd, attr->pd); 408 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 409 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 410 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 411 MLX5_SET(mkc, mkc, relaxed_ordering_write, 412 attr->relaxed_ordering_write); 413 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 414 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 415 MLX5_SET64(mkc, mkc, len, attr->size); 416 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 417 if (attr->crypto_en) { 418 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 419 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 420 } 421 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 422 sizeof(out)); 423 if (!mkey->obj) { 424 DEVX_DRV_LOG(ERR, out, klm_num ? "create indirect mkey" 425 : "create direct key", NULL, 0); 426 mlx5_free(mkey); 427 return NULL; 428 } 429 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 430 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 431 return mkey; 432 } 433 434 /** 435 * Get status of devx command response. 436 * Mainly used for asynchronous commands. 437 * 438 * @param[in] out 439 * The out response buffer. 440 * 441 * @return 442 * 0 on success, non-zero value otherwise. 443 */ 444 int 445 mlx5_devx_get_out_command_status(void *out) 446 { 447 int status; 448 449 if (!out) 450 return -EINVAL; 451 status = MLX5_GET(query_flow_counter_out, out, status); 452 if (status) { 453 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 454 455 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 456 syndrome); 457 } 458 return status; 459 } 460 461 /** 462 * Destroy any object allocated by a Devx API. 463 * 464 * @param[in] obj 465 * Pointer to a general object. 466 * 467 * @return 468 * 0 on success, a negative value otherwise. 469 */ 470 int 471 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 472 { 473 int ret; 474 475 if (!obj) 476 return 0; 477 ret = mlx5_glue->devx_obj_destroy(obj->obj); 478 mlx5_free(obj); 479 return ret; 480 } 481 482 /** 483 * Query NIC vport context. 484 * Fills minimal inline attribute. 485 * 486 * @param[in] ctx 487 * ibv contexts returned from mlx5dv_open_device. 488 * @param[in] vport 489 * vport index 490 * @param[out] attr 491 * Attributes device values. 492 * 493 * @return 494 * 0 on success, a negative value otherwise. 495 */ 496 static int 497 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 498 unsigned int vport, 499 struct mlx5_hca_attr *attr) 500 { 501 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 502 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 503 void *vctx; 504 int rc; 505 506 /* Query NIC vport context to determine inline mode. */ 507 MLX5_SET(query_nic_vport_context_in, in, opcode, 508 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 509 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 510 if (vport) 511 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 512 rc = mlx5_glue->devx_general_cmd(ctx, 513 in, sizeof(in), 514 out, sizeof(out)); 515 if (rc || MLX5_FW_STATUS(out)) { 516 DEVX_DRV_LOG(ERR, out, "query NIC vport context", NULL, 0); 517 return MLX5_DEVX_ERR_RC(rc); 518 } 519 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 520 nic_vport_context); 521 if (attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) 522 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 523 min_wqe_inline_mode); 524 attr->system_image_guid = MLX5_GET64(nic_vport_context, vctx, 525 system_image_guid); 526 return 0; 527 } 528 529 /** 530 * Query NIC vDPA attributes. 531 * 532 * @param[in] ctx 533 * Context returned from mlx5 open_device() glue function. 534 * @param[out] vdpa_attr 535 * vDPA Attributes structure to fill. 536 */ 537 static void 538 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 539 struct mlx5_hca_vdpa_attr *vdpa_attr) 540 { 541 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 542 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 543 void *hcattr; 544 545 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, 546 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 547 MLX5_HCA_CAP_OPMOD_GET_CUR); 548 if (!hcattr) { 549 DRV_LOG(DEBUG, "Failed to query devx VDPA capabilities"); 550 vdpa_attr->valid = 0; 551 } else { 552 vdpa_attr->valid = 1; 553 vdpa_attr->desc_tunnel_offload_type = 554 MLX5_GET(virtio_emulation_cap, hcattr, 555 desc_tunnel_offload_type); 556 vdpa_attr->eth_frame_offload_type = 557 MLX5_GET(virtio_emulation_cap, hcattr, 558 eth_frame_offload_type); 559 vdpa_attr->virtio_version_1_0 = 560 MLX5_GET(virtio_emulation_cap, hcattr, 561 virtio_version_1_0); 562 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 563 tso_ipv4); 564 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 565 tso_ipv6); 566 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 567 tx_csum); 568 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 569 rx_csum); 570 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 571 event_mode); 572 vdpa_attr->virtio_queue_type = 573 MLX5_GET(virtio_emulation_cap, hcattr, 574 virtio_queue_type); 575 vdpa_attr->log_doorbell_stride = 576 MLX5_GET(virtio_emulation_cap, hcattr, 577 log_doorbell_stride); 578 vdpa_attr->vnet_modify_ext = 579 MLX5_GET(virtio_emulation_cap, hcattr, 580 vnet_modify_ext); 581 vdpa_attr->virtio_net_q_addr_modify = 582 MLX5_GET(virtio_emulation_cap, hcattr, 583 virtio_net_q_addr_modify); 584 vdpa_attr->virtio_q_index_modify = 585 MLX5_GET(virtio_emulation_cap, hcattr, 586 virtio_q_index_modify); 587 vdpa_attr->log_doorbell_bar_size = 588 MLX5_GET(virtio_emulation_cap, hcattr, 589 log_doorbell_bar_size); 590 vdpa_attr->doorbell_bar_offset = 591 MLX5_GET64(virtio_emulation_cap, hcattr, 592 doorbell_bar_offset); 593 vdpa_attr->max_num_virtio_queues = 594 MLX5_GET(virtio_emulation_cap, hcattr, 595 max_num_virtio_queues); 596 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 597 umem_1_buffer_param_a); 598 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 599 umem_1_buffer_param_b); 600 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 601 umem_2_buffer_param_a); 602 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 603 umem_2_buffer_param_b); 604 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 605 umem_3_buffer_param_a); 606 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 607 umem_3_buffer_param_b); 608 } 609 } 610 611 /** 612 * Query match sample handle parameters. 613 * 614 * This command allows translating a field sample handle returned by either 615 * PARSE_GRAPH_FLOW_MATCH_SAMPLE or by GENEVE TLV OPTION object into values 616 * used for header modification or header matching/hashing. 617 * 618 * @param[in] ctx 619 * Context used to create either GENEVE TLV option or FLEX PARSE GRAPH object. 620 * @param[in] sample_field_id 621 * Field sample handle returned by either PARSE_GRAPH_FLOW_MATCH_SAMPLE 622 * or by GENEVE TLV OPTION object. 623 * @param[out] attr 624 * Pointer to match sample info attributes structure. 625 * 626 * @return 627 * 0 on success, a negative errno otherwise and rte_errno is set. 628 */ 629 int 630 mlx5_devx_cmd_match_sample_info_query(void *ctx, uint32_t sample_field_id, 631 struct mlx5_devx_match_sample_info_query_attr *attr) 632 { 633 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 634 uint32_t out[MLX5_ST_SZ_DW(query_match_sample_info_out)] = {0}; 635 uint32_t in[MLX5_ST_SZ_DW(query_match_sample_info_in)] = {0}; 636 int rc; 637 638 MLX5_SET(query_match_sample_info_in, in, opcode, 639 MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO); 640 MLX5_SET(query_match_sample_info_in, in, op_mod, 0); 641 MLX5_SET(query_match_sample_info_in, in, sample_field_id, 642 sample_field_id); 643 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 644 if (rc || MLX5_FW_STATUS(out)) { 645 DEVX_DRV_LOG(ERR, out, "query match sample info", 646 "sample_field_id", sample_field_id); 647 return MLX5_DEVX_ERR_RC(rc); 648 } 649 attr->modify_field_id = MLX5_GET(query_match_sample_info_out, out, 650 modify_field_id); 651 attr->sample_dw_data = MLX5_GET(query_match_sample_info_out, out, 652 field_format_select_dw); 653 attr->sample_dw_ok_bit = MLX5_GET(query_match_sample_info_out, out, 654 ok_bit_format_select_dw); 655 attr->sample_dw_ok_bit_offset = MLX5_GET(query_match_sample_info_out, 656 out, ok_bit_offset); 657 return 0; 658 #else 659 (void)ctx; 660 (void)sample_field_id; 661 (void)attr; 662 return -ENOTSUP; 663 #endif 664 } 665 666 int 667 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 668 uint32_t *ids, 669 uint32_t num, uint8_t *anchor) 670 { 671 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 672 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 673 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 674 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 675 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 676 int ret; 677 uint32_t idx = 0; 678 uint32_t i; 679 680 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 681 rte_errno = EINVAL; 682 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 683 return -rte_errno; 684 } 685 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 686 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 687 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 688 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 689 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 690 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 691 out, sizeof(out)); 692 if (ret) { 693 rte_errno = ret; 694 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 695 (void *)flex_obj); 696 return -rte_errno; 697 } 698 if (anchor) 699 *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id); 700 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx < num; i++) { 701 void *s_off = (void *)((char *)sample + i * 702 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 703 uint32_t en; 704 705 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 706 flow_match_sample_en); 707 if (!en) 708 continue; 709 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 710 flow_match_sample_field_id); 711 } 712 if (num != idx) { 713 rte_errno = EINVAL; 714 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 715 return -rte_errno; 716 } 717 return ret; 718 } 719 720 struct mlx5_devx_obj * 721 mlx5_devx_cmd_create_flex_parser(void *ctx, 722 struct mlx5_devx_graph_node_attr *data) 723 { 724 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 725 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 726 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 727 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 728 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 729 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 730 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 731 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 732 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 733 uint32_t i; 734 735 if (!parse_flex_obj) { 736 DRV_LOG(ERR, "Failed to allocate flex parser data."); 737 rte_errno = ENOMEM; 738 return NULL; 739 } 740 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 741 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 742 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 743 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 744 MLX5_SET(parse_graph_flex, flex, header_length_mode, 745 data->header_length_mode); 746 MLX5_SET64(parse_graph_flex, flex, modify_field_select, 747 data->modify_field_select); 748 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 749 data->header_length_base_value); 750 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 751 data->header_length_field_offset); 752 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 753 data->header_length_field_shift); 754 MLX5_SET(parse_graph_flex, flex, next_header_field_offset, 755 data->next_header_field_offset); 756 MLX5_SET(parse_graph_flex, flex, next_header_field_size, 757 data->next_header_field_size); 758 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 759 data->header_length_field_mask); 760 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 761 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 762 void *s_off = (void *)((char *)sample + i * 763 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 764 765 if (!s->flow_match_sample_en) 766 continue; 767 MLX5_SET(parse_graph_flow_match_sample, s_off, 768 flow_match_sample_en, !!s->flow_match_sample_en); 769 MLX5_SET(parse_graph_flow_match_sample, s_off, 770 flow_match_sample_field_offset, 771 s->flow_match_sample_field_offset); 772 MLX5_SET(parse_graph_flow_match_sample, s_off, 773 flow_match_sample_offset_mode, 774 s->flow_match_sample_offset_mode); 775 MLX5_SET(parse_graph_flow_match_sample, s_off, 776 flow_match_sample_field_offset_mask, 777 s->flow_match_sample_field_offset_mask); 778 MLX5_SET(parse_graph_flow_match_sample, s_off, 779 flow_match_sample_field_offset_shift, 780 s->flow_match_sample_field_offset_shift); 781 MLX5_SET(parse_graph_flow_match_sample, s_off, 782 flow_match_sample_field_base_offset, 783 s->flow_match_sample_field_base_offset); 784 MLX5_SET(parse_graph_flow_match_sample, s_off, 785 flow_match_sample_tunnel_mode, 786 s->flow_match_sample_tunnel_mode); 787 } 788 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 789 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 790 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 791 void *in_off = (void *)((char *)in_arc + i * 792 MLX5_ST_SZ_BYTES(parse_graph_arc)); 793 void *out_off = (void *)((char *)out_arc + i * 794 MLX5_ST_SZ_BYTES(parse_graph_arc)); 795 796 if (ia->arc_parse_graph_node != 0) { 797 MLX5_SET(parse_graph_arc, in_off, 798 compare_condition_value, 799 ia->compare_condition_value); 800 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 801 ia->start_inner_tunnel); 802 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 803 ia->arc_parse_graph_node); 804 MLX5_SET(parse_graph_arc, in_off, 805 parse_graph_node_handle, 806 ia->parse_graph_node_handle); 807 } 808 if (oa->arc_parse_graph_node != 0) { 809 MLX5_SET(parse_graph_arc, out_off, 810 compare_condition_value, 811 oa->compare_condition_value); 812 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 813 oa->start_inner_tunnel); 814 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 815 oa->arc_parse_graph_node); 816 MLX5_SET(parse_graph_arc, out_off, 817 parse_graph_node_handle, 818 oa->parse_graph_node_handle); 819 } 820 } 821 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 822 out, sizeof(out)); 823 if (!parse_flex_obj->obj) { 824 DEVX_DRV_LOG(ERR, out, "create FLEX PARSE GRAPH", NULL, 0); 825 mlx5_free(parse_flex_obj); 826 return NULL; 827 } 828 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 829 return parse_flex_obj; 830 } 831 832 static int 833 mlx5_devx_cmd_query_hca_parse_graph_node_cap 834 (void *ctx, struct mlx5_hca_flex_attr *attr) 835 { 836 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 837 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 838 void *hcattr; 839 int rc; 840 841 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 842 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | 843 MLX5_HCA_CAP_OPMOD_GET_CUR); 844 if (!hcattr) 845 return rc; 846 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); 847 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); 848 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, 849 header_length_mode); 850 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, 851 sample_offset_mode); 852 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, 853 max_num_arc_in); 854 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, 855 max_num_arc_out); 856 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, 857 max_num_sample); 858 attr->parse_graph_anchor = MLX5_GET(parse_graph_node_cap, hcattr, parse_graph_anchor); 859 attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr, 860 sample_tunnel_inner2); 861 attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr, 862 zero_size_supported); 863 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, 864 sample_id_in_out); 865 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, 866 max_base_header_length); 867 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, 868 max_sample_base_offset); 869 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, 870 max_next_header_offset); 871 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, 872 header_length_mask_width); 873 /* Get the max supported samples from HCA CAP 2 */ 874 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 875 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 876 MLX5_HCA_CAP_OPMOD_GET_CUR); 877 if (!hcattr) 878 return rc; 879 attr->max_num_prog_sample = 880 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); 881 return 0; 882 } 883 884 static int 885 mlx5_devx_query_pkt_integrity_match(void *hcattr) 886 { 887 return MLX5_GET(flow_table_nic_cap, hcattr, 888 ft_field_support_2_nic_receive.inner_l3_ok) && 889 MLX5_GET(flow_table_nic_cap, hcattr, 890 ft_field_support_2_nic_receive.inner_l4_ok) && 891 MLX5_GET(flow_table_nic_cap, hcattr, 892 ft_field_support_2_nic_receive.outer_l3_ok) && 893 MLX5_GET(flow_table_nic_cap, hcattr, 894 ft_field_support_2_nic_receive.outer_l4_ok) && 895 MLX5_GET(flow_table_nic_cap, hcattr, 896 ft_field_support_2_nic_receive 897 .inner_ipv4_checksum_ok) && 898 MLX5_GET(flow_table_nic_cap, hcattr, 899 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 900 MLX5_GET(flow_table_nic_cap, hcattr, 901 ft_field_support_2_nic_receive 902 .outer_ipv4_checksum_ok) && 903 MLX5_GET(flow_table_nic_cap, hcattr, 904 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 905 } 906 907 /** 908 * Query HCA attributes. 909 * Using those attributes we can check on run time if the device 910 * is having the required capabilities. 911 * 912 * @param[in] ctx 913 * Context returned from mlx5 open_device() glue function. 914 * @param[out] attr 915 * Attributes device values. 916 * 917 * @return 918 * 0 on success, a negative value otherwise. 919 */ 920 int 921 mlx5_devx_cmd_query_hca_attr(void *ctx, 922 struct mlx5_hca_attr *attr) 923 { 924 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 925 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 926 bool hca_cap_2_sup; 927 uint64_t general_obj_types_supported = 0; 928 void *hcattr; 929 int rc, i; 930 931 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 932 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 933 MLX5_HCA_CAP_OPMOD_GET_CUR); 934 if (!hcattr) 935 return rc; 936 hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2); 937 attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq); 938 attr->flow_counter_bulk_alloc_bitmap = 939 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 940 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 941 flow_counters_dump); 942 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp); 943 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp); 944 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 945 log_max_rqt_size); 946 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 947 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 948 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 949 log_max_hairpin_queues); 950 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 951 log_max_hairpin_wq_data_sz); 952 attr->log_max_hairpin_num_packets = MLX5_GET 953 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 954 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 955 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 956 relaxed_ordering_write); 957 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 958 relaxed_ordering_read); 959 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 960 access_register_user); 961 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 962 eth_net_offloads); 963 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 964 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 965 flex_parser_protocols); 966 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 967 max_geneve_tlv_options); 968 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 969 max_geneve_tlv_option_data_len); 970 attr->geneve_tlv_option_offset = MLX5_GET(cmd_hca_cap, hcattr, 971 geneve_tlv_option_offset); 972 attr->geneve_tlv_sample = MLX5_GET(cmd_hca_cap, hcattr, 973 geneve_tlv_sample); 974 attr->query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr, 975 query_match_sample_info); 976 attr->geneve_tlv_option_sample_id = MLX5_GET(cmd_hca_cap, hcattr, 977 flex_parser_id_geneve_opt_0); 978 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 979 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 980 wqe_index_ignore_cap); 981 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 982 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 983 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 984 log_max_static_sq_wq); 985 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 986 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 987 device_frequency_khz); 988 attr->scatter_fcs_w_decap_disable = 989 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 990 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 991 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 992 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 993 attr->steering_format_version = 994 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 995 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 996 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 997 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 998 regexp_num_of_engines); 999 /* Read the general_obj_types bitmap and extract the relevant bits. */ 1000 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 1001 general_obj_types); 1002 attr->qos.flow_meter_aso_sup = 1003 !!(general_obj_types_supported & 1004 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 1005 attr->vdpa.valid = !!(general_obj_types_supported & 1006 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 1007 attr->vdpa.queue_counters_valid = 1008 !!(general_obj_types_supported & 1009 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 1010 attr->parse_graph_flex_node = 1011 !!(general_obj_types_supported & 1012 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 1013 attr->flow_hit_aso = !!(general_obj_types_supported & 1014 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 1015 attr->geneve_tlv_opt = !!(general_obj_types_supported & 1016 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 1017 attr->dek = !!(general_obj_types_supported & 1018 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 1019 attr->import_kek = !!(general_obj_types_supported & 1020 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 1021 attr->credential = !!(general_obj_types_supported & 1022 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 1023 attr->crypto_login = !!(general_obj_types_supported & 1024 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 1025 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 1026 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 1027 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 1028 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 1029 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 1030 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 1031 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 1032 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 1033 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 1034 attr->reg_c_preserve = 1035 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 1036 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 1037 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 1038 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 1039 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 1040 compress_mmo_sq); 1041 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 1042 decompress_mmo_sq); 1043 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 1044 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 1045 compress_mmo_qp); 1046 attr->decomp_deflate_v1_en = MLX5_GET(cmd_hca_cap, hcattr, 1047 decompress_deflate_v1); 1048 attr->decomp_deflate_v2_en = MLX5_GET(cmd_hca_cap, hcattr, 1049 decompress_deflate_v2); 1050 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 1051 compress_min_block_size); 1052 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 1053 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 1054 log_compress_mmo_size); 1055 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 1056 log_decompress_mmo_size); 1057 attr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr, 1058 decompress_lz4_data_only_v2); 1059 attr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, 1060 decompress_lz4_no_checksum_v2); 1061 attr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, 1062 decompress_lz4_checksum_v2); 1063 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 1064 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 1065 mini_cqe_resp_flow_tag); 1066 attr->cqe_compression_128 = MLX5_GET(cmd_hca_cap, hcattr, 1067 cqe_compression_128); 1068 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 1069 mini_cqe_resp_l3_l4_tag); 1070 attr->enhanced_cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, 1071 enhanced_cqe_compression); 1072 attr->umr_indirect_mkey_disabled = 1073 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 1074 attr->umr_modify_entity_size_disabled = 1075 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 1076 attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time); 1077 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 1078 attr->ct_offload = !!(general_obj_types_supported & 1079 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 1080 attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); 1081 attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table); 1082 attr->striding_rq = MLX5_GET(cmd_hca_cap, hcattr, striding_rq); 1083 attr->ext_stride_num_range = 1084 MLX5_GET(cmd_hca_cap, hcattr, ext_stride_num_range); 1085 attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table); 1086 attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr, 1087 max_flow_counter_15_0); 1088 attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr, 1089 max_flow_counter_31_16); 1090 attr->alloc_flow_counter_pd = MLX5_GET(cmd_hca_cap, hcattr, 1091 alloc_flow_counter_pd); 1092 attr->flow_counter_access_aso = MLX5_GET(cmd_hca_cap, hcattr, 1093 flow_counter_access_aso); 1094 attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr, 1095 flow_access_aso_opc_mod); 1096 attr->wqe_based_flow_table_sup = MLX5_GET(cmd_hca_cap, hcattr, 1097 wqe_based_flow_table_update_cap); 1098 /* 1099 * Flex item support needs max_num_prog_sample_field 1100 * from the Capabilities 2 table for PARSE_GRAPH_NODE 1101 */ 1102 if (attr->parse_graph_flex_node) { 1103 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap 1104 (ctx, &attr->flex); 1105 if (rc) 1106 return -1; 1107 attr->flex.query_match_sample_info = 1108 attr->query_match_sample_info; 1109 } 1110 if (attr->crypto) { 1111 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) || 1112 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_multi_block_be_tweak) || 1113 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_single_block_le_tweak); 1114 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1115 MLX5_GET_HCA_CAP_OP_MOD_CRYPTO | 1116 MLX5_HCA_CAP_OPMOD_GET_CUR); 1117 if (!hcattr) 1118 return -1; 1119 attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps, 1120 hcattr, wrapped_import_method) 1121 & 1 << 2); 1122 attr->crypto_mmo.crypto_mmo_qp = MLX5_GET(crypto_caps, hcattr, crypto_mmo_qp); 1123 attr->crypto_mmo.gcm_256_encrypt = 1124 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_encrypt); 1125 attr->crypto_mmo.gcm_128_encrypt = 1126 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_encrypt); 1127 attr->crypto_mmo.gcm_256_decrypt = 1128 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_decrypt); 1129 attr->crypto_mmo.gcm_128_decrypt = 1130 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_decrypt); 1131 attr->crypto_mmo.gcm_auth_tag_128 = 1132 MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_128); 1133 attr->crypto_mmo.gcm_auth_tag_96 = 1134 MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_96); 1135 attr->crypto_mmo.log_crypto_mmo_max_size = 1136 MLX5_GET(crypto_caps, hcattr, log_crypto_mmo_max_size); 1137 } 1138 if (hca_cap_2_sup) { 1139 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1140 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 1141 MLX5_HCA_CAP_OPMOD_GET_CUR); 1142 if (!hcattr) { 1143 DRV_LOG(DEBUG, 1144 "Failed to query DevX HCA capabilities 2."); 1145 return rc; 1146 } 1147 attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, 1148 log_min_stride_wqe_sz); 1149 attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr, 1150 hairpin_sq_wqe_bb_size); 1151 attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr, 1152 hairpin_sq_wq_in_host_mem); 1153 attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr, 1154 hairpin_data_buffer_locked); 1155 attr->flow_counter_bulk_log_max_alloc = MLX5_GET(cmd_hca_cap_2, 1156 hcattr, flow_counter_bulk_log_max_alloc); 1157 attr->flow_counter_bulk_log_granularity = 1158 MLX5_GET(cmd_hca_cap_2, hcattr, 1159 flow_counter_bulk_log_granularity); 1160 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1161 cross_vhca_object_to_object_supported); 1162 attr->cross_vhca = 1163 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR) && 1164 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT) && 1165 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT) && 1166 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC); 1167 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1168 allowed_object_for_other_vhca_access); 1169 attr->cross_vhca = attr->cross_vhca && 1170 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR) && 1171 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_FT) && 1172 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC); 1173 } 1174 if (attr->log_min_stride_wqe_sz == 0) 1175 attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 1176 if (attr->qos.sup) { 1177 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1178 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 1179 MLX5_HCA_CAP_OPMOD_GET_CUR); 1180 if (!hcattr) { 1181 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); 1182 return rc; 1183 } 1184 attr->qos.flow_meter_old = 1185 MLX5_GET(qos_cap, hcattr, flow_meter_old); 1186 attr->qos.log_max_flow_meter = 1187 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 1188 attr->qos.flow_meter_reg_c_ids = 1189 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 1190 attr->qos.flow_meter = 1191 MLX5_GET(qos_cap, hcattr, flow_meter); 1192 attr->qos.packet_pacing = 1193 MLX5_GET(qos_cap, hcattr, packet_pacing); 1194 attr->qos.wqe_rate_pp = 1195 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 1196 if (attr->qos.flow_meter_aso_sup) { 1197 attr->qos.log_meter_aso_granularity = 1198 MLX5_GET(qos_cap, hcattr, 1199 log_meter_aso_granularity); 1200 attr->qos.log_meter_aso_max_alloc = 1201 MLX5_GET(qos_cap, hcattr, 1202 log_meter_aso_max_alloc); 1203 attr->qos.log_max_num_meter_aso = 1204 MLX5_GET(qos_cap, hcattr, 1205 log_max_num_meter_aso); 1206 } 1207 } 1208 if (attr->vdpa.valid) 1209 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 1210 if (!attr->eth_net_offloads) 1211 return 0; 1212 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 1213 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1214 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 1215 MLX5_HCA_CAP_OPMOD_GET_CUR); 1216 if (!hcattr) { 1217 attr->log_max_ft_sampler_num = 0; 1218 return rc; 1219 } 1220 attr->log_max_ft_sampler_num = MLX5_GET 1221 (flow_table_nic_cap, hcattr, 1222 flow_table_properties_nic_receive.log_max_ft_sampler_num); 1223 attr->flow.tunnel_header_0_1 = MLX5_GET 1224 (flow_table_nic_cap, hcattr, 1225 ft_field_support_2_nic_receive.tunnel_header_0_1); 1226 attr->flow.tunnel_header_2_3 = MLX5_GET 1227 (flow_table_nic_cap, hcattr, 1228 ft_field_support_2_nic_receive.tunnel_header_2_3); 1229 attr->modify_outer_ip_ecn = MLX5_GET 1230 (flow_table_nic_cap, hcattr, 1231 ft_header_modify_nic_receive.outer_ip_ecn); 1232 attr->modify_outer_ipv6_traffic_class = MLX5_GET 1233 (flow_table_nic_cap, hcattr, 1234 ft_header_modify_nic_receive.outer_ipv6_traffic_class); 1235 attr->set_reg_c = 0xffff; 1236 if (attr->nic_flow_table) { 1237 #define GET_RX_REG_X_BITS \ 1238 MLX5_GET(flow_table_nic_cap, hcattr, \ 1239 ft_header_modify_nic_receive.metadata_reg_c_x) 1240 #define GET_TX_REG_X_BITS \ 1241 MLX5_GET(flow_table_nic_cap, hcattr, \ 1242 ft_header_modify_nic_transmit.metadata_reg_c_x) 1243 1244 uint32_t tx_reg, rx_reg, reg_c_8_15; 1245 1246 tx_reg = GET_TX_REG_X_BITS; 1247 reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr, 1248 ft_field_support_2_nic_transmit.metadata_reg_c_8_15); 1249 tx_reg |= ((0xff & reg_c_8_15) << 8); 1250 rx_reg = GET_RX_REG_X_BITS; 1251 reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr, 1252 ft_field_support_2_nic_receive.metadata_reg_c_8_15); 1253 rx_reg |= ((0xff & reg_c_8_15) << 8); 1254 attr->set_reg_c &= (rx_reg & tx_reg); 1255 1256 #undef GET_RX_REG_X_BITS 1257 #undef GET_TX_REG_X_BITS 1258 } 1259 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 1260 attr->inner_ipv4_ihl = MLX5_GET 1261 (flow_table_nic_cap, hcattr, 1262 ft_field_support_2_nic_receive.inner_ipv4_ihl); 1263 attr->outer_ipv4_ihl = MLX5_GET 1264 (flow_table_nic_cap, hcattr, 1265 ft_field_support_2_nic_receive.outer_ipv4_ihl); 1266 attr->lag_rx_port_affinity = MLX5_GET 1267 (flow_table_nic_cap, hcattr, 1268 ft_field_support_2_nic_receive.lag_rx_port_affinity); 1269 /* Query HCA offloads for Ethernet protocol. */ 1270 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1271 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 1272 MLX5_HCA_CAP_OPMOD_GET_CUR); 1273 if (!hcattr) { 1274 attr->eth_net_offloads = 0; 1275 return rc; 1276 } 1277 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 1278 hcattr, wqe_vlan_insert); 1279 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 1280 hcattr, csum_cap); 1281 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 1282 hcattr, vlan_cap); 1283 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1284 lro_cap); 1285 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1286 hcattr, max_lso_cap); 1287 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1288 hcattr, scatter_fcs); 1289 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1290 hcattr, tunnel_lro_gre); 1291 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1292 hcattr, tunnel_lro_vxlan); 1293 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1294 hcattr, swp); 1295 attr->tunnel_stateless_gre = 1296 MLX5_GET(per_protocol_networking_offload_caps, 1297 hcattr, tunnel_stateless_gre); 1298 attr->tunnel_stateless_vxlan = 1299 MLX5_GET(per_protocol_networking_offload_caps, 1300 hcattr, tunnel_stateless_vxlan); 1301 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1302 hcattr, swp_csum); 1303 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1304 hcattr, swp_lso); 1305 attr->lro_max_msg_sz_mode = MLX5_GET 1306 (per_protocol_networking_offload_caps, 1307 hcattr, lro_max_msg_sz_mode); 1308 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1309 attr->lro_timer_supported_periods[i] = 1310 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1311 lro_timer_supported_periods[i]); 1312 } 1313 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1314 hcattr, lro_min_mss_size); 1315 attr->tunnel_stateless_geneve_rx = 1316 MLX5_GET(per_protocol_networking_offload_caps, 1317 hcattr, tunnel_stateless_geneve_rx); 1318 attr->geneve_max_opt_len = 1319 MLX5_GET(per_protocol_networking_offload_caps, 1320 hcattr, max_geneve_opt_len); 1321 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1322 hcattr, wqe_inline_mode); 1323 attr->tunnel_stateless_gtp = MLX5_GET 1324 (per_protocol_networking_offload_caps, 1325 hcattr, tunnel_stateless_gtp); 1326 attr->tunnel_stateless_vxlan_gpe_nsh = MLX5_GET 1327 (per_protocol_networking_offload_caps, 1328 hcattr, tunnel_stateless_vxlan_gpe_nsh); 1329 attr->rss_ind_tbl_cap = MLX5_GET 1330 (per_protocol_networking_offload_caps, 1331 hcattr, rss_ind_tbl_cap); 1332 attr->multi_pkt_send_wqe = MLX5_GET 1333 (per_protocol_networking_offload_caps, 1334 hcattr, multi_pkt_send_wqe); 1335 attr->enhanced_multi_pkt_send_wqe = MLX5_GET 1336 (per_protocol_networking_offload_caps, 1337 hcattr, enhanced_multi_pkt_send_wqe); 1338 if (attr->wqe_based_flow_table_sup) { 1339 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1340 MLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE | 1341 MLX5_HCA_CAP_OPMOD_GET_CUR); 1342 if (!hcattr) { 1343 DRV_LOG(DEBUG, "Failed to query WQE Based Flow table capabilities"); 1344 return rc; 1345 } 1346 attr->max_header_modify_pattern_length = MLX5_GET(wqe_based_flow_table_cap, 1347 hcattr, 1348 max_header_modify_pattern_length); 1349 } 1350 /* Query HCA attribute for ROCE. */ 1351 if (attr->roce) { 1352 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1353 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1354 MLX5_HCA_CAP_OPMOD_GET_CUR); 1355 if (!hcattr) { 1356 DRV_LOG(DEBUG, 1357 "Failed to query devx HCA ROCE capabilities"); 1358 return rc; 1359 } 1360 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1361 } 1362 if (attr->eth_virt) { 1363 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1364 if (rc) { 1365 attr->eth_virt = 0; 1366 goto error; 1367 } 1368 } 1369 if (attr->eswitch_manager) { 1370 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1371 MLX5_SET_HCA_CAP_OP_MOD_ESW | 1372 MLX5_HCA_CAP_OPMOD_GET_CUR); 1373 if (!hcattr) 1374 return rc; 1375 attr->esw_mgr_vport_id_valid = 1376 MLX5_GET(esw_cap, hcattr, 1377 esw_manager_vport_number_valid); 1378 attr->esw_mgr_vport_id = 1379 MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); 1380 } 1381 if (attr->eswitch_manager) { 1382 uint32_t esw_reg, reg_c_8_15; 1383 1384 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1385 MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE | 1386 MLX5_HCA_CAP_OPMOD_GET_CUR); 1387 if (!hcattr) 1388 return rc; 1389 esw_reg = MLX5_GET(flow_table_esw_cap, hcattr, 1390 ft_header_modify_esw_fdb.metadata_reg_c_x); 1391 reg_c_8_15 = MLX5_GET(flow_table_esw_cap, hcattr, 1392 ft_field_support_2_esw_fdb.metadata_reg_c_8_15); 1393 attr->set_reg_c &= ((0xff & reg_c_8_15) << 8) | esw_reg; 1394 } 1395 return 0; 1396 error: 1397 rc = (rc > 0) ? -rc : rc; 1398 return rc; 1399 } 1400 1401 /** 1402 * Query TIS transport domain from QP verbs object using DevX API. 1403 * 1404 * @param[in] qp 1405 * Pointer to verbs QP returned by ibv_create_qp . 1406 * @param[in] tis_num 1407 * TIS number of TIS to query. 1408 * @param[out] tis_td 1409 * Pointer to TIS transport domain variable, to be set by the routine. 1410 * 1411 * @return 1412 * 0 on success, a negative value otherwise. 1413 */ 1414 int 1415 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1416 uint32_t *tis_td) 1417 { 1418 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1419 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1420 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1421 int rc; 1422 void *tis_ctx; 1423 1424 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1425 MLX5_SET(query_tis_in, in, tisn, tis_num); 1426 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1427 if (rc) { 1428 DRV_LOG(ERR, "Failed to query QP using DevX"); 1429 return -rc; 1430 }; 1431 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1432 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1433 return 0; 1434 #else 1435 (void)qp; 1436 (void)tis_num; 1437 (void)tis_td; 1438 return -ENOTSUP; 1439 #endif 1440 } 1441 1442 /** 1443 * Fill WQ data for DevX API command. 1444 * Utility function for use when creating DevX objects containing a WQ. 1445 * 1446 * @param[in] wq_ctx 1447 * Pointer to WQ context to fill with data. 1448 * @param [in] wq_attr 1449 * Pointer to WQ attributes structure to fill in WQ context. 1450 */ 1451 static void 1452 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1453 { 1454 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1455 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1456 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1457 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1458 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1459 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1460 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1461 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1462 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1463 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1464 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1465 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1466 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1467 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1468 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1469 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1470 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1471 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1472 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1473 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1474 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1475 wq_attr->log_hairpin_num_packets); 1476 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1477 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1478 wq_attr->single_wqe_log_num_of_strides); 1479 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1480 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1481 wq_attr->single_stride_log_num_of_bytes); 1482 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1483 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1484 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1485 } 1486 1487 /** 1488 * Create RQ using DevX API. 1489 * 1490 * @param[in] ctx 1491 * Context returned from mlx5 open_device() glue function. 1492 * @param [in] rq_attr 1493 * Pointer to create RQ attributes structure. 1494 * @param [in] socket 1495 * CPU socket ID for allocations. 1496 * 1497 * @return 1498 * The DevX object created, NULL otherwise and rte_errno is set. 1499 */ 1500 struct mlx5_devx_obj * 1501 mlx5_devx_cmd_create_rq(void *ctx, 1502 struct mlx5_devx_create_rq_attr *rq_attr, 1503 int socket) 1504 { 1505 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1506 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1507 void *rq_ctx, *wq_ctx; 1508 struct mlx5_devx_wq_attr *wq_attr; 1509 struct mlx5_devx_obj *rq = NULL; 1510 1511 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1512 if (!rq) { 1513 DRV_LOG(ERR, "Failed to allocate RQ data"); 1514 rte_errno = ENOMEM; 1515 return NULL; 1516 } 1517 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1518 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1519 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1520 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1521 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1522 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1523 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1524 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1525 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1526 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1527 MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type); 1528 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1529 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1530 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1531 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1532 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1533 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1534 wq_attr = &rq_attr->wq_attr; 1535 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1536 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1537 out, sizeof(out)); 1538 if (!rq->obj) { 1539 DEVX_DRV_LOG(ERR, out, "create RQ", NULL, 0); 1540 mlx5_free(rq); 1541 return NULL; 1542 } 1543 rq->id = MLX5_GET(create_rq_out, out, rqn); 1544 return rq; 1545 } 1546 1547 /** 1548 * Modify RQ using DevX API. 1549 * 1550 * @param[in] rq 1551 * Pointer to RQ object structure. 1552 * @param [in] rq_attr 1553 * Pointer to modify RQ attributes structure. 1554 * 1555 * @return 1556 * 0 on success, a negative errno value otherwise and rte_errno is set. 1557 */ 1558 int 1559 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1560 struct mlx5_devx_modify_rq_attr *rq_attr) 1561 { 1562 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1563 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1564 void *rq_ctx, *wq_ctx; 1565 int ret; 1566 1567 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1568 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1569 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1570 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1571 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1572 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1573 if (rq_attr->modify_bitmask & 1574 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1575 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1576 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1577 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1578 if (rq_attr->modify_bitmask & 1579 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1580 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1581 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1582 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1583 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1584 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1585 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1586 } 1587 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1588 out, sizeof(out)); 1589 if (ret) { 1590 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1591 rte_errno = errno; 1592 return -errno; 1593 } 1594 return ret; 1595 } 1596 1597 /** 1598 * Create RMP using DevX API. 1599 * 1600 * @param[in] ctx 1601 * Context returned from mlx5 open_device() glue function. 1602 * @param [in] rmp_attr 1603 * Pointer to create RMP attributes structure. 1604 * @param [in] socket 1605 * CPU socket ID for allocations. 1606 * 1607 * @return 1608 * The DevX object created, NULL otherwise and rte_errno is set. 1609 */ 1610 struct mlx5_devx_obj * 1611 mlx5_devx_cmd_create_rmp(void *ctx, 1612 struct mlx5_devx_create_rmp_attr *rmp_attr, 1613 int socket) 1614 { 1615 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0}; 1616 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0}; 1617 void *rmp_ctx, *wq_ctx; 1618 struct mlx5_devx_wq_attr *wq_attr; 1619 struct mlx5_devx_obj *rmp = NULL; 1620 1621 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket); 1622 if (!rmp) { 1623 DRV_LOG(ERR, "Failed to allocate RMP data"); 1624 rte_errno = ENOMEM; 1625 return NULL; 1626 } 1627 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP); 1628 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx); 1629 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state); 1630 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe, 1631 rmp_attr->basic_cyclic_rcv_wqe); 1632 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq); 1633 wq_attr = &rmp_attr->wq_attr; 1634 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1635 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1636 sizeof(out)); 1637 if (!rmp->obj) { 1638 DEVX_DRV_LOG(ERR, out, "create RMP", NULL, 0); 1639 mlx5_free(rmp); 1640 return NULL; 1641 } 1642 rmp->id = MLX5_GET(create_rmp_out, out, rmpn); 1643 return rmp; 1644 } 1645 1646 /* 1647 * Create TIR using DevX API. 1648 * 1649 * @param[in] ctx 1650 * Context returned from mlx5 open_device() glue function. 1651 * @param [in] tir_attr 1652 * Pointer to TIR attributes structure. 1653 * 1654 * @return 1655 * The DevX object created, NULL otherwise and rte_errno is set. 1656 */ 1657 struct mlx5_devx_obj * 1658 mlx5_devx_cmd_create_tir(void *ctx, 1659 struct mlx5_devx_tir_attr *tir_attr) 1660 { 1661 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1662 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1663 void *tir_ctx, *outer, *inner, *rss_key; 1664 struct mlx5_devx_obj *tir = NULL; 1665 1666 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1667 if (!tir) { 1668 DRV_LOG(ERR, "Failed to allocate TIR data"); 1669 rte_errno = ENOMEM; 1670 return NULL; 1671 } 1672 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1673 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1674 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1675 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1676 tir_attr->lro_timeout_period_usecs); 1677 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1678 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1679 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1680 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1681 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1682 tir_attr->tunneled_offload_en); 1683 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1684 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1685 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1686 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1687 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1688 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1689 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1690 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1691 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1692 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1693 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1694 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1695 tir_attr->rx_hash_field_selector_outer.selected_fields); 1696 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1697 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1698 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1699 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1700 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1701 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1702 tir_attr->rx_hash_field_selector_inner.selected_fields); 1703 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1704 out, sizeof(out)); 1705 if (!tir->obj) { 1706 DEVX_DRV_LOG(ERR, out, "create TIR", NULL, 0); 1707 mlx5_free(tir); 1708 return NULL; 1709 } 1710 tir->id = MLX5_GET(create_tir_out, out, tirn); 1711 return tir; 1712 } 1713 1714 /** 1715 * Modify TIR using DevX API. 1716 * 1717 * @param[in] tir 1718 * Pointer to TIR DevX object structure. 1719 * @param [in] modify_tir_attr 1720 * Pointer to TIR modification attributes structure. 1721 * 1722 * @return 1723 * 0 on success, a negative errno value otherwise and rte_errno is set. 1724 */ 1725 int 1726 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1727 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1728 { 1729 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1730 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1731 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1732 void *tir_ctx; 1733 int ret; 1734 1735 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1736 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1737 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1738 modify_tir_attr->modify_bitmask); 1739 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1740 if (modify_tir_attr->modify_bitmask & 1741 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1742 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1743 tir_attr->lro_timeout_period_usecs); 1744 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1745 tir_attr->lro_enable_mask); 1746 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1747 tir_attr->lro_max_msg_sz); 1748 } 1749 if (modify_tir_attr->modify_bitmask & 1750 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1751 MLX5_SET(tirc, tir_ctx, indirect_table, 1752 tir_attr->indirect_table); 1753 if (modify_tir_attr->modify_bitmask & 1754 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1755 int i; 1756 void *outer, *inner; 1757 1758 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1759 tir_attr->rx_hash_symmetric); 1760 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1761 for (i = 0; i < 10; i++) { 1762 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1763 tir_attr->rx_hash_toeplitz_key[i]); 1764 } 1765 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1766 rx_hash_field_selector_outer); 1767 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1768 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1769 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1770 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1771 MLX5_SET 1772 (rx_hash_field_select, outer, selected_fields, 1773 tir_attr->rx_hash_field_selector_outer.selected_fields); 1774 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1775 rx_hash_field_selector_inner); 1776 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1777 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1778 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1779 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1780 MLX5_SET 1781 (rx_hash_field_select, inner, selected_fields, 1782 tir_attr->rx_hash_field_selector_inner.selected_fields); 1783 } 1784 if (modify_tir_attr->modify_bitmask & 1785 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1786 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1787 } 1788 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1789 out, sizeof(out)); 1790 if (ret) { 1791 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1792 rte_errno = errno; 1793 return -errno; 1794 } 1795 return ret; 1796 } 1797 1798 /** 1799 * Create RQT using DevX API. 1800 * 1801 * @param[in] ctx 1802 * Context returned from mlx5 open_device() glue function. 1803 * @param [in] rqt_attr 1804 * Pointer to RQT attributes structure. 1805 * 1806 * @return 1807 * The DevX object created, NULL otherwise and rte_errno is set. 1808 */ 1809 struct mlx5_devx_obj * 1810 mlx5_devx_cmd_create_rqt(void *ctx, 1811 struct mlx5_devx_rqt_attr *rqt_attr) 1812 { 1813 uint32_t *in = NULL; 1814 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1815 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1816 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1817 void *rqt_ctx; 1818 struct mlx5_devx_obj *rqt = NULL; 1819 int i; 1820 1821 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1822 if (!in) { 1823 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1824 rte_errno = ENOMEM; 1825 return NULL; 1826 } 1827 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1828 if (!rqt) { 1829 DRV_LOG(ERR, "Failed to allocate RQT data"); 1830 rte_errno = ENOMEM; 1831 mlx5_free(in); 1832 return NULL; 1833 } 1834 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1835 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1836 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1837 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1838 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1839 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1840 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1841 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1842 mlx5_free(in); 1843 if (!rqt->obj) { 1844 DEVX_DRV_LOG(ERR, out, "create RQT", NULL, 0); 1845 mlx5_free(rqt); 1846 return NULL; 1847 } 1848 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1849 return rqt; 1850 } 1851 1852 /** 1853 * Modify RQT using DevX API. 1854 * 1855 * @param[in] rqt 1856 * Pointer to RQT DevX object structure. 1857 * @param [in] rqt_attr 1858 * Pointer to RQT attributes structure. 1859 * 1860 * @return 1861 * 0 on success, a negative errno value otherwise and rte_errno is set. 1862 */ 1863 int 1864 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1865 struct mlx5_devx_rqt_attr *rqt_attr) 1866 { 1867 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1868 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1869 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1870 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1871 void *rqt_ctx; 1872 int i; 1873 int ret; 1874 1875 if (!in) { 1876 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1877 rte_errno = ENOMEM; 1878 return -ENOMEM; 1879 } 1880 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1881 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1882 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1883 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1884 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1885 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1886 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1887 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1888 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1889 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1890 mlx5_free(in); 1891 if (ret) { 1892 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1893 rte_errno = errno; 1894 return -rte_errno; 1895 } 1896 return ret; 1897 } 1898 1899 /** 1900 * Create SQ using DevX API. 1901 * 1902 * @param[in] ctx 1903 * Context returned from mlx5 open_device() glue function. 1904 * @param [in] sq_attr 1905 * Pointer to SQ attributes structure. 1906 * @param [in] socket 1907 * CPU socket ID for allocations. 1908 * 1909 * @return 1910 * The DevX object created, NULL otherwise and rte_errno is set. 1911 **/ 1912 struct mlx5_devx_obj * 1913 mlx5_devx_cmd_create_sq(void *ctx, 1914 struct mlx5_devx_create_sq_attr *sq_attr) 1915 { 1916 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1917 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1918 void *sq_ctx; 1919 void *wq_ctx; 1920 struct mlx5_devx_wq_attr *wq_attr; 1921 struct mlx5_devx_obj *sq = NULL; 1922 1923 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1924 if (!sq) { 1925 DRV_LOG(ERR, "Failed to allocate SQ data"); 1926 rte_errno = ENOMEM; 1927 return NULL; 1928 } 1929 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1930 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1931 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1932 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1933 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1934 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1935 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1936 sq_attr->allow_multi_pkt_send_wqe); 1937 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1938 sq_attr->min_wqe_inline_mode); 1939 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1940 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1941 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1942 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1943 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1944 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1945 MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type); 1946 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1947 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1948 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1949 sq_attr->packet_pacing_rate_limit_index); 1950 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1951 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1952 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1953 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1954 wq_attr = &sq_attr->wq_attr; 1955 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1956 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1957 out, sizeof(out)); 1958 if (!sq->obj) { 1959 DEVX_DRV_LOG(ERR, out, "create SQ", NULL, 0); 1960 mlx5_free(sq); 1961 return NULL; 1962 } 1963 sq->id = MLX5_GET(create_sq_out, out, sqn); 1964 return sq; 1965 } 1966 1967 /** 1968 * Modify SQ using DevX API. 1969 * 1970 * @param[in] sq 1971 * Pointer to SQ object structure. 1972 * @param [in] sq_attr 1973 * Pointer to SQ attributes structure. 1974 * 1975 * @return 1976 * 0 on success, a negative errno value otherwise and rte_errno is set. 1977 */ 1978 int 1979 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1980 struct mlx5_devx_modify_sq_attr *sq_attr) 1981 { 1982 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1983 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1984 void *sq_ctx; 1985 int ret; 1986 1987 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1988 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1989 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1990 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1991 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1992 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1993 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1994 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1995 out, sizeof(out)); 1996 if (ret) { 1997 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1998 rte_errno = errno; 1999 return -rte_errno; 2000 } 2001 return ret; 2002 } 2003 2004 /** 2005 * Create TIS using DevX API. 2006 * 2007 * @param[in] ctx 2008 * Context returned from mlx5 open_device() glue function. 2009 * @param [in] tis_attr 2010 * Pointer to TIS attributes structure. 2011 * 2012 * @return 2013 * The DevX object created, NULL otherwise and rte_errno is set. 2014 */ 2015 struct mlx5_devx_obj * 2016 mlx5_devx_cmd_create_tis(void *ctx, 2017 struct mlx5_devx_tis_attr *tis_attr) 2018 { 2019 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 2020 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 2021 struct mlx5_devx_obj *tis = NULL; 2022 void *tis_ctx; 2023 2024 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 2025 if (!tis) { 2026 DRV_LOG(ERR, "Failed to allocate TIS object"); 2027 rte_errno = ENOMEM; 2028 return NULL; 2029 } 2030 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 2031 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 2032 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 2033 tis_attr->strict_lag_tx_port_affinity); 2034 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 2035 tis_attr->lag_tx_port_affinity); 2036 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 2037 MLX5_SET(tisc, tis_ctx, transport_domain, 2038 tis_attr->transport_domain); 2039 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2040 out, sizeof(out)); 2041 if (!tis->obj) { 2042 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 2043 mlx5_free(tis); 2044 return NULL; 2045 } 2046 tis->id = MLX5_GET(create_tis_out, out, tisn); 2047 return tis; 2048 } 2049 2050 /** 2051 * Create transport domain using DevX API. 2052 * 2053 * @param[in] ctx 2054 * Context returned from mlx5 open_device() glue function. 2055 * @return 2056 * The DevX object created, NULL otherwise and rte_errno is set. 2057 */ 2058 struct mlx5_devx_obj * 2059 mlx5_devx_cmd_create_td(void *ctx) 2060 { 2061 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 2062 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 2063 struct mlx5_devx_obj *td = NULL; 2064 2065 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 2066 if (!td) { 2067 DRV_LOG(ERR, "Failed to allocate TD object"); 2068 rte_errno = ENOMEM; 2069 return NULL; 2070 } 2071 MLX5_SET(alloc_transport_domain_in, in, opcode, 2072 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 2073 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2074 out, sizeof(out)); 2075 if (!td->obj) { 2076 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 2077 mlx5_free(td); 2078 return NULL; 2079 } 2080 td->id = MLX5_GET(alloc_transport_domain_out, out, 2081 transport_domain); 2082 return td; 2083 } 2084 2085 /** 2086 * Dump all flows to file. 2087 * 2088 * @param[in] fdb_domain 2089 * FDB domain. 2090 * @param[in] rx_domain 2091 * RX domain. 2092 * @param[in] tx_domain 2093 * TX domain. 2094 * @param[out] file 2095 * Pointer to file stream. 2096 * 2097 * @return 2098 * 0 on success, a negative value otherwise. 2099 */ 2100 int 2101 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 2102 void *rx_domain __rte_unused, 2103 void *tx_domain __rte_unused, FILE *file __rte_unused) 2104 { 2105 int ret = 0; 2106 2107 #ifdef HAVE_MLX5_DR_FLOW_DUMP 2108 if (fdb_domain) { 2109 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 2110 if (ret) 2111 return ret; 2112 } 2113 MLX5_ASSERT(rx_domain); 2114 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 2115 if (ret) 2116 return ret; 2117 MLX5_ASSERT(tx_domain); 2118 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 2119 #else 2120 ret = ENOTSUP; 2121 #endif 2122 return -ret; 2123 } 2124 2125 int 2126 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 2127 FILE *file __rte_unused) 2128 { 2129 int ret = 0; 2130 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 2131 if (rule_info) 2132 ret = mlx5_glue->dr_dump_rule(file, rule_info); 2133 #else 2134 ret = ENOTSUP; 2135 #endif 2136 return -ret; 2137 } 2138 2139 /* 2140 * Create CQ using DevX API. 2141 * 2142 * @param[in] ctx 2143 * Context returned from mlx5 open_device() glue function. 2144 * @param [in] attr 2145 * Pointer to CQ attributes structure. 2146 * 2147 * @return 2148 * The DevX object created, NULL otherwise and rte_errno is set. 2149 */ 2150 struct mlx5_devx_obj * 2151 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 2152 { 2153 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 2154 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 2155 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2156 sizeof(*cq_obj), 2157 0, SOCKET_ID_ANY); 2158 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 2159 2160 if (!cq_obj) { 2161 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 2162 rte_errno = ENOMEM; 2163 return NULL; 2164 } 2165 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 2166 if (attr->db_umem_valid) { 2167 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 2168 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 2169 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 2170 } else { 2171 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 2172 } 2173 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 2174 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 2175 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 2176 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 2177 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 2178 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2179 MLX5_SET(cqc, cqctx, log_page_size, 2180 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2181 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 2182 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 2183 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 2184 MLX5_SET(cqc, cqctx, cqe_comp_layout, !!attr->cqe_comp_layout); 2185 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 2186 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 2187 attr->mini_cqe_res_format_ext); 2188 if (attr->q_umem_valid) { 2189 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 2190 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 2191 MLX5_SET64(create_cq_in, in, cq_umem_offset, 2192 attr->q_umem_offset); 2193 } 2194 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2195 sizeof(out)); 2196 if (!cq_obj->obj) { 2197 DEVX_DRV_LOG(ERR, out, "create CQ", NULL, 0); 2198 mlx5_free(cq_obj); 2199 return NULL; 2200 } 2201 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 2202 return cq_obj; 2203 } 2204 2205 /** 2206 * Create VIRTQ using DevX API. 2207 * 2208 * @param[in] ctx 2209 * Context returned from mlx5 open_device() glue function. 2210 * @param [in] attr 2211 * Pointer to VIRTQ attributes structure. 2212 * 2213 * @return 2214 * The DevX object created, NULL otherwise and rte_errno is set. 2215 */ 2216 struct mlx5_devx_obj * 2217 mlx5_devx_cmd_create_virtq(void *ctx, 2218 struct mlx5_devx_virtq_attr *attr) 2219 { 2220 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2221 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2222 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2223 sizeof(*virtq_obj), 2224 0, SOCKET_ID_ANY); 2225 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2226 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2227 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2228 2229 if (!virtq_obj) { 2230 DRV_LOG(ERR, "Failed to allocate virtq data."); 2231 rte_errno = ENOMEM; 2232 return NULL; 2233 } 2234 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2235 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2236 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2237 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2238 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2239 attr->hw_available_index); 2240 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 2241 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2242 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2243 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2244 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2245 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2246 attr->virtio_version_1_0); 2247 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2248 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2249 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2250 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2251 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 2252 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2253 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 2254 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2255 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 2256 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 2257 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 2258 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 2259 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 2260 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 2261 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 2262 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 2263 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 2264 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 2265 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 2266 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 2267 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 2268 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 2269 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 2270 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2271 sizeof(out)); 2272 if (!virtq_obj->obj) { 2273 DEVX_DRV_LOG(ERR, out, "create VIRTQ", NULL, 0); 2274 mlx5_free(virtq_obj); 2275 return NULL; 2276 } 2277 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2278 return virtq_obj; 2279 } 2280 2281 /** 2282 * Modify VIRTQ using DevX API. 2283 * 2284 * @param[in] virtq_obj 2285 * Pointer to virtq object structure. 2286 * @param [in] attr 2287 * Pointer to modify virtq attributes structure. 2288 * 2289 * @return 2290 * 0 on success, a negative errno value otherwise and rte_errno is set. 2291 */ 2292 int 2293 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 2294 struct mlx5_devx_virtq_attr *attr) 2295 { 2296 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2297 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2298 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2299 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2300 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2301 int ret; 2302 2303 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2304 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 2305 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2306 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2307 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2308 MLX5_SET64(virtio_net_q, virtq, modify_field_select, 2309 attr->mod_fields_bitmap); 2310 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2311 if (!attr->mod_fields_bitmap) { 2312 DRV_LOG(ERR, "Failed to modify VIRTQ for no type set."); 2313 rte_errno = EINVAL; 2314 return -rte_errno; 2315 } 2316 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE) 2317 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 2318 if (attr->mod_fields_bitmap & 2319 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) { 2320 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 2321 attr->dirty_bitmap_mkey); 2322 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 2323 attr->dirty_bitmap_addr); 2324 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 2325 attr->dirty_bitmap_size); 2326 } 2327 if (attr->mod_fields_bitmap & 2328 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE) 2329 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 2330 attr->dirty_bitmap_dump_enable); 2331 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) { 2332 MLX5_SET(virtio_q, virtctx, queue_period_mode, 2333 attr->hw_latency_mode); 2334 MLX5_SET(virtio_q, virtctx, queue_period_us, 2335 attr->hw_max_latency_us); 2336 MLX5_SET(virtio_q, virtctx, queue_max_count, 2337 attr->hw_max_pending_comp); 2338 } 2339 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) { 2340 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2341 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2342 MLX5_SET64(virtio_q, virtctx, available_addr, 2343 attr->available_addr); 2344 } 2345 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX) 2346 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2347 attr->hw_available_index); 2348 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX) 2349 MLX5_SET16(virtio_net_q, virtq, hw_used_index, 2350 attr->hw_used_index); 2351 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE) 2352 MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type); 2353 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0) 2354 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2355 attr->virtio_version_1_0); 2356 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY) 2357 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2358 if (attr->mod_fields_bitmap & 2359 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) { 2360 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2361 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2362 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2363 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2364 } 2365 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) { 2366 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2367 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2368 } 2369 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 2370 out, sizeof(out)); 2371 if (ret) { 2372 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2373 rte_errno = errno; 2374 return -rte_errno; 2375 } 2376 return ret; 2377 } 2378 2379 /** 2380 * Query VIRTQ using DevX API. 2381 * 2382 * @param[in] virtq_obj 2383 * Pointer to virtq object structure. 2384 * @param [in/out] attr 2385 * Pointer to virtq attributes structure. 2386 * 2387 * @return 2388 * 0 on success, a negative errno value otherwise and rte_errno is set. 2389 */ 2390 int 2391 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 2392 struct mlx5_devx_virtq_attr *attr) 2393 { 2394 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2395 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 2396 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 2397 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 2398 int ret; 2399 2400 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2401 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2402 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2403 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2404 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2405 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2406 out, sizeof(out)); 2407 if (ret) { 2408 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2409 rte_errno = errno; 2410 return -errno; 2411 } 2412 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2413 hw_available_index); 2414 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2415 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2416 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2417 virtio_q_context.error_type); 2418 return ret; 2419 } 2420 2421 /** 2422 * Create QP using DevX API. 2423 * 2424 * @param[in] ctx 2425 * Context returned from mlx5 open_device() glue function. 2426 * @param [in] attr 2427 * Pointer to QP attributes structure. 2428 * 2429 * @return 2430 * The DevX object created, NULL otherwise and rte_errno is set. 2431 */ 2432 struct mlx5_devx_obj * 2433 mlx5_devx_cmd_create_qp(void *ctx, 2434 struct mlx5_devx_qp_attr *attr) 2435 { 2436 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2437 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2438 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2439 sizeof(*qp_obj), 2440 0, SOCKET_ID_ANY); 2441 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2442 2443 if (!qp_obj) { 2444 DRV_LOG(ERR, "Failed to allocate QP data."); 2445 rte_errno = ENOMEM; 2446 return NULL; 2447 } 2448 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2449 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2450 MLX5_SET(qpc, qpc, pd, attr->pd); 2451 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2452 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2453 if (attr->uar_index) { 2454 if (attr->mmo) { 2455 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2456 in, qpc_extension_and_pas_list); 2457 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2458 qpc_ext_and_pas_list, qpc_data_extension); 2459 2460 MLX5_SET(create_qp_in, in, qpc_ext, 1); 2461 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2462 } 2463 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2464 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2465 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2466 MLX5_SET(qpc, qpc, log_page_size, 2467 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2468 if (attr->num_of_send_wqbbs) { 2469 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs)); 2470 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2471 MLX5_SET(qpc, qpc, log_sq_size, 2472 rte_log2_u32(attr->num_of_send_wqbbs)); 2473 } else { 2474 MLX5_SET(qpc, qpc, no_sq, 1); 2475 } 2476 if (attr->num_of_receive_wqes) { 2477 MLX5_ASSERT(RTE_IS_POWER_OF_2( 2478 attr->num_of_receive_wqes)); 2479 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2480 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2481 MLX5_LOG_RQ_STRIDE_SHIFT); 2482 MLX5_SET(qpc, qpc, log_rq_size, 2483 rte_log2_u32(attr->num_of_receive_wqes)); 2484 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2485 } else { 2486 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2487 } 2488 if (attr->dbr_umem_valid) { 2489 MLX5_SET(qpc, qpc, dbr_umem_valid, 2490 attr->dbr_umem_valid); 2491 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2492 } 2493 if (attr->cd_master) 2494 MLX5_SET(qpc, qpc, cd_master, attr->cd_master); 2495 if (attr->cd_slave_send) 2496 MLX5_SET(qpc, qpc, cd_slave_send, attr->cd_slave_send); 2497 if (attr->cd_slave_recv) 2498 MLX5_SET(qpc, qpc, cd_slave_receive, attr->cd_slave_recv); 2499 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2500 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2501 attr->wq_umem_offset); 2502 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2503 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2504 } else { 2505 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2506 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2507 MLX5_SET(qpc, qpc, no_sq, 1); 2508 } 2509 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2510 sizeof(out)); 2511 if (!qp_obj->obj) { 2512 DEVX_DRV_LOG(ERR, out, "create QP", NULL, 0); 2513 mlx5_free(qp_obj); 2514 return NULL; 2515 } 2516 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2517 return qp_obj; 2518 } 2519 2520 /** 2521 * Modify QP using DevX API. 2522 * Currently supports only force loop-back QP. 2523 * 2524 * @param[in] qp 2525 * Pointer to QP object structure. 2526 * @param [in] qp_st_mod_op 2527 * The QP state modification operation. 2528 * @param [in] remote_qp_id 2529 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2530 * 2531 * @return 2532 * 0 on success, a negative errno value otherwise and rte_errno is set. 2533 */ 2534 int 2535 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2536 uint32_t remote_qp_id) 2537 { 2538 union { 2539 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2540 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2541 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2542 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)]; 2543 } in; 2544 union { 2545 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2546 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2547 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2548 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)]; 2549 } out; 2550 void *qpc; 2551 int ret; 2552 unsigned int inlen; 2553 unsigned int outlen; 2554 2555 memset(&in, 0, sizeof(in)); 2556 memset(&out, 0, sizeof(out)); 2557 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2558 switch (qp_st_mod_op) { 2559 case MLX5_CMD_OP_RST2INIT_QP: 2560 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2561 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2562 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2563 MLX5_SET(qpc, qpc, rre, 1); 2564 MLX5_SET(qpc, qpc, rwe, 1); 2565 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2566 inlen = sizeof(in.rst2init); 2567 outlen = sizeof(out.rst2init); 2568 break; 2569 case MLX5_CMD_OP_INIT2RTR_QP: 2570 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2571 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2572 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2573 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2574 MLX5_SET(qpc, qpc, mtu, 1); 2575 MLX5_SET(qpc, qpc, log_msg_max, 30); 2576 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2577 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2578 inlen = sizeof(in.init2rtr); 2579 outlen = sizeof(out.init2rtr); 2580 break; 2581 case MLX5_CMD_OP_RTR2RTS_QP: 2582 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2583 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2584 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16); 2585 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2586 MLX5_SET(qpc, qpc, retry_count, 7); 2587 MLX5_SET(qpc, qpc, rnr_retry, 7); 2588 inlen = sizeof(in.rtr2rts); 2589 outlen = sizeof(out.rtr2rts); 2590 break; 2591 case MLX5_CMD_OP_QP_2RST: 2592 MLX5_SET(2rst_qp_in, &in, qpn, qp->id); 2593 inlen = sizeof(in.qp2rst); 2594 outlen = sizeof(out.qp2rst); 2595 break; 2596 default: 2597 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2598 qp_st_mod_op); 2599 rte_errno = EINVAL; 2600 return -rte_errno; 2601 } 2602 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2603 if (ret) { 2604 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2605 rte_errno = errno; 2606 return -rte_errno; 2607 } 2608 return ret; 2609 } 2610 2611 struct mlx5_devx_obj * 2612 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2613 { 2614 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2615 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2616 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2617 sizeof(*couners_obj), 0, 2618 SOCKET_ID_ANY); 2619 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2620 2621 if (!couners_obj) { 2622 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2623 rte_errno = ENOMEM; 2624 return NULL; 2625 } 2626 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2627 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2628 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2629 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2630 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2631 sizeof(out)); 2632 if (!couners_obj->obj) { 2633 DEVX_DRV_LOG(ERR, out, "create virtio queue counters Obj", NULL, 2634 0); 2635 mlx5_free(couners_obj); 2636 return NULL; 2637 } 2638 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2639 return couners_obj; 2640 } 2641 2642 int 2643 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2644 struct mlx5_devx_virtio_q_couners_attr *attr) 2645 { 2646 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2647 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2648 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2649 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2650 virtio_q_counters); 2651 int ret; 2652 2653 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2654 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2655 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2656 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2657 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2658 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2659 sizeof(out)); 2660 if (ret) { 2661 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2662 rte_errno = errno; 2663 return -errno; 2664 } 2665 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2666 received_desc); 2667 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2668 completed_desc); 2669 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2670 error_cqes); 2671 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2672 bad_desc_errors); 2673 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2674 exceed_max_chain); 2675 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2676 invalid_buffer); 2677 return ret; 2678 } 2679 2680 /** 2681 * Create general object of type FLOW_HIT_ASO using DevX API. 2682 * 2683 * @param[in] ctx 2684 * Context returned from mlx5 open_device() glue function. 2685 * @param [in] pd 2686 * PD value to associate the FLOW_HIT_ASO object with. 2687 * 2688 * @return 2689 * The DevX object created, NULL otherwise and rte_errno is set. 2690 */ 2691 struct mlx5_devx_obj * 2692 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2693 { 2694 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2695 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2696 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2697 void *ptr = NULL; 2698 2699 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2700 0, SOCKET_ID_ANY); 2701 if (!flow_hit_aso_obj) { 2702 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2703 rte_errno = ENOMEM; 2704 return NULL; 2705 } 2706 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2707 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2708 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2709 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2710 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2711 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2712 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2713 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2714 out, sizeof(out)); 2715 if (!flow_hit_aso_obj->obj) { 2716 DEVX_DRV_LOG(ERR, out, "create FLOW_HIT_ASO", NULL, 0); 2717 mlx5_free(flow_hit_aso_obj); 2718 return NULL; 2719 } 2720 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2721 return flow_hit_aso_obj; 2722 } 2723 2724 /* 2725 * Create PD using DevX API. 2726 * 2727 * @param[in] ctx 2728 * Context returned from mlx5 open_device() glue function. 2729 * 2730 * @return 2731 * The DevX object created, NULL otherwise and rte_errno is set. 2732 */ 2733 struct mlx5_devx_obj * 2734 mlx5_devx_cmd_alloc_pd(void *ctx) 2735 { 2736 struct mlx5_devx_obj *ppd = 2737 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2738 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2739 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2740 2741 if (!ppd) { 2742 DRV_LOG(ERR, "Failed to allocate PD data."); 2743 rte_errno = ENOMEM; 2744 return NULL; 2745 } 2746 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2747 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2748 out, sizeof(out)); 2749 if (!ppd->obj) { 2750 mlx5_free(ppd); 2751 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2752 rte_errno = errno; 2753 return NULL; 2754 } 2755 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2756 return ppd; 2757 } 2758 2759 /** 2760 * Create general object of type FLOW_METER_ASO using DevX API. 2761 * 2762 * @param[in] ctx 2763 * Context returned from mlx5 open_device() glue function. 2764 * @param [in] pd 2765 * PD value to associate the FLOW_METER_ASO object with. 2766 * @param [in] log_obj_size 2767 * log_obj_size define to allocate number of 2 * meters 2768 * in one FLOW_METER_ASO object. 2769 * 2770 * @return 2771 * The DevX object created, NULL otherwise and rte_errno is set. 2772 */ 2773 struct mlx5_devx_obj * 2774 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2775 uint32_t log_obj_size) 2776 { 2777 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2778 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2779 struct mlx5_devx_obj *flow_meter_aso_obj; 2780 void *ptr; 2781 2782 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2783 sizeof(*flow_meter_aso_obj), 2784 0, SOCKET_ID_ANY); 2785 if (!flow_meter_aso_obj) { 2786 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2787 rte_errno = ENOMEM; 2788 return NULL; 2789 } 2790 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2791 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2792 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2793 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2794 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2795 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2796 log_obj_size); 2797 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2798 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2799 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2800 ctx, in, sizeof(in), 2801 out, sizeof(out)); 2802 if (!flow_meter_aso_obj->obj) { 2803 DEVX_DRV_LOG(ERR, out, "create FLOW_METTER_ASO", NULL, 0); 2804 mlx5_free(flow_meter_aso_obj); 2805 return NULL; 2806 } 2807 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2808 out, obj_id); 2809 return flow_meter_aso_obj; 2810 } 2811 2812 /* 2813 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2814 * 2815 * @param[in] ctx 2816 * Context returned from mlx5 open_device() glue function. 2817 * @param [in] pd 2818 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2819 * @param [in] log_obj_size 2820 * log_obj_size to allocate its power of 2 * objects 2821 * in one CONN_TRACK_OFFLOAD bulk allocation. 2822 * 2823 * @return 2824 * The DevX object created, NULL otherwise and rte_errno is set. 2825 */ 2826 struct mlx5_devx_obj * 2827 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2828 uint32_t log_obj_size) 2829 { 2830 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2831 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2832 struct mlx5_devx_obj *ct_aso_obj; 2833 void *ptr; 2834 2835 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2836 0, SOCKET_ID_ANY); 2837 if (!ct_aso_obj) { 2838 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2839 rte_errno = ENOMEM; 2840 return NULL; 2841 } 2842 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2843 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2844 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2845 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2846 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2847 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2848 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2849 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2850 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2851 out, sizeof(out)); 2852 if (!ct_aso_obj->obj) { 2853 DEVX_DRV_LOG(ERR, out, "create CONN_TRACK_OFFLOAD", NULL, 0); 2854 mlx5_free(ct_aso_obj); 2855 return NULL; 2856 } 2857 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2858 return ct_aso_obj; 2859 } 2860 2861 /** 2862 * Create general object of type GENEVE TLV option using DevX API. 2863 * 2864 * @param[in] ctx 2865 * Context returned from mlx5 open_device() glue function. 2866 * @param[in] attr 2867 * Pointer to GENEVE TLV option attributes structure. 2868 * 2869 * @return 2870 * The DevX object created, NULL otherwise and rte_errno is set. 2871 */ 2872 struct mlx5_devx_obj * 2873 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2874 struct mlx5_devx_geneve_tlv_option_attr *attr) 2875 { 2876 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2877 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2878 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2879 sizeof(*geneve_tlv_opt_obj), 2880 0, SOCKET_ID_ANY); 2881 2882 if (!geneve_tlv_opt_obj) { 2883 DRV_LOG(ERR, "Failed to allocate GENEVE TLV option object."); 2884 rte_errno = ENOMEM; 2885 return NULL; 2886 } 2887 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2888 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2889 geneve_tlv_opt); 2890 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2891 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2892 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2893 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2894 MLX5_SET(geneve_tlv_option, opt, option_type, attr->option_type); 2895 MLX5_SET(geneve_tlv_option, opt, option_data_length, 2896 attr->option_data_len); 2897 if (attr->option_class_ignore) 2898 MLX5_SET(geneve_tlv_option, opt, option_class_ignore, 2899 attr->option_class_ignore); 2900 else 2901 MLX5_SET(geneve_tlv_option, opt, option_class, 2902 rte_be_to_cpu_16(attr->option_class)); 2903 if (attr->offset_valid) { 2904 MLX5_SET(geneve_tlv_option, opt, sample_offset_valid, 2905 attr->offset_valid); 2906 MLX5_SET(geneve_tlv_option, opt, sample_offset, 2907 attr->sample_offset); 2908 } 2909 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2910 sizeof(in), out, 2911 sizeof(out)); 2912 if (!geneve_tlv_opt_obj->obj) { 2913 DEVX_DRV_LOG(ERR, out, "create GENEVE TLV option", NULL, 0); 2914 mlx5_free(geneve_tlv_opt_obj); 2915 return NULL; 2916 } 2917 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2918 return geneve_tlv_opt_obj; 2919 } 2920 2921 /** 2922 * Query GENEVE TLV option using DevX API. 2923 * 2924 * @param[in] ctx 2925 * Context used to create GENEVE TLV option object. 2926 * @param[in] geneve_tlv_opt_obj 2927 * DevX object of the GENEVE TLV option. 2928 * @param[out] attr 2929 * Pointer to match sample info attributes structure. 2930 * 2931 * @return 2932 * 0 on success, a negative errno otherwise and rte_errno is set. 2933 */ 2934 int 2935 mlx5_devx_cmd_query_geneve_tlv_option(void *ctx, 2936 struct mlx5_devx_obj *geneve_tlv_opt_obj, 2937 struct mlx5_devx_match_sample_info_query_attr *attr) 2938 { 2939 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2940 uint32_t out[MLX5_ST_SZ_DW(query_geneve_tlv_option_out)] = {0}; 2941 void *hdr = MLX5_ADDR_OF(query_geneve_tlv_option_out, in, hdr); 2942 void *opt = MLX5_ADDR_OF(query_geneve_tlv_option_out, out, 2943 geneve_tlv_opt); 2944 int ret; 2945 2946 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2947 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2948 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2949 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2950 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, geneve_tlv_opt_obj->id); 2951 /* Call first query to get sample handle. */ 2952 ret = mlx5_glue->devx_obj_query(geneve_tlv_opt_obj->obj, in, sizeof(in), 2953 out, sizeof(out)); 2954 if (ret) { 2955 DRV_LOG(ERR, "Failed to query GENEVE TLV option using DevX."); 2956 rte_errno = errno; 2957 return -errno; 2958 } 2959 /* Call second query to get sample information. */ 2960 if (MLX5_GET(geneve_tlv_option, opt, sample_id_valid)) { 2961 uint32_t sample_id = MLX5_GET(geneve_tlv_option, opt, 2962 geneve_sample_field_id); 2963 2964 return mlx5_devx_cmd_match_sample_info_query(ctx, sample_id, 2965 attr); 2966 } 2967 DRV_LOG(DEBUG, "GENEVE TLV option sample isn't valid."); 2968 return 0; 2969 } 2970 2971 int 2972 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2973 { 2974 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2975 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2976 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2977 int rc; 2978 void *rq_ctx; 2979 2980 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2981 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2982 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2983 if (rc) { 2984 rte_errno = errno; 2985 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2986 "rc = %d, errno = %d.", rc, errno); 2987 return -rc; 2988 }; 2989 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2990 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2991 return 0; 2992 #else 2993 (void)wq; 2994 (void)counter_set_id; 2995 return -ENOTSUP; 2996 #endif 2997 } 2998 2999 /* 3000 * Allocate queue counters via devx interface. 3001 * 3002 * @param[in] ctx 3003 * Context returned from mlx5 open_device() glue function. 3004 * 3005 * @return 3006 * Pointer to counter object on success, a NULL value otherwise and 3007 * rte_errno is set. 3008 */ 3009 struct mlx5_devx_obj * 3010 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 3011 { 3012 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 3013 SOCKET_ID_ANY); 3014 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 3015 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 3016 3017 if (!dcs) { 3018 rte_errno = ENOMEM; 3019 return NULL; 3020 } 3021 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 3022 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 3023 sizeof(out)); 3024 if (!dcs->obj) { 3025 DEVX_DRV_LOG(DEBUG, out, "create q counter set", NULL, 0); 3026 mlx5_free(dcs); 3027 return NULL; 3028 } 3029 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 3030 return dcs; 3031 } 3032 3033 /** 3034 * Query queue counters values. 3035 * 3036 * @param[in] dcs 3037 * devx object of the queue counter set. 3038 * @param[in] clear 3039 * Whether hardware should clear the counters after the query or not. 3040 * @param[out] out_of_buffers 3041 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 3042 * 3043 * @return 3044 * 0 on success, a negative value otherwise. 3045 */ 3046 int 3047 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 3048 uint32_t *out_of_buffers) 3049 { 3050 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 3051 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 3052 int rc; 3053 3054 MLX5_SET(query_q_counter_in, in, opcode, 3055 MLX5_CMD_OP_QUERY_Q_COUNTER); 3056 MLX5_SET(query_q_counter_in, in, op_mod, 0); 3057 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 3058 MLX5_SET(query_q_counter_in, in, clear, !!clear); 3059 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 3060 sizeof(out)); 3061 if (rc) { 3062 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 3063 rte_errno = rc; 3064 return -rc; 3065 } 3066 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 3067 return 0; 3068 } 3069 3070 /** 3071 * Create general object of type DEK using DevX API. 3072 * 3073 * @param[in] ctx 3074 * Context returned from mlx5 open_device() glue function. 3075 * @param [in] attr 3076 * Pointer to DEK attributes structure. 3077 * 3078 * @return 3079 * The DevX object created, NULL otherwise and rte_errno is set. 3080 */ 3081 struct mlx5_devx_obj * 3082 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 3083 { 3084 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 3085 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3086 struct mlx5_devx_obj *dek_obj = NULL; 3087 void *ptr = NULL, *key_addr = NULL; 3088 3089 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 3090 0, SOCKET_ID_ANY); 3091 if (dek_obj == NULL) { 3092 DRV_LOG(ERR, "Failed to allocate DEK object data"); 3093 rte_errno = ENOMEM; 3094 return NULL; 3095 } 3096 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 3097 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3098 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3099 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3100 MLX5_GENERAL_OBJ_TYPE_DEK); 3101 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 3102 MLX5_SET(dek, ptr, key_size, attr->key_size); 3103 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 3104 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 3105 MLX5_SET(dek, ptr, pd, attr->pd); 3106 MLX5_SET64(dek, ptr, opaque, attr->opaque); 3107 key_addr = MLX5_ADDR_OF(dek, ptr, key); 3108 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 3109 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3110 out, sizeof(out)); 3111 if (dek_obj->obj == NULL) { 3112 DEVX_DRV_LOG(ERR, out, "create DEK", NULL, 0); 3113 mlx5_free(dek_obj); 3114 return NULL; 3115 } 3116 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3117 return dek_obj; 3118 } 3119 3120 /** 3121 * Create general object of type IMPORT_KEK using DevX API. 3122 * 3123 * @param[in] ctx 3124 * Context returned from mlx5 open_device() glue function. 3125 * @param [in] attr 3126 * Pointer to IMPORT_KEK attributes structure. 3127 * 3128 * @return 3129 * The DevX object created, NULL otherwise and rte_errno is set. 3130 */ 3131 struct mlx5_devx_obj * 3132 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 3133 struct mlx5_devx_import_kek_attr *attr) 3134 { 3135 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 3136 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3137 struct mlx5_devx_obj *import_kek_obj = NULL; 3138 void *ptr = NULL, *key_addr = NULL; 3139 3140 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 3141 0, SOCKET_ID_ANY); 3142 if (import_kek_obj == NULL) { 3143 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 3144 rte_errno = ENOMEM; 3145 return NULL; 3146 } 3147 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 3148 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3149 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3150 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3151 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 3152 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 3153 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 3154 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 3155 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 3156 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3157 out, sizeof(out)); 3158 if (import_kek_obj->obj == NULL) { 3159 DEVX_DRV_LOG(ERR, out, "create IMPORT_KEK", NULL, 0); 3160 mlx5_free(import_kek_obj); 3161 return NULL; 3162 } 3163 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3164 return import_kek_obj; 3165 } 3166 3167 /** 3168 * Create general object of type CREDENTIAL using DevX API. 3169 * 3170 * @param[in] ctx 3171 * Context returned from mlx5 open_device() glue function. 3172 * @param [in] attr 3173 * Pointer to CREDENTIAL attributes structure. 3174 * 3175 * @return 3176 * The DevX object created, NULL otherwise and rte_errno is set. 3177 */ 3178 struct mlx5_devx_obj * 3179 mlx5_devx_cmd_create_credential_obj(void *ctx, 3180 struct mlx5_devx_credential_attr *attr) 3181 { 3182 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 3183 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3184 struct mlx5_devx_obj *credential_obj = NULL; 3185 void *ptr = NULL, *credential_addr = NULL; 3186 3187 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 3188 0, SOCKET_ID_ANY); 3189 if (credential_obj == NULL) { 3190 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 3191 rte_errno = ENOMEM; 3192 return NULL; 3193 } 3194 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 3195 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3196 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3197 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3198 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 3199 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 3200 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 3201 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 3202 memcpy(credential_addr, (void *)(attr->credential), 3203 MLX5_CRYPTO_CREDENTIAL_SIZE); 3204 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3205 out, sizeof(out)); 3206 if (credential_obj->obj == NULL) { 3207 DEVX_DRV_LOG(ERR, out, "create CREDENTIAL", NULL, 0); 3208 mlx5_free(credential_obj); 3209 return NULL; 3210 } 3211 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3212 return credential_obj; 3213 } 3214 3215 /** 3216 * Create general object of type CRYPTO_LOGIN using DevX API. 3217 * 3218 * @param[in] ctx 3219 * Context returned from mlx5 open_device() glue function. 3220 * @param [in] attr 3221 * Pointer to CRYPTO_LOGIN attributes structure. 3222 * 3223 * @return 3224 * The DevX object created, NULL otherwise and rte_errno is set. 3225 */ 3226 struct mlx5_devx_obj * 3227 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 3228 struct mlx5_devx_crypto_login_attr *attr) 3229 { 3230 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 3231 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3232 struct mlx5_devx_obj *crypto_login_obj = NULL; 3233 void *ptr = NULL, *credential_addr = NULL; 3234 3235 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 3236 0, SOCKET_ID_ANY); 3237 if (crypto_login_obj == NULL) { 3238 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 3239 rte_errno = ENOMEM; 3240 return NULL; 3241 } 3242 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 3243 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3244 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3245 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3246 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 3247 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 3248 MLX5_SET(crypto_login, ptr, credential_pointer, 3249 attr->credential_pointer); 3250 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 3251 attr->session_import_kek_ptr); 3252 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 3253 memcpy(credential_addr, (void *)(attr->credential), 3254 MLX5_CRYPTO_CREDENTIAL_SIZE); 3255 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3256 out, sizeof(out)); 3257 if (crypto_login_obj->obj == NULL) { 3258 DEVX_DRV_LOG(ERR, out, "create CRYPTO_LOGIN", NULL, 0); 3259 mlx5_free(crypto_login_obj); 3260 return NULL; 3261 } 3262 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3263 return crypto_login_obj; 3264 } 3265 3266 /** 3267 * Query LAG context. 3268 * 3269 * @param[in] ctx 3270 * Pointer to ibv_context, returned from mlx5dv_open_device. 3271 * @param[out] lag_ctx 3272 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 3273 * 3274 * @return 3275 * 0 on success, a negative value otherwise. 3276 */ 3277 int 3278 mlx5_devx_cmd_query_lag(void *ctx, 3279 struct mlx5_devx_lag_context *lag_ctx) 3280 { 3281 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 3282 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 3283 void *lctx; 3284 int rc; 3285 3286 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 3287 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 3288 if (rc) 3289 goto error; 3290 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 3291 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 3292 fdb_selection_mode); 3293 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 3294 port_select_mode); 3295 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 3296 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 3297 tx_remap_affinity_2); 3298 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 3299 tx_remap_affinity_1); 3300 return 0; 3301 error: 3302 rc = (rc > 0) ? -rc : rc; 3303 return rc; 3304 } 3305