1 // SPDX-License-Identifier: BSD-3-Clause 2 /* Copyright 2018 Mellanox Technologies, Ltd */ 3 4 #include <unistd.h> 5 6 #include <rte_errno.h> 7 #include <rte_malloc.h> 8 #include <rte_eal_paging.h> 9 10 #include "mlx5_prm.h" 11 #include "mlx5_devx_cmds.h" 12 #include "mlx5_common_utils.h" 13 #include "mlx5_malloc.h" 14 15 16 /** 17 * Perform read access to the registers. Reads data from register 18 * and writes ones to the specified buffer. 19 * 20 * @param[in] ctx 21 * Context returned from mlx5 open_device() glue function. 22 * @param[in] reg_id 23 * Register identifier according to the PRM. 24 * @param[in] arg 25 * Register access auxiliary parameter according to the PRM. 26 * @param[out] data 27 * Pointer to the buffer to store read data. 28 * @param[in] dw_cnt 29 * Buffer size in double words. 30 * 31 * @return 32 * 0 on success, a negative value otherwise. 33 */ 34 int 35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 36 uint32_t *data, uint32_t dw_cnt) 37 { 38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 41 int status, rc; 42 43 MLX5_ASSERT(data && dw_cnt); 44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 46 DRV_LOG(ERR, "Not enough buffer for register read data"); 47 return -1; 48 } 49 MLX5_SET(access_register_in, in, opcode, 50 MLX5_CMD_OP_ACCESS_REGISTER_USER); 51 MLX5_SET(access_register_in, in, op_mod, 52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 53 MLX5_SET(access_register_in, in, register_id, reg_id); 54 MLX5_SET(access_register_in, in, argument, arg); 55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 56 MLX5_ST_SZ_DW(access_register_out) * 57 sizeof(uint32_t) + dw_cnt); 58 if (rc) 59 goto error; 60 status = MLX5_GET(access_register_out, out, status); 61 if (status) { 62 int syndrome = MLX5_GET(access_register_out, out, syndrome); 63 64 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, " 65 "status %x, syndrome = %x", 66 reg_id, status, syndrome); 67 return -1; 68 } 69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 70 dw_cnt * sizeof(uint32_t)); 71 return 0; 72 error: 73 rc = (rc > 0) ? -rc : rc; 74 return rc; 75 } 76 77 /** 78 * Allocate flow counters via devx interface. 79 * 80 * @param[in] ctx 81 * Context returned from mlx5 open_device() glue function. 82 * @param dcs 83 * Pointer to counters properties structure to be filled by the routine. 84 * @param bulk_n_128 85 * Bulk counter numbers in 128 counters units. 86 * 87 * @return 88 * Pointer to counter object on success, a negative value otherwise and 89 * rte_errno is set. 90 */ 91 struct mlx5_devx_obj * 92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 93 { 94 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 95 0, SOCKET_ID_ANY); 96 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 97 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 98 99 if (!dcs) { 100 rte_errno = ENOMEM; 101 return NULL; 102 } 103 MLX5_SET(alloc_flow_counter_in, in, opcode, 104 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 105 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 106 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 107 sizeof(in), out, sizeof(out)); 108 if (!dcs->obj) { 109 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 110 rte_errno = errno; 111 mlx5_free(dcs); 112 return NULL; 113 } 114 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 115 return dcs; 116 } 117 118 /** 119 * Query flow counters values. 120 * 121 * @param[in] dcs 122 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 123 * @param[in] clear 124 * Whether hardware should clear the counters after the query or not. 125 * @param[in] n_counters 126 * 0 in case of 1 counter to read, otherwise the counter number to read. 127 * @param pkts 128 * The number of packets that matched the flow. 129 * @param bytes 130 * The number of bytes that matched the flow. 131 * @param mkey 132 * The mkey key for batch query. 133 * @param addr 134 * The address in the mkey range for batch query. 135 * @param cmd_comp 136 * The completion object for asynchronous batch query. 137 * @param async_id 138 * The ID to be returned in the asynchronous batch query response. 139 * 140 * @return 141 * 0 on success, a negative value otherwise. 142 */ 143 int 144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 145 int clear, uint32_t n_counters, 146 uint64_t *pkts, uint64_t *bytes, 147 uint32_t mkey, void *addr, 148 void *cmd_comp, 149 uint64_t async_id) 150 { 151 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 152 MLX5_ST_SZ_BYTES(traffic_counter); 153 uint32_t out[out_len]; 154 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 155 void *stats; 156 int rc; 157 158 MLX5_SET(query_flow_counter_in, in, opcode, 159 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 160 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 161 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 162 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 163 164 if (n_counters) { 165 MLX5_SET(query_flow_counter_in, in, num_of_counters, 166 n_counters); 167 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 168 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 169 MLX5_SET64(query_flow_counter_in, in, address, 170 (uint64_t)(uintptr_t)addr); 171 } 172 if (!cmd_comp) 173 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 174 out_len); 175 else 176 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 177 out_len, async_id, 178 cmd_comp); 179 if (rc) { 180 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 181 rte_errno = rc; 182 return -rc; 183 } 184 if (!n_counters) { 185 stats = MLX5_ADDR_OF(query_flow_counter_out, 186 out, flow_statistics); 187 *pkts = MLX5_GET64(traffic_counter, stats, packets); 188 *bytes = MLX5_GET64(traffic_counter, stats, octets); 189 } 190 return 0; 191 } 192 193 /** 194 * Create a new mkey. 195 * 196 * @param[in] ctx 197 * Context returned from mlx5 open_device() glue function. 198 * @param[in] attr 199 * Attributes of the requested mkey. 200 * 201 * @return 202 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 203 * is set. 204 */ 205 struct mlx5_devx_obj * 206 mlx5_devx_cmd_mkey_create(void *ctx, 207 struct mlx5_devx_mkey_attr *attr) 208 { 209 struct mlx5_klm *klm_array = attr->klm_array; 210 int klm_num = attr->klm_num; 211 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 212 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 213 uint32_t in[in_size_dw]; 214 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 215 void *mkc; 216 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 217 0, SOCKET_ID_ANY); 218 size_t pgsize; 219 uint32_t translation_size; 220 221 if (!mkey) { 222 rte_errno = ENOMEM; 223 return NULL; 224 } 225 memset(in, 0, in_size_dw * 4); 226 pgsize = rte_mem_page_size(); 227 if (pgsize == (size_t)-1) { 228 mlx5_free(mkey); 229 DRV_LOG(ERR, "Failed to get page size"); 230 rte_errno = ENOMEM; 231 return NULL; 232 } 233 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 234 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 235 if (klm_num > 0) { 236 int i; 237 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 238 klm_pas_mtt); 239 translation_size = RTE_ALIGN(klm_num, 4); 240 for (i = 0; i < klm_num; i++) { 241 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 242 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 243 MLX5_SET64(klm, klm, address, klm_array[i].address); 244 klm += MLX5_ST_SZ_BYTES(klm); 245 } 246 for (; i < (int)translation_size; i++) { 247 MLX5_SET(klm, klm, mkey, 0x0); 248 MLX5_SET64(klm, klm, address, 0x0); 249 klm += MLX5_ST_SZ_BYTES(klm); 250 } 251 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 252 MLX5_MKC_ACCESS_MODE_KLM_FBS : 253 MLX5_MKC_ACCESS_MODE_KLM); 254 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 255 } else { 256 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 257 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 258 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 259 } 260 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 261 translation_size); 262 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 263 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 264 MLX5_SET(mkc, mkc, lw, 0x1); 265 MLX5_SET(mkc, mkc, lr, 0x1); 266 MLX5_SET(mkc, mkc, qpn, 0xffffff); 267 MLX5_SET(mkc, mkc, pd, attr->pd); 268 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 269 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 270 MLX5_SET(mkc, mkc, relaxed_ordering_write, 271 attr->relaxed_ordering_write); 272 MLX5_SET(mkc, mkc, relaxed_ordering_read, 273 attr->relaxed_ordering_read); 274 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 275 MLX5_SET64(mkc, mkc, len, attr->size); 276 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 277 sizeof(out)); 278 if (!mkey->obj) { 279 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d\n", 280 klm_num ? "an in" : "a ", errno); 281 rte_errno = errno; 282 mlx5_free(mkey); 283 return NULL; 284 } 285 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 286 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 287 return mkey; 288 } 289 290 /** 291 * Get status of devx command response. 292 * Mainly used for asynchronous commands. 293 * 294 * @param[in] out 295 * The out response buffer. 296 * 297 * @return 298 * 0 on success, non-zero value otherwise. 299 */ 300 int 301 mlx5_devx_get_out_command_status(void *out) 302 { 303 int status; 304 305 if (!out) 306 return -EINVAL; 307 status = MLX5_GET(query_flow_counter_out, out, status); 308 if (status) { 309 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 310 311 DRV_LOG(ERR, "Bad devX status %x, syndrome = %x", status, 312 syndrome); 313 } 314 return status; 315 } 316 317 /** 318 * Destroy any object allocated by a Devx API. 319 * 320 * @param[in] obj 321 * Pointer to a general object. 322 * 323 * @return 324 * 0 on success, a negative value otherwise. 325 */ 326 int 327 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 328 { 329 int ret; 330 331 if (!obj) 332 return 0; 333 ret = mlx5_glue->devx_obj_destroy(obj->obj); 334 mlx5_free(obj); 335 return ret; 336 } 337 338 /** 339 * Query NIC vport context. 340 * Fills minimal inline attribute. 341 * 342 * @param[in] ctx 343 * ibv contexts returned from mlx5dv_open_device. 344 * @param[in] vport 345 * vport index 346 * @param[out] attr 347 * Attributes device values. 348 * 349 * @return 350 * 0 on success, a negative value otherwise. 351 */ 352 static int 353 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 354 unsigned int vport, 355 struct mlx5_hca_attr *attr) 356 { 357 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 358 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 359 void *vctx; 360 int status, syndrome, rc; 361 362 /* Query NIC vport context to determine inline mode. */ 363 MLX5_SET(query_nic_vport_context_in, in, opcode, 364 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 365 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 366 if (vport) 367 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 368 rc = mlx5_glue->devx_general_cmd(ctx, 369 in, sizeof(in), 370 out, sizeof(out)); 371 if (rc) 372 goto error; 373 status = MLX5_GET(query_nic_vport_context_out, out, status); 374 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 375 if (status) { 376 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 377 "status %x, syndrome = %x", 378 status, syndrome); 379 return -1; 380 } 381 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 382 nic_vport_context); 383 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 384 min_wqe_inline_mode); 385 return 0; 386 error: 387 rc = (rc > 0) ? -rc : rc; 388 return rc; 389 } 390 391 /** 392 * Query NIC vDPA attributes. 393 * 394 * @param[in] ctx 395 * Context returned from mlx5 open_device() glue function. 396 * @param[out] vdpa_attr 397 * vDPA Attributes structure to fill. 398 */ 399 static void 400 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 401 struct mlx5_hca_vdpa_attr *vdpa_attr) 402 { 403 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 404 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 405 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 406 int status, syndrome, rc; 407 408 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 409 MLX5_SET(query_hca_cap_in, in, op_mod, 410 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 411 MLX5_HCA_CAP_OPMOD_GET_CUR); 412 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 413 status = MLX5_GET(query_hca_cap_out, out, status); 414 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 415 if (rc || status) { 416 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities," 417 " status %x, syndrome = %x", status, syndrome); 418 vdpa_attr->valid = 0; 419 } else { 420 vdpa_attr->valid = 1; 421 vdpa_attr->desc_tunnel_offload_type = 422 MLX5_GET(virtio_emulation_cap, hcattr, 423 desc_tunnel_offload_type); 424 vdpa_attr->eth_frame_offload_type = 425 MLX5_GET(virtio_emulation_cap, hcattr, 426 eth_frame_offload_type); 427 vdpa_attr->virtio_version_1_0 = 428 MLX5_GET(virtio_emulation_cap, hcattr, 429 virtio_version_1_0); 430 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 431 tso_ipv4); 432 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 433 tso_ipv6); 434 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 435 tx_csum); 436 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 437 rx_csum); 438 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 439 event_mode); 440 vdpa_attr->virtio_queue_type = 441 MLX5_GET(virtio_emulation_cap, hcattr, 442 virtio_queue_type); 443 vdpa_attr->log_doorbell_stride = 444 MLX5_GET(virtio_emulation_cap, hcattr, 445 log_doorbell_stride); 446 vdpa_attr->log_doorbell_bar_size = 447 MLX5_GET(virtio_emulation_cap, hcattr, 448 log_doorbell_bar_size); 449 vdpa_attr->doorbell_bar_offset = 450 MLX5_GET64(virtio_emulation_cap, hcattr, 451 doorbell_bar_offset); 452 vdpa_attr->max_num_virtio_queues = 453 MLX5_GET(virtio_emulation_cap, hcattr, 454 max_num_virtio_queues); 455 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 456 umem_1_buffer_param_a); 457 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 458 umem_1_buffer_param_b); 459 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 460 umem_2_buffer_param_a); 461 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 462 umem_2_buffer_param_b); 463 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 464 umem_3_buffer_param_a); 465 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 466 umem_3_buffer_param_b); 467 } 468 } 469 470 int 471 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 472 uint32_t ids[], uint32_t num) 473 { 474 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 475 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 476 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 477 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 478 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 479 int ret; 480 uint32_t idx = 0; 481 uint32_t i; 482 483 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 484 rte_errno = EINVAL; 485 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 486 return -rte_errno; 487 } 488 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 489 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 490 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 491 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 492 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 493 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 494 out, sizeof(out)); 495 if (ret) { 496 rte_errno = ret; 497 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 498 (void *)flex_obj); 499 return -rte_errno; 500 } 501 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 502 void *s_off = (void *)((char *)sample + i * 503 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 504 uint32_t en; 505 506 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 507 flow_match_sample_en); 508 if (!en) 509 continue; 510 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 511 flow_match_sample_field_id); 512 } 513 if (num != idx) { 514 rte_errno = EINVAL; 515 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 516 return -rte_errno; 517 } 518 return ret; 519 } 520 521 522 struct mlx5_devx_obj * 523 mlx5_devx_cmd_create_flex_parser(void *ctx, 524 struct mlx5_devx_graph_node_attr *data) 525 { 526 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 527 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 528 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 529 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 530 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 531 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 532 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 533 struct mlx5_devx_obj *parse_flex_obj = NULL; 534 uint32_t i; 535 536 parse_flex_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, 537 SOCKET_ID_ANY); 538 if (!parse_flex_obj) { 539 DRV_LOG(ERR, "Failed to allocate flex parser data"); 540 rte_errno = ENOMEM; 541 mlx5_free(in); 542 return NULL; 543 } 544 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 545 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 546 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 547 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 548 MLX5_SET(parse_graph_flex, flex, header_length_mode, 549 data->header_length_mode); 550 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 551 data->header_length_base_value); 552 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 553 data->header_length_field_offset); 554 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 555 data->header_length_field_shift); 556 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 557 data->header_length_field_mask); 558 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 559 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 560 void *s_off = (void *)((char *)sample + i * 561 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 562 563 if (!s->flow_match_sample_en) 564 continue; 565 MLX5_SET(parse_graph_flow_match_sample, s_off, 566 flow_match_sample_en, !!s->flow_match_sample_en); 567 MLX5_SET(parse_graph_flow_match_sample, s_off, 568 flow_match_sample_field_offset, 569 s->flow_match_sample_field_offset); 570 MLX5_SET(parse_graph_flow_match_sample, s_off, 571 flow_match_sample_offset_mode, 572 s->flow_match_sample_offset_mode); 573 MLX5_SET(parse_graph_flow_match_sample, s_off, 574 flow_match_sample_field_offset_mask, 575 s->flow_match_sample_field_offset_mask); 576 MLX5_SET(parse_graph_flow_match_sample, s_off, 577 flow_match_sample_field_offset_shift, 578 s->flow_match_sample_field_offset_shift); 579 MLX5_SET(parse_graph_flow_match_sample, s_off, 580 flow_match_sample_field_base_offset, 581 s->flow_match_sample_field_base_offset); 582 MLX5_SET(parse_graph_flow_match_sample, s_off, 583 flow_match_sample_tunnel_mode, 584 s->flow_match_sample_tunnel_mode); 585 } 586 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 587 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 588 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 589 void *in_off = (void *)((char *)in_arc + i * 590 MLX5_ST_SZ_BYTES(parse_graph_arc)); 591 void *out_off = (void *)((char *)out_arc + i * 592 MLX5_ST_SZ_BYTES(parse_graph_arc)); 593 594 if (ia->arc_parse_graph_node != 0) { 595 MLX5_SET(parse_graph_arc, in_off, 596 compare_condition_value, 597 ia->compare_condition_value); 598 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 599 ia->start_inner_tunnel); 600 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 601 ia->arc_parse_graph_node); 602 MLX5_SET(parse_graph_arc, in_off, 603 parse_graph_node_handle, 604 ia->parse_graph_node_handle); 605 } 606 if (oa->arc_parse_graph_node != 0) { 607 MLX5_SET(parse_graph_arc, out_off, 608 compare_condition_value, 609 oa->compare_condition_value); 610 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 611 oa->start_inner_tunnel); 612 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 613 oa->arc_parse_graph_node); 614 MLX5_SET(parse_graph_arc, out_off, 615 parse_graph_node_handle, 616 oa->parse_graph_node_handle); 617 } 618 } 619 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 620 out, sizeof(out)); 621 if (!parse_flex_obj->obj) { 622 rte_errno = errno; 623 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 624 "by using DevX."); 625 mlx5_free(parse_flex_obj); 626 return NULL; 627 } 628 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 629 return parse_flex_obj; 630 } 631 632 /** 633 * Query HCA attributes. 634 * Using those attributes we can check on run time if the device 635 * is having the required capabilities. 636 * 637 * @param[in] ctx 638 * Context returned from mlx5 open_device() glue function. 639 * @param[out] attr 640 * Attributes device values. 641 * 642 * @return 643 * 0 on success, a negative value otherwise. 644 */ 645 int 646 mlx5_devx_cmd_query_hca_attr(void *ctx, 647 struct mlx5_hca_attr *attr) 648 { 649 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 650 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 651 void *hcattr; 652 int status, syndrome, rc, i; 653 654 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 655 MLX5_SET(query_hca_cap_in, in, op_mod, 656 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 657 MLX5_HCA_CAP_OPMOD_GET_CUR); 658 659 rc = mlx5_glue->devx_general_cmd(ctx, 660 in, sizeof(in), out, sizeof(out)); 661 if (rc) 662 goto error; 663 status = MLX5_GET(query_hca_cap_out, out, status); 664 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 665 if (status) { 666 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 667 "status %x, syndrome = %x", 668 status, syndrome); 669 return -1; 670 } 671 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 672 attr->flow_counter_bulk_alloc_bitmap = 673 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 674 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 675 flow_counters_dump); 676 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 677 log_max_rqt_size); 678 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 679 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 680 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 681 log_max_hairpin_queues); 682 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 683 log_max_hairpin_wq_data_sz); 684 attr->log_max_hairpin_num_packets = MLX5_GET 685 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 686 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 687 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 688 relaxed_ordering_write); 689 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 690 relaxed_ordering_read); 691 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 692 access_register_user); 693 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 694 eth_net_offloads); 695 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 696 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 697 flex_parser_protocols); 698 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 699 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 700 general_obj_types) & 701 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 702 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 703 general_obj_types) & 704 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 705 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 706 general_obj_types) & 707 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 708 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 709 wqe_index_ignore_cap); 710 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 711 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 712 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 713 log_max_static_sq_wq); 714 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 715 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 716 device_frequency_khz); 717 attr->scatter_fcs_w_decap_disable = 718 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 719 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp); 720 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 721 regexp_num_of_engines); 722 attr->flow_hit_aso = !!(MLX5_GET64(cmd_hca_cap, hcattr, 723 general_obj_types) & 724 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 725 if (attr->qos.sup) { 726 MLX5_SET(query_hca_cap_in, in, op_mod, 727 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 728 MLX5_HCA_CAP_OPMOD_GET_CUR); 729 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 730 out, sizeof(out)); 731 if (rc) 732 goto error; 733 if (status) { 734 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities," 735 " status %x, syndrome = %x", 736 status, syndrome); 737 return -1; 738 } 739 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 740 attr->qos.srtcm_sup = 741 MLX5_GET(qos_cap, hcattr, flow_meter_srtcm); 742 attr->qos.log_max_flow_meter = 743 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 744 attr->qos.flow_meter_reg_c_ids = 745 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 746 attr->qos.flow_meter_reg_share = 747 MLX5_GET(qos_cap, hcattr, flow_meter_reg_share); 748 attr->qos.packet_pacing = 749 MLX5_GET(qos_cap, hcattr, packet_pacing); 750 attr->qos.wqe_rate_pp = 751 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 752 } 753 if (attr->vdpa.valid) 754 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 755 if (!attr->eth_net_offloads) 756 return 0; 757 758 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 759 memset(in, 0, sizeof(in)); 760 memset(out, 0, sizeof(out)); 761 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 762 MLX5_SET(query_hca_cap_in, in, op_mod, 763 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 764 MLX5_HCA_CAP_OPMOD_GET_CUR); 765 766 rc = mlx5_glue->devx_general_cmd(ctx, 767 in, sizeof(in), 768 out, sizeof(out)); 769 if (rc) 770 goto error; 771 status = MLX5_GET(query_hca_cap_out, out, status); 772 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 773 if (status) { 774 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 775 "status %x, syndrome = %x", 776 status, syndrome); 777 attr->log_max_ft_sampler_num = 0; 778 return -1; 779 } 780 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 781 attr->log_max_ft_sampler_num = 782 MLX5_GET(flow_table_nic_cap, 783 hcattr, flow_table_properties.log_max_ft_sampler_num); 784 785 /* Query HCA offloads for Ethernet protocol. */ 786 memset(in, 0, sizeof(in)); 787 memset(out, 0, sizeof(out)); 788 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 789 MLX5_SET(query_hca_cap_in, in, op_mod, 790 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 791 MLX5_HCA_CAP_OPMOD_GET_CUR); 792 793 rc = mlx5_glue->devx_general_cmd(ctx, 794 in, sizeof(in), 795 out, sizeof(out)); 796 if (rc) { 797 attr->eth_net_offloads = 0; 798 goto error; 799 } 800 status = MLX5_GET(query_hca_cap_out, out, status); 801 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 802 if (status) { 803 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 804 "status %x, syndrome = %x", 805 status, syndrome); 806 attr->eth_net_offloads = 0; 807 return -1; 808 } 809 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 810 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 811 hcattr, wqe_vlan_insert); 812 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 813 lro_cap); 814 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 815 hcattr, tunnel_lro_gre); 816 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 817 hcattr, tunnel_lro_vxlan); 818 attr->lro_max_msg_sz_mode = MLX5_GET 819 (per_protocol_networking_offload_caps, 820 hcattr, lro_max_msg_sz_mode); 821 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 822 attr->lro_timer_supported_periods[i] = 823 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 824 lro_timer_supported_periods[i]); 825 } 826 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 827 hcattr, lro_min_mss_size); 828 attr->tunnel_stateless_geneve_rx = 829 MLX5_GET(per_protocol_networking_offload_caps, 830 hcattr, tunnel_stateless_geneve_rx); 831 attr->geneve_max_opt_len = 832 MLX5_GET(per_protocol_networking_offload_caps, 833 hcattr, max_geneve_opt_len); 834 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 835 hcattr, wqe_inline_mode); 836 attr->tunnel_stateless_gtp = MLX5_GET 837 (per_protocol_networking_offload_caps, 838 hcattr, tunnel_stateless_gtp); 839 if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) 840 return 0; 841 if (attr->eth_virt) { 842 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 843 if (rc) { 844 attr->eth_virt = 0; 845 goto error; 846 } 847 } 848 return 0; 849 error: 850 rc = (rc > 0) ? -rc : rc; 851 return rc; 852 } 853 854 /** 855 * Query TIS transport domain from QP verbs object using DevX API. 856 * 857 * @param[in] qp 858 * Pointer to verbs QP returned by ibv_create_qp . 859 * @param[in] tis_num 860 * TIS number of TIS to query. 861 * @param[out] tis_td 862 * Pointer to TIS transport domain variable, to be set by the routine. 863 * 864 * @return 865 * 0 on success, a negative value otherwise. 866 */ 867 int 868 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 869 uint32_t *tis_td) 870 { 871 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 872 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 873 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 874 int rc; 875 void *tis_ctx; 876 877 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 878 MLX5_SET(query_tis_in, in, tisn, tis_num); 879 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 880 if (rc) { 881 DRV_LOG(ERR, "Failed to query QP using DevX"); 882 return -rc; 883 }; 884 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 885 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 886 return 0; 887 #else 888 (void)qp; 889 (void)tis_num; 890 (void)tis_td; 891 return -ENOTSUP; 892 #endif 893 } 894 895 /** 896 * Fill WQ data for DevX API command. 897 * Utility function for use when creating DevX objects containing a WQ. 898 * 899 * @param[in] wq_ctx 900 * Pointer to WQ context to fill with data. 901 * @param [in] wq_attr 902 * Pointer to WQ attributes structure to fill in WQ context. 903 */ 904 static void 905 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 906 { 907 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 908 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 909 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 910 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 911 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 912 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 913 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 914 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 915 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 916 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 917 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 918 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 919 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 920 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 921 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz); 922 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 923 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 924 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 925 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 926 wq_attr->log_hairpin_num_packets); 927 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 928 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 929 wq_attr->single_wqe_log_num_of_strides); 930 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 931 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 932 wq_attr->single_stride_log_num_of_bytes); 933 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 934 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 935 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 936 } 937 938 /** 939 * Create RQ using DevX API. 940 * 941 * @param[in] ctx 942 * Context returned from mlx5 open_device() glue function. 943 * @param [in] rq_attr 944 * Pointer to create RQ attributes structure. 945 * @param [in] socket 946 * CPU socket ID for allocations. 947 * 948 * @return 949 * The DevX object created, NULL otherwise and rte_errno is set. 950 */ 951 struct mlx5_devx_obj * 952 mlx5_devx_cmd_create_rq(void *ctx, 953 struct mlx5_devx_create_rq_attr *rq_attr, 954 int socket) 955 { 956 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 957 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 958 void *rq_ctx, *wq_ctx; 959 struct mlx5_devx_wq_attr *wq_attr; 960 struct mlx5_devx_obj *rq = NULL; 961 962 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 963 if (!rq) { 964 DRV_LOG(ERR, "Failed to allocate RQ data"); 965 rte_errno = ENOMEM; 966 return NULL; 967 } 968 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 969 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 970 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 971 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 972 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 973 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 974 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 975 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 976 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 977 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 978 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 979 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 980 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 981 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 982 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 983 wq_attr = &rq_attr->wq_attr; 984 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 985 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 986 out, sizeof(out)); 987 if (!rq->obj) { 988 DRV_LOG(ERR, "Failed to create RQ using DevX"); 989 rte_errno = errno; 990 mlx5_free(rq); 991 return NULL; 992 } 993 rq->id = MLX5_GET(create_rq_out, out, rqn); 994 return rq; 995 } 996 997 /** 998 * Modify RQ using DevX API. 999 * 1000 * @param[in] rq 1001 * Pointer to RQ object structure. 1002 * @param [in] rq_attr 1003 * Pointer to modify RQ attributes structure. 1004 * 1005 * @return 1006 * 0 on success, a negative errno value otherwise and rte_errno is set. 1007 */ 1008 int 1009 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1010 struct mlx5_devx_modify_rq_attr *rq_attr) 1011 { 1012 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1013 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1014 void *rq_ctx, *wq_ctx; 1015 int ret; 1016 1017 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1018 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1019 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1020 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1021 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1022 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1023 if (rq_attr->modify_bitmask & 1024 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1025 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1026 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1027 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1028 if (rq_attr->modify_bitmask & 1029 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1030 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1031 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1032 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1033 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1034 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1035 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1036 } 1037 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1038 out, sizeof(out)); 1039 if (ret) { 1040 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1041 rte_errno = errno; 1042 return -errno; 1043 } 1044 return ret; 1045 } 1046 1047 /** 1048 * Create TIR using DevX API. 1049 * 1050 * @param[in] ctx 1051 * Context returned from mlx5 open_device() glue function. 1052 * @param [in] tir_attr 1053 * Pointer to TIR attributes structure. 1054 * 1055 * @return 1056 * The DevX object created, NULL otherwise and rte_errno is set. 1057 */ 1058 struct mlx5_devx_obj * 1059 mlx5_devx_cmd_create_tir(void *ctx, 1060 struct mlx5_devx_tir_attr *tir_attr) 1061 { 1062 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1063 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1064 void *tir_ctx, *outer, *inner, *rss_key; 1065 struct mlx5_devx_obj *tir = NULL; 1066 1067 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1068 if (!tir) { 1069 DRV_LOG(ERR, "Failed to allocate TIR data"); 1070 rte_errno = ENOMEM; 1071 return NULL; 1072 } 1073 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1074 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1075 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1076 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1077 tir_attr->lro_timeout_period_usecs); 1078 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1079 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1080 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1081 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1082 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1083 tir_attr->tunneled_offload_en); 1084 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1085 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1086 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1087 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1088 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1089 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1090 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1091 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1092 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1093 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1094 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1095 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1096 tir_attr->rx_hash_field_selector_outer.selected_fields); 1097 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1098 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1099 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1100 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1101 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1102 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1103 tir_attr->rx_hash_field_selector_inner.selected_fields); 1104 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1105 out, sizeof(out)); 1106 if (!tir->obj) { 1107 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1108 rte_errno = errno; 1109 mlx5_free(tir); 1110 return NULL; 1111 } 1112 tir->id = MLX5_GET(create_tir_out, out, tirn); 1113 return tir; 1114 } 1115 1116 /** 1117 * Modify TIR using DevX API. 1118 * 1119 * @param[in] tir 1120 * Pointer to TIR DevX object structure. 1121 * @param [in] modify_tir_attr 1122 * Pointer to TIR modification attributes structure. 1123 * 1124 * @return 1125 * 0 on success, a negative errno value otherwise and rte_errno is set. 1126 */ 1127 int 1128 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1129 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1130 { 1131 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1132 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1133 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1134 void *tir_ctx; 1135 int ret; 1136 1137 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1138 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1139 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1140 modify_tir_attr->modify_bitmask); 1141 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1142 if (modify_tir_attr->modify_bitmask & 1143 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1144 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1145 tir_attr->lro_timeout_period_usecs); 1146 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1147 tir_attr->lro_enable_mask); 1148 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1149 tir_attr->lro_max_msg_sz); 1150 } 1151 if (modify_tir_attr->modify_bitmask & 1152 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1153 MLX5_SET(tirc, tir_ctx, indirect_table, 1154 tir_attr->indirect_table); 1155 if (modify_tir_attr->modify_bitmask & 1156 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1157 int i; 1158 void *outer, *inner; 1159 1160 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1161 tir_attr->rx_hash_symmetric); 1162 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1163 for (i = 0; i < 10; i++) { 1164 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1165 tir_attr->rx_hash_toeplitz_key[i]); 1166 } 1167 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1168 rx_hash_field_selector_outer); 1169 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1170 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1171 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1172 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1173 MLX5_SET 1174 (rx_hash_field_select, outer, selected_fields, 1175 tir_attr->rx_hash_field_selector_outer.selected_fields); 1176 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1177 rx_hash_field_selector_inner); 1178 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1179 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1180 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1181 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1182 MLX5_SET 1183 (rx_hash_field_select, inner, selected_fields, 1184 tir_attr->rx_hash_field_selector_inner.selected_fields); 1185 } 1186 if (modify_tir_attr->modify_bitmask & 1187 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1188 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1189 } 1190 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1191 out, sizeof(out)); 1192 if (ret) { 1193 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1194 rte_errno = errno; 1195 return -errno; 1196 } 1197 return ret; 1198 } 1199 1200 /** 1201 * Create RQT using DevX API. 1202 * 1203 * @param[in] ctx 1204 * Context returned from mlx5 open_device() glue function. 1205 * @param [in] rqt_attr 1206 * Pointer to RQT attributes structure. 1207 * 1208 * @return 1209 * The DevX object created, NULL otherwise and rte_errno is set. 1210 */ 1211 struct mlx5_devx_obj * 1212 mlx5_devx_cmd_create_rqt(void *ctx, 1213 struct mlx5_devx_rqt_attr *rqt_attr) 1214 { 1215 uint32_t *in = NULL; 1216 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1217 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1218 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1219 void *rqt_ctx; 1220 struct mlx5_devx_obj *rqt = NULL; 1221 int i; 1222 1223 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1224 if (!in) { 1225 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1226 rte_errno = ENOMEM; 1227 return NULL; 1228 } 1229 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1230 if (!rqt) { 1231 DRV_LOG(ERR, "Failed to allocate RQT data"); 1232 rte_errno = ENOMEM; 1233 mlx5_free(in); 1234 return NULL; 1235 } 1236 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1237 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1238 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1239 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1240 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1241 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1242 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1243 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1244 mlx5_free(in); 1245 if (!rqt->obj) { 1246 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1247 rte_errno = errno; 1248 mlx5_free(rqt); 1249 return NULL; 1250 } 1251 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1252 return rqt; 1253 } 1254 1255 /** 1256 * Modify RQT using DevX API. 1257 * 1258 * @param[in] rqt 1259 * Pointer to RQT DevX object structure. 1260 * @param [in] rqt_attr 1261 * Pointer to RQT attributes structure. 1262 * 1263 * @return 1264 * 0 on success, a negative errno value otherwise and rte_errno is set. 1265 */ 1266 int 1267 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1268 struct mlx5_devx_rqt_attr *rqt_attr) 1269 { 1270 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1271 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1272 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1273 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1274 void *rqt_ctx; 1275 int i; 1276 int ret; 1277 1278 if (!in) { 1279 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1280 rte_errno = ENOMEM; 1281 return -ENOMEM; 1282 } 1283 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1284 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1285 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1286 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1287 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1288 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1289 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1290 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1291 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1292 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1293 mlx5_free(in); 1294 if (ret) { 1295 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1296 rte_errno = errno; 1297 return -rte_errno; 1298 } 1299 return ret; 1300 } 1301 1302 /** 1303 * Create SQ using DevX API. 1304 * 1305 * @param[in] ctx 1306 * Context returned from mlx5 open_device() glue function. 1307 * @param [in] sq_attr 1308 * Pointer to SQ attributes structure. 1309 * @param [in] socket 1310 * CPU socket ID for allocations. 1311 * 1312 * @return 1313 * The DevX object created, NULL otherwise and rte_errno is set. 1314 **/ 1315 struct mlx5_devx_obj * 1316 mlx5_devx_cmd_create_sq(void *ctx, 1317 struct mlx5_devx_create_sq_attr *sq_attr) 1318 { 1319 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1320 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1321 void *sq_ctx; 1322 void *wq_ctx; 1323 struct mlx5_devx_wq_attr *wq_attr; 1324 struct mlx5_devx_obj *sq = NULL; 1325 1326 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1327 if (!sq) { 1328 DRV_LOG(ERR, "Failed to allocate SQ data"); 1329 rte_errno = ENOMEM; 1330 return NULL; 1331 } 1332 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1333 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1334 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1335 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1336 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1337 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1338 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1339 sq_attr->allow_multi_pkt_send_wqe); 1340 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1341 sq_attr->min_wqe_inline_mode); 1342 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1343 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1344 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1345 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1346 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1347 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1348 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1349 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1350 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1351 sq_attr->packet_pacing_rate_limit_index); 1352 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1353 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1354 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1355 wq_attr = &sq_attr->wq_attr; 1356 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1357 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1358 out, sizeof(out)); 1359 if (!sq->obj) { 1360 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1361 rte_errno = errno; 1362 mlx5_free(sq); 1363 return NULL; 1364 } 1365 sq->id = MLX5_GET(create_sq_out, out, sqn); 1366 return sq; 1367 } 1368 1369 /** 1370 * Modify SQ using DevX API. 1371 * 1372 * @param[in] sq 1373 * Pointer to SQ object structure. 1374 * @param [in] sq_attr 1375 * Pointer to SQ attributes structure. 1376 * 1377 * @return 1378 * 0 on success, a negative errno value otherwise and rte_errno is set. 1379 */ 1380 int 1381 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1382 struct mlx5_devx_modify_sq_attr *sq_attr) 1383 { 1384 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1385 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1386 void *sq_ctx; 1387 int ret; 1388 1389 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1390 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1391 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1392 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1393 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1394 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1395 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1396 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1397 out, sizeof(out)); 1398 if (ret) { 1399 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1400 rte_errno = errno; 1401 return -rte_errno; 1402 } 1403 return ret; 1404 } 1405 1406 /** 1407 * Create TIS using DevX API. 1408 * 1409 * @param[in] ctx 1410 * Context returned from mlx5 open_device() glue function. 1411 * @param [in] tis_attr 1412 * Pointer to TIS attributes structure. 1413 * 1414 * @return 1415 * The DevX object created, NULL otherwise and rte_errno is set. 1416 */ 1417 struct mlx5_devx_obj * 1418 mlx5_devx_cmd_create_tis(void *ctx, 1419 struct mlx5_devx_tis_attr *tis_attr) 1420 { 1421 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1422 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1423 struct mlx5_devx_obj *tis = NULL; 1424 void *tis_ctx; 1425 1426 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1427 if (!tis) { 1428 DRV_LOG(ERR, "Failed to allocate TIS object"); 1429 rte_errno = ENOMEM; 1430 return NULL; 1431 } 1432 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1433 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1434 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1435 tis_attr->strict_lag_tx_port_affinity); 1436 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1437 tis_attr->lag_tx_port_affinity); 1438 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1439 MLX5_SET(tisc, tis_ctx, transport_domain, 1440 tis_attr->transport_domain); 1441 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1442 out, sizeof(out)); 1443 if (!tis->obj) { 1444 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1445 rte_errno = errno; 1446 mlx5_free(tis); 1447 return NULL; 1448 } 1449 tis->id = MLX5_GET(create_tis_out, out, tisn); 1450 return tis; 1451 } 1452 1453 /** 1454 * Create transport domain using DevX API. 1455 * 1456 * @param[in] ctx 1457 * Context returned from mlx5 open_device() glue function. 1458 * @return 1459 * The DevX object created, NULL otherwise and rte_errno is set. 1460 */ 1461 struct mlx5_devx_obj * 1462 mlx5_devx_cmd_create_td(void *ctx) 1463 { 1464 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1465 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1466 struct mlx5_devx_obj *td = NULL; 1467 1468 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1469 if (!td) { 1470 DRV_LOG(ERR, "Failed to allocate TD object"); 1471 rte_errno = ENOMEM; 1472 return NULL; 1473 } 1474 MLX5_SET(alloc_transport_domain_in, in, opcode, 1475 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1476 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1477 out, sizeof(out)); 1478 if (!td->obj) { 1479 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1480 rte_errno = errno; 1481 mlx5_free(td); 1482 return NULL; 1483 } 1484 td->id = MLX5_GET(alloc_transport_domain_out, out, 1485 transport_domain); 1486 return td; 1487 } 1488 1489 /** 1490 * Dump all flows to file. 1491 * 1492 * @param[in] fdb_domain 1493 * FDB domain. 1494 * @param[in] rx_domain 1495 * RX domain. 1496 * @param[in] tx_domain 1497 * TX domain. 1498 * @param[out] file 1499 * Pointer to file stream. 1500 * 1501 * @return 1502 * 0 on success, a nagative value otherwise. 1503 */ 1504 int 1505 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1506 void *rx_domain __rte_unused, 1507 void *tx_domain __rte_unused, FILE *file __rte_unused) 1508 { 1509 int ret = 0; 1510 1511 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1512 if (fdb_domain) { 1513 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1514 if (ret) 1515 return ret; 1516 } 1517 MLX5_ASSERT(rx_domain); 1518 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1519 if (ret) 1520 return ret; 1521 MLX5_ASSERT(tx_domain); 1522 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1523 #else 1524 ret = ENOTSUP; 1525 #endif 1526 return -ret; 1527 } 1528 1529 /* 1530 * Create CQ using DevX API. 1531 * 1532 * @param[in] ctx 1533 * Context returned from mlx5 open_device() glue function. 1534 * @param [in] attr 1535 * Pointer to CQ attributes structure. 1536 * 1537 * @return 1538 * The DevX object created, NULL otherwise and rte_errno is set. 1539 */ 1540 struct mlx5_devx_obj * 1541 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1542 { 1543 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1544 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1545 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1546 sizeof(*cq_obj), 1547 0, SOCKET_ID_ANY); 1548 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1549 1550 if (!cq_obj) { 1551 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1552 rte_errno = ENOMEM; 1553 return NULL; 1554 } 1555 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1556 if (attr->db_umem_valid) { 1557 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1558 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1559 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1560 } else { 1561 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1562 } 1563 MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size); 1564 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1565 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1566 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1567 MLX5_SET(cqc, cqctx, log_page_size, attr->log_page_size - 1568 MLX5_ADAPTER_PAGE_SHIFT); 1569 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1570 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1571 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1572 MLX5_SET(cqc, cqctx, mini_cqe_res_format, 1573 attr->mini_cqe_res_format); 1574 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1575 attr->mini_cqe_res_format_ext); 1576 MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size); 1577 if (attr->q_umem_valid) { 1578 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1579 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1580 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1581 attr->q_umem_offset); 1582 } 1583 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1584 sizeof(out)); 1585 if (!cq_obj->obj) { 1586 rte_errno = errno; 1587 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1588 mlx5_free(cq_obj); 1589 return NULL; 1590 } 1591 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1592 return cq_obj; 1593 } 1594 1595 /** 1596 * Create VIRTQ using DevX API. 1597 * 1598 * @param[in] ctx 1599 * Context returned from mlx5 open_device() glue function. 1600 * @param [in] attr 1601 * Pointer to VIRTQ attributes structure. 1602 * 1603 * @return 1604 * The DevX object created, NULL otherwise and rte_errno is set. 1605 */ 1606 struct mlx5_devx_obj * 1607 mlx5_devx_cmd_create_virtq(void *ctx, 1608 struct mlx5_devx_virtq_attr *attr) 1609 { 1610 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1611 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1612 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1613 sizeof(*virtq_obj), 1614 0, SOCKET_ID_ANY); 1615 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1616 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1617 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1618 1619 if (!virtq_obj) { 1620 DRV_LOG(ERR, "Failed to allocate virtq data."); 1621 rte_errno = ENOMEM; 1622 return NULL; 1623 } 1624 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1625 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1626 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1627 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1628 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1629 attr->hw_available_index); 1630 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1631 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1632 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1633 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1634 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1635 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1636 attr->virtio_version_1_0); 1637 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1638 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1639 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1640 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1641 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1642 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1643 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1644 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1645 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1646 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 1647 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 1648 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 1649 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 1650 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 1651 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 1652 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 1653 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 1654 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 1655 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 1656 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 1657 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1658 sizeof(out)); 1659 if (!virtq_obj->obj) { 1660 rte_errno = errno; 1661 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 1662 mlx5_free(virtq_obj); 1663 return NULL; 1664 } 1665 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1666 return virtq_obj; 1667 } 1668 1669 /** 1670 * Modify VIRTQ using DevX API. 1671 * 1672 * @param[in] virtq_obj 1673 * Pointer to virtq object structure. 1674 * @param [in] attr 1675 * Pointer to modify virtq attributes structure. 1676 * 1677 * @return 1678 * 0 on success, a negative errno value otherwise and rte_errno is set. 1679 */ 1680 int 1681 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 1682 struct mlx5_devx_virtq_attr *attr) 1683 { 1684 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1685 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1686 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1687 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1688 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1689 int ret; 1690 1691 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1692 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 1693 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1694 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1695 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1696 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 1697 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1698 switch (attr->type) { 1699 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 1700 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 1701 break; 1702 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 1703 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 1704 attr->dirty_bitmap_mkey); 1705 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 1706 attr->dirty_bitmap_addr); 1707 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 1708 attr->dirty_bitmap_size); 1709 break; 1710 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 1711 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 1712 attr->dirty_bitmap_dump_enable); 1713 break; 1714 default: 1715 rte_errno = EINVAL; 1716 return -rte_errno; 1717 } 1718 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 1719 out, sizeof(out)); 1720 if (ret) { 1721 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1722 rte_errno = errno; 1723 return -rte_errno; 1724 } 1725 return ret; 1726 } 1727 1728 /** 1729 * Query VIRTQ using DevX API. 1730 * 1731 * @param[in] virtq_obj 1732 * Pointer to virtq object structure. 1733 * @param [in/out] attr 1734 * Pointer to virtq attributes structure. 1735 * 1736 * @return 1737 * 0 on success, a negative errno value otherwise and rte_errno is set. 1738 */ 1739 int 1740 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 1741 struct mlx5_devx_virtq_attr *attr) 1742 { 1743 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1744 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 1745 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 1746 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 1747 int ret; 1748 1749 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1750 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1751 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1752 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1753 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1754 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 1755 out, sizeof(out)); 1756 if (ret) { 1757 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1758 rte_errno = errno; 1759 return -errno; 1760 } 1761 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 1762 hw_available_index); 1763 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 1764 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 1765 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 1766 virtio_q_context.error_type); 1767 return ret; 1768 } 1769 1770 /** 1771 * Create QP using DevX API. 1772 * 1773 * @param[in] ctx 1774 * Context returned from mlx5 open_device() glue function. 1775 * @param [in] attr 1776 * Pointer to QP attributes structure. 1777 * 1778 * @return 1779 * The DevX object created, NULL otherwise and rte_errno is set. 1780 */ 1781 struct mlx5_devx_obj * 1782 mlx5_devx_cmd_create_qp(void *ctx, 1783 struct mlx5_devx_qp_attr *attr) 1784 { 1785 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 1786 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 1787 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 1788 sizeof(*qp_obj), 1789 0, SOCKET_ID_ANY); 1790 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1791 1792 if (!qp_obj) { 1793 DRV_LOG(ERR, "Failed to allocate QP data."); 1794 rte_errno = ENOMEM; 1795 return NULL; 1796 } 1797 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 1798 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 1799 MLX5_SET(qpc, qpc, pd, attr->pd); 1800 if (attr->uar_index) { 1801 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1802 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 1803 MLX5_SET(qpc, qpc, log_page_size, attr->log_page_size - 1804 MLX5_ADAPTER_PAGE_SHIFT); 1805 if (attr->sq_size) { 1806 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); 1807 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 1808 MLX5_SET(qpc, qpc, log_sq_size, 1809 rte_log2_u32(attr->sq_size)); 1810 } else { 1811 MLX5_SET(qpc, qpc, no_sq, 1); 1812 } 1813 if (attr->rq_size) { 1814 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); 1815 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 1816 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 1817 MLX5_LOG_RQ_STRIDE_SHIFT); 1818 MLX5_SET(qpc, qpc, log_rq_size, 1819 rte_log2_u32(attr->rq_size)); 1820 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 1821 } else { 1822 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1823 } 1824 if (attr->dbr_umem_valid) { 1825 MLX5_SET(qpc, qpc, dbr_umem_valid, 1826 attr->dbr_umem_valid); 1827 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 1828 } 1829 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 1830 MLX5_SET64(create_qp_in, in, wq_umem_offset, 1831 attr->wq_umem_offset); 1832 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 1833 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 1834 } else { 1835 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 1836 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1837 MLX5_SET(qpc, qpc, no_sq, 1); 1838 } 1839 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1840 sizeof(out)); 1841 if (!qp_obj->obj) { 1842 rte_errno = errno; 1843 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 1844 mlx5_free(qp_obj); 1845 return NULL; 1846 } 1847 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 1848 return qp_obj; 1849 } 1850 1851 /** 1852 * Modify QP using DevX API. 1853 * Currently supports only force loop-back QP. 1854 * 1855 * @param[in] qp 1856 * Pointer to QP object structure. 1857 * @param [in] qp_st_mod_op 1858 * The QP state modification operation. 1859 * @param [in] remote_qp_id 1860 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 1861 * 1862 * @return 1863 * 0 on success, a negative errno value otherwise and rte_errno is set. 1864 */ 1865 int 1866 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 1867 uint32_t remote_qp_id) 1868 { 1869 union { 1870 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 1871 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 1872 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 1873 } in; 1874 union { 1875 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 1876 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 1877 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 1878 } out; 1879 void *qpc; 1880 int ret; 1881 unsigned int inlen; 1882 unsigned int outlen; 1883 1884 memset(&in, 0, sizeof(in)); 1885 memset(&out, 0, sizeof(out)); 1886 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 1887 switch (qp_st_mod_op) { 1888 case MLX5_CMD_OP_RST2INIT_QP: 1889 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 1890 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 1891 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1892 MLX5_SET(qpc, qpc, rre, 1); 1893 MLX5_SET(qpc, qpc, rwe, 1); 1894 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1895 inlen = sizeof(in.rst2init); 1896 outlen = sizeof(out.rst2init); 1897 break; 1898 case MLX5_CMD_OP_INIT2RTR_QP: 1899 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 1900 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 1901 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 1902 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1903 MLX5_SET(qpc, qpc, mtu, 1); 1904 MLX5_SET(qpc, qpc, log_msg_max, 30); 1905 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 1906 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 1907 inlen = sizeof(in.init2rtr); 1908 outlen = sizeof(out.init2rtr); 1909 break; 1910 case MLX5_CMD_OP_RTR2RTS_QP: 1911 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 1912 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 1913 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 1914 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 1915 MLX5_SET(qpc, qpc, retry_count, 7); 1916 MLX5_SET(qpc, qpc, rnr_retry, 7); 1917 inlen = sizeof(in.rtr2rts); 1918 outlen = sizeof(out.rtr2rts); 1919 break; 1920 default: 1921 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 1922 qp_st_mod_op); 1923 rte_errno = EINVAL; 1924 return -rte_errno; 1925 } 1926 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 1927 if (ret) { 1928 DRV_LOG(ERR, "Failed to modify QP using DevX."); 1929 rte_errno = errno; 1930 return -rte_errno; 1931 } 1932 return ret; 1933 } 1934 1935 struct mlx5_devx_obj * 1936 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 1937 { 1938 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 1939 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1940 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 1941 sizeof(*couners_obj), 0, 1942 SOCKET_ID_ANY); 1943 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 1944 1945 if (!couners_obj) { 1946 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 1947 rte_errno = ENOMEM; 1948 return NULL; 1949 } 1950 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1951 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1952 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1953 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 1954 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1955 sizeof(out)); 1956 if (!couners_obj->obj) { 1957 rte_errno = errno; 1958 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 1959 " DevX."); 1960 mlx5_free(couners_obj); 1961 return NULL; 1962 } 1963 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1964 return couners_obj; 1965 } 1966 1967 int 1968 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 1969 struct mlx5_devx_virtio_q_couners_attr *attr) 1970 { 1971 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1972 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 1973 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 1974 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 1975 virtio_q_counters); 1976 int ret; 1977 1978 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1979 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1980 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1981 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 1982 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 1983 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 1984 sizeof(out)); 1985 if (ret) { 1986 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 1987 rte_errno = errno; 1988 return -errno; 1989 } 1990 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 1991 received_desc); 1992 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 1993 completed_desc); 1994 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 1995 error_cqes); 1996 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 1997 bad_desc_errors); 1998 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 1999 exceed_max_chain); 2000 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2001 invalid_buffer); 2002 return ret; 2003 } 2004 2005 /** 2006 * Create general object of type FLOW_HIT_ASO using DevX API. 2007 * 2008 * @param[in] ctx 2009 * Context returned from mlx5 open_device() glue function. 2010 * @param [in] pd 2011 * PD value to associate the FLOW_HIT_ASO object with. 2012 * 2013 * @return 2014 * The DevX object created, NULL otherwise and rte_errno is set. 2015 */ 2016 struct mlx5_devx_obj * 2017 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2018 { 2019 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2020 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2021 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2022 void *ptr = NULL; 2023 2024 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2025 0, SOCKET_ID_ANY); 2026 if (!flow_hit_aso_obj) { 2027 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2028 rte_errno = ENOMEM; 2029 return NULL; 2030 } 2031 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2032 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2033 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2034 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2035 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2036 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2037 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2038 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2039 out, sizeof(out)); 2040 if (!flow_hit_aso_obj->obj) { 2041 rte_errno = errno; 2042 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX."); 2043 mlx5_free(flow_hit_aso_obj); 2044 return NULL; 2045 } 2046 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2047 return flow_hit_aso_obj; 2048 } 2049