1 // SPDX-License-Identifier: BSD-3-Clause 2 /* Copyright 2018 Mellanox Technologies, Ltd */ 3 4 #include <unistd.h> 5 6 #include <rte_errno.h> 7 #include <rte_malloc.h> 8 #include <rte_eal_paging.h> 9 10 #include "mlx5_prm.h" 11 #include "mlx5_devx_cmds.h" 12 #include "mlx5_common_utils.h" 13 #include "mlx5_malloc.h" 14 15 16 /** 17 * Perform read access to the registers. Reads data from register 18 * and writes ones to the specified buffer. 19 * 20 * @param[in] ctx 21 * Context returned from mlx5 open_device() glue function. 22 * @param[in] reg_id 23 * Register identifier according to the PRM. 24 * @param[in] arg 25 * Register access auxiliary parameter according to the PRM. 26 * @param[out] data 27 * Pointer to the buffer to store read data. 28 * @param[in] dw_cnt 29 * Buffer size in double words. 30 * 31 * @return 32 * 0 on success, a negative value otherwise. 33 */ 34 int 35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 36 uint32_t *data, uint32_t dw_cnt) 37 { 38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 41 int status, rc; 42 43 MLX5_ASSERT(data && dw_cnt); 44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 46 DRV_LOG(ERR, "Not enough buffer for register read data"); 47 return -1; 48 } 49 MLX5_SET(access_register_in, in, opcode, 50 MLX5_CMD_OP_ACCESS_REGISTER_USER); 51 MLX5_SET(access_register_in, in, op_mod, 52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 53 MLX5_SET(access_register_in, in, register_id, reg_id); 54 MLX5_SET(access_register_in, in, argument, arg); 55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 56 MLX5_ST_SZ_BYTES(access_register_out) + 57 sizeof(uint32_t) * dw_cnt); 58 if (rc) 59 goto error; 60 status = MLX5_GET(access_register_out, out, status); 61 if (status) { 62 int syndrome = MLX5_GET(access_register_out, out, syndrome); 63 64 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, " 65 "status %x, syndrome = %x", 66 reg_id, status, syndrome); 67 return -1; 68 } 69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 70 dw_cnt * sizeof(uint32_t)); 71 return 0; 72 error: 73 rc = (rc > 0) ? -rc : rc; 74 return rc; 75 } 76 77 /** 78 * Allocate flow counters via devx interface. 79 * 80 * @param[in] ctx 81 * Context returned from mlx5 open_device() glue function. 82 * @param dcs 83 * Pointer to counters properties structure to be filled by the routine. 84 * @param bulk_n_128 85 * Bulk counter numbers in 128 counters units. 86 * 87 * @return 88 * Pointer to counter object on success, a negative value otherwise and 89 * rte_errno is set. 90 */ 91 struct mlx5_devx_obj * 92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 93 { 94 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 95 0, SOCKET_ID_ANY); 96 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 97 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 98 99 if (!dcs) { 100 rte_errno = ENOMEM; 101 return NULL; 102 } 103 MLX5_SET(alloc_flow_counter_in, in, opcode, 104 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 105 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 106 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 107 sizeof(in), out, sizeof(out)); 108 if (!dcs->obj) { 109 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 110 rte_errno = errno; 111 mlx5_free(dcs); 112 return NULL; 113 } 114 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 115 return dcs; 116 } 117 118 /** 119 * Query flow counters values. 120 * 121 * @param[in] dcs 122 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 123 * @param[in] clear 124 * Whether hardware should clear the counters after the query or not. 125 * @param[in] n_counters 126 * 0 in case of 1 counter to read, otherwise the counter number to read. 127 * @param pkts 128 * The number of packets that matched the flow. 129 * @param bytes 130 * The number of bytes that matched the flow. 131 * @param mkey 132 * The mkey key for batch query. 133 * @param addr 134 * The address in the mkey range for batch query. 135 * @param cmd_comp 136 * The completion object for asynchronous batch query. 137 * @param async_id 138 * The ID to be returned in the asynchronous batch query response. 139 * 140 * @return 141 * 0 on success, a negative value otherwise. 142 */ 143 int 144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 145 int clear, uint32_t n_counters, 146 uint64_t *pkts, uint64_t *bytes, 147 uint32_t mkey, void *addr, 148 void *cmd_comp, 149 uint64_t async_id) 150 { 151 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 152 MLX5_ST_SZ_BYTES(traffic_counter); 153 uint32_t out[out_len]; 154 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 155 void *stats; 156 int rc; 157 158 MLX5_SET(query_flow_counter_in, in, opcode, 159 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 160 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 161 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 162 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 163 164 if (n_counters) { 165 MLX5_SET(query_flow_counter_in, in, num_of_counters, 166 n_counters); 167 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 168 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 169 MLX5_SET64(query_flow_counter_in, in, address, 170 (uint64_t)(uintptr_t)addr); 171 } 172 if (!cmd_comp) 173 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 174 out_len); 175 else 176 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 177 out_len, async_id, 178 cmd_comp); 179 if (rc) { 180 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 181 rte_errno = rc; 182 return -rc; 183 } 184 if (!n_counters) { 185 stats = MLX5_ADDR_OF(query_flow_counter_out, 186 out, flow_statistics); 187 *pkts = MLX5_GET64(traffic_counter, stats, packets); 188 *bytes = MLX5_GET64(traffic_counter, stats, octets); 189 } 190 return 0; 191 } 192 193 /** 194 * Create a new mkey. 195 * 196 * @param[in] ctx 197 * Context returned from mlx5 open_device() glue function. 198 * @param[in] attr 199 * Attributes of the requested mkey. 200 * 201 * @return 202 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 203 * is set. 204 */ 205 struct mlx5_devx_obj * 206 mlx5_devx_cmd_mkey_create(void *ctx, 207 struct mlx5_devx_mkey_attr *attr) 208 { 209 struct mlx5_klm *klm_array = attr->klm_array; 210 int klm_num = attr->klm_num; 211 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 212 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 213 uint32_t in[in_size_dw]; 214 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 215 void *mkc; 216 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 217 0, SOCKET_ID_ANY); 218 size_t pgsize; 219 uint32_t translation_size; 220 221 if (!mkey) { 222 rte_errno = ENOMEM; 223 return NULL; 224 } 225 memset(in, 0, in_size_dw * 4); 226 pgsize = rte_mem_page_size(); 227 if (pgsize == (size_t)-1) { 228 mlx5_free(mkey); 229 DRV_LOG(ERR, "Failed to get page size"); 230 rte_errno = ENOMEM; 231 return NULL; 232 } 233 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 234 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 235 if (klm_num > 0) { 236 int i; 237 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 238 klm_pas_mtt); 239 translation_size = RTE_ALIGN(klm_num, 4); 240 for (i = 0; i < klm_num; i++) { 241 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 242 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 243 MLX5_SET64(klm, klm, address, klm_array[i].address); 244 klm += MLX5_ST_SZ_BYTES(klm); 245 } 246 for (; i < (int)translation_size; i++) { 247 MLX5_SET(klm, klm, mkey, 0x0); 248 MLX5_SET64(klm, klm, address, 0x0); 249 klm += MLX5_ST_SZ_BYTES(klm); 250 } 251 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 252 MLX5_MKC_ACCESS_MODE_KLM_FBS : 253 MLX5_MKC_ACCESS_MODE_KLM); 254 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 255 } else { 256 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 257 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 258 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 259 } 260 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 261 translation_size); 262 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 263 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 264 MLX5_SET(mkc, mkc, lw, 0x1); 265 MLX5_SET(mkc, mkc, lr, 0x1); 266 MLX5_SET(mkc, mkc, qpn, 0xffffff); 267 MLX5_SET(mkc, mkc, pd, attr->pd); 268 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 269 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 270 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 271 MLX5_SET(mkc, mkc, relaxed_ordering_write, 272 attr->relaxed_ordering_write); 273 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 274 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 275 MLX5_SET64(mkc, mkc, len, attr->size); 276 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 277 sizeof(out)); 278 if (!mkey->obj) { 279 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d", 280 klm_num ? "an in" : "a ", errno); 281 rte_errno = errno; 282 mlx5_free(mkey); 283 return NULL; 284 } 285 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 286 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 287 return mkey; 288 } 289 290 /** 291 * Get status of devx command response. 292 * Mainly used for asynchronous commands. 293 * 294 * @param[in] out 295 * The out response buffer. 296 * 297 * @return 298 * 0 on success, non-zero value otherwise. 299 */ 300 int 301 mlx5_devx_get_out_command_status(void *out) 302 { 303 int status; 304 305 if (!out) 306 return -EINVAL; 307 status = MLX5_GET(query_flow_counter_out, out, status); 308 if (status) { 309 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 310 311 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 312 syndrome); 313 } 314 return status; 315 } 316 317 /** 318 * Destroy any object allocated by a Devx API. 319 * 320 * @param[in] obj 321 * Pointer to a general object. 322 * 323 * @return 324 * 0 on success, a negative value otherwise. 325 */ 326 int 327 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 328 { 329 int ret; 330 331 if (!obj) 332 return 0; 333 ret = mlx5_glue->devx_obj_destroy(obj->obj); 334 mlx5_free(obj); 335 return ret; 336 } 337 338 /** 339 * Query NIC vport context. 340 * Fills minimal inline attribute. 341 * 342 * @param[in] ctx 343 * ibv contexts returned from mlx5dv_open_device. 344 * @param[in] vport 345 * vport index 346 * @param[out] attr 347 * Attributes device values. 348 * 349 * @return 350 * 0 on success, a negative value otherwise. 351 */ 352 static int 353 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 354 unsigned int vport, 355 struct mlx5_hca_attr *attr) 356 { 357 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 358 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 359 void *vctx; 360 int status, syndrome, rc; 361 362 /* Query NIC vport context to determine inline mode. */ 363 MLX5_SET(query_nic_vport_context_in, in, opcode, 364 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 365 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 366 if (vport) 367 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 368 rc = mlx5_glue->devx_general_cmd(ctx, 369 in, sizeof(in), 370 out, sizeof(out)); 371 if (rc) 372 goto error; 373 status = MLX5_GET(query_nic_vport_context_out, out, status); 374 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 375 if (status) { 376 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 377 "status %x, syndrome = %x", status, syndrome); 378 return -1; 379 } 380 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 381 nic_vport_context); 382 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 383 min_wqe_inline_mode); 384 return 0; 385 error: 386 rc = (rc > 0) ? -rc : rc; 387 return rc; 388 } 389 390 /** 391 * Query NIC vDPA attributes. 392 * 393 * @param[in] ctx 394 * Context returned from mlx5 open_device() glue function. 395 * @param[out] vdpa_attr 396 * vDPA Attributes structure to fill. 397 */ 398 static void 399 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 400 struct mlx5_hca_vdpa_attr *vdpa_attr) 401 { 402 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 403 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 404 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 405 int status, syndrome, rc; 406 407 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 408 MLX5_SET(query_hca_cap_in, in, op_mod, 409 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 410 MLX5_HCA_CAP_OPMOD_GET_CUR); 411 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 412 status = MLX5_GET(query_hca_cap_out, out, status); 413 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 414 if (rc || status) { 415 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities," 416 " status %x, syndrome = %x", status, syndrome); 417 vdpa_attr->valid = 0; 418 } else { 419 vdpa_attr->valid = 1; 420 vdpa_attr->desc_tunnel_offload_type = 421 MLX5_GET(virtio_emulation_cap, hcattr, 422 desc_tunnel_offload_type); 423 vdpa_attr->eth_frame_offload_type = 424 MLX5_GET(virtio_emulation_cap, hcattr, 425 eth_frame_offload_type); 426 vdpa_attr->virtio_version_1_0 = 427 MLX5_GET(virtio_emulation_cap, hcattr, 428 virtio_version_1_0); 429 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 430 tso_ipv4); 431 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 432 tso_ipv6); 433 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 434 tx_csum); 435 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 436 rx_csum); 437 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 438 event_mode); 439 vdpa_attr->virtio_queue_type = 440 MLX5_GET(virtio_emulation_cap, hcattr, 441 virtio_queue_type); 442 vdpa_attr->log_doorbell_stride = 443 MLX5_GET(virtio_emulation_cap, hcattr, 444 log_doorbell_stride); 445 vdpa_attr->log_doorbell_bar_size = 446 MLX5_GET(virtio_emulation_cap, hcattr, 447 log_doorbell_bar_size); 448 vdpa_attr->doorbell_bar_offset = 449 MLX5_GET64(virtio_emulation_cap, hcattr, 450 doorbell_bar_offset); 451 vdpa_attr->max_num_virtio_queues = 452 MLX5_GET(virtio_emulation_cap, hcattr, 453 max_num_virtio_queues); 454 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 455 umem_1_buffer_param_a); 456 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 457 umem_1_buffer_param_b); 458 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 459 umem_2_buffer_param_a); 460 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 461 umem_2_buffer_param_b); 462 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 463 umem_3_buffer_param_a); 464 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 465 umem_3_buffer_param_b); 466 } 467 } 468 469 int 470 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 471 uint32_t ids[], uint32_t num) 472 { 473 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 474 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 475 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 476 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 477 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 478 int ret; 479 uint32_t idx = 0; 480 uint32_t i; 481 482 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 483 rte_errno = EINVAL; 484 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 485 return -rte_errno; 486 } 487 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 488 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 489 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 490 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 491 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 492 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 493 out, sizeof(out)); 494 if (ret) { 495 rte_errno = ret; 496 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 497 (void *)flex_obj); 498 return -rte_errno; 499 } 500 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 501 void *s_off = (void *)((char *)sample + i * 502 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 503 uint32_t en; 504 505 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 506 flow_match_sample_en); 507 if (!en) 508 continue; 509 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 510 flow_match_sample_field_id); 511 } 512 if (num != idx) { 513 rte_errno = EINVAL; 514 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 515 return -rte_errno; 516 } 517 return ret; 518 } 519 520 521 struct mlx5_devx_obj * 522 mlx5_devx_cmd_create_flex_parser(void *ctx, 523 struct mlx5_devx_graph_node_attr *data) 524 { 525 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 526 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 527 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 528 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 529 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 530 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 531 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 532 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 533 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 534 uint32_t i; 535 536 if (!parse_flex_obj) { 537 DRV_LOG(ERR, "Failed to allocate flex parser data."); 538 rte_errno = ENOMEM; 539 return NULL; 540 } 541 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 542 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 543 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 544 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 545 MLX5_SET(parse_graph_flex, flex, header_length_mode, 546 data->header_length_mode); 547 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 548 data->header_length_base_value); 549 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 550 data->header_length_field_offset); 551 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 552 data->header_length_field_shift); 553 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 554 data->header_length_field_mask); 555 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 556 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 557 void *s_off = (void *)((char *)sample + i * 558 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 559 560 if (!s->flow_match_sample_en) 561 continue; 562 MLX5_SET(parse_graph_flow_match_sample, s_off, 563 flow_match_sample_en, !!s->flow_match_sample_en); 564 MLX5_SET(parse_graph_flow_match_sample, s_off, 565 flow_match_sample_field_offset, 566 s->flow_match_sample_field_offset); 567 MLX5_SET(parse_graph_flow_match_sample, s_off, 568 flow_match_sample_offset_mode, 569 s->flow_match_sample_offset_mode); 570 MLX5_SET(parse_graph_flow_match_sample, s_off, 571 flow_match_sample_field_offset_mask, 572 s->flow_match_sample_field_offset_mask); 573 MLX5_SET(parse_graph_flow_match_sample, s_off, 574 flow_match_sample_field_offset_shift, 575 s->flow_match_sample_field_offset_shift); 576 MLX5_SET(parse_graph_flow_match_sample, s_off, 577 flow_match_sample_field_base_offset, 578 s->flow_match_sample_field_base_offset); 579 MLX5_SET(parse_graph_flow_match_sample, s_off, 580 flow_match_sample_tunnel_mode, 581 s->flow_match_sample_tunnel_mode); 582 } 583 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 584 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 585 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 586 void *in_off = (void *)((char *)in_arc + i * 587 MLX5_ST_SZ_BYTES(parse_graph_arc)); 588 void *out_off = (void *)((char *)out_arc + i * 589 MLX5_ST_SZ_BYTES(parse_graph_arc)); 590 591 if (ia->arc_parse_graph_node != 0) { 592 MLX5_SET(parse_graph_arc, in_off, 593 compare_condition_value, 594 ia->compare_condition_value); 595 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 596 ia->start_inner_tunnel); 597 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 598 ia->arc_parse_graph_node); 599 MLX5_SET(parse_graph_arc, in_off, 600 parse_graph_node_handle, 601 ia->parse_graph_node_handle); 602 } 603 if (oa->arc_parse_graph_node != 0) { 604 MLX5_SET(parse_graph_arc, out_off, 605 compare_condition_value, 606 oa->compare_condition_value); 607 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 608 oa->start_inner_tunnel); 609 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 610 oa->arc_parse_graph_node); 611 MLX5_SET(parse_graph_arc, out_off, 612 parse_graph_node_handle, 613 oa->parse_graph_node_handle); 614 } 615 } 616 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 617 out, sizeof(out)); 618 if (!parse_flex_obj->obj) { 619 rte_errno = errno; 620 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 621 "by using DevX."); 622 mlx5_free(parse_flex_obj); 623 return NULL; 624 } 625 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 626 return parse_flex_obj; 627 } 628 629 /** 630 * Query HCA attributes. 631 * Using those attributes we can check on run time if the device 632 * is having the required capabilities. 633 * 634 * @param[in] ctx 635 * Context returned from mlx5 open_device() glue function. 636 * @param[out] attr 637 * Attributes device values. 638 * 639 * @return 640 * 0 on success, a negative value otherwise. 641 */ 642 int 643 mlx5_devx_cmd_query_hca_attr(void *ctx, 644 struct mlx5_hca_attr *attr) 645 { 646 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 647 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 648 void *hcattr; 649 int status, syndrome, rc, i; 650 651 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 652 MLX5_SET(query_hca_cap_in, in, op_mod, 653 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 654 MLX5_HCA_CAP_OPMOD_GET_CUR); 655 656 rc = mlx5_glue->devx_general_cmd(ctx, 657 in, sizeof(in), out, sizeof(out)); 658 if (rc) 659 goto error; 660 status = MLX5_GET(query_hca_cap_out, out, status); 661 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 662 if (status) { 663 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 664 "status %x, syndrome = %x", status, syndrome); 665 return -1; 666 } 667 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 668 attr->flow_counter_bulk_alloc_bitmap = 669 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 670 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 671 flow_counters_dump); 672 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 673 log_max_rqt_size); 674 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 675 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 676 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 677 log_max_hairpin_queues); 678 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 679 log_max_hairpin_wq_data_sz); 680 attr->log_max_hairpin_num_packets = MLX5_GET 681 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 682 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 683 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 684 relaxed_ordering_write); 685 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 686 relaxed_ordering_read); 687 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 688 access_register_user); 689 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 690 eth_net_offloads); 691 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 692 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 693 flex_parser_protocols); 694 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 695 max_geneve_tlv_options); 696 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 697 max_geneve_tlv_option_data_len); 698 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 699 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 700 general_obj_types) & 701 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 702 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 703 general_obj_types) & 704 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 705 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 706 general_obj_types) & 707 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 708 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 709 general_obj_types) & 710 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 711 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 712 wqe_index_ignore_cap); 713 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 714 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 715 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 716 log_max_static_sq_wq); 717 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 718 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 719 device_frequency_khz); 720 attr->scatter_fcs_w_decap_disable = 721 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 722 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 723 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 724 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 725 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp); 726 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 727 regexp_num_of_engines); 728 attr->flow_hit_aso = !!(MLX5_GET64(cmd_hca_cap, hcattr, 729 general_obj_types) & 730 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 731 attr->geneve_tlv_opt = !!(MLX5_GET64(cmd_hca_cap, hcattr, 732 general_obj_types) & 733 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 734 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 735 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 736 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 737 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 738 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 739 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 740 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 741 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 742 attr->reg_c_preserve = 743 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 744 attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo); 745 attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress); 746 attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress); 747 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 748 compress_min_block_size); 749 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 750 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 751 log_compress_mmo_size); 752 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 753 log_decompress_mmo_size); 754 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 755 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 756 mini_cqe_resp_flow_tag); 757 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 758 mini_cqe_resp_l3_l4_tag); 759 attr->umr_indirect_mkey_disabled = 760 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 761 attr->umr_modify_entity_size_disabled = 762 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 763 if (attr->qos.sup) { 764 MLX5_SET(query_hca_cap_in, in, op_mod, 765 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 766 MLX5_HCA_CAP_OPMOD_GET_CUR); 767 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 768 out, sizeof(out)); 769 if (rc) 770 goto error; 771 if (status) { 772 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities," 773 " status %x, syndrome = %x", status, syndrome); 774 return -1; 775 } 776 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 777 attr->qos.flow_meter_old = 778 MLX5_GET(qos_cap, hcattr, flow_meter_old); 779 attr->qos.log_max_flow_meter = 780 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 781 attr->qos.flow_meter_reg_c_ids = 782 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 783 attr->qos.flow_meter = 784 MLX5_GET(qos_cap, hcattr, flow_meter); 785 attr->qos.packet_pacing = 786 MLX5_GET(qos_cap, hcattr, packet_pacing); 787 attr->qos.wqe_rate_pp = 788 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 789 if (attr->qos.flow_meter_aso_sup) { 790 attr->qos.log_meter_aso_granularity = 791 MLX5_GET(qos_cap, hcattr, 792 log_meter_aso_granularity); 793 attr->qos.log_meter_aso_max_alloc = 794 MLX5_GET(qos_cap, hcattr, 795 log_meter_aso_max_alloc); 796 attr->qos.log_max_num_meter_aso = 797 MLX5_GET(qos_cap, hcattr, 798 log_max_num_meter_aso); 799 } 800 } 801 if (attr->vdpa.valid) 802 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 803 if (!attr->eth_net_offloads) 804 return 0; 805 806 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 807 memset(in, 0, sizeof(in)); 808 memset(out, 0, sizeof(out)); 809 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 810 MLX5_SET(query_hca_cap_in, in, op_mod, 811 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 812 MLX5_HCA_CAP_OPMOD_GET_CUR); 813 814 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 815 if (rc) 816 goto error; 817 status = MLX5_GET(query_hca_cap_out, out, status); 818 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 819 if (status) { 820 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 821 "status %x, syndrome = %x", status, syndrome); 822 attr->log_max_ft_sampler_num = 0; 823 return -1; 824 } 825 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 826 attr->log_max_ft_sampler_num = 827 MLX5_GET(flow_table_nic_cap, 828 hcattr, flow_table_properties.log_max_ft_sampler_num); 829 830 /* Query HCA offloads for Ethernet protocol. */ 831 memset(in, 0, sizeof(in)); 832 memset(out, 0, sizeof(out)); 833 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 834 MLX5_SET(query_hca_cap_in, in, op_mod, 835 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 836 MLX5_HCA_CAP_OPMOD_GET_CUR); 837 838 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 839 if (rc) { 840 attr->eth_net_offloads = 0; 841 goto error; 842 } 843 status = MLX5_GET(query_hca_cap_out, out, status); 844 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 845 if (status) { 846 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 847 "status %x, syndrome = %x", status, syndrome); 848 attr->eth_net_offloads = 0; 849 return -1; 850 } 851 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 852 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 853 hcattr, wqe_vlan_insert); 854 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 855 lro_cap); 856 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 857 hcattr, tunnel_lro_gre); 858 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 859 hcattr, tunnel_lro_vxlan); 860 attr->lro_max_msg_sz_mode = MLX5_GET 861 (per_protocol_networking_offload_caps, 862 hcattr, lro_max_msg_sz_mode); 863 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 864 attr->lro_timer_supported_periods[i] = 865 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 866 lro_timer_supported_periods[i]); 867 } 868 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 869 hcattr, lro_min_mss_size); 870 attr->tunnel_stateless_geneve_rx = 871 MLX5_GET(per_protocol_networking_offload_caps, 872 hcattr, tunnel_stateless_geneve_rx); 873 attr->geneve_max_opt_len = 874 MLX5_GET(per_protocol_networking_offload_caps, 875 hcattr, max_geneve_opt_len); 876 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 877 hcattr, wqe_inline_mode); 878 attr->tunnel_stateless_gtp = MLX5_GET 879 (per_protocol_networking_offload_caps, 880 hcattr, tunnel_stateless_gtp); 881 attr->rss_ind_tbl_cap = MLX5_GET 882 (per_protocol_networking_offload_caps, 883 hcattr, rss_ind_tbl_cap); 884 /* Query HCA attribute for ROCE. */ 885 if (attr->roce) { 886 memset(in, 0, sizeof(in)); 887 memset(out, 0, sizeof(out)); 888 MLX5_SET(query_hca_cap_in, in, opcode, 889 MLX5_CMD_OP_QUERY_HCA_CAP); 890 MLX5_SET(query_hca_cap_in, in, op_mod, 891 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 892 MLX5_HCA_CAP_OPMOD_GET_CUR); 893 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 894 out, sizeof(out)); 895 if (rc) 896 goto error; 897 status = MLX5_GET(query_hca_cap_out, out, status); 898 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 899 if (status) { 900 DRV_LOG(DEBUG, 901 "Failed to query devx HCA ROCE capabilities, " 902 "status %x, syndrome = %x", status, syndrome); 903 return -1; 904 } 905 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 906 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 907 } 908 if (attr->eth_virt && 909 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 910 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 911 if (rc) { 912 attr->eth_virt = 0; 913 goto error; 914 } 915 } 916 return 0; 917 error: 918 rc = (rc > 0) ? -rc : rc; 919 return rc; 920 } 921 922 /** 923 * Query TIS transport domain from QP verbs object using DevX API. 924 * 925 * @param[in] qp 926 * Pointer to verbs QP returned by ibv_create_qp . 927 * @param[in] tis_num 928 * TIS number of TIS to query. 929 * @param[out] tis_td 930 * Pointer to TIS transport domain variable, to be set by the routine. 931 * 932 * @return 933 * 0 on success, a negative value otherwise. 934 */ 935 int 936 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 937 uint32_t *tis_td) 938 { 939 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 940 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 941 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 942 int rc; 943 void *tis_ctx; 944 945 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 946 MLX5_SET(query_tis_in, in, tisn, tis_num); 947 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 948 if (rc) { 949 DRV_LOG(ERR, "Failed to query QP using DevX"); 950 return -rc; 951 }; 952 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 953 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 954 return 0; 955 #else 956 (void)qp; 957 (void)tis_num; 958 (void)tis_td; 959 return -ENOTSUP; 960 #endif 961 } 962 963 /** 964 * Fill WQ data for DevX API command. 965 * Utility function for use when creating DevX objects containing a WQ. 966 * 967 * @param[in] wq_ctx 968 * Pointer to WQ context to fill with data. 969 * @param [in] wq_attr 970 * Pointer to WQ attributes structure to fill in WQ context. 971 */ 972 static void 973 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 974 { 975 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 976 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 977 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 978 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 979 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 980 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 981 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 982 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 983 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 984 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 985 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 986 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 987 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 988 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 989 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 990 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 991 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 992 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 993 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 994 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 995 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 996 wq_attr->log_hairpin_num_packets); 997 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 998 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 999 wq_attr->single_wqe_log_num_of_strides); 1000 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1001 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1002 wq_attr->single_stride_log_num_of_bytes); 1003 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1004 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1005 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1006 } 1007 1008 /** 1009 * Create RQ using DevX API. 1010 * 1011 * @param[in] ctx 1012 * Context returned from mlx5 open_device() glue function. 1013 * @param [in] rq_attr 1014 * Pointer to create RQ attributes structure. 1015 * @param [in] socket 1016 * CPU socket ID for allocations. 1017 * 1018 * @return 1019 * The DevX object created, NULL otherwise and rte_errno is set. 1020 */ 1021 struct mlx5_devx_obj * 1022 mlx5_devx_cmd_create_rq(void *ctx, 1023 struct mlx5_devx_create_rq_attr *rq_attr, 1024 int socket) 1025 { 1026 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1027 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1028 void *rq_ctx, *wq_ctx; 1029 struct mlx5_devx_wq_attr *wq_attr; 1030 struct mlx5_devx_obj *rq = NULL; 1031 1032 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1033 if (!rq) { 1034 DRV_LOG(ERR, "Failed to allocate RQ data"); 1035 rte_errno = ENOMEM; 1036 return NULL; 1037 } 1038 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1039 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1040 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1041 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1042 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1043 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1044 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1045 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1046 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1047 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1048 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1049 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1050 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1051 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1052 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1053 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1054 wq_attr = &rq_attr->wq_attr; 1055 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1056 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1057 out, sizeof(out)); 1058 if (!rq->obj) { 1059 DRV_LOG(ERR, "Failed to create RQ using DevX"); 1060 rte_errno = errno; 1061 mlx5_free(rq); 1062 return NULL; 1063 } 1064 rq->id = MLX5_GET(create_rq_out, out, rqn); 1065 return rq; 1066 } 1067 1068 /** 1069 * Modify RQ using DevX API. 1070 * 1071 * @param[in] rq 1072 * Pointer to RQ object structure. 1073 * @param [in] rq_attr 1074 * Pointer to modify RQ attributes structure. 1075 * 1076 * @return 1077 * 0 on success, a negative errno value otherwise and rte_errno is set. 1078 */ 1079 int 1080 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1081 struct mlx5_devx_modify_rq_attr *rq_attr) 1082 { 1083 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1084 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1085 void *rq_ctx, *wq_ctx; 1086 int ret; 1087 1088 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1089 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1090 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1091 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1092 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1093 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1094 if (rq_attr->modify_bitmask & 1095 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1096 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1097 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1098 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1099 if (rq_attr->modify_bitmask & 1100 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1101 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1102 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1103 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1104 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1105 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1106 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1107 } 1108 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1109 out, sizeof(out)); 1110 if (ret) { 1111 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1112 rte_errno = errno; 1113 return -errno; 1114 } 1115 return ret; 1116 } 1117 1118 /** 1119 * Create TIR using DevX API. 1120 * 1121 * @param[in] ctx 1122 * Context returned from mlx5 open_device() glue function. 1123 * @param [in] tir_attr 1124 * Pointer to TIR attributes structure. 1125 * 1126 * @return 1127 * The DevX object created, NULL otherwise and rte_errno is set. 1128 */ 1129 struct mlx5_devx_obj * 1130 mlx5_devx_cmd_create_tir(void *ctx, 1131 struct mlx5_devx_tir_attr *tir_attr) 1132 { 1133 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1134 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1135 void *tir_ctx, *outer, *inner, *rss_key; 1136 struct mlx5_devx_obj *tir = NULL; 1137 1138 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1139 if (!tir) { 1140 DRV_LOG(ERR, "Failed to allocate TIR data"); 1141 rte_errno = ENOMEM; 1142 return NULL; 1143 } 1144 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1145 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1146 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1147 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1148 tir_attr->lro_timeout_period_usecs); 1149 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1150 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1151 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1152 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1153 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1154 tir_attr->tunneled_offload_en); 1155 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1156 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1157 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1158 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1159 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1160 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1161 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1162 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1163 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1164 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1165 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1166 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1167 tir_attr->rx_hash_field_selector_outer.selected_fields); 1168 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1169 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1170 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1171 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1172 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1173 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1174 tir_attr->rx_hash_field_selector_inner.selected_fields); 1175 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1176 out, sizeof(out)); 1177 if (!tir->obj) { 1178 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1179 rte_errno = errno; 1180 mlx5_free(tir); 1181 return NULL; 1182 } 1183 tir->id = MLX5_GET(create_tir_out, out, tirn); 1184 return tir; 1185 } 1186 1187 /** 1188 * Modify TIR using DevX API. 1189 * 1190 * @param[in] tir 1191 * Pointer to TIR DevX object structure. 1192 * @param [in] modify_tir_attr 1193 * Pointer to TIR modification attributes structure. 1194 * 1195 * @return 1196 * 0 on success, a negative errno value otherwise and rte_errno is set. 1197 */ 1198 int 1199 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1200 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1201 { 1202 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1203 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1204 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1205 void *tir_ctx; 1206 int ret; 1207 1208 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1209 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1210 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1211 modify_tir_attr->modify_bitmask); 1212 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1213 if (modify_tir_attr->modify_bitmask & 1214 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1215 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1216 tir_attr->lro_timeout_period_usecs); 1217 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1218 tir_attr->lro_enable_mask); 1219 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1220 tir_attr->lro_max_msg_sz); 1221 } 1222 if (modify_tir_attr->modify_bitmask & 1223 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1224 MLX5_SET(tirc, tir_ctx, indirect_table, 1225 tir_attr->indirect_table); 1226 if (modify_tir_attr->modify_bitmask & 1227 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1228 int i; 1229 void *outer, *inner; 1230 1231 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1232 tir_attr->rx_hash_symmetric); 1233 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1234 for (i = 0; i < 10; i++) { 1235 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1236 tir_attr->rx_hash_toeplitz_key[i]); 1237 } 1238 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1239 rx_hash_field_selector_outer); 1240 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1241 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1242 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1243 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1244 MLX5_SET 1245 (rx_hash_field_select, outer, selected_fields, 1246 tir_attr->rx_hash_field_selector_outer.selected_fields); 1247 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1248 rx_hash_field_selector_inner); 1249 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1250 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1251 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1252 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1253 MLX5_SET 1254 (rx_hash_field_select, inner, selected_fields, 1255 tir_attr->rx_hash_field_selector_inner.selected_fields); 1256 } 1257 if (modify_tir_attr->modify_bitmask & 1258 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1259 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1260 } 1261 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1262 out, sizeof(out)); 1263 if (ret) { 1264 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1265 rte_errno = errno; 1266 return -errno; 1267 } 1268 return ret; 1269 } 1270 1271 /** 1272 * Create RQT using DevX API. 1273 * 1274 * @param[in] ctx 1275 * Context returned from mlx5 open_device() glue function. 1276 * @param [in] rqt_attr 1277 * Pointer to RQT attributes structure. 1278 * 1279 * @return 1280 * The DevX object created, NULL otherwise and rte_errno is set. 1281 */ 1282 struct mlx5_devx_obj * 1283 mlx5_devx_cmd_create_rqt(void *ctx, 1284 struct mlx5_devx_rqt_attr *rqt_attr) 1285 { 1286 uint32_t *in = NULL; 1287 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1288 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1289 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1290 void *rqt_ctx; 1291 struct mlx5_devx_obj *rqt = NULL; 1292 int i; 1293 1294 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1295 if (!in) { 1296 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1297 rte_errno = ENOMEM; 1298 return NULL; 1299 } 1300 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1301 if (!rqt) { 1302 DRV_LOG(ERR, "Failed to allocate RQT data"); 1303 rte_errno = ENOMEM; 1304 mlx5_free(in); 1305 return NULL; 1306 } 1307 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1308 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1309 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1310 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1311 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1312 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1313 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1314 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1315 mlx5_free(in); 1316 if (!rqt->obj) { 1317 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1318 rte_errno = errno; 1319 mlx5_free(rqt); 1320 return NULL; 1321 } 1322 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1323 return rqt; 1324 } 1325 1326 /** 1327 * Modify RQT using DevX API. 1328 * 1329 * @param[in] rqt 1330 * Pointer to RQT DevX object structure. 1331 * @param [in] rqt_attr 1332 * Pointer to RQT attributes structure. 1333 * 1334 * @return 1335 * 0 on success, a negative errno value otherwise and rte_errno is set. 1336 */ 1337 int 1338 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1339 struct mlx5_devx_rqt_attr *rqt_attr) 1340 { 1341 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1342 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1343 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1344 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1345 void *rqt_ctx; 1346 int i; 1347 int ret; 1348 1349 if (!in) { 1350 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1351 rte_errno = ENOMEM; 1352 return -ENOMEM; 1353 } 1354 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1355 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1356 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1357 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1358 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1359 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1360 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1361 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1362 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1363 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1364 mlx5_free(in); 1365 if (ret) { 1366 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1367 rte_errno = errno; 1368 return -rte_errno; 1369 } 1370 return ret; 1371 } 1372 1373 /** 1374 * Create SQ using DevX API. 1375 * 1376 * @param[in] ctx 1377 * Context returned from mlx5 open_device() glue function. 1378 * @param [in] sq_attr 1379 * Pointer to SQ attributes structure. 1380 * @param [in] socket 1381 * CPU socket ID for allocations. 1382 * 1383 * @return 1384 * The DevX object created, NULL otherwise and rte_errno is set. 1385 **/ 1386 struct mlx5_devx_obj * 1387 mlx5_devx_cmd_create_sq(void *ctx, 1388 struct mlx5_devx_create_sq_attr *sq_attr) 1389 { 1390 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1391 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1392 void *sq_ctx; 1393 void *wq_ctx; 1394 struct mlx5_devx_wq_attr *wq_attr; 1395 struct mlx5_devx_obj *sq = NULL; 1396 1397 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1398 if (!sq) { 1399 DRV_LOG(ERR, "Failed to allocate SQ data"); 1400 rte_errno = ENOMEM; 1401 return NULL; 1402 } 1403 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1404 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1405 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1406 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1407 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1408 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1409 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1410 sq_attr->allow_multi_pkt_send_wqe); 1411 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1412 sq_attr->min_wqe_inline_mode); 1413 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1414 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1415 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1416 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1417 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1418 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1419 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1420 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1421 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1422 sq_attr->packet_pacing_rate_limit_index); 1423 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1424 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1425 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1426 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1427 wq_attr = &sq_attr->wq_attr; 1428 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1429 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1430 out, sizeof(out)); 1431 if (!sq->obj) { 1432 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1433 rte_errno = errno; 1434 mlx5_free(sq); 1435 return NULL; 1436 } 1437 sq->id = MLX5_GET(create_sq_out, out, sqn); 1438 return sq; 1439 } 1440 1441 /** 1442 * Modify SQ using DevX API. 1443 * 1444 * @param[in] sq 1445 * Pointer to SQ object structure. 1446 * @param [in] sq_attr 1447 * Pointer to SQ attributes structure. 1448 * 1449 * @return 1450 * 0 on success, a negative errno value otherwise and rte_errno is set. 1451 */ 1452 int 1453 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1454 struct mlx5_devx_modify_sq_attr *sq_attr) 1455 { 1456 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1457 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1458 void *sq_ctx; 1459 int ret; 1460 1461 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1462 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1463 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1464 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1465 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1466 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1467 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1468 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1469 out, sizeof(out)); 1470 if (ret) { 1471 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1472 rte_errno = errno; 1473 return -rte_errno; 1474 } 1475 return ret; 1476 } 1477 1478 /** 1479 * Create TIS using DevX API. 1480 * 1481 * @param[in] ctx 1482 * Context returned from mlx5 open_device() glue function. 1483 * @param [in] tis_attr 1484 * Pointer to TIS attributes structure. 1485 * 1486 * @return 1487 * The DevX object created, NULL otherwise and rte_errno is set. 1488 */ 1489 struct mlx5_devx_obj * 1490 mlx5_devx_cmd_create_tis(void *ctx, 1491 struct mlx5_devx_tis_attr *tis_attr) 1492 { 1493 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1494 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1495 struct mlx5_devx_obj *tis = NULL; 1496 void *tis_ctx; 1497 1498 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1499 if (!tis) { 1500 DRV_LOG(ERR, "Failed to allocate TIS object"); 1501 rte_errno = ENOMEM; 1502 return NULL; 1503 } 1504 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1505 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1506 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1507 tis_attr->strict_lag_tx_port_affinity); 1508 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1509 tis_attr->lag_tx_port_affinity); 1510 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1511 MLX5_SET(tisc, tis_ctx, transport_domain, 1512 tis_attr->transport_domain); 1513 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1514 out, sizeof(out)); 1515 if (!tis->obj) { 1516 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1517 rte_errno = errno; 1518 mlx5_free(tis); 1519 return NULL; 1520 } 1521 tis->id = MLX5_GET(create_tis_out, out, tisn); 1522 return tis; 1523 } 1524 1525 /** 1526 * Create transport domain using DevX API. 1527 * 1528 * @param[in] ctx 1529 * Context returned from mlx5 open_device() glue function. 1530 * @return 1531 * The DevX object created, NULL otherwise and rte_errno is set. 1532 */ 1533 struct mlx5_devx_obj * 1534 mlx5_devx_cmd_create_td(void *ctx) 1535 { 1536 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1537 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1538 struct mlx5_devx_obj *td = NULL; 1539 1540 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1541 if (!td) { 1542 DRV_LOG(ERR, "Failed to allocate TD object"); 1543 rte_errno = ENOMEM; 1544 return NULL; 1545 } 1546 MLX5_SET(alloc_transport_domain_in, in, opcode, 1547 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1548 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1549 out, sizeof(out)); 1550 if (!td->obj) { 1551 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1552 rte_errno = errno; 1553 mlx5_free(td); 1554 return NULL; 1555 } 1556 td->id = MLX5_GET(alloc_transport_domain_out, out, 1557 transport_domain); 1558 return td; 1559 } 1560 1561 /** 1562 * Dump all flows to file. 1563 * 1564 * @param[in] fdb_domain 1565 * FDB domain. 1566 * @param[in] rx_domain 1567 * RX domain. 1568 * @param[in] tx_domain 1569 * TX domain. 1570 * @param[out] file 1571 * Pointer to file stream. 1572 * 1573 * @return 1574 * 0 on success, a nagative value otherwise. 1575 */ 1576 int 1577 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1578 void *rx_domain __rte_unused, 1579 void *tx_domain __rte_unused, FILE *file __rte_unused) 1580 { 1581 int ret = 0; 1582 1583 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1584 if (fdb_domain) { 1585 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1586 if (ret) 1587 return ret; 1588 } 1589 MLX5_ASSERT(rx_domain); 1590 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1591 if (ret) 1592 return ret; 1593 MLX5_ASSERT(tx_domain); 1594 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1595 #else 1596 ret = ENOTSUP; 1597 #endif 1598 return -ret; 1599 } 1600 1601 int 1602 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 1603 FILE *file __rte_unused) 1604 { 1605 int ret = 0; 1606 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 1607 if (rule_info) 1608 ret = mlx5_glue->dr_dump_rule(file, rule_info); 1609 #else 1610 ret = ENOTSUP; 1611 #endif 1612 return -ret; 1613 } 1614 1615 /* 1616 * Create CQ using DevX API. 1617 * 1618 * @param[in] ctx 1619 * Context returned from mlx5 open_device() glue function. 1620 * @param [in] attr 1621 * Pointer to CQ attributes structure. 1622 * 1623 * @return 1624 * The DevX object created, NULL otherwise and rte_errno is set. 1625 */ 1626 struct mlx5_devx_obj * 1627 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1628 { 1629 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1630 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1631 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1632 sizeof(*cq_obj), 1633 0, SOCKET_ID_ANY); 1634 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1635 1636 if (!cq_obj) { 1637 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1638 rte_errno = ENOMEM; 1639 return NULL; 1640 } 1641 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1642 if (attr->db_umem_valid) { 1643 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1644 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1645 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1646 } else { 1647 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1648 } 1649 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1650 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1651 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1652 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1653 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1654 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1655 MLX5_SET(cqc, cqctx, log_page_size, 1656 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1657 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1658 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1659 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1660 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1661 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1662 attr->mini_cqe_res_format_ext); 1663 if (attr->q_umem_valid) { 1664 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1665 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1666 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1667 attr->q_umem_offset); 1668 } 1669 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1670 sizeof(out)); 1671 if (!cq_obj->obj) { 1672 rte_errno = errno; 1673 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1674 mlx5_free(cq_obj); 1675 return NULL; 1676 } 1677 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1678 return cq_obj; 1679 } 1680 1681 /** 1682 * Create VIRTQ using DevX API. 1683 * 1684 * @param[in] ctx 1685 * Context returned from mlx5 open_device() glue function. 1686 * @param [in] attr 1687 * Pointer to VIRTQ attributes structure. 1688 * 1689 * @return 1690 * The DevX object created, NULL otherwise and rte_errno is set. 1691 */ 1692 struct mlx5_devx_obj * 1693 mlx5_devx_cmd_create_virtq(void *ctx, 1694 struct mlx5_devx_virtq_attr *attr) 1695 { 1696 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1697 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1698 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1699 sizeof(*virtq_obj), 1700 0, SOCKET_ID_ANY); 1701 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1702 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1703 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1704 1705 if (!virtq_obj) { 1706 DRV_LOG(ERR, "Failed to allocate virtq data."); 1707 rte_errno = ENOMEM; 1708 return NULL; 1709 } 1710 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1711 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1712 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1713 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1714 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1715 attr->hw_available_index); 1716 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1717 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1718 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1719 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1720 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1721 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1722 attr->virtio_version_1_0); 1723 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1724 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1725 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1726 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1727 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1728 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1729 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1730 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1731 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1732 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 1733 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 1734 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 1735 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 1736 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 1737 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 1738 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 1739 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 1740 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 1741 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 1742 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 1743 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 1744 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 1745 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 1746 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1747 sizeof(out)); 1748 if (!virtq_obj->obj) { 1749 rte_errno = errno; 1750 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 1751 mlx5_free(virtq_obj); 1752 return NULL; 1753 } 1754 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1755 return virtq_obj; 1756 } 1757 1758 /** 1759 * Modify VIRTQ using DevX API. 1760 * 1761 * @param[in] virtq_obj 1762 * Pointer to virtq object structure. 1763 * @param [in] attr 1764 * Pointer to modify virtq attributes structure. 1765 * 1766 * @return 1767 * 0 on success, a negative errno value otherwise and rte_errno is set. 1768 */ 1769 int 1770 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 1771 struct mlx5_devx_virtq_attr *attr) 1772 { 1773 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1774 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1775 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1776 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1777 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1778 int ret; 1779 1780 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1781 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 1782 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1783 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1784 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1785 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 1786 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1787 switch (attr->type) { 1788 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 1789 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 1790 break; 1791 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 1792 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 1793 attr->dirty_bitmap_mkey); 1794 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 1795 attr->dirty_bitmap_addr); 1796 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 1797 attr->dirty_bitmap_size); 1798 break; 1799 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 1800 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 1801 attr->dirty_bitmap_dump_enable); 1802 break; 1803 default: 1804 rte_errno = EINVAL; 1805 return -rte_errno; 1806 } 1807 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 1808 out, sizeof(out)); 1809 if (ret) { 1810 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1811 rte_errno = errno; 1812 return -rte_errno; 1813 } 1814 return ret; 1815 } 1816 1817 /** 1818 * Query VIRTQ using DevX API. 1819 * 1820 * @param[in] virtq_obj 1821 * Pointer to virtq object structure. 1822 * @param [in/out] attr 1823 * Pointer to virtq attributes structure. 1824 * 1825 * @return 1826 * 0 on success, a negative errno value otherwise and rte_errno is set. 1827 */ 1828 int 1829 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 1830 struct mlx5_devx_virtq_attr *attr) 1831 { 1832 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1833 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 1834 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 1835 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 1836 int ret; 1837 1838 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1839 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1840 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1841 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1842 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1843 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 1844 out, sizeof(out)); 1845 if (ret) { 1846 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1847 rte_errno = errno; 1848 return -errno; 1849 } 1850 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 1851 hw_available_index); 1852 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 1853 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 1854 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 1855 virtio_q_context.error_type); 1856 return ret; 1857 } 1858 1859 /** 1860 * Create QP using DevX API. 1861 * 1862 * @param[in] ctx 1863 * Context returned from mlx5 open_device() glue function. 1864 * @param [in] attr 1865 * Pointer to QP attributes structure. 1866 * 1867 * @return 1868 * The DevX object created, NULL otherwise and rte_errno is set. 1869 */ 1870 struct mlx5_devx_obj * 1871 mlx5_devx_cmd_create_qp(void *ctx, 1872 struct mlx5_devx_qp_attr *attr) 1873 { 1874 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 1875 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 1876 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 1877 sizeof(*qp_obj), 1878 0, SOCKET_ID_ANY); 1879 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1880 1881 if (!qp_obj) { 1882 DRV_LOG(ERR, "Failed to allocate QP data."); 1883 rte_errno = ENOMEM; 1884 return NULL; 1885 } 1886 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 1887 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 1888 MLX5_SET(qpc, qpc, pd, attr->pd); 1889 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 1890 if (attr->uar_index) { 1891 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1892 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 1893 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1894 MLX5_SET(qpc, qpc, log_page_size, 1895 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1896 if (attr->sq_size) { 1897 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); 1898 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 1899 MLX5_SET(qpc, qpc, log_sq_size, 1900 rte_log2_u32(attr->sq_size)); 1901 } else { 1902 MLX5_SET(qpc, qpc, no_sq, 1); 1903 } 1904 if (attr->rq_size) { 1905 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); 1906 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 1907 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 1908 MLX5_LOG_RQ_STRIDE_SHIFT); 1909 MLX5_SET(qpc, qpc, log_rq_size, 1910 rte_log2_u32(attr->rq_size)); 1911 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 1912 } else { 1913 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1914 } 1915 if (attr->dbr_umem_valid) { 1916 MLX5_SET(qpc, qpc, dbr_umem_valid, 1917 attr->dbr_umem_valid); 1918 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 1919 } 1920 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 1921 MLX5_SET64(create_qp_in, in, wq_umem_offset, 1922 attr->wq_umem_offset); 1923 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 1924 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 1925 } else { 1926 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 1927 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1928 MLX5_SET(qpc, qpc, no_sq, 1); 1929 } 1930 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1931 sizeof(out)); 1932 if (!qp_obj->obj) { 1933 rte_errno = errno; 1934 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 1935 mlx5_free(qp_obj); 1936 return NULL; 1937 } 1938 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 1939 return qp_obj; 1940 } 1941 1942 /** 1943 * Modify QP using DevX API. 1944 * Currently supports only force loop-back QP. 1945 * 1946 * @param[in] qp 1947 * Pointer to QP object structure. 1948 * @param [in] qp_st_mod_op 1949 * The QP state modification operation. 1950 * @param [in] remote_qp_id 1951 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 1952 * 1953 * @return 1954 * 0 on success, a negative errno value otherwise and rte_errno is set. 1955 */ 1956 int 1957 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 1958 uint32_t remote_qp_id) 1959 { 1960 union { 1961 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 1962 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 1963 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 1964 } in; 1965 union { 1966 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 1967 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 1968 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 1969 } out; 1970 void *qpc; 1971 int ret; 1972 unsigned int inlen; 1973 unsigned int outlen; 1974 1975 memset(&in, 0, sizeof(in)); 1976 memset(&out, 0, sizeof(out)); 1977 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 1978 switch (qp_st_mod_op) { 1979 case MLX5_CMD_OP_RST2INIT_QP: 1980 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 1981 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 1982 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1983 MLX5_SET(qpc, qpc, rre, 1); 1984 MLX5_SET(qpc, qpc, rwe, 1); 1985 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1986 inlen = sizeof(in.rst2init); 1987 outlen = sizeof(out.rst2init); 1988 break; 1989 case MLX5_CMD_OP_INIT2RTR_QP: 1990 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 1991 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 1992 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 1993 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1994 MLX5_SET(qpc, qpc, mtu, 1); 1995 MLX5_SET(qpc, qpc, log_msg_max, 30); 1996 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 1997 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 1998 inlen = sizeof(in.init2rtr); 1999 outlen = sizeof(out.init2rtr); 2000 break; 2001 case MLX5_CMD_OP_RTR2RTS_QP: 2002 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2003 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2004 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 2005 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2006 MLX5_SET(qpc, qpc, retry_count, 7); 2007 MLX5_SET(qpc, qpc, rnr_retry, 7); 2008 inlen = sizeof(in.rtr2rts); 2009 outlen = sizeof(out.rtr2rts); 2010 break; 2011 default: 2012 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2013 qp_st_mod_op); 2014 rte_errno = EINVAL; 2015 return -rte_errno; 2016 } 2017 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2018 if (ret) { 2019 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2020 rte_errno = errno; 2021 return -rte_errno; 2022 } 2023 return ret; 2024 } 2025 2026 struct mlx5_devx_obj * 2027 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2028 { 2029 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2030 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2031 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2032 sizeof(*couners_obj), 0, 2033 SOCKET_ID_ANY); 2034 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2035 2036 if (!couners_obj) { 2037 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2038 rte_errno = ENOMEM; 2039 return NULL; 2040 } 2041 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2042 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2043 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2044 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2045 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2046 sizeof(out)); 2047 if (!couners_obj->obj) { 2048 rte_errno = errno; 2049 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 2050 " DevX."); 2051 mlx5_free(couners_obj); 2052 return NULL; 2053 } 2054 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2055 return couners_obj; 2056 } 2057 2058 int 2059 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2060 struct mlx5_devx_virtio_q_couners_attr *attr) 2061 { 2062 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2063 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2064 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2065 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2066 virtio_q_counters); 2067 int ret; 2068 2069 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2070 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2071 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2072 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2073 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2074 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2075 sizeof(out)); 2076 if (ret) { 2077 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2078 rte_errno = errno; 2079 return -errno; 2080 } 2081 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2082 received_desc); 2083 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2084 completed_desc); 2085 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2086 error_cqes); 2087 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2088 bad_desc_errors); 2089 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2090 exceed_max_chain); 2091 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2092 invalid_buffer); 2093 return ret; 2094 } 2095 2096 /** 2097 * Create general object of type FLOW_HIT_ASO using DevX API. 2098 * 2099 * @param[in] ctx 2100 * Context returned from mlx5 open_device() glue function. 2101 * @param [in] pd 2102 * PD value to associate the FLOW_HIT_ASO object with. 2103 * 2104 * @return 2105 * The DevX object created, NULL otherwise and rte_errno is set. 2106 */ 2107 struct mlx5_devx_obj * 2108 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2109 { 2110 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2111 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2112 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2113 void *ptr = NULL; 2114 2115 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2116 0, SOCKET_ID_ANY); 2117 if (!flow_hit_aso_obj) { 2118 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2119 rte_errno = ENOMEM; 2120 return NULL; 2121 } 2122 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2123 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2124 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2125 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2126 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2127 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2128 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2129 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2130 out, sizeof(out)); 2131 if (!flow_hit_aso_obj->obj) { 2132 rte_errno = errno; 2133 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX."); 2134 mlx5_free(flow_hit_aso_obj); 2135 return NULL; 2136 } 2137 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2138 return flow_hit_aso_obj; 2139 } 2140 2141 /* 2142 * Create PD using DevX API. 2143 * 2144 * @param[in] ctx 2145 * Context returned from mlx5 open_device() glue function. 2146 * 2147 * @return 2148 * The DevX object created, NULL otherwise and rte_errno is set. 2149 */ 2150 struct mlx5_devx_obj * 2151 mlx5_devx_cmd_alloc_pd(void *ctx) 2152 { 2153 struct mlx5_devx_obj *ppd = 2154 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2155 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2156 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2157 2158 if (!ppd) { 2159 DRV_LOG(ERR, "Failed to allocate PD data."); 2160 rte_errno = ENOMEM; 2161 return NULL; 2162 } 2163 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2164 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2165 out, sizeof(out)); 2166 if (!ppd->obj) { 2167 mlx5_free(ppd); 2168 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2169 rte_errno = errno; 2170 return NULL; 2171 } 2172 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2173 return ppd; 2174 } 2175 2176 /** 2177 * Create general object of type FLOW_METER_ASO using DevX API. 2178 * 2179 * @param[in] ctx 2180 * Context returned from mlx5 open_device() glue function. 2181 * @param [in] pd 2182 * PD value to associate the FLOW_METER_ASO object with. 2183 * @param [in] log_obj_size 2184 * log_obj_size define to allocate number of 2 * meters 2185 * in one FLOW_METER_ASO object. 2186 * 2187 * @return 2188 * The DevX object created, NULL otherwise and rte_errno is set. 2189 */ 2190 struct mlx5_devx_obj * 2191 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2192 uint32_t log_obj_size) 2193 { 2194 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2195 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2196 struct mlx5_devx_obj *flow_meter_aso_obj; 2197 void *ptr; 2198 2199 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2200 sizeof(*flow_meter_aso_obj), 2201 0, SOCKET_ID_ANY); 2202 if (!flow_meter_aso_obj) { 2203 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2204 rte_errno = ENOMEM; 2205 return NULL; 2206 } 2207 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2208 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2209 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2210 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2211 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2212 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2213 log_obj_size); 2214 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2215 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2216 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2217 ctx, in, sizeof(in), 2218 out, sizeof(out)); 2219 if (!flow_meter_aso_obj->obj) { 2220 rte_errno = errno; 2221 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX."); 2222 mlx5_free(flow_meter_aso_obj); 2223 return NULL; 2224 } 2225 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2226 out, obj_id); 2227 return flow_meter_aso_obj; 2228 } 2229 2230 /** 2231 * Create general object of type GENEVE TLV option using DevX API. 2232 * 2233 * @param[in] ctx 2234 * Context returned from mlx5 open_device() glue function. 2235 * @param [in] class 2236 * TLV option variable value of class 2237 * @param [in] type 2238 * TLV option variable value of type 2239 * @param [in] len 2240 * TLV option variable value of len 2241 * 2242 * @return 2243 * The DevX object created, NULL otherwise and rte_errno is set. 2244 */ 2245 struct mlx5_devx_obj * 2246 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2247 uint16_t class, uint8_t type, uint8_t len) 2248 { 2249 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2250 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2251 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2252 sizeof(*geneve_tlv_opt_obj), 2253 0, SOCKET_ID_ANY); 2254 2255 if (!geneve_tlv_opt_obj) { 2256 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2257 rte_errno = ENOMEM; 2258 return NULL; 2259 } 2260 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2261 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2262 geneve_tlv_opt); 2263 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2264 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2265 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2266 MLX5_OBJ_TYPE_GENEVE_TLV_OPT); 2267 MLX5_SET(geneve_tlv_option, opt, option_class, 2268 rte_be_to_cpu_16(class)); 2269 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2270 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2271 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2272 sizeof(in), out, sizeof(out)); 2273 if (!geneve_tlv_opt_obj->obj) { 2274 rte_errno = errno; 2275 DRV_LOG(ERR, "Failed to create Geneve tlv option " 2276 "Obj using DevX."); 2277 mlx5_free(geneve_tlv_opt_obj); 2278 return NULL; 2279 } 2280 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2281 return geneve_tlv_opt_obj; 2282 } 2283 2284 int 2285 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2286 { 2287 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2288 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2289 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2290 int rc; 2291 void *rq_ctx; 2292 2293 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2294 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2295 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2296 if (rc) { 2297 rte_errno = errno; 2298 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2299 "rc = %d, errno = %d.", rc, errno); 2300 return -rc; 2301 }; 2302 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2303 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2304 return 0; 2305 #else 2306 (void)wq; 2307 (void)counter_set_id; 2308 return -ENOTSUP; 2309 #endif 2310 } 2311 2312 /* 2313 * Allocate queue counters via devx interface. 2314 * 2315 * @param[in] ctx 2316 * Context returned from mlx5 open_device() glue function. 2317 * 2318 * @return 2319 * Pointer to counter object on success, a NULL value otherwise and 2320 * rte_errno is set. 2321 */ 2322 struct mlx5_devx_obj * 2323 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2324 { 2325 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2326 SOCKET_ID_ANY); 2327 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2328 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2329 2330 if (!dcs) { 2331 rte_errno = ENOMEM; 2332 return NULL; 2333 } 2334 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2335 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2336 sizeof(out)); 2337 if (!dcs->obj) { 2338 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error " 2339 "%d.", errno); 2340 rte_errno = errno; 2341 mlx5_free(dcs); 2342 return NULL; 2343 } 2344 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2345 return dcs; 2346 } 2347 2348 /** 2349 * Query queue counters values. 2350 * 2351 * @param[in] dcs 2352 * devx object of the queue counter set. 2353 * @param[in] clear 2354 * Whether hardware should clear the counters after the query or not. 2355 * @param[out] out_of_buffers 2356 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2357 * 2358 * @return 2359 * 0 on success, a negative value otherwise. 2360 */ 2361 int 2362 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2363 uint32_t *out_of_buffers) 2364 { 2365 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2366 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2367 int rc; 2368 2369 MLX5_SET(query_q_counter_in, in, opcode, 2370 MLX5_CMD_OP_QUERY_Q_COUNTER); 2371 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2372 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2373 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2374 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2375 sizeof(out)); 2376 if (rc) { 2377 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2378 rte_errno = rc; 2379 return -rc; 2380 } 2381 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2382 return 0; 2383 } 2384