1 // SPDX-License-Identifier: BSD-3-Clause 2 /* Copyright 2018 Mellanox Technologies, Ltd */ 3 4 #include <unistd.h> 5 6 #include <rte_errno.h> 7 #include <rte_malloc.h> 8 #include <rte_eal_paging.h> 9 10 #include "mlx5_prm.h" 11 #include "mlx5_devx_cmds.h" 12 #include "mlx5_common_utils.h" 13 #include "mlx5_malloc.h" 14 15 16 /** 17 * Perform read access to the registers. Reads data from register 18 * and writes ones to the specified buffer. 19 * 20 * @param[in] ctx 21 * Context returned from mlx5 open_device() glue function. 22 * @param[in] reg_id 23 * Register identifier according to the PRM. 24 * @param[in] arg 25 * Register access auxiliary parameter according to the PRM. 26 * @param[out] data 27 * Pointer to the buffer to store read data. 28 * @param[in] dw_cnt 29 * Buffer size in double words. 30 * 31 * @return 32 * 0 on success, a negative value otherwise. 33 */ 34 int 35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 36 uint32_t *data, uint32_t dw_cnt) 37 { 38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 41 int status, rc; 42 43 MLX5_ASSERT(data && dw_cnt); 44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 46 DRV_LOG(ERR, "Not enough buffer for register read data"); 47 return -1; 48 } 49 MLX5_SET(access_register_in, in, opcode, 50 MLX5_CMD_OP_ACCESS_REGISTER_USER); 51 MLX5_SET(access_register_in, in, op_mod, 52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 53 MLX5_SET(access_register_in, in, register_id, reg_id); 54 MLX5_SET(access_register_in, in, argument, arg); 55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 56 MLX5_ST_SZ_BYTES(access_register_out) + 57 sizeof(uint32_t) * dw_cnt); 58 if (rc) 59 goto error; 60 status = MLX5_GET(access_register_out, out, status); 61 if (status) { 62 int syndrome = MLX5_GET(access_register_out, out, syndrome); 63 64 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, " 65 "status %x, syndrome = %x", 66 reg_id, status, syndrome); 67 return -1; 68 } 69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 70 dw_cnt * sizeof(uint32_t)); 71 return 0; 72 error: 73 rc = (rc > 0) ? -rc : rc; 74 return rc; 75 } 76 77 /** 78 * Allocate flow counters via devx interface. 79 * 80 * @param[in] ctx 81 * Context returned from mlx5 open_device() glue function. 82 * @param dcs 83 * Pointer to counters properties structure to be filled by the routine. 84 * @param bulk_n_128 85 * Bulk counter numbers in 128 counters units. 86 * 87 * @return 88 * Pointer to counter object on success, a negative value otherwise and 89 * rte_errno is set. 90 */ 91 struct mlx5_devx_obj * 92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 93 { 94 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 95 0, SOCKET_ID_ANY); 96 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 97 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 98 99 if (!dcs) { 100 rte_errno = ENOMEM; 101 return NULL; 102 } 103 MLX5_SET(alloc_flow_counter_in, in, opcode, 104 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 105 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 106 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 107 sizeof(in), out, sizeof(out)); 108 if (!dcs->obj) { 109 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 110 rte_errno = errno; 111 mlx5_free(dcs); 112 return NULL; 113 } 114 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 115 return dcs; 116 } 117 118 /** 119 * Query flow counters values. 120 * 121 * @param[in] dcs 122 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 123 * @param[in] clear 124 * Whether hardware should clear the counters after the query or not. 125 * @param[in] n_counters 126 * 0 in case of 1 counter to read, otherwise the counter number to read. 127 * @param pkts 128 * The number of packets that matched the flow. 129 * @param bytes 130 * The number of bytes that matched the flow. 131 * @param mkey 132 * The mkey key for batch query. 133 * @param addr 134 * The address in the mkey range for batch query. 135 * @param cmd_comp 136 * The completion object for asynchronous batch query. 137 * @param async_id 138 * The ID to be returned in the asynchronous batch query response. 139 * 140 * @return 141 * 0 on success, a negative value otherwise. 142 */ 143 int 144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 145 int clear, uint32_t n_counters, 146 uint64_t *pkts, uint64_t *bytes, 147 uint32_t mkey, void *addr, 148 void *cmd_comp, 149 uint64_t async_id) 150 { 151 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 152 MLX5_ST_SZ_BYTES(traffic_counter); 153 uint32_t out[out_len]; 154 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 155 void *stats; 156 int rc; 157 158 MLX5_SET(query_flow_counter_in, in, opcode, 159 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 160 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 161 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 162 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 163 164 if (n_counters) { 165 MLX5_SET(query_flow_counter_in, in, num_of_counters, 166 n_counters); 167 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 168 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 169 MLX5_SET64(query_flow_counter_in, in, address, 170 (uint64_t)(uintptr_t)addr); 171 } 172 if (!cmd_comp) 173 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 174 out_len); 175 else 176 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 177 out_len, async_id, 178 cmd_comp); 179 if (rc) { 180 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 181 rte_errno = rc; 182 return -rc; 183 } 184 if (!n_counters) { 185 stats = MLX5_ADDR_OF(query_flow_counter_out, 186 out, flow_statistics); 187 *pkts = MLX5_GET64(traffic_counter, stats, packets); 188 *bytes = MLX5_GET64(traffic_counter, stats, octets); 189 } 190 return 0; 191 } 192 193 /** 194 * Create a new mkey. 195 * 196 * @param[in] ctx 197 * Context returned from mlx5 open_device() glue function. 198 * @param[in] attr 199 * Attributes of the requested mkey. 200 * 201 * @return 202 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 203 * is set. 204 */ 205 struct mlx5_devx_obj * 206 mlx5_devx_cmd_mkey_create(void *ctx, 207 struct mlx5_devx_mkey_attr *attr) 208 { 209 struct mlx5_klm *klm_array = attr->klm_array; 210 int klm_num = attr->klm_num; 211 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 212 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 213 uint32_t in[in_size_dw]; 214 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 215 void *mkc; 216 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 217 0, SOCKET_ID_ANY); 218 size_t pgsize; 219 uint32_t translation_size; 220 221 if (!mkey) { 222 rte_errno = ENOMEM; 223 return NULL; 224 } 225 memset(in, 0, in_size_dw * 4); 226 pgsize = rte_mem_page_size(); 227 if (pgsize == (size_t)-1) { 228 mlx5_free(mkey); 229 DRV_LOG(ERR, "Failed to get page size"); 230 rte_errno = ENOMEM; 231 return NULL; 232 } 233 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 234 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 235 if (klm_num > 0) { 236 int i; 237 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 238 klm_pas_mtt); 239 translation_size = RTE_ALIGN(klm_num, 4); 240 for (i = 0; i < klm_num; i++) { 241 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 242 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 243 MLX5_SET64(klm, klm, address, klm_array[i].address); 244 klm += MLX5_ST_SZ_BYTES(klm); 245 } 246 for (; i < (int)translation_size; i++) { 247 MLX5_SET(klm, klm, mkey, 0x0); 248 MLX5_SET64(klm, klm, address, 0x0); 249 klm += MLX5_ST_SZ_BYTES(klm); 250 } 251 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 252 MLX5_MKC_ACCESS_MODE_KLM_FBS : 253 MLX5_MKC_ACCESS_MODE_KLM); 254 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 255 } else { 256 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 257 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 258 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 259 } 260 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 261 translation_size); 262 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 263 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 264 MLX5_SET(mkc, mkc, lw, 0x1); 265 MLX5_SET(mkc, mkc, lr, 0x1); 266 MLX5_SET(mkc, mkc, qpn, 0xffffff); 267 MLX5_SET(mkc, mkc, pd, attr->pd); 268 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 269 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 270 MLX5_SET(mkc, mkc, relaxed_ordering_write, 271 attr->relaxed_ordering_write); 272 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 273 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 274 MLX5_SET64(mkc, mkc, len, attr->size); 275 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 276 sizeof(out)); 277 if (!mkey->obj) { 278 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d\n", 279 klm_num ? "an in" : "a ", errno); 280 rte_errno = errno; 281 mlx5_free(mkey); 282 return NULL; 283 } 284 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 285 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 286 return mkey; 287 } 288 289 /** 290 * Get status of devx command response. 291 * Mainly used for asynchronous commands. 292 * 293 * @param[in] out 294 * The out response buffer. 295 * 296 * @return 297 * 0 on success, non-zero value otherwise. 298 */ 299 int 300 mlx5_devx_get_out_command_status(void *out) 301 { 302 int status; 303 304 if (!out) 305 return -EINVAL; 306 status = MLX5_GET(query_flow_counter_out, out, status); 307 if (status) { 308 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 309 310 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 311 syndrome); 312 } 313 return status; 314 } 315 316 /** 317 * Destroy any object allocated by a Devx API. 318 * 319 * @param[in] obj 320 * Pointer to a general object. 321 * 322 * @return 323 * 0 on success, a negative value otherwise. 324 */ 325 int 326 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 327 { 328 int ret; 329 330 if (!obj) 331 return 0; 332 ret = mlx5_glue->devx_obj_destroy(obj->obj); 333 mlx5_free(obj); 334 return ret; 335 } 336 337 /** 338 * Query NIC vport context. 339 * Fills minimal inline attribute. 340 * 341 * @param[in] ctx 342 * ibv contexts returned from mlx5dv_open_device. 343 * @param[in] vport 344 * vport index 345 * @param[out] attr 346 * Attributes device values. 347 * 348 * @return 349 * 0 on success, a negative value otherwise. 350 */ 351 static int 352 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 353 unsigned int vport, 354 struct mlx5_hca_attr *attr) 355 { 356 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 357 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 358 void *vctx; 359 int status, syndrome, rc; 360 361 /* Query NIC vport context to determine inline mode. */ 362 MLX5_SET(query_nic_vport_context_in, in, opcode, 363 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 364 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 365 if (vport) 366 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 367 rc = mlx5_glue->devx_general_cmd(ctx, 368 in, sizeof(in), 369 out, sizeof(out)); 370 if (rc) 371 goto error; 372 status = MLX5_GET(query_nic_vport_context_out, out, status); 373 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 374 if (status) { 375 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 376 "status %x, syndrome = %x", status, syndrome); 377 return -1; 378 } 379 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 380 nic_vport_context); 381 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 382 min_wqe_inline_mode); 383 return 0; 384 error: 385 rc = (rc > 0) ? -rc : rc; 386 return rc; 387 } 388 389 /** 390 * Query NIC vDPA attributes. 391 * 392 * @param[in] ctx 393 * Context returned from mlx5 open_device() glue function. 394 * @param[out] vdpa_attr 395 * vDPA Attributes structure to fill. 396 */ 397 static void 398 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 399 struct mlx5_hca_vdpa_attr *vdpa_attr) 400 { 401 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 402 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 403 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 404 int status, syndrome, rc; 405 406 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 407 MLX5_SET(query_hca_cap_in, in, op_mod, 408 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 409 MLX5_HCA_CAP_OPMOD_GET_CUR); 410 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 411 status = MLX5_GET(query_hca_cap_out, out, status); 412 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 413 if (rc || status) { 414 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities," 415 " status %x, syndrome = %x", status, syndrome); 416 vdpa_attr->valid = 0; 417 } else { 418 vdpa_attr->valid = 1; 419 vdpa_attr->desc_tunnel_offload_type = 420 MLX5_GET(virtio_emulation_cap, hcattr, 421 desc_tunnel_offload_type); 422 vdpa_attr->eth_frame_offload_type = 423 MLX5_GET(virtio_emulation_cap, hcattr, 424 eth_frame_offload_type); 425 vdpa_attr->virtio_version_1_0 = 426 MLX5_GET(virtio_emulation_cap, hcattr, 427 virtio_version_1_0); 428 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 429 tso_ipv4); 430 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 431 tso_ipv6); 432 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 433 tx_csum); 434 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 435 rx_csum); 436 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 437 event_mode); 438 vdpa_attr->virtio_queue_type = 439 MLX5_GET(virtio_emulation_cap, hcattr, 440 virtio_queue_type); 441 vdpa_attr->log_doorbell_stride = 442 MLX5_GET(virtio_emulation_cap, hcattr, 443 log_doorbell_stride); 444 vdpa_attr->log_doorbell_bar_size = 445 MLX5_GET(virtio_emulation_cap, hcattr, 446 log_doorbell_bar_size); 447 vdpa_attr->doorbell_bar_offset = 448 MLX5_GET64(virtio_emulation_cap, hcattr, 449 doorbell_bar_offset); 450 vdpa_attr->max_num_virtio_queues = 451 MLX5_GET(virtio_emulation_cap, hcattr, 452 max_num_virtio_queues); 453 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 454 umem_1_buffer_param_a); 455 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 456 umem_1_buffer_param_b); 457 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 458 umem_2_buffer_param_a); 459 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 460 umem_2_buffer_param_b); 461 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 462 umem_3_buffer_param_a); 463 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 464 umem_3_buffer_param_b); 465 } 466 } 467 468 int 469 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 470 uint32_t ids[], uint32_t num) 471 { 472 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 473 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 474 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 475 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 476 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 477 int ret; 478 uint32_t idx = 0; 479 uint32_t i; 480 481 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 482 rte_errno = EINVAL; 483 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 484 return -rte_errno; 485 } 486 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 487 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 488 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 489 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 490 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 491 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 492 out, sizeof(out)); 493 if (ret) { 494 rte_errno = ret; 495 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 496 (void *)flex_obj); 497 return -rte_errno; 498 } 499 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 500 void *s_off = (void *)((char *)sample + i * 501 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 502 uint32_t en; 503 504 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 505 flow_match_sample_en); 506 if (!en) 507 continue; 508 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 509 flow_match_sample_field_id); 510 } 511 if (num != idx) { 512 rte_errno = EINVAL; 513 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 514 return -rte_errno; 515 } 516 return ret; 517 } 518 519 520 struct mlx5_devx_obj * 521 mlx5_devx_cmd_create_flex_parser(void *ctx, 522 struct mlx5_devx_graph_node_attr *data) 523 { 524 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 525 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 526 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 527 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 528 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 529 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 530 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 531 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 532 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 533 uint32_t i; 534 535 if (!parse_flex_obj) { 536 DRV_LOG(ERR, "Failed to allocate flex parser data."); 537 rte_errno = ENOMEM; 538 return NULL; 539 } 540 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 541 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 542 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 543 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 544 MLX5_SET(parse_graph_flex, flex, header_length_mode, 545 data->header_length_mode); 546 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 547 data->header_length_base_value); 548 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 549 data->header_length_field_offset); 550 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 551 data->header_length_field_shift); 552 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 553 data->header_length_field_mask); 554 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 555 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 556 void *s_off = (void *)((char *)sample + i * 557 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 558 559 if (!s->flow_match_sample_en) 560 continue; 561 MLX5_SET(parse_graph_flow_match_sample, s_off, 562 flow_match_sample_en, !!s->flow_match_sample_en); 563 MLX5_SET(parse_graph_flow_match_sample, s_off, 564 flow_match_sample_field_offset, 565 s->flow_match_sample_field_offset); 566 MLX5_SET(parse_graph_flow_match_sample, s_off, 567 flow_match_sample_offset_mode, 568 s->flow_match_sample_offset_mode); 569 MLX5_SET(parse_graph_flow_match_sample, s_off, 570 flow_match_sample_field_offset_mask, 571 s->flow_match_sample_field_offset_mask); 572 MLX5_SET(parse_graph_flow_match_sample, s_off, 573 flow_match_sample_field_offset_shift, 574 s->flow_match_sample_field_offset_shift); 575 MLX5_SET(parse_graph_flow_match_sample, s_off, 576 flow_match_sample_field_base_offset, 577 s->flow_match_sample_field_base_offset); 578 MLX5_SET(parse_graph_flow_match_sample, s_off, 579 flow_match_sample_tunnel_mode, 580 s->flow_match_sample_tunnel_mode); 581 } 582 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 583 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 584 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 585 void *in_off = (void *)((char *)in_arc + i * 586 MLX5_ST_SZ_BYTES(parse_graph_arc)); 587 void *out_off = (void *)((char *)out_arc + i * 588 MLX5_ST_SZ_BYTES(parse_graph_arc)); 589 590 if (ia->arc_parse_graph_node != 0) { 591 MLX5_SET(parse_graph_arc, in_off, 592 compare_condition_value, 593 ia->compare_condition_value); 594 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 595 ia->start_inner_tunnel); 596 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 597 ia->arc_parse_graph_node); 598 MLX5_SET(parse_graph_arc, in_off, 599 parse_graph_node_handle, 600 ia->parse_graph_node_handle); 601 } 602 if (oa->arc_parse_graph_node != 0) { 603 MLX5_SET(parse_graph_arc, out_off, 604 compare_condition_value, 605 oa->compare_condition_value); 606 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 607 oa->start_inner_tunnel); 608 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 609 oa->arc_parse_graph_node); 610 MLX5_SET(parse_graph_arc, out_off, 611 parse_graph_node_handle, 612 oa->parse_graph_node_handle); 613 } 614 } 615 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 616 out, sizeof(out)); 617 if (!parse_flex_obj->obj) { 618 rte_errno = errno; 619 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 620 "by using DevX."); 621 mlx5_free(parse_flex_obj); 622 return NULL; 623 } 624 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 625 return parse_flex_obj; 626 } 627 628 /** 629 * Query HCA attributes. 630 * Using those attributes we can check on run time if the device 631 * is having the required capabilities. 632 * 633 * @param[in] ctx 634 * Context returned from mlx5 open_device() glue function. 635 * @param[out] attr 636 * Attributes device values. 637 * 638 * @return 639 * 0 on success, a negative value otherwise. 640 */ 641 int 642 mlx5_devx_cmd_query_hca_attr(void *ctx, 643 struct mlx5_hca_attr *attr) 644 { 645 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 646 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 647 void *hcattr; 648 int status, syndrome, rc, i; 649 650 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 651 MLX5_SET(query_hca_cap_in, in, op_mod, 652 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 653 MLX5_HCA_CAP_OPMOD_GET_CUR); 654 655 rc = mlx5_glue->devx_general_cmd(ctx, 656 in, sizeof(in), out, sizeof(out)); 657 if (rc) 658 goto error; 659 status = MLX5_GET(query_hca_cap_out, out, status); 660 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 661 if (status) { 662 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 663 "status %x, syndrome = %x", status, syndrome); 664 return -1; 665 } 666 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 667 attr->flow_counter_bulk_alloc_bitmap = 668 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 669 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 670 flow_counters_dump); 671 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 672 log_max_rqt_size); 673 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 674 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 675 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 676 log_max_hairpin_queues); 677 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 678 log_max_hairpin_wq_data_sz); 679 attr->log_max_hairpin_num_packets = MLX5_GET 680 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 681 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 682 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 683 relaxed_ordering_write); 684 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 685 relaxed_ordering_read); 686 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 687 access_register_user); 688 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 689 eth_net_offloads); 690 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 691 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 692 flex_parser_protocols); 693 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 694 max_geneve_tlv_options); 695 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 696 max_geneve_tlv_option_data_len); 697 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 698 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 699 general_obj_types) & 700 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 701 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 702 general_obj_types) & 703 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 704 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 705 general_obj_types) & 706 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 707 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 708 wqe_index_ignore_cap); 709 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 710 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 711 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 712 log_max_static_sq_wq); 713 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 714 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 715 device_frequency_khz); 716 attr->scatter_fcs_w_decap_disable = 717 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 718 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp); 719 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 720 regexp_num_of_engines); 721 attr->flow_hit_aso = !!(MLX5_GET64(cmd_hca_cap, hcattr, 722 general_obj_types) & 723 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 724 attr->geneve_tlv_opt = !!(MLX5_GET64(cmd_hca_cap, hcattr, 725 general_obj_types) & 726 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 727 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 728 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 729 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 730 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 731 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 732 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 733 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 734 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 735 attr->reg_c_preserve = 736 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 737 attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo); 738 attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress); 739 attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress); 740 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 741 compress_min_block_size); 742 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 743 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 744 log_compress_mmo_size); 745 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 746 log_decompress_mmo_size); 747 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 748 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 749 mini_cqe_resp_flow_tag); 750 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 751 mini_cqe_resp_l3_l4_tag); 752 if (attr->qos.sup) { 753 MLX5_SET(query_hca_cap_in, in, op_mod, 754 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 755 MLX5_HCA_CAP_OPMOD_GET_CUR); 756 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 757 out, sizeof(out)); 758 if (rc) 759 goto error; 760 if (status) { 761 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities," 762 " status %x, syndrome = %x", status, syndrome); 763 return -1; 764 } 765 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 766 attr->qos.flow_meter_old = 767 MLX5_GET(qos_cap, hcattr, flow_meter_old); 768 attr->qos.log_max_flow_meter = 769 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 770 attr->qos.flow_meter_reg_c_ids = 771 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 772 attr->qos.flow_meter = 773 MLX5_GET(qos_cap, hcattr, flow_meter); 774 attr->qos.packet_pacing = 775 MLX5_GET(qos_cap, hcattr, packet_pacing); 776 attr->qos.wqe_rate_pp = 777 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 778 } 779 if (attr->vdpa.valid) 780 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 781 if (!attr->eth_net_offloads) 782 return 0; 783 784 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 785 memset(in, 0, sizeof(in)); 786 memset(out, 0, sizeof(out)); 787 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 788 MLX5_SET(query_hca_cap_in, in, op_mod, 789 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 790 MLX5_HCA_CAP_OPMOD_GET_CUR); 791 792 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 793 if (rc) 794 goto error; 795 status = MLX5_GET(query_hca_cap_out, out, status); 796 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 797 if (status) { 798 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 799 "status %x, syndrome = %x", status, syndrome); 800 attr->log_max_ft_sampler_num = 0; 801 return -1; 802 } 803 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 804 attr->log_max_ft_sampler_num = 805 MLX5_GET(flow_table_nic_cap, 806 hcattr, flow_table_properties.log_max_ft_sampler_num); 807 808 /* Query HCA offloads for Ethernet protocol. */ 809 memset(in, 0, sizeof(in)); 810 memset(out, 0, sizeof(out)); 811 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 812 MLX5_SET(query_hca_cap_in, in, op_mod, 813 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 814 MLX5_HCA_CAP_OPMOD_GET_CUR); 815 816 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 817 if (rc) { 818 attr->eth_net_offloads = 0; 819 goto error; 820 } 821 status = MLX5_GET(query_hca_cap_out, out, status); 822 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 823 if (status) { 824 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 825 "status %x, syndrome = %x", status, syndrome); 826 attr->eth_net_offloads = 0; 827 return -1; 828 } 829 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 830 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 831 hcattr, wqe_vlan_insert); 832 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 833 lro_cap); 834 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 835 hcattr, tunnel_lro_gre); 836 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 837 hcattr, tunnel_lro_vxlan); 838 attr->lro_max_msg_sz_mode = MLX5_GET 839 (per_protocol_networking_offload_caps, 840 hcattr, lro_max_msg_sz_mode); 841 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 842 attr->lro_timer_supported_periods[i] = 843 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 844 lro_timer_supported_periods[i]); 845 } 846 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 847 hcattr, lro_min_mss_size); 848 attr->tunnel_stateless_geneve_rx = 849 MLX5_GET(per_protocol_networking_offload_caps, 850 hcattr, tunnel_stateless_geneve_rx); 851 attr->geneve_max_opt_len = 852 MLX5_GET(per_protocol_networking_offload_caps, 853 hcattr, max_geneve_opt_len); 854 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 855 hcattr, wqe_inline_mode); 856 attr->tunnel_stateless_gtp = MLX5_GET 857 (per_protocol_networking_offload_caps, 858 hcattr, tunnel_stateless_gtp); 859 attr->rss_ind_tbl_cap = MLX5_GET 860 (per_protocol_networking_offload_caps, 861 hcattr, rss_ind_tbl_cap); 862 if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) 863 return 0; 864 if (attr->eth_virt) { 865 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 866 if (rc) { 867 attr->eth_virt = 0; 868 goto error; 869 } 870 } 871 return 0; 872 error: 873 rc = (rc > 0) ? -rc : rc; 874 return rc; 875 } 876 877 /** 878 * Query TIS transport domain from QP verbs object using DevX API. 879 * 880 * @param[in] qp 881 * Pointer to verbs QP returned by ibv_create_qp . 882 * @param[in] tis_num 883 * TIS number of TIS to query. 884 * @param[out] tis_td 885 * Pointer to TIS transport domain variable, to be set by the routine. 886 * 887 * @return 888 * 0 on success, a negative value otherwise. 889 */ 890 int 891 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 892 uint32_t *tis_td) 893 { 894 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 895 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 896 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 897 int rc; 898 void *tis_ctx; 899 900 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 901 MLX5_SET(query_tis_in, in, tisn, tis_num); 902 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 903 if (rc) { 904 DRV_LOG(ERR, "Failed to query QP using DevX"); 905 return -rc; 906 }; 907 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 908 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 909 return 0; 910 #else 911 (void)qp; 912 (void)tis_num; 913 (void)tis_td; 914 return -ENOTSUP; 915 #endif 916 } 917 918 /** 919 * Fill WQ data for DevX API command. 920 * Utility function for use when creating DevX objects containing a WQ. 921 * 922 * @param[in] wq_ctx 923 * Pointer to WQ context to fill with data. 924 * @param [in] wq_attr 925 * Pointer to WQ attributes structure to fill in WQ context. 926 */ 927 static void 928 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 929 { 930 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 931 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 932 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 933 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 934 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 935 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 936 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 937 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 938 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 939 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 940 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 941 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 942 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 943 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 944 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 945 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 946 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 947 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 948 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 949 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 950 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 951 wq_attr->log_hairpin_num_packets); 952 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 953 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 954 wq_attr->single_wqe_log_num_of_strides); 955 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 956 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 957 wq_attr->single_stride_log_num_of_bytes); 958 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 959 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 960 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 961 } 962 963 /** 964 * Create RQ using DevX API. 965 * 966 * @param[in] ctx 967 * Context returned from mlx5 open_device() glue function. 968 * @param [in] rq_attr 969 * Pointer to create RQ attributes structure. 970 * @param [in] socket 971 * CPU socket ID for allocations. 972 * 973 * @return 974 * The DevX object created, NULL otherwise and rte_errno is set. 975 */ 976 struct mlx5_devx_obj * 977 mlx5_devx_cmd_create_rq(void *ctx, 978 struct mlx5_devx_create_rq_attr *rq_attr, 979 int socket) 980 { 981 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 982 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 983 void *rq_ctx, *wq_ctx; 984 struct mlx5_devx_wq_attr *wq_attr; 985 struct mlx5_devx_obj *rq = NULL; 986 987 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 988 if (!rq) { 989 DRV_LOG(ERR, "Failed to allocate RQ data"); 990 rte_errno = ENOMEM; 991 return NULL; 992 } 993 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 994 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 995 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 996 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 997 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 998 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 999 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1000 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1001 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1002 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1003 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1004 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1005 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1006 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1007 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1008 wq_attr = &rq_attr->wq_attr; 1009 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1010 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1011 out, sizeof(out)); 1012 if (!rq->obj) { 1013 DRV_LOG(ERR, "Failed to create RQ using DevX"); 1014 rte_errno = errno; 1015 mlx5_free(rq); 1016 return NULL; 1017 } 1018 rq->id = MLX5_GET(create_rq_out, out, rqn); 1019 return rq; 1020 } 1021 1022 /** 1023 * Modify RQ using DevX API. 1024 * 1025 * @param[in] rq 1026 * Pointer to RQ object structure. 1027 * @param [in] rq_attr 1028 * Pointer to modify RQ attributes structure. 1029 * 1030 * @return 1031 * 0 on success, a negative errno value otherwise and rte_errno is set. 1032 */ 1033 int 1034 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1035 struct mlx5_devx_modify_rq_attr *rq_attr) 1036 { 1037 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1038 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1039 void *rq_ctx, *wq_ctx; 1040 int ret; 1041 1042 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1043 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1044 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1045 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1046 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1047 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1048 if (rq_attr->modify_bitmask & 1049 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1050 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1051 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1052 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1053 if (rq_attr->modify_bitmask & 1054 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1055 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1056 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1057 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1058 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1059 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1060 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1061 } 1062 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1063 out, sizeof(out)); 1064 if (ret) { 1065 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1066 rte_errno = errno; 1067 return -errno; 1068 } 1069 return ret; 1070 } 1071 1072 /** 1073 * Create TIR using DevX API. 1074 * 1075 * @param[in] ctx 1076 * Context returned from mlx5 open_device() glue function. 1077 * @param [in] tir_attr 1078 * Pointer to TIR attributes structure. 1079 * 1080 * @return 1081 * The DevX object created, NULL otherwise and rte_errno is set. 1082 */ 1083 struct mlx5_devx_obj * 1084 mlx5_devx_cmd_create_tir(void *ctx, 1085 struct mlx5_devx_tir_attr *tir_attr) 1086 { 1087 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1088 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1089 void *tir_ctx, *outer, *inner, *rss_key; 1090 struct mlx5_devx_obj *tir = NULL; 1091 1092 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1093 if (!tir) { 1094 DRV_LOG(ERR, "Failed to allocate TIR data"); 1095 rte_errno = ENOMEM; 1096 return NULL; 1097 } 1098 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1099 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1100 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1101 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1102 tir_attr->lro_timeout_period_usecs); 1103 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1104 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1105 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1106 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1107 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1108 tir_attr->tunneled_offload_en); 1109 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1110 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1111 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1112 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1113 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1114 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1115 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1116 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1117 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1118 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1119 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1120 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1121 tir_attr->rx_hash_field_selector_outer.selected_fields); 1122 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1123 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1124 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1125 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1126 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1127 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1128 tir_attr->rx_hash_field_selector_inner.selected_fields); 1129 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1130 out, sizeof(out)); 1131 if (!tir->obj) { 1132 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1133 rte_errno = errno; 1134 mlx5_free(tir); 1135 return NULL; 1136 } 1137 tir->id = MLX5_GET(create_tir_out, out, tirn); 1138 return tir; 1139 } 1140 1141 /** 1142 * Modify TIR using DevX API. 1143 * 1144 * @param[in] tir 1145 * Pointer to TIR DevX object structure. 1146 * @param [in] modify_tir_attr 1147 * Pointer to TIR modification attributes structure. 1148 * 1149 * @return 1150 * 0 on success, a negative errno value otherwise and rte_errno is set. 1151 */ 1152 int 1153 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1154 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1155 { 1156 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1157 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1158 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1159 void *tir_ctx; 1160 int ret; 1161 1162 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1163 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1164 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1165 modify_tir_attr->modify_bitmask); 1166 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1167 if (modify_tir_attr->modify_bitmask & 1168 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1169 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1170 tir_attr->lro_timeout_period_usecs); 1171 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1172 tir_attr->lro_enable_mask); 1173 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1174 tir_attr->lro_max_msg_sz); 1175 } 1176 if (modify_tir_attr->modify_bitmask & 1177 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1178 MLX5_SET(tirc, tir_ctx, indirect_table, 1179 tir_attr->indirect_table); 1180 if (modify_tir_attr->modify_bitmask & 1181 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1182 int i; 1183 void *outer, *inner; 1184 1185 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1186 tir_attr->rx_hash_symmetric); 1187 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1188 for (i = 0; i < 10; i++) { 1189 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1190 tir_attr->rx_hash_toeplitz_key[i]); 1191 } 1192 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1193 rx_hash_field_selector_outer); 1194 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1195 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1196 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1197 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1198 MLX5_SET 1199 (rx_hash_field_select, outer, selected_fields, 1200 tir_attr->rx_hash_field_selector_outer.selected_fields); 1201 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1202 rx_hash_field_selector_inner); 1203 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1204 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1205 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1206 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1207 MLX5_SET 1208 (rx_hash_field_select, inner, selected_fields, 1209 tir_attr->rx_hash_field_selector_inner.selected_fields); 1210 } 1211 if (modify_tir_attr->modify_bitmask & 1212 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1213 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1214 } 1215 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1216 out, sizeof(out)); 1217 if (ret) { 1218 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1219 rte_errno = errno; 1220 return -errno; 1221 } 1222 return ret; 1223 } 1224 1225 /** 1226 * Create RQT using DevX API. 1227 * 1228 * @param[in] ctx 1229 * Context returned from mlx5 open_device() glue function. 1230 * @param [in] rqt_attr 1231 * Pointer to RQT attributes structure. 1232 * 1233 * @return 1234 * The DevX object created, NULL otherwise and rte_errno is set. 1235 */ 1236 struct mlx5_devx_obj * 1237 mlx5_devx_cmd_create_rqt(void *ctx, 1238 struct mlx5_devx_rqt_attr *rqt_attr) 1239 { 1240 uint32_t *in = NULL; 1241 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1242 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1243 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1244 void *rqt_ctx; 1245 struct mlx5_devx_obj *rqt = NULL; 1246 int i; 1247 1248 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1249 if (!in) { 1250 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1251 rte_errno = ENOMEM; 1252 return NULL; 1253 } 1254 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1255 if (!rqt) { 1256 DRV_LOG(ERR, "Failed to allocate RQT data"); 1257 rte_errno = ENOMEM; 1258 mlx5_free(in); 1259 return NULL; 1260 } 1261 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1262 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1263 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1264 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1265 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1266 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1267 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1268 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1269 mlx5_free(in); 1270 if (!rqt->obj) { 1271 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1272 rte_errno = errno; 1273 mlx5_free(rqt); 1274 return NULL; 1275 } 1276 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1277 return rqt; 1278 } 1279 1280 /** 1281 * Modify RQT using DevX API. 1282 * 1283 * @param[in] rqt 1284 * Pointer to RQT DevX object structure. 1285 * @param [in] rqt_attr 1286 * Pointer to RQT attributes structure. 1287 * 1288 * @return 1289 * 0 on success, a negative errno value otherwise and rte_errno is set. 1290 */ 1291 int 1292 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1293 struct mlx5_devx_rqt_attr *rqt_attr) 1294 { 1295 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1296 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1297 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1298 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1299 void *rqt_ctx; 1300 int i; 1301 int ret; 1302 1303 if (!in) { 1304 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1305 rte_errno = ENOMEM; 1306 return -ENOMEM; 1307 } 1308 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1309 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1310 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1311 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1312 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1313 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1314 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1315 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1316 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1317 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1318 mlx5_free(in); 1319 if (ret) { 1320 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1321 rte_errno = errno; 1322 return -rte_errno; 1323 } 1324 return ret; 1325 } 1326 1327 /** 1328 * Create SQ using DevX API. 1329 * 1330 * @param[in] ctx 1331 * Context returned from mlx5 open_device() glue function. 1332 * @param [in] sq_attr 1333 * Pointer to SQ attributes structure. 1334 * @param [in] socket 1335 * CPU socket ID for allocations. 1336 * 1337 * @return 1338 * The DevX object created, NULL otherwise and rte_errno is set. 1339 **/ 1340 struct mlx5_devx_obj * 1341 mlx5_devx_cmd_create_sq(void *ctx, 1342 struct mlx5_devx_create_sq_attr *sq_attr) 1343 { 1344 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1345 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1346 void *sq_ctx; 1347 void *wq_ctx; 1348 struct mlx5_devx_wq_attr *wq_attr; 1349 struct mlx5_devx_obj *sq = NULL; 1350 1351 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1352 if (!sq) { 1353 DRV_LOG(ERR, "Failed to allocate SQ data"); 1354 rte_errno = ENOMEM; 1355 return NULL; 1356 } 1357 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1358 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1359 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1360 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1361 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1362 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1363 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1364 sq_attr->allow_multi_pkt_send_wqe); 1365 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1366 sq_attr->min_wqe_inline_mode); 1367 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1368 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1369 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1370 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1371 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1372 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1373 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1374 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1375 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1376 sq_attr->packet_pacing_rate_limit_index); 1377 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1378 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1379 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1380 wq_attr = &sq_attr->wq_attr; 1381 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1382 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1383 out, sizeof(out)); 1384 if (!sq->obj) { 1385 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1386 rte_errno = errno; 1387 mlx5_free(sq); 1388 return NULL; 1389 } 1390 sq->id = MLX5_GET(create_sq_out, out, sqn); 1391 return sq; 1392 } 1393 1394 /** 1395 * Modify SQ using DevX API. 1396 * 1397 * @param[in] sq 1398 * Pointer to SQ object structure. 1399 * @param [in] sq_attr 1400 * Pointer to SQ attributes structure. 1401 * 1402 * @return 1403 * 0 on success, a negative errno value otherwise and rte_errno is set. 1404 */ 1405 int 1406 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1407 struct mlx5_devx_modify_sq_attr *sq_attr) 1408 { 1409 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1410 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1411 void *sq_ctx; 1412 int ret; 1413 1414 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1415 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1416 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1417 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1418 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1419 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1420 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1421 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1422 out, sizeof(out)); 1423 if (ret) { 1424 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1425 rte_errno = errno; 1426 return -rte_errno; 1427 } 1428 return ret; 1429 } 1430 1431 /** 1432 * Create TIS using DevX API. 1433 * 1434 * @param[in] ctx 1435 * Context returned from mlx5 open_device() glue function. 1436 * @param [in] tis_attr 1437 * Pointer to TIS attributes structure. 1438 * 1439 * @return 1440 * The DevX object created, NULL otherwise and rte_errno is set. 1441 */ 1442 struct mlx5_devx_obj * 1443 mlx5_devx_cmd_create_tis(void *ctx, 1444 struct mlx5_devx_tis_attr *tis_attr) 1445 { 1446 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1447 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1448 struct mlx5_devx_obj *tis = NULL; 1449 void *tis_ctx; 1450 1451 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1452 if (!tis) { 1453 DRV_LOG(ERR, "Failed to allocate TIS object"); 1454 rte_errno = ENOMEM; 1455 return NULL; 1456 } 1457 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1458 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1459 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1460 tis_attr->strict_lag_tx_port_affinity); 1461 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1462 tis_attr->lag_tx_port_affinity); 1463 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1464 MLX5_SET(tisc, tis_ctx, transport_domain, 1465 tis_attr->transport_domain); 1466 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1467 out, sizeof(out)); 1468 if (!tis->obj) { 1469 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1470 rte_errno = errno; 1471 mlx5_free(tis); 1472 return NULL; 1473 } 1474 tis->id = MLX5_GET(create_tis_out, out, tisn); 1475 return tis; 1476 } 1477 1478 /** 1479 * Create transport domain using DevX API. 1480 * 1481 * @param[in] ctx 1482 * Context returned from mlx5 open_device() glue function. 1483 * @return 1484 * The DevX object created, NULL otherwise and rte_errno is set. 1485 */ 1486 struct mlx5_devx_obj * 1487 mlx5_devx_cmd_create_td(void *ctx) 1488 { 1489 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1490 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1491 struct mlx5_devx_obj *td = NULL; 1492 1493 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1494 if (!td) { 1495 DRV_LOG(ERR, "Failed to allocate TD object"); 1496 rte_errno = ENOMEM; 1497 return NULL; 1498 } 1499 MLX5_SET(alloc_transport_domain_in, in, opcode, 1500 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1501 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1502 out, sizeof(out)); 1503 if (!td->obj) { 1504 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1505 rte_errno = errno; 1506 mlx5_free(td); 1507 return NULL; 1508 } 1509 td->id = MLX5_GET(alloc_transport_domain_out, out, 1510 transport_domain); 1511 return td; 1512 } 1513 1514 /** 1515 * Dump all flows to file. 1516 * 1517 * @param[in] fdb_domain 1518 * FDB domain. 1519 * @param[in] rx_domain 1520 * RX domain. 1521 * @param[in] tx_domain 1522 * TX domain. 1523 * @param[out] file 1524 * Pointer to file stream. 1525 * 1526 * @return 1527 * 0 on success, a nagative value otherwise. 1528 */ 1529 int 1530 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1531 void *rx_domain __rte_unused, 1532 void *tx_domain __rte_unused, FILE *file __rte_unused) 1533 { 1534 int ret = 0; 1535 1536 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1537 if (fdb_domain) { 1538 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1539 if (ret) 1540 return ret; 1541 } 1542 MLX5_ASSERT(rx_domain); 1543 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1544 if (ret) 1545 return ret; 1546 MLX5_ASSERT(tx_domain); 1547 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1548 #else 1549 ret = ENOTSUP; 1550 #endif 1551 return -ret; 1552 } 1553 1554 /* 1555 * Create CQ using DevX API. 1556 * 1557 * @param[in] ctx 1558 * Context returned from mlx5 open_device() glue function. 1559 * @param [in] attr 1560 * Pointer to CQ attributes structure. 1561 * 1562 * @return 1563 * The DevX object created, NULL otherwise and rte_errno is set. 1564 */ 1565 struct mlx5_devx_obj * 1566 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1567 { 1568 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1569 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1570 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1571 sizeof(*cq_obj), 1572 0, SOCKET_ID_ANY); 1573 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1574 1575 if (!cq_obj) { 1576 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1577 rte_errno = ENOMEM; 1578 return NULL; 1579 } 1580 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1581 if (attr->db_umem_valid) { 1582 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1583 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1584 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1585 } else { 1586 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1587 } 1588 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1589 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1590 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1591 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1592 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1593 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1594 MLX5_SET(cqc, cqctx, log_page_size, 1595 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1596 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1597 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1598 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1599 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1600 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1601 attr->mini_cqe_res_format_ext); 1602 if (attr->q_umem_valid) { 1603 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1604 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1605 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1606 attr->q_umem_offset); 1607 } 1608 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1609 sizeof(out)); 1610 if (!cq_obj->obj) { 1611 rte_errno = errno; 1612 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1613 mlx5_free(cq_obj); 1614 return NULL; 1615 } 1616 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1617 return cq_obj; 1618 } 1619 1620 /** 1621 * Create VIRTQ using DevX API. 1622 * 1623 * @param[in] ctx 1624 * Context returned from mlx5 open_device() glue function. 1625 * @param [in] attr 1626 * Pointer to VIRTQ attributes structure. 1627 * 1628 * @return 1629 * The DevX object created, NULL otherwise and rte_errno is set. 1630 */ 1631 struct mlx5_devx_obj * 1632 mlx5_devx_cmd_create_virtq(void *ctx, 1633 struct mlx5_devx_virtq_attr *attr) 1634 { 1635 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1636 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1637 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1638 sizeof(*virtq_obj), 1639 0, SOCKET_ID_ANY); 1640 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1641 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1642 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1643 1644 if (!virtq_obj) { 1645 DRV_LOG(ERR, "Failed to allocate virtq data."); 1646 rte_errno = ENOMEM; 1647 return NULL; 1648 } 1649 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1650 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1651 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1652 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1653 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1654 attr->hw_available_index); 1655 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1656 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1657 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1658 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1659 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1660 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1661 attr->virtio_version_1_0); 1662 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1663 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1664 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1665 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1666 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1667 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1668 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1669 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1670 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1671 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 1672 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 1673 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 1674 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 1675 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 1676 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 1677 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 1678 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 1679 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 1680 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 1681 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 1682 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 1683 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 1684 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 1685 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1686 sizeof(out)); 1687 if (!virtq_obj->obj) { 1688 rte_errno = errno; 1689 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 1690 mlx5_free(virtq_obj); 1691 return NULL; 1692 } 1693 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1694 return virtq_obj; 1695 } 1696 1697 /** 1698 * Modify VIRTQ using DevX API. 1699 * 1700 * @param[in] virtq_obj 1701 * Pointer to virtq object structure. 1702 * @param [in] attr 1703 * Pointer to modify virtq attributes structure. 1704 * 1705 * @return 1706 * 0 on success, a negative errno value otherwise and rte_errno is set. 1707 */ 1708 int 1709 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 1710 struct mlx5_devx_virtq_attr *attr) 1711 { 1712 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1713 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1714 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1715 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1716 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1717 int ret; 1718 1719 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1720 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 1721 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1722 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1723 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1724 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 1725 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1726 switch (attr->type) { 1727 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 1728 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 1729 break; 1730 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 1731 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 1732 attr->dirty_bitmap_mkey); 1733 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 1734 attr->dirty_bitmap_addr); 1735 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 1736 attr->dirty_bitmap_size); 1737 break; 1738 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 1739 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 1740 attr->dirty_bitmap_dump_enable); 1741 break; 1742 default: 1743 rte_errno = EINVAL; 1744 return -rte_errno; 1745 } 1746 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 1747 out, sizeof(out)); 1748 if (ret) { 1749 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1750 rte_errno = errno; 1751 return -rte_errno; 1752 } 1753 return ret; 1754 } 1755 1756 /** 1757 * Query VIRTQ using DevX API. 1758 * 1759 * @param[in] virtq_obj 1760 * Pointer to virtq object structure. 1761 * @param [in/out] attr 1762 * Pointer to virtq attributes structure. 1763 * 1764 * @return 1765 * 0 on success, a negative errno value otherwise and rte_errno is set. 1766 */ 1767 int 1768 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 1769 struct mlx5_devx_virtq_attr *attr) 1770 { 1771 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1772 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 1773 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 1774 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 1775 int ret; 1776 1777 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1778 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1779 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1780 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1781 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1782 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 1783 out, sizeof(out)); 1784 if (ret) { 1785 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1786 rte_errno = errno; 1787 return -errno; 1788 } 1789 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 1790 hw_available_index); 1791 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 1792 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 1793 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 1794 virtio_q_context.error_type); 1795 return ret; 1796 } 1797 1798 /** 1799 * Create QP using DevX API. 1800 * 1801 * @param[in] ctx 1802 * Context returned from mlx5 open_device() glue function. 1803 * @param [in] attr 1804 * Pointer to QP attributes structure. 1805 * 1806 * @return 1807 * The DevX object created, NULL otherwise and rte_errno is set. 1808 */ 1809 struct mlx5_devx_obj * 1810 mlx5_devx_cmd_create_qp(void *ctx, 1811 struct mlx5_devx_qp_attr *attr) 1812 { 1813 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 1814 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 1815 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 1816 sizeof(*qp_obj), 1817 0, SOCKET_ID_ANY); 1818 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1819 1820 if (!qp_obj) { 1821 DRV_LOG(ERR, "Failed to allocate QP data."); 1822 rte_errno = ENOMEM; 1823 return NULL; 1824 } 1825 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 1826 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 1827 MLX5_SET(qpc, qpc, pd, attr->pd); 1828 if (attr->uar_index) { 1829 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1830 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 1831 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1832 MLX5_SET(qpc, qpc, log_page_size, 1833 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1834 if (attr->sq_size) { 1835 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); 1836 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 1837 MLX5_SET(qpc, qpc, log_sq_size, 1838 rte_log2_u32(attr->sq_size)); 1839 } else { 1840 MLX5_SET(qpc, qpc, no_sq, 1); 1841 } 1842 if (attr->rq_size) { 1843 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); 1844 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 1845 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 1846 MLX5_LOG_RQ_STRIDE_SHIFT); 1847 MLX5_SET(qpc, qpc, log_rq_size, 1848 rte_log2_u32(attr->rq_size)); 1849 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 1850 } else { 1851 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1852 } 1853 if (attr->dbr_umem_valid) { 1854 MLX5_SET(qpc, qpc, dbr_umem_valid, 1855 attr->dbr_umem_valid); 1856 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 1857 } 1858 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 1859 MLX5_SET64(create_qp_in, in, wq_umem_offset, 1860 attr->wq_umem_offset); 1861 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 1862 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 1863 } else { 1864 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 1865 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1866 MLX5_SET(qpc, qpc, no_sq, 1); 1867 } 1868 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1869 sizeof(out)); 1870 if (!qp_obj->obj) { 1871 rte_errno = errno; 1872 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 1873 mlx5_free(qp_obj); 1874 return NULL; 1875 } 1876 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 1877 return qp_obj; 1878 } 1879 1880 /** 1881 * Modify QP using DevX API. 1882 * Currently supports only force loop-back QP. 1883 * 1884 * @param[in] qp 1885 * Pointer to QP object structure. 1886 * @param [in] qp_st_mod_op 1887 * The QP state modification operation. 1888 * @param [in] remote_qp_id 1889 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 1890 * 1891 * @return 1892 * 0 on success, a negative errno value otherwise and rte_errno is set. 1893 */ 1894 int 1895 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 1896 uint32_t remote_qp_id) 1897 { 1898 union { 1899 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 1900 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 1901 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 1902 } in; 1903 union { 1904 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 1905 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 1906 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 1907 } out; 1908 void *qpc; 1909 int ret; 1910 unsigned int inlen; 1911 unsigned int outlen; 1912 1913 memset(&in, 0, sizeof(in)); 1914 memset(&out, 0, sizeof(out)); 1915 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 1916 switch (qp_st_mod_op) { 1917 case MLX5_CMD_OP_RST2INIT_QP: 1918 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 1919 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 1920 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1921 MLX5_SET(qpc, qpc, rre, 1); 1922 MLX5_SET(qpc, qpc, rwe, 1); 1923 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1924 inlen = sizeof(in.rst2init); 1925 outlen = sizeof(out.rst2init); 1926 break; 1927 case MLX5_CMD_OP_INIT2RTR_QP: 1928 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 1929 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 1930 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 1931 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1932 MLX5_SET(qpc, qpc, mtu, 1); 1933 MLX5_SET(qpc, qpc, log_msg_max, 30); 1934 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 1935 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 1936 inlen = sizeof(in.init2rtr); 1937 outlen = sizeof(out.init2rtr); 1938 break; 1939 case MLX5_CMD_OP_RTR2RTS_QP: 1940 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 1941 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 1942 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 1943 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 1944 MLX5_SET(qpc, qpc, retry_count, 7); 1945 MLX5_SET(qpc, qpc, rnr_retry, 7); 1946 inlen = sizeof(in.rtr2rts); 1947 outlen = sizeof(out.rtr2rts); 1948 break; 1949 default: 1950 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 1951 qp_st_mod_op); 1952 rte_errno = EINVAL; 1953 return -rte_errno; 1954 } 1955 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 1956 if (ret) { 1957 DRV_LOG(ERR, "Failed to modify QP using DevX."); 1958 rte_errno = errno; 1959 return -rte_errno; 1960 } 1961 return ret; 1962 } 1963 1964 struct mlx5_devx_obj * 1965 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 1966 { 1967 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 1968 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1969 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 1970 sizeof(*couners_obj), 0, 1971 SOCKET_ID_ANY); 1972 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 1973 1974 if (!couners_obj) { 1975 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 1976 rte_errno = ENOMEM; 1977 return NULL; 1978 } 1979 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1980 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1981 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1982 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 1983 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1984 sizeof(out)); 1985 if (!couners_obj->obj) { 1986 rte_errno = errno; 1987 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 1988 " DevX."); 1989 mlx5_free(couners_obj); 1990 return NULL; 1991 } 1992 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1993 return couners_obj; 1994 } 1995 1996 int 1997 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 1998 struct mlx5_devx_virtio_q_couners_attr *attr) 1999 { 2000 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2001 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2002 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2003 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2004 virtio_q_counters); 2005 int ret; 2006 2007 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2008 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2009 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2010 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2011 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2012 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2013 sizeof(out)); 2014 if (ret) { 2015 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2016 rte_errno = errno; 2017 return -errno; 2018 } 2019 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2020 received_desc); 2021 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2022 completed_desc); 2023 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2024 error_cqes); 2025 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2026 bad_desc_errors); 2027 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2028 exceed_max_chain); 2029 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2030 invalid_buffer); 2031 return ret; 2032 } 2033 2034 /** 2035 * Create general object of type FLOW_HIT_ASO using DevX API. 2036 * 2037 * @param[in] ctx 2038 * Context returned from mlx5 open_device() glue function. 2039 * @param [in] pd 2040 * PD value to associate the FLOW_HIT_ASO object with. 2041 * 2042 * @return 2043 * The DevX object created, NULL otherwise and rte_errno is set. 2044 */ 2045 struct mlx5_devx_obj * 2046 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2047 { 2048 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2049 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2050 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2051 void *ptr = NULL; 2052 2053 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2054 0, SOCKET_ID_ANY); 2055 if (!flow_hit_aso_obj) { 2056 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2057 rte_errno = ENOMEM; 2058 return NULL; 2059 } 2060 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2061 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2062 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2063 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2064 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2065 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2066 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2067 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2068 out, sizeof(out)); 2069 if (!flow_hit_aso_obj->obj) { 2070 rte_errno = errno; 2071 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX."); 2072 mlx5_free(flow_hit_aso_obj); 2073 return NULL; 2074 } 2075 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2076 return flow_hit_aso_obj; 2077 } 2078 2079 /* 2080 * Create PD using DevX API. 2081 * 2082 * @param[in] ctx 2083 * Context returned from mlx5 open_device() glue function. 2084 * 2085 * @return 2086 * The DevX object created, NULL otherwise and rte_errno is set. 2087 */ 2088 struct mlx5_devx_obj * 2089 mlx5_devx_cmd_alloc_pd(void *ctx) 2090 { 2091 struct mlx5_devx_obj *ppd = 2092 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2093 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2094 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2095 2096 if (!ppd) { 2097 DRV_LOG(ERR, "Failed to allocate PD data."); 2098 rte_errno = ENOMEM; 2099 return NULL; 2100 } 2101 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2102 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2103 out, sizeof(out)); 2104 if (!ppd->obj) { 2105 mlx5_free(ppd); 2106 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2107 rte_errno = errno; 2108 return NULL; 2109 } 2110 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2111 return ppd; 2112 } 2113 2114 /** 2115 * Create general object of type GENEVE TLV option using DevX API. 2116 * 2117 * @param[in] ctx 2118 * Context returned from mlx5 open_device() glue function. 2119 * @param [in] class 2120 * TLV option variable value of class 2121 * @param [in] type 2122 * TLV option variable value of type 2123 * @param [in] len 2124 * TLV option variable value of len 2125 * 2126 * @return 2127 * The DevX object created, NULL otherwise and rte_errno is set. 2128 */ 2129 struct mlx5_devx_obj * 2130 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2131 uint16_t class, uint8_t type, uint8_t len) 2132 { 2133 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2134 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2135 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2136 sizeof(*geneve_tlv_opt_obj), 2137 0, SOCKET_ID_ANY); 2138 2139 if (!geneve_tlv_opt_obj) { 2140 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2141 rte_errno = ENOMEM; 2142 return NULL; 2143 } 2144 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2145 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2146 geneve_tlv_opt); 2147 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2148 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2149 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2150 MLX5_OBJ_TYPE_GENEVE_TLV_OPT); 2151 MLX5_SET(geneve_tlv_option, opt, option_class, 2152 rte_be_to_cpu_16(class)); 2153 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2154 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2155 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2156 sizeof(in), out, sizeof(out)); 2157 if (!geneve_tlv_opt_obj->obj) { 2158 rte_errno = errno; 2159 DRV_LOG(ERR, "Failed to create Geneve tlv option " 2160 "Obj using DevX."); 2161 mlx5_free(geneve_tlv_opt_obj); 2162 return NULL; 2163 } 2164 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2165 return geneve_tlv_opt_obj; 2166 } 2167 2168 int 2169 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2170 { 2171 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2172 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2173 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2174 int rc; 2175 void *rq_ctx; 2176 2177 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2178 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2179 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2180 if (rc) { 2181 rte_errno = errno; 2182 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2183 "rc = %d, errno = %d.", rc, errno); 2184 return -rc; 2185 }; 2186 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2187 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2188 return 0; 2189 #else 2190 (void)wq; 2191 (void)counter_set_id; 2192 return -ENOTSUP; 2193 #endif 2194 } 2195 2196 /* 2197 * Allocate queue counters via devx interface. 2198 * 2199 * @param[in] ctx 2200 * Context returned from mlx5 open_device() glue function. 2201 * 2202 * @return 2203 * Pointer to counter object on success, a NULL value otherwise and 2204 * rte_errno is set. 2205 */ 2206 struct mlx5_devx_obj * 2207 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2208 { 2209 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2210 SOCKET_ID_ANY); 2211 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2212 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2213 2214 if (!dcs) { 2215 rte_errno = ENOMEM; 2216 return NULL; 2217 } 2218 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2219 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2220 sizeof(out)); 2221 if (!dcs->obj) { 2222 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error " 2223 "%d.", errno); 2224 rte_errno = errno; 2225 mlx5_free(dcs); 2226 return NULL; 2227 } 2228 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2229 return dcs; 2230 } 2231 2232 /** 2233 * Query queue counters values. 2234 * 2235 * @param[in] dcs 2236 * devx object of the queue counter set. 2237 * @param[in] clear 2238 * Whether hardware should clear the counters after the query or not. 2239 * @param[out] out_of_buffers 2240 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2241 * 2242 * @return 2243 * 0 on success, a negative value otherwise. 2244 */ 2245 int 2246 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2247 uint32_t *out_of_buffers) 2248 { 2249 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2250 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2251 int rc; 2252 2253 MLX5_SET(query_q_counter_in, in, opcode, 2254 MLX5_CMD_OP_QUERY_Q_COUNTER); 2255 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2256 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2257 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2258 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2259 sizeof(out)); 2260 if (rc) { 2261 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2262 rte_errno = rc; 2263 return -rc; 2264 } 2265 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2266 return 0; 2267 } 2268