1 // SPDX-License-Identifier: BSD-3-Clause 2 /* Copyright 2018 Mellanox Technologies, Ltd */ 3 4 #include <unistd.h> 5 6 #include <rte_errno.h> 7 #include <rte_malloc.h> 8 #include <rte_eal_paging.h> 9 10 #include "mlx5_prm.h" 11 #include "mlx5_devx_cmds.h" 12 #include "mlx5_common_utils.h" 13 #include "mlx5_malloc.h" 14 15 16 /** 17 * Perform read access to the registers. Reads data from register 18 * and writes ones to the specified buffer. 19 * 20 * @param[in] ctx 21 * Context returned from mlx5 open_device() glue function. 22 * @param[in] reg_id 23 * Register identifier according to the PRM. 24 * @param[in] arg 25 * Register access auxiliary parameter according to the PRM. 26 * @param[out] data 27 * Pointer to the buffer to store read data. 28 * @param[in] dw_cnt 29 * Buffer size in double words. 30 * 31 * @return 32 * 0 on success, a negative value otherwise. 33 */ 34 int 35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 36 uint32_t *data, uint32_t dw_cnt) 37 { 38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 41 int status, rc; 42 43 MLX5_ASSERT(data && dw_cnt); 44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 46 DRV_LOG(ERR, "Not enough buffer for register read data"); 47 return -1; 48 } 49 MLX5_SET(access_register_in, in, opcode, 50 MLX5_CMD_OP_ACCESS_REGISTER_USER); 51 MLX5_SET(access_register_in, in, op_mod, 52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 53 MLX5_SET(access_register_in, in, register_id, reg_id); 54 MLX5_SET(access_register_in, in, argument, arg); 55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 56 MLX5_ST_SZ_BYTES(access_register_out) + 57 sizeof(uint32_t) * dw_cnt); 58 if (rc) 59 goto error; 60 status = MLX5_GET(access_register_out, out, status); 61 if (status) { 62 int syndrome = MLX5_GET(access_register_out, out, syndrome); 63 64 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, " 65 "status %x, syndrome = %x", 66 reg_id, status, syndrome); 67 return -1; 68 } 69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 70 dw_cnt * sizeof(uint32_t)); 71 return 0; 72 error: 73 rc = (rc > 0) ? -rc : rc; 74 return rc; 75 } 76 77 /** 78 * Allocate flow counters via devx interface. 79 * 80 * @param[in] ctx 81 * Context returned from mlx5 open_device() glue function. 82 * @param dcs 83 * Pointer to counters properties structure to be filled by the routine. 84 * @param bulk_n_128 85 * Bulk counter numbers in 128 counters units. 86 * 87 * @return 88 * Pointer to counter object on success, a negative value otherwise and 89 * rte_errno is set. 90 */ 91 struct mlx5_devx_obj * 92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 93 { 94 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 95 0, SOCKET_ID_ANY); 96 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 97 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 98 99 if (!dcs) { 100 rte_errno = ENOMEM; 101 return NULL; 102 } 103 MLX5_SET(alloc_flow_counter_in, in, opcode, 104 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 105 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 106 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 107 sizeof(in), out, sizeof(out)); 108 if (!dcs->obj) { 109 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 110 rte_errno = errno; 111 mlx5_free(dcs); 112 return NULL; 113 } 114 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 115 return dcs; 116 } 117 118 /** 119 * Query flow counters values. 120 * 121 * @param[in] dcs 122 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 123 * @param[in] clear 124 * Whether hardware should clear the counters after the query or not. 125 * @param[in] n_counters 126 * 0 in case of 1 counter to read, otherwise the counter number to read. 127 * @param pkts 128 * The number of packets that matched the flow. 129 * @param bytes 130 * The number of bytes that matched the flow. 131 * @param mkey 132 * The mkey key for batch query. 133 * @param addr 134 * The address in the mkey range for batch query. 135 * @param cmd_comp 136 * The completion object for asynchronous batch query. 137 * @param async_id 138 * The ID to be returned in the asynchronous batch query response. 139 * 140 * @return 141 * 0 on success, a negative value otherwise. 142 */ 143 int 144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 145 int clear, uint32_t n_counters, 146 uint64_t *pkts, uint64_t *bytes, 147 uint32_t mkey, void *addr, 148 void *cmd_comp, 149 uint64_t async_id) 150 { 151 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 152 MLX5_ST_SZ_BYTES(traffic_counter); 153 uint32_t out[out_len]; 154 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 155 void *stats; 156 int rc; 157 158 MLX5_SET(query_flow_counter_in, in, opcode, 159 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 160 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 161 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 162 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 163 164 if (n_counters) { 165 MLX5_SET(query_flow_counter_in, in, num_of_counters, 166 n_counters); 167 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 168 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 169 MLX5_SET64(query_flow_counter_in, in, address, 170 (uint64_t)(uintptr_t)addr); 171 } 172 if (!cmd_comp) 173 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 174 out_len); 175 else 176 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 177 out_len, async_id, 178 cmd_comp); 179 if (rc) { 180 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 181 rte_errno = rc; 182 return -rc; 183 } 184 if (!n_counters) { 185 stats = MLX5_ADDR_OF(query_flow_counter_out, 186 out, flow_statistics); 187 *pkts = MLX5_GET64(traffic_counter, stats, packets); 188 *bytes = MLX5_GET64(traffic_counter, stats, octets); 189 } 190 return 0; 191 } 192 193 /** 194 * Create a new mkey. 195 * 196 * @param[in] ctx 197 * Context returned from mlx5 open_device() glue function. 198 * @param[in] attr 199 * Attributes of the requested mkey. 200 * 201 * @return 202 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 203 * is set. 204 */ 205 struct mlx5_devx_obj * 206 mlx5_devx_cmd_mkey_create(void *ctx, 207 struct mlx5_devx_mkey_attr *attr) 208 { 209 struct mlx5_klm *klm_array = attr->klm_array; 210 int klm_num = attr->klm_num; 211 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 212 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 213 uint32_t in[in_size_dw]; 214 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 215 void *mkc; 216 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 217 0, SOCKET_ID_ANY); 218 size_t pgsize; 219 uint32_t translation_size; 220 221 if (!mkey) { 222 rte_errno = ENOMEM; 223 return NULL; 224 } 225 memset(in, 0, in_size_dw * 4); 226 pgsize = rte_mem_page_size(); 227 if (pgsize == (size_t)-1) { 228 mlx5_free(mkey); 229 DRV_LOG(ERR, "Failed to get page size"); 230 rte_errno = ENOMEM; 231 return NULL; 232 } 233 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 234 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 235 if (klm_num > 0) { 236 int i; 237 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 238 klm_pas_mtt); 239 translation_size = RTE_ALIGN(klm_num, 4); 240 for (i = 0; i < klm_num; i++) { 241 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 242 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 243 MLX5_SET64(klm, klm, address, klm_array[i].address); 244 klm += MLX5_ST_SZ_BYTES(klm); 245 } 246 for (; i < (int)translation_size; i++) { 247 MLX5_SET(klm, klm, mkey, 0x0); 248 MLX5_SET64(klm, klm, address, 0x0); 249 klm += MLX5_ST_SZ_BYTES(klm); 250 } 251 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 252 MLX5_MKC_ACCESS_MODE_KLM_FBS : 253 MLX5_MKC_ACCESS_MODE_KLM); 254 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 255 } else { 256 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 257 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 258 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 259 } 260 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 261 translation_size); 262 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 263 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 264 MLX5_SET(mkc, mkc, lw, 0x1); 265 MLX5_SET(mkc, mkc, lr, 0x1); 266 MLX5_SET(mkc, mkc, qpn, 0xffffff); 267 MLX5_SET(mkc, mkc, pd, attr->pd); 268 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 269 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 270 MLX5_SET(mkc, mkc, relaxed_ordering_write, 271 attr->relaxed_ordering_write); 272 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 273 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 274 MLX5_SET64(mkc, mkc, len, attr->size); 275 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 276 sizeof(out)); 277 if (!mkey->obj) { 278 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d", 279 klm_num ? "an in" : "a ", errno); 280 rte_errno = errno; 281 mlx5_free(mkey); 282 return NULL; 283 } 284 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 285 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 286 return mkey; 287 } 288 289 /** 290 * Get status of devx command response. 291 * Mainly used for asynchronous commands. 292 * 293 * @param[in] out 294 * The out response buffer. 295 * 296 * @return 297 * 0 on success, non-zero value otherwise. 298 */ 299 int 300 mlx5_devx_get_out_command_status(void *out) 301 { 302 int status; 303 304 if (!out) 305 return -EINVAL; 306 status = MLX5_GET(query_flow_counter_out, out, status); 307 if (status) { 308 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 309 310 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 311 syndrome); 312 } 313 return status; 314 } 315 316 /** 317 * Destroy any object allocated by a Devx API. 318 * 319 * @param[in] obj 320 * Pointer to a general object. 321 * 322 * @return 323 * 0 on success, a negative value otherwise. 324 */ 325 int 326 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 327 { 328 int ret; 329 330 if (!obj) 331 return 0; 332 ret = mlx5_glue->devx_obj_destroy(obj->obj); 333 mlx5_free(obj); 334 return ret; 335 } 336 337 /** 338 * Query NIC vport context. 339 * Fills minimal inline attribute. 340 * 341 * @param[in] ctx 342 * ibv contexts returned from mlx5dv_open_device. 343 * @param[in] vport 344 * vport index 345 * @param[out] attr 346 * Attributes device values. 347 * 348 * @return 349 * 0 on success, a negative value otherwise. 350 */ 351 static int 352 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 353 unsigned int vport, 354 struct mlx5_hca_attr *attr) 355 { 356 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 357 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 358 void *vctx; 359 int status, syndrome, rc; 360 361 /* Query NIC vport context to determine inline mode. */ 362 MLX5_SET(query_nic_vport_context_in, in, opcode, 363 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 364 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 365 if (vport) 366 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 367 rc = mlx5_glue->devx_general_cmd(ctx, 368 in, sizeof(in), 369 out, sizeof(out)); 370 if (rc) 371 goto error; 372 status = MLX5_GET(query_nic_vport_context_out, out, status); 373 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 374 if (status) { 375 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 376 "status %x, syndrome = %x", status, syndrome); 377 return -1; 378 } 379 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 380 nic_vport_context); 381 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 382 min_wqe_inline_mode); 383 return 0; 384 error: 385 rc = (rc > 0) ? -rc : rc; 386 return rc; 387 } 388 389 /** 390 * Query NIC vDPA attributes. 391 * 392 * @param[in] ctx 393 * Context returned from mlx5 open_device() glue function. 394 * @param[out] vdpa_attr 395 * vDPA Attributes structure to fill. 396 */ 397 static void 398 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 399 struct mlx5_hca_vdpa_attr *vdpa_attr) 400 { 401 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 402 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 403 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 404 int status, syndrome, rc; 405 406 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 407 MLX5_SET(query_hca_cap_in, in, op_mod, 408 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 409 MLX5_HCA_CAP_OPMOD_GET_CUR); 410 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 411 status = MLX5_GET(query_hca_cap_out, out, status); 412 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 413 if (rc || status) { 414 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities," 415 " status %x, syndrome = %x", status, syndrome); 416 vdpa_attr->valid = 0; 417 } else { 418 vdpa_attr->valid = 1; 419 vdpa_attr->desc_tunnel_offload_type = 420 MLX5_GET(virtio_emulation_cap, hcattr, 421 desc_tunnel_offload_type); 422 vdpa_attr->eth_frame_offload_type = 423 MLX5_GET(virtio_emulation_cap, hcattr, 424 eth_frame_offload_type); 425 vdpa_attr->virtio_version_1_0 = 426 MLX5_GET(virtio_emulation_cap, hcattr, 427 virtio_version_1_0); 428 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 429 tso_ipv4); 430 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 431 tso_ipv6); 432 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 433 tx_csum); 434 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 435 rx_csum); 436 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 437 event_mode); 438 vdpa_attr->virtio_queue_type = 439 MLX5_GET(virtio_emulation_cap, hcattr, 440 virtio_queue_type); 441 vdpa_attr->log_doorbell_stride = 442 MLX5_GET(virtio_emulation_cap, hcattr, 443 log_doorbell_stride); 444 vdpa_attr->log_doorbell_bar_size = 445 MLX5_GET(virtio_emulation_cap, hcattr, 446 log_doorbell_bar_size); 447 vdpa_attr->doorbell_bar_offset = 448 MLX5_GET64(virtio_emulation_cap, hcattr, 449 doorbell_bar_offset); 450 vdpa_attr->max_num_virtio_queues = 451 MLX5_GET(virtio_emulation_cap, hcattr, 452 max_num_virtio_queues); 453 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 454 umem_1_buffer_param_a); 455 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 456 umem_1_buffer_param_b); 457 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 458 umem_2_buffer_param_a); 459 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 460 umem_2_buffer_param_b); 461 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 462 umem_3_buffer_param_a); 463 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 464 umem_3_buffer_param_b); 465 } 466 } 467 468 int 469 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 470 uint32_t ids[], uint32_t num) 471 { 472 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 473 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 474 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 475 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 476 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 477 int ret; 478 uint32_t idx = 0; 479 uint32_t i; 480 481 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 482 rte_errno = EINVAL; 483 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 484 return -rte_errno; 485 } 486 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 487 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 488 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 489 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 490 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 491 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 492 out, sizeof(out)); 493 if (ret) { 494 rte_errno = ret; 495 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 496 (void *)flex_obj); 497 return -rte_errno; 498 } 499 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 500 void *s_off = (void *)((char *)sample + i * 501 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 502 uint32_t en; 503 504 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 505 flow_match_sample_en); 506 if (!en) 507 continue; 508 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 509 flow_match_sample_field_id); 510 } 511 if (num != idx) { 512 rte_errno = EINVAL; 513 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 514 return -rte_errno; 515 } 516 return ret; 517 } 518 519 520 struct mlx5_devx_obj * 521 mlx5_devx_cmd_create_flex_parser(void *ctx, 522 struct mlx5_devx_graph_node_attr *data) 523 { 524 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 525 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 526 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 527 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 528 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 529 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 530 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 531 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 532 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 533 uint32_t i; 534 535 if (!parse_flex_obj) { 536 DRV_LOG(ERR, "Failed to allocate flex parser data."); 537 rte_errno = ENOMEM; 538 return NULL; 539 } 540 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 541 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 542 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 543 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 544 MLX5_SET(parse_graph_flex, flex, header_length_mode, 545 data->header_length_mode); 546 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 547 data->header_length_base_value); 548 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 549 data->header_length_field_offset); 550 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 551 data->header_length_field_shift); 552 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 553 data->header_length_field_mask); 554 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 555 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 556 void *s_off = (void *)((char *)sample + i * 557 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 558 559 if (!s->flow_match_sample_en) 560 continue; 561 MLX5_SET(parse_graph_flow_match_sample, s_off, 562 flow_match_sample_en, !!s->flow_match_sample_en); 563 MLX5_SET(parse_graph_flow_match_sample, s_off, 564 flow_match_sample_field_offset, 565 s->flow_match_sample_field_offset); 566 MLX5_SET(parse_graph_flow_match_sample, s_off, 567 flow_match_sample_offset_mode, 568 s->flow_match_sample_offset_mode); 569 MLX5_SET(parse_graph_flow_match_sample, s_off, 570 flow_match_sample_field_offset_mask, 571 s->flow_match_sample_field_offset_mask); 572 MLX5_SET(parse_graph_flow_match_sample, s_off, 573 flow_match_sample_field_offset_shift, 574 s->flow_match_sample_field_offset_shift); 575 MLX5_SET(parse_graph_flow_match_sample, s_off, 576 flow_match_sample_field_base_offset, 577 s->flow_match_sample_field_base_offset); 578 MLX5_SET(parse_graph_flow_match_sample, s_off, 579 flow_match_sample_tunnel_mode, 580 s->flow_match_sample_tunnel_mode); 581 } 582 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 583 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 584 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 585 void *in_off = (void *)((char *)in_arc + i * 586 MLX5_ST_SZ_BYTES(parse_graph_arc)); 587 void *out_off = (void *)((char *)out_arc + i * 588 MLX5_ST_SZ_BYTES(parse_graph_arc)); 589 590 if (ia->arc_parse_graph_node != 0) { 591 MLX5_SET(parse_graph_arc, in_off, 592 compare_condition_value, 593 ia->compare_condition_value); 594 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 595 ia->start_inner_tunnel); 596 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 597 ia->arc_parse_graph_node); 598 MLX5_SET(parse_graph_arc, in_off, 599 parse_graph_node_handle, 600 ia->parse_graph_node_handle); 601 } 602 if (oa->arc_parse_graph_node != 0) { 603 MLX5_SET(parse_graph_arc, out_off, 604 compare_condition_value, 605 oa->compare_condition_value); 606 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 607 oa->start_inner_tunnel); 608 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 609 oa->arc_parse_graph_node); 610 MLX5_SET(parse_graph_arc, out_off, 611 parse_graph_node_handle, 612 oa->parse_graph_node_handle); 613 } 614 } 615 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 616 out, sizeof(out)); 617 if (!parse_flex_obj->obj) { 618 rte_errno = errno; 619 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 620 "by using DevX."); 621 mlx5_free(parse_flex_obj); 622 return NULL; 623 } 624 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 625 return parse_flex_obj; 626 } 627 628 /** 629 * Query HCA attributes. 630 * Using those attributes we can check on run time if the device 631 * is having the required capabilities. 632 * 633 * @param[in] ctx 634 * Context returned from mlx5 open_device() glue function. 635 * @param[out] attr 636 * Attributes device values. 637 * 638 * @return 639 * 0 on success, a negative value otherwise. 640 */ 641 int 642 mlx5_devx_cmd_query_hca_attr(void *ctx, 643 struct mlx5_hca_attr *attr) 644 { 645 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 646 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 647 void *hcattr; 648 int status, syndrome, rc, i; 649 650 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 651 MLX5_SET(query_hca_cap_in, in, op_mod, 652 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 653 MLX5_HCA_CAP_OPMOD_GET_CUR); 654 655 rc = mlx5_glue->devx_general_cmd(ctx, 656 in, sizeof(in), out, sizeof(out)); 657 if (rc) 658 goto error; 659 status = MLX5_GET(query_hca_cap_out, out, status); 660 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 661 if (status) { 662 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 663 "status %x, syndrome = %x", status, syndrome); 664 return -1; 665 } 666 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 667 attr->flow_counter_bulk_alloc_bitmap = 668 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 669 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 670 flow_counters_dump); 671 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 672 log_max_rqt_size); 673 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 674 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 675 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 676 log_max_hairpin_queues); 677 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 678 log_max_hairpin_wq_data_sz); 679 attr->log_max_hairpin_num_packets = MLX5_GET 680 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 681 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 682 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 683 relaxed_ordering_write); 684 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 685 relaxed_ordering_read); 686 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 687 access_register_user); 688 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 689 eth_net_offloads); 690 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 691 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 692 flex_parser_protocols); 693 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 694 max_geneve_tlv_options); 695 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 696 max_geneve_tlv_option_data_len); 697 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 698 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 699 general_obj_types) & 700 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 701 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 702 general_obj_types) & 703 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 704 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 705 general_obj_types) & 706 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 707 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 708 wqe_index_ignore_cap); 709 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 710 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 711 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 712 log_max_static_sq_wq); 713 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 714 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 715 device_frequency_khz); 716 attr->scatter_fcs_w_decap_disable = 717 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 718 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 719 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 720 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 721 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp); 722 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 723 regexp_num_of_engines); 724 attr->flow_hit_aso = !!(MLX5_GET64(cmd_hca_cap, hcattr, 725 general_obj_types) & 726 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 727 attr->geneve_tlv_opt = !!(MLX5_GET64(cmd_hca_cap, hcattr, 728 general_obj_types) & 729 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 730 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 731 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 732 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 733 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 734 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 735 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 736 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 737 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 738 attr->reg_c_preserve = 739 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 740 attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo); 741 attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress); 742 attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress); 743 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 744 compress_min_block_size); 745 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 746 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 747 log_compress_mmo_size); 748 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 749 log_decompress_mmo_size); 750 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 751 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 752 mini_cqe_resp_flow_tag); 753 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 754 mini_cqe_resp_l3_l4_tag); 755 if (attr->qos.sup) { 756 MLX5_SET(query_hca_cap_in, in, op_mod, 757 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 758 MLX5_HCA_CAP_OPMOD_GET_CUR); 759 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 760 out, sizeof(out)); 761 if (rc) 762 goto error; 763 if (status) { 764 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities," 765 " status %x, syndrome = %x", status, syndrome); 766 return -1; 767 } 768 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 769 attr->qos.flow_meter_old = 770 MLX5_GET(qos_cap, hcattr, flow_meter_old); 771 attr->qos.log_max_flow_meter = 772 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 773 attr->qos.flow_meter_reg_c_ids = 774 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 775 attr->qos.flow_meter = 776 MLX5_GET(qos_cap, hcattr, flow_meter); 777 attr->qos.packet_pacing = 778 MLX5_GET(qos_cap, hcattr, packet_pacing); 779 attr->qos.wqe_rate_pp = 780 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 781 } 782 if (attr->vdpa.valid) 783 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 784 if (!attr->eth_net_offloads) 785 return 0; 786 787 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 788 memset(in, 0, sizeof(in)); 789 memset(out, 0, sizeof(out)); 790 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 791 MLX5_SET(query_hca_cap_in, in, op_mod, 792 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 793 MLX5_HCA_CAP_OPMOD_GET_CUR); 794 795 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 796 if (rc) 797 goto error; 798 status = MLX5_GET(query_hca_cap_out, out, status); 799 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 800 if (status) { 801 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 802 "status %x, syndrome = %x", status, syndrome); 803 attr->log_max_ft_sampler_num = 0; 804 return -1; 805 } 806 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 807 attr->log_max_ft_sampler_num = 808 MLX5_GET(flow_table_nic_cap, 809 hcattr, flow_table_properties.log_max_ft_sampler_num); 810 811 /* Query HCA offloads for Ethernet protocol. */ 812 memset(in, 0, sizeof(in)); 813 memset(out, 0, sizeof(out)); 814 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 815 MLX5_SET(query_hca_cap_in, in, op_mod, 816 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 817 MLX5_HCA_CAP_OPMOD_GET_CUR); 818 819 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 820 if (rc) { 821 attr->eth_net_offloads = 0; 822 goto error; 823 } 824 status = MLX5_GET(query_hca_cap_out, out, status); 825 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 826 if (status) { 827 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 828 "status %x, syndrome = %x", status, syndrome); 829 attr->eth_net_offloads = 0; 830 return -1; 831 } 832 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 833 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 834 hcattr, wqe_vlan_insert); 835 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 836 lro_cap); 837 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 838 hcattr, tunnel_lro_gre); 839 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 840 hcattr, tunnel_lro_vxlan); 841 attr->lro_max_msg_sz_mode = MLX5_GET 842 (per_protocol_networking_offload_caps, 843 hcattr, lro_max_msg_sz_mode); 844 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 845 attr->lro_timer_supported_periods[i] = 846 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 847 lro_timer_supported_periods[i]); 848 } 849 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 850 hcattr, lro_min_mss_size); 851 attr->tunnel_stateless_geneve_rx = 852 MLX5_GET(per_protocol_networking_offload_caps, 853 hcattr, tunnel_stateless_geneve_rx); 854 attr->geneve_max_opt_len = 855 MLX5_GET(per_protocol_networking_offload_caps, 856 hcattr, max_geneve_opt_len); 857 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 858 hcattr, wqe_inline_mode); 859 attr->tunnel_stateless_gtp = MLX5_GET 860 (per_protocol_networking_offload_caps, 861 hcattr, tunnel_stateless_gtp); 862 attr->rss_ind_tbl_cap = MLX5_GET 863 (per_protocol_networking_offload_caps, 864 hcattr, rss_ind_tbl_cap); 865 /* Query HCA attribute for ROCE. */ 866 if (attr->roce) { 867 memset(in, 0, sizeof(in)); 868 memset(out, 0, sizeof(out)); 869 MLX5_SET(query_hca_cap_in, in, opcode, 870 MLX5_CMD_OP_QUERY_HCA_CAP); 871 MLX5_SET(query_hca_cap_in, in, op_mod, 872 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 873 MLX5_HCA_CAP_OPMOD_GET_CUR); 874 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 875 out, sizeof(out)); 876 if (rc) 877 goto error; 878 status = MLX5_GET(query_hca_cap_out, out, status); 879 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 880 if (status) { 881 DRV_LOG(DEBUG, 882 "Failed to query devx HCA ROCE capabilities, " 883 "status %x, syndrome = %x", status, syndrome); 884 return -1; 885 } 886 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 887 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 888 } 889 if (attr->eth_virt && 890 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 891 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 892 if (rc) { 893 attr->eth_virt = 0; 894 goto error; 895 } 896 } 897 return 0; 898 error: 899 rc = (rc > 0) ? -rc : rc; 900 return rc; 901 } 902 903 /** 904 * Query TIS transport domain from QP verbs object using DevX API. 905 * 906 * @param[in] qp 907 * Pointer to verbs QP returned by ibv_create_qp . 908 * @param[in] tis_num 909 * TIS number of TIS to query. 910 * @param[out] tis_td 911 * Pointer to TIS transport domain variable, to be set by the routine. 912 * 913 * @return 914 * 0 on success, a negative value otherwise. 915 */ 916 int 917 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 918 uint32_t *tis_td) 919 { 920 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 921 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 922 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 923 int rc; 924 void *tis_ctx; 925 926 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 927 MLX5_SET(query_tis_in, in, tisn, tis_num); 928 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 929 if (rc) { 930 DRV_LOG(ERR, "Failed to query QP using DevX"); 931 return -rc; 932 }; 933 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 934 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 935 return 0; 936 #else 937 (void)qp; 938 (void)tis_num; 939 (void)tis_td; 940 return -ENOTSUP; 941 #endif 942 } 943 944 /** 945 * Fill WQ data for DevX API command. 946 * Utility function for use when creating DevX objects containing a WQ. 947 * 948 * @param[in] wq_ctx 949 * Pointer to WQ context to fill with data. 950 * @param [in] wq_attr 951 * Pointer to WQ attributes structure to fill in WQ context. 952 */ 953 static void 954 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 955 { 956 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 957 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 958 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 959 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 960 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 961 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 962 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 963 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 964 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 965 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 966 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 967 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 968 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 969 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 970 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 971 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 972 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 973 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 974 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 975 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 976 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 977 wq_attr->log_hairpin_num_packets); 978 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 979 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 980 wq_attr->single_wqe_log_num_of_strides); 981 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 982 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 983 wq_attr->single_stride_log_num_of_bytes); 984 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 985 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 986 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 987 } 988 989 /** 990 * Create RQ using DevX API. 991 * 992 * @param[in] ctx 993 * Context returned from mlx5 open_device() glue function. 994 * @param [in] rq_attr 995 * Pointer to create RQ attributes structure. 996 * @param [in] socket 997 * CPU socket ID for allocations. 998 * 999 * @return 1000 * The DevX object created, NULL otherwise and rte_errno is set. 1001 */ 1002 struct mlx5_devx_obj * 1003 mlx5_devx_cmd_create_rq(void *ctx, 1004 struct mlx5_devx_create_rq_attr *rq_attr, 1005 int socket) 1006 { 1007 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1008 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1009 void *rq_ctx, *wq_ctx; 1010 struct mlx5_devx_wq_attr *wq_attr; 1011 struct mlx5_devx_obj *rq = NULL; 1012 1013 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1014 if (!rq) { 1015 DRV_LOG(ERR, "Failed to allocate RQ data"); 1016 rte_errno = ENOMEM; 1017 return NULL; 1018 } 1019 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1020 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1021 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1022 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1023 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1024 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1025 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1026 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1027 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1028 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1029 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1030 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1031 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1032 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1033 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1034 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1035 wq_attr = &rq_attr->wq_attr; 1036 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1037 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1038 out, sizeof(out)); 1039 if (!rq->obj) { 1040 DRV_LOG(ERR, "Failed to create RQ using DevX"); 1041 rte_errno = errno; 1042 mlx5_free(rq); 1043 return NULL; 1044 } 1045 rq->id = MLX5_GET(create_rq_out, out, rqn); 1046 return rq; 1047 } 1048 1049 /** 1050 * Modify RQ using DevX API. 1051 * 1052 * @param[in] rq 1053 * Pointer to RQ object structure. 1054 * @param [in] rq_attr 1055 * Pointer to modify RQ attributes structure. 1056 * 1057 * @return 1058 * 0 on success, a negative errno value otherwise and rte_errno is set. 1059 */ 1060 int 1061 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1062 struct mlx5_devx_modify_rq_attr *rq_attr) 1063 { 1064 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1065 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1066 void *rq_ctx, *wq_ctx; 1067 int ret; 1068 1069 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1070 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1071 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1072 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1073 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1074 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1075 if (rq_attr->modify_bitmask & 1076 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1077 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1078 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1079 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1080 if (rq_attr->modify_bitmask & 1081 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1082 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1083 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1084 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1085 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1086 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1087 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1088 } 1089 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1090 out, sizeof(out)); 1091 if (ret) { 1092 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1093 rte_errno = errno; 1094 return -errno; 1095 } 1096 return ret; 1097 } 1098 1099 /** 1100 * Create TIR using DevX API. 1101 * 1102 * @param[in] ctx 1103 * Context returned from mlx5 open_device() glue function. 1104 * @param [in] tir_attr 1105 * Pointer to TIR attributes structure. 1106 * 1107 * @return 1108 * The DevX object created, NULL otherwise and rte_errno is set. 1109 */ 1110 struct mlx5_devx_obj * 1111 mlx5_devx_cmd_create_tir(void *ctx, 1112 struct mlx5_devx_tir_attr *tir_attr) 1113 { 1114 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1115 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1116 void *tir_ctx, *outer, *inner, *rss_key; 1117 struct mlx5_devx_obj *tir = NULL; 1118 1119 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1120 if (!tir) { 1121 DRV_LOG(ERR, "Failed to allocate TIR data"); 1122 rte_errno = ENOMEM; 1123 return NULL; 1124 } 1125 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1126 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1127 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1128 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1129 tir_attr->lro_timeout_period_usecs); 1130 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1131 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1132 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1133 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1134 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1135 tir_attr->tunneled_offload_en); 1136 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1137 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1138 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1139 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1140 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1141 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1142 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1143 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1144 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1145 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1146 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1147 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1148 tir_attr->rx_hash_field_selector_outer.selected_fields); 1149 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1150 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1151 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1152 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1153 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1154 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1155 tir_attr->rx_hash_field_selector_inner.selected_fields); 1156 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1157 out, sizeof(out)); 1158 if (!tir->obj) { 1159 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1160 rte_errno = errno; 1161 mlx5_free(tir); 1162 return NULL; 1163 } 1164 tir->id = MLX5_GET(create_tir_out, out, tirn); 1165 return tir; 1166 } 1167 1168 /** 1169 * Modify TIR using DevX API. 1170 * 1171 * @param[in] tir 1172 * Pointer to TIR DevX object structure. 1173 * @param [in] modify_tir_attr 1174 * Pointer to TIR modification attributes structure. 1175 * 1176 * @return 1177 * 0 on success, a negative errno value otherwise and rte_errno is set. 1178 */ 1179 int 1180 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1181 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1182 { 1183 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1184 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1185 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1186 void *tir_ctx; 1187 int ret; 1188 1189 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1190 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1191 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1192 modify_tir_attr->modify_bitmask); 1193 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1194 if (modify_tir_attr->modify_bitmask & 1195 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1196 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1197 tir_attr->lro_timeout_period_usecs); 1198 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1199 tir_attr->lro_enable_mask); 1200 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1201 tir_attr->lro_max_msg_sz); 1202 } 1203 if (modify_tir_attr->modify_bitmask & 1204 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1205 MLX5_SET(tirc, tir_ctx, indirect_table, 1206 tir_attr->indirect_table); 1207 if (modify_tir_attr->modify_bitmask & 1208 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1209 int i; 1210 void *outer, *inner; 1211 1212 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1213 tir_attr->rx_hash_symmetric); 1214 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1215 for (i = 0; i < 10; i++) { 1216 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1217 tir_attr->rx_hash_toeplitz_key[i]); 1218 } 1219 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1220 rx_hash_field_selector_outer); 1221 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1222 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1223 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1224 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1225 MLX5_SET 1226 (rx_hash_field_select, outer, selected_fields, 1227 tir_attr->rx_hash_field_selector_outer.selected_fields); 1228 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1229 rx_hash_field_selector_inner); 1230 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1231 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1232 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1233 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1234 MLX5_SET 1235 (rx_hash_field_select, inner, selected_fields, 1236 tir_attr->rx_hash_field_selector_inner.selected_fields); 1237 } 1238 if (modify_tir_attr->modify_bitmask & 1239 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1240 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1241 } 1242 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1243 out, sizeof(out)); 1244 if (ret) { 1245 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1246 rte_errno = errno; 1247 return -errno; 1248 } 1249 return ret; 1250 } 1251 1252 /** 1253 * Create RQT using DevX API. 1254 * 1255 * @param[in] ctx 1256 * Context returned from mlx5 open_device() glue function. 1257 * @param [in] rqt_attr 1258 * Pointer to RQT attributes structure. 1259 * 1260 * @return 1261 * The DevX object created, NULL otherwise and rte_errno is set. 1262 */ 1263 struct mlx5_devx_obj * 1264 mlx5_devx_cmd_create_rqt(void *ctx, 1265 struct mlx5_devx_rqt_attr *rqt_attr) 1266 { 1267 uint32_t *in = NULL; 1268 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1269 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1270 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1271 void *rqt_ctx; 1272 struct mlx5_devx_obj *rqt = NULL; 1273 int i; 1274 1275 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1276 if (!in) { 1277 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1278 rte_errno = ENOMEM; 1279 return NULL; 1280 } 1281 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1282 if (!rqt) { 1283 DRV_LOG(ERR, "Failed to allocate RQT data"); 1284 rte_errno = ENOMEM; 1285 mlx5_free(in); 1286 return NULL; 1287 } 1288 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1289 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1290 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1291 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1292 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1293 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1294 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1295 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1296 mlx5_free(in); 1297 if (!rqt->obj) { 1298 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1299 rte_errno = errno; 1300 mlx5_free(rqt); 1301 return NULL; 1302 } 1303 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1304 return rqt; 1305 } 1306 1307 /** 1308 * Modify RQT using DevX API. 1309 * 1310 * @param[in] rqt 1311 * Pointer to RQT DevX object structure. 1312 * @param [in] rqt_attr 1313 * Pointer to RQT attributes structure. 1314 * 1315 * @return 1316 * 0 on success, a negative errno value otherwise and rte_errno is set. 1317 */ 1318 int 1319 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1320 struct mlx5_devx_rqt_attr *rqt_attr) 1321 { 1322 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1323 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1324 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1325 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1326 void *rqt_ctx; 1327 int i; 1328 int ret; 1329 1330 if (!in) { 1331 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1332 rte_errno = ENOMEM; 1333 return -ENOMEM; 1334 } 1335 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1336 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1337 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1338 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1339 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1340 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1341 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1342 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1343 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1344 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1345 mlx5_free(in); 1346 if (ret) { 1347 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1348 rte_errno = errno; 1349 return -rte_errno; 1350 } 1351 return ret; 1352 } 1353 1354 /** 1355 * Create SQ using DevX API. 1356 * 1357 * @param[in] ctx 1358 * Context returned from mlx5 open_device() glue function. 1359 * @param [in] sq_attr 1360 * Pointer to SQ attributes structure. 1361 * @param [in] socket 1362 * CPU socket ID for allocations. 1363 * 1364 * @return 1365 * The DevX object created, NULL otherwise and rte_errno is set. 1366 **/ 1367 struct mlx5_devx_obj * 1368 mlx5_devx_cmd_create_sq(void *ctx, 1369 struct mlx5_devx_create_sq_attr *sq_attr) 1370 { 1371 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1372 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1373 void *sq_ctx; 1374 void *wq_ctx; 1375 struct mlx5_devx_wq_attr *wq_attr; 1376 struct mlx5_devx_obj *sq = NULL; 1377 1378 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1379 if (!sq) { 1380 DRV_LOG(ERR, "Failed to allocate SQ data"); 1381 rte_errno = ENOMEM; 1382 return NULL; 1383 } 1384 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1385 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1386 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1387 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1388 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1389 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1390 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1391 sq_attr->allow_multi_pkt_send_wqe); 1392 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1393 sq_attr->min_wqe_inline_mode); 1394 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1395 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1396 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1397 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1398 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1399 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1400 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1401 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1402 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1403 sq_attr->packet_pacing_rate_limit_index); 1404 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1405 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1406 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1407 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1408 wq_attr = &sq_attr->wq_attr; 1409 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1410 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1411 out, sizeof(out)); 1412 if (!sq->obj) { 1413 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1414 rte_errno = errno; 1415 mlx5_free(sq); 1416 return NULL; 1417 } 1418 sq->id = MLX5_GET(create_sq_out, out, sqn); 1419 return sq; 1420 } 1421 1422 /** 1423 * Modify SQ using DevX API. 1424 * 1425 * @param[in] sq 1426 * Pointer to SQ object structure. 1427 * @param [in] sq_attr 1428 * Pointer to SQ attributes structure. 1429 * 1430 * @return 1431 * 0 on success, a negative errno value otherwise and rte_errno is set. 1432 */ 1433 int 1434 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1435 struct mlx5_devx_modify_sq_attr *sq_attr) 1436 { 1437 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1438 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1439 void *sq_ctx; 1440 int ret; 1441 1442 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1443 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1444 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1445 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1446 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1447 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1448 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1449 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1450 out, sizeof(out)); 1451 if (ret) { 1452 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1453 rte_errno = errno; 1454 return -rte_errno; 1455 } 1456 return ret; 1457 } 1458 1459 /** 1460 * Create TIS using DevX API. 1461 * 1462 * @param[in] ctx 1463 * Context returned from mlx5 open_device() glue function. 1464 * @param [in] tis_attr 1465 * Pointer to TIS attributes structure. 1466 * 1467 * @return 1468 * The DevX object created, NULL otherwise and rte_errno is set. 1469 */ 1470 struct mlx5_devx_obj * 1471 mlx5_devx_cmd_create_tis(void *ctx, 1472 struct mlx5_devx_tis_attr *tis_attr) 1473 { 1474 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1475 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1476 struct mlx5_devx_obj *tis = NULL; 1477 void *tis_ctx; 1478 1479 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1480 if (!tis) { 1481 DRV_LOG(ERR, "Failed to allocate TIS object"); 1482 rte_errno = ENOMEM; 1483 return NULL; 1484 } 1485 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1486 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1487 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1488 tis_attr->strict_lag_tx_port_affinity); 1489 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1490 tis_attr->lag_tx_port_affinity); 1491 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1492 MLX5_SET(tisc, tis_ctx, transport_domain, 1493 tis_attr->transport_domain); 1494 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1495 out, sizeof(out)); 1496 if (!tis->obj) { 1497 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1498 rte_errno = errno; 1499 mlx5_free(tis); 1500 return NULL; 1501 } 1502 tis->id = MLX5_GET(create_tis_out, out, tisn); 1503 return tis; 1504 } 1505 1506 /** 1507 * Create transport domain using DevX API. 1508 * 1509 * @param[in] ctx 1510 * Context returned from mlx5 open_device() glue function. 1511 * @return 1512 * The DevX object created, NULL otherwise and rte_errno is set. 1513 */ 1514 struct mlx5_devx_obj * 1515 mlx5_devx_cmd_create_td(void *ctx) 1516 { 1517 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1518 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1519 struct mlx5_devx_obj *td = NULL; 1520 1521 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1522 if (!td) { 1523 DRV_LOG(ERR, "Failed to allocate TD object"); 1524 rte_errno = ENOMEM; 1525 return NULL; 1526 } 1527 MLX5_SET(alloc_transport_domain_in, in, opcode, 1528 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1529 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1530 out, sizeof(out)); 1531 if (!td->obj) { 1532 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1533 rte_errno = errno; 1534 mlx5_free(td); 1535 return NULL; 1536 } 1537 td->id = MLX5_GET(alloc_transport_domain_out, out, 1538 transport_domain); 1539 return td; 1540 } 1541 1542 /** 1543 * Dump all flows to file. 1544 * 1545 * @param[in] fdb_domain 1546 * FDB domain. 1547 * @param[in] rx_domain 1548 * RX domain. 1549 * @param[in] tx_domain 1550 * TX domain. 1551 * @param[out] file 1552 * Pointer to file stream. 1553 * 1554 * @return 1555 * 0 on success, a nagative value otherwise. 1556 */ 1557 int 1558 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1559 void *rx_domain __rte_unused, 1560 void *tx_domain __rte_unused, FILE *file __rte_unused) 1561 { 1562 int ret = 0; 1563 1564 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1565 if (fdb_domain) { 1566 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1567 if (ret) 1568 return ret; 1569 } 1570 MLX5_ASSERT(rx_domain); 1571 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1572 if (ret) 1573 return ret; 1574 MLX5_ASSERT(tx_domain); 1575 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1576 #else 1577 ret = ENOTSUP; 1578 #endif 1579 return -ret; 1580 } 1581 1582 /* 1583 * Create CQ using DevX API. 1584 * 1585 * @param[in] ctx 1586 * Context returned from mlx5 open_device() glue function. 1587 * @param [in] attr 1588 * Pointer to CQ attributes structure. 1589 * 1590 * @return 1591 * The DevX object created, NULL otherwise and rte_errno is set. 1592 */ 1593 struct mlx5_devx_obj * 1594 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1595 { 1596 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1597 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1598 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1599 sizeof(*cq_obj), 1600 0, SOCKET_ID_ANY); 1601 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1602 1603 if (!cq_obj) { 1604 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1605 rte_errno = ENOMEM; 1606 return NULL; 1607 } 1608 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1609 if (attr->db_umem_valid) { 1610 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1611 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1612 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1613 } else { 1614 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1615 } 1616 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1617 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1618 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1619 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1620 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1621 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1622 MLX5_SET(cqc, cqctx, log_page_size, 1623 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1624 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1625 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1626 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1627 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1628 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1629 attr->mini_cqe_res_format_ext); 1630 if (attr->q_umem_valid) { 1631 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1632 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1633 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1634 attr->q_umem_offset); 1635 } 1636 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1637 sizeof(out)); 1638 if (!cq_obj->obj) { 1639 rte_errno = errno; 1640 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1641 mlx5_free(cq_obj); 1642 return NULL; 1643 } 1644 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1645 return cq_obj; 1646 } 1647 1648 /** 1649 * Create VIRTQ using DevX API. 1650 * 1651 * @param[in] ctx 1652 * Context returned from mlx5 open_device() glue function. 1653 * @param [in] attr 1654 * Pointer to VIRTQ attributes structure. 1655 * 1656 * @return 1657 * The DevX object created, NULL otherwise and rte_errno is set. 1658 */ 1659 struct mlx5_devx_obj * 1660 mlx5_devx_cmd_create_virtq(void *ctx, 1661 struct mlx5_devx_virtq_attr *attr) 1662 { 1663 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1664 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1665 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1666 sizeof(*virtq_obj), 1667 0, SOCKET_ID_ANY); 1668 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1669 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1670 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1671 1672 if (!virtq_obj) { 1673 DRV_LOG(ERR, "Failed to allocate virtq data."); 1674 rte_errno = ENOMEM; 1675 return NULL; 1676 } 1677 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1678 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1679 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1680 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1681 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1682 attr->hw_available_index); 1683 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1684 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1685 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1686 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1687 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1688 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1689 attr->virtio_version_1_0); 1690 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1691 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1692 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1693 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1694 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1695 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1696 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1697 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1698 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1699 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 1700 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 1701 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 1702 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 1703 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 1704 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 1705 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 1706 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 1707 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 1708 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 1709 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 1710 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 1711 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 1712 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 1713 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1714 sizeof(out)); 1715 if (!virtq_obj->obj) { 1716 rte_errno = errno; 1717 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 1718 mlx5_free(virtq_obj); 1719 return NULL; 1720 } 1721 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1722 return virtq_obj; 1723 } 1724 1725 /** 1726 * Modify VIRTQ using DevX API. 1727 * 1728 * @param[in] virtq_obj 1729 * Pointer to virtq object structure. 1730 * @param [in] attr 1731 * Pointer to modify virtq attributes structure. 1732 * 1733 * @return 1734 * 0 on success, a negative errno value otherwise and rte_errno is set. 1735 */ 1736 int 1737 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 1738 struct mlx5_devx_virtq_attr *attr) 1739 { 1740 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1741 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1742 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1743 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1744 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1745 int ret; 1746 1747 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1748 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 1749 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1750 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1751 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1752 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 1753 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1754 switch (attr->type) { 1755 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 1756 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 1757 break; 1758 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 1759 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 1760 attr->dirty_bitmap_mkey); 1761 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 1762 attr->dirty_bitmap_addr); 1763 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 1764 attr->dirty_bitmap_size); 1765 break; 1766 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 1767 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 1768 attr->dirty_bitmap_dump_enable); 1769 break; 1770 default: 1771 rte_errno = EINVAL; 1772 return -rte_errno; 1773 } 1774 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 1775 out, sizeof(out)); 1776 if (ret) { 1777 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1778 rte_errno = errno; 1779 return -rte_errno; 1780 } 1781 return ret; 1782 } 1783 1784 /** 1785 * Query VIRTQ using DevX API. 1786 * 1787 * @param[in] virtq_obj 1788 * Pointer to virtq object structure. 1789 * @param [in/out] attr 1790 * Pointer to virtq attributes structure. 1791 * 1792 * @return 1793 * 0 on success, a negative errno value otherwise and rte_errno is set. 1794 */ 1795 int 1796 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 1797 struct mlx5_devx_virtq_attr *attr) 1798 { 1799 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1800 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 1801 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 1802 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 1803 int ret; 1804 1805 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1806 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1807 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1808 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1809 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1810 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 1811 out, sizeof(out)); 1812 if (ret) { 1813 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1814 rte_errno = errno; 1815 return -errno; 1816 } 1817 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 1818 hw_available_index); 1819 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 1820 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 1821 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 1822 virtio_q_context.error_type); 1823 return ret; 1824 } 1825 1826 /** 1827 * Create QP using DevX API. 1828 * 1829 * @param[in] ctx 1830 * Context returned from mlx5 open_device() glue function. 1831 * @param [in] attr 1832 * Pointer to QP attributes structure. 1833 * 1834 * @return 1835 * The DevX object created, NULL otherwise and rte_errno is set. 1836 */ 1837 struct mlx5_devx_obj * 1838 mlx5_devx_cmd_create_qp(void *ctx, 1839 struct mlx5_devx_qp_attr *attr) 1840 { 1841 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 1842 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 1843 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 1844 sizeof(*qp_obj), 1845 0, SOCKET_ID_ANY); 1846 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1847 1848 if (!qp_obj) { 1849 DRV_LOG(ERR, "Failed to allocate QP data."); 1850 rte_errno = ENOMEM; 1851 return NULL; 1852 } 1853 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 1854 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 1855 MLX5_SET(qpc, qpc, pd, attr->pd); 1856 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 1857 if (attr->uar_index) { 1858 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1859 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 1860 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1861 MLX5_SET(qpc, qpc, log_page_size, 1862 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1863 if (attr->sq_size) { 1864 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); 1865 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 1866 MLX5_SET(qpc, qpc, log_sq_size, 1867 rte_log2_u32(attr->sq_size)); 1868 } else { 1869 MLX5_SET(qpc, qpc, no_sq, 1); 1870 } 1871 if (attr->rq_size) { 1872 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); 1873 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 1874 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 1875 MLX5_LOG_RQ_STRIDE_SHIFT); 1876 MLX5_SET(qpc, qpc, log_rq_size, 1877 rte_log2_u32(attr->rq_size)); 1878 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 1879 } else { 1880 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1881 } 1882 if (attr->dbr_umem_valid) { 1883 MLX5_SET(qpc, qpc, dbr_umem_valid, 1884 attr->dbr_umem_valid); 1885 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 1886 } 1887 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 1888 MLX5_SET64(create_qp_in, in, wq_umem_offset, 1889 attr->wq_umem_offset); 1890 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 1891 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 1892 } else { 1893 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 1894 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1895 MLX5_SET(qpc, qpc, no_sq, 1); 1896 } 1897 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1898 sizeof(out)); 1899 if (!qp_obj->obj) { 1900 rte_errno = errno; 1901 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 1902 mlx5_free(qp_obj); 1903 return NULL; 1904 } 1905 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 1906 return qp_obj; 1907 } 1908 1909 /** 1910 * Modify QP using DevX API. 1911 * Currently supports only force loop-back QP. 1912 * 1913 * @param[in] qp 1914 * Pointer to QP object structure. 1915 * @param [in] qp_st_mod_op 1916 * The QP state modification operation. 1917 * @param [in] remote_qp_id 1918 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 1919 * 1920 * @return 1921 * 0 on success, a negative errno value otherwise and rte_errno is set. 1922 */ 1923 int 1924 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 1925 uint32_t remote_qp_id) 1926 { 1927 union { 1928 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 1929 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 1930 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 1931 } in; 1932 union { 1933 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 1934 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 1935 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 1936 } out; 1937 void *qpc; 1938 int ret; 1939 unsigned int inlen; 1940 unsigned int outlen; 1941 1942 memset(&in, 0, sizeof(in)); 1943 memset(&out, 0, sizeof(out)); 1944 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 1945 switch (qp_st_mod_op) { 1946 case MLX5_CMD_OP_RST2INIT_QP: 1947 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 1948 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 1949 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1950 MLX5_SET(qpc, qpc, rre, 1); 1951 MLX5_SET(qpc, qpc, rwe, 1); 1952 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1953 inlen = sizeof(in.rst2init); 1954 outlen = sizeof(out.rst2init); 1955 break; 1956 case MLX5_CMD_OP_INIT2RTR_QP: 1957 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 1958 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 1959 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 1960 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1961 MLX5_SET(qpc, qpc, mtu, 1); 1962 MLX5_SET(qpc, qpc, log_msg_max, 30); 1963 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 1964 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 1965 inlen = sizeof(in.init2rtr); 1966 outlen = sizeof(out.init2rtr); 1967 break; 1968 case MLX5_CMD_OP_RTR2RTS_QP: 1969 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 1970 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 1971 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 1972 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 1973 MLX5_SET(qpc, qpc, retry_count, 7); 1974 MLX5_SET(qpc, qpc, rnr_retry, 7); 1975 inlen = sizeof(in.rtr2rts); 1976 outlen = sizeof(out.rtr2rts); 1977 break; 1978 default: 1979 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 1980 qp_st_mod_op); 1981 rte_errno = EINVAL; 1982 return -rte_errno; 1983 } 1984 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 1985 if (ret) { 1986 DRV_LOG(ERR, "Failed to modify QP using DevX."); 1987 rte_errno = errno; 1988 return -rte_errno; 1989 } 1990 return ret; 1991 } 1992 1993 struct mlx5_devx_obj * 1994 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 1995 { 1996 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 1997 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1998 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 1999 sizeof(*couners_obj), 0, 2000 SOCKET_ID_ANY); 2001 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2002 2003 if (!couners_obj) { 2004 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2005 rte_errno = ENOMEM; 2006 return NULL; 2007 } 2008 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2009 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2010 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2011 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2012 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2013 sizeof(out)); 2014 if (!couners_obj->obj) { 2015 rte_errno = errno; 2016 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 2017 " DevX."); 2018 mlx5_free(couners_obj); 2019 return NULL; 2020 } 2021 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2022 return couners_obj; 2023 } 2024 2025 int 2026 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2027 struct mlx5_devx_virtio_q_couners_attr *attr) 2028 { 2029 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2030 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2031 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2032 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2033 virtio_q_counters); 2034 int ret; 2035 2036 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2037 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2038 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2039 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2040 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2041 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2042 sizeof(out)); 2043 if (ret) { 2044 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2045 rte_errno = errno; 2046 return -errno; 2047 } 2048 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2049 received_desc); 2050 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2051 completed_desc); 2052 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2053 error_cqes); 2054 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2055 bad_desc_errors); 2056 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2057 exceed_max_chain); 2058 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2059 invalid_buffer); 2060 return ret; 2061 } 2062 2063 /** 2064 * Create general object of type FLOW_HIT_ASO using DevX API. 2065 * 2066 * @param[in] ctx 2067 * Context returned from mlx5 open_device() glue function. 2068 * @param [in] pd 2069 * PD value to associate the FLOW_HIT_ASO object with. 2070 * 2071 * @return 2072 * The DevX object created, NULL otherwise and rte_errno is set. 2073 */ 2074 struct mlx5_devx_obj * 2075 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2076 { 2077 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2078 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2079 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2080 void *ptr = NULL; 2081 2082 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2083 0, SOCKET_ID_ANY); 2084 if (!flow_hit_aso_obj) { 2085 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2086 rte_errno = ENOMEM; 2087 return NULL; 2088 } 2089 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2090 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2091 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2092 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2093 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2094 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2095 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2096 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2097 out, sizeof(out)); 2098 if (!flow_hit_aso_obj->obj) { 2099 rte_errno = errno; 2100 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX."); 2101 mlx5_free(flow_hit_aso_obj); 2102 return NULL; 2103 } 2104 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2105 return flow_hit_aso_obj; 2106 } 2107 2108 /* 2109 * Create PD using DevX API. 2110 * 2111 * @param[in] ctx 2112 * Context returned from mlx5 open_device() glue function. 2113 * 2114 * @return 2115 * The DevX object created, NULL otherwise and rte_errno is set. 2116 */ 2117 struct mlx5_devx_obj * 2118 mlx5_devx_cmd_alloc_pd(void *ctx) 2119 { 2120 struct mlx5_devx_obj *ppd = 2121 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2122 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2123 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2124 2125 if (!ppd) { 2126 DRV_LOG(ERR, "Failed to allocate PD data."); 2127 rte_errno = ENOMEM; 2128 return NULL; 2129 } 2130 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2131 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2132 out, sizeof(out)); 2133 if (!ppd->obj) { 2134 mlx5_free(ppd); 2135 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2136 rte_errno = errno; 2137 return NULL; 2138 } 2139 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2140 return ppd; 2141 } 2142 2143 /** 2144 * Create general object of type GENEVE TLV option using DevX API. 2145 * 2146 * @param[in] ctx 2147 * Context returned from mlx5 open_device() glue function. 2148 * @param [in] class 2149 * TLV option variable value of class 2150 * @param [in] type 2151 * TLV option variable value of type 2152 * @param [in] len 2153 * TLV option variable value of len 2154 * 2155 * @return 2156 * The DevX object created, NULL otherwise and rte_errno is set. 2157 */ 2158 struct mlx5_devx_obj * 2159 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2160 uint16_t class, uint8_t type, uint8_t len) 2161 { 2162 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2163 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2164 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2165 sizeof(*geneve_tlv_opt_obj), 2166 0, SOCKET_ID_ANY); 2167 2168 if (!geneve_tlv_opt_obj) { 2169 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2170 rte_errno = ENOMEM; 2171 return NULL; 2172 } 2173 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2174 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2175 geneve_tlv_opt); 2176 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2177 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2178 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2179 MLX5_OBJ_TYPE_GENEVE_TLV_OPT); 2180 MLX5_SET(geneve_tlv_option, opt, option_class, 2181 rte_be_to_cpu_16(class)); 2182 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2183 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2184 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2185 sizeof(in), out, sizeof(out)); 2186 if (!geneve_tlv_opt_obj->obj) { 2187 rte_errno = errno; 2188 DRV_LOG(ERR, "Failed to create Geneve tlv option " 2189 "Obj using DevX."); 2190 mlx5_free(geneve_tlv_opt_obj); 2191 return NULL; 2192 } 2193 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2194 return geneve_tlv_opt_obj; 2195 } 2196 2197 int 2198 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2199 { 2200 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2201 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2202 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2203 int rc; 2204 void *rq_ctx; 2205 2206 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2207 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2208 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2209 if (rc) { 2210 rte_errno = errno; 2211 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2212 "rc = %d, errno = %d.", rc, errno); 2213 return -rc; 2214 }; 2215 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2216 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2217 return 0; 2218 #else 2219 (void)wq; 2220 (void)counter_set_id; 2221 return -ENOTSUP; 2222 #endif 2223 } 2224 2225 /* 2226 * Allocate queue counters via devx interface. 2227 * 2228 * @param[in] ctx 2229 * Context returned from mlx5 open_device() glue function. 2230 * 2231 * @return 2232 * Pointer to counter object on success, a NULL value otherwise and 2233 * rte_errno is set. 2234 */ 2235 struct mlx5_devx_obj * 2236 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2237 { 2238 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2239 SOCKET_ID_ANY); 2240 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2241 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2242 2243 if (!dcs) { 2244 rte_errno = ENOMEM; 2245 return NULL; 2246 } 2247 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2248 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2249 sizeof(out)); 2250 if (!dcs->obj) { 2251 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error " 2252 "%d.", errno); 2253 rte_errno = errno; 2254 mlx5_free(dcs); 2255 return NULL; 2256 } 2257 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2258 return dcs; 2259 } 2260 2261 /** 2262 * Query queue counters values. 2263 * 2264 * @param[in] dcs 2265 * devx object of the queue counter set. 2266 * @param[in] clear 2267 * Whether hardware should clear the counters after the query or not. 2268 * @param[out] out_of_buffers 2269 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2270 * 2271 * @return 2272 * 0 on success, a negative value otherwise. 2273 */ 2274 int 2275 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2276 uint32_t *out_of_buffers) 2277 { 2278 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2279 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2280 int rc; 2281 2282 MLX5_SET(query_q_counter_in, in, opcode, 2283 MLX5_CMD_OP_QUERY_Q_COUNTER); 2284 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2285 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2286 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2287 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2288 sizeof(out)); 2289 if (rc) { 2290 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2291 rte_errno = rc; 2292 return -rc; 2293 } 2294 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2295 return 0; 2296 } 2297