1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /* FW writes status value to the OUT buffer at offset 00H */ 17 #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status) 18 /* FW writes syndrome value to the OUT buffer at offset 04H */ 19 #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome) 20 21 #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1)) 22 23 #define DEVX_DRV_LOG(level, out, reason, param, value) \ 24 do { \ 25 /* \ 26 * Some (old) GCC compilers like 7.5.0 and aarch64 GCC 7.1-2017.08 \ 27 * do not expand correctly when the macro invoked when the `param` \ 28 * is `NULL`. \ 29 * Use `local_param` to avoid direct `NULL` expansion. \ 30 */ \ 31 const char *local_param = (const char *)param; \ 32 \ 33 rte_errno = errno; \ 34 if (!local_param) { \ 35 DRV_LOG(level, \ 36 "DevX %s failed errno=%d status=%#x syndrome=%#x", \ 37 (reason), errno, MLX5_FW_STATUS((out)), \ 38 MLX5_FW_SYNDROME((out))); \ 39 } else { \ 40 DRV_LOG(level, \ 41 "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x",\ 42 (reason), local_param, (value), errno, \ 43 MLX5_FW_STATUS((out)), MLX5_FW_SYNDROME((out))); \ 44 } \ 45 } while (0) 46 47 static void * 48 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, 49 int *err, uint32_t flags) 50 { 51 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); 52 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); 53 int rc; 54 55 memset(in, 0, size_in); 56 memset(out, 0, size_out); 57 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 58 MLX5_SET(query_hca_cap_in, in, op_mod, flags); 59 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); 60 if (rc || MLX5_FW_STATUS(out)) { 61 DEVX_DRV_LOG(ERR, out, "HCA capabilities", "func", flags >> 1); 62 if (err) 63 *err = MLX5_DEVX_ERR_RC(rc); 64 return NULL; 65 } 66 if (err) 67 *err = 0; 68 return MLX5_ADDR_OF(query_hca_cap_out, out, capability); 69 } 70 71 /** 72 * Perform read access to the registers. Reads data from register 73 * and writes ones to the specified buffer. 74 * 75 * @param[in] ctx 76 * Context returned from mlx5 open_device() glue function. 77 * @param[in] reg_id 78 * Register identifier according to the PRM. 79 * @param[in] arg 80 * Register access auxiliary parameter according to the PRM. 81 * @param[out] data 82 * Pointer to the buffer to store read data. 83 * @param[in] dw_cnt 84 * Buffer size in double words. 85 * 86 * @return 87 * 0 on success, a negative value otherwise. 88 */ 89 int 90 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 91 uint32_t *data, uint32_t dw_cnt) 92 { 93 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 94 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 95 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 96 int rc; 97 98 MLX5_ASSERT(data && dw_cnt); 99 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 100 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 101 DRV_LOG(ERR, "Not enough buffer for register read data"); 102 return -1; 103 } 104 MLX5_SET(access_register_in, in, opcode, 105 MLX5_CMD_OP_ACCESS_REGISTER_USER); 106 MLX5_SET(access_register_in, in, op_mod, 107 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 108 MLX5_SET(access_register_in, in, register_id, reg_id); 109 MLX5_SET(access_register_in, in, argument, arg); 110 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 111 MLX5_ST_SZ_BYTES(access_register_out) + 112 sizeof(uint32_t) * dw_cnt); 113 if (rc || MLX5_FW_STATUS(out)) { 114 DEVX_DRV_LOG(DEBUG, out, "read access", "NIC register", reg_id); 115 return MLX5_DEVX_ERR_RC(rc); 116 } 117 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 118 dw_cnt * sizeof(uint32_t)); 119 return 0; 120 } 121 122 /** 123 * Perform write access to the registers. 124 * 125 * @param[in] ctx 126 * Context returned from mlx5 open_device() glue function. 127 * @param[in] reg_id 128 * Register identifier according to the PRM. 129 * @param[in] arg 130 * Register access auxiliary parameter according to the PRM. 131 * @param[out] data 132 * Pointer to the buffer containing data to write. 133 * @param[in] dw_cnt 134 * Buffer size in double words (32bit units). 135 * 136 * @return 137 * 0 on success, a negative value otherwise. 138 */ 139 int 140 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 141 uint32_t *data, uint32_t dw_cnt) 142 { 143 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 144 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 145 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 146 int rc; 147 void *ptr; 148 149 MLX5_ASSERT(data && dw_cnt); 150 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 151 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 152 DRV_LOG(ERR, "Data to write exceeds max size"); 153 return -1; 154 } 155 MLX5_SET(access_register_in, in, opcode, 156 MLX5_CMD_OP_ACCESS_REGISTER_USER); 157 MLX5_SET(access_register_in, in, op_mod, 158 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 159 MLX5_SET(access_register_in, in, register_id, reg_id); 160 MLX5_SET(access_register_in, in, argument, arg); 161 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 162 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 163 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 164 if (rc || MLX5_FW_STATUS(out)) { 165 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 166 return MLX5_DEVX_ERR_RC(rc); 167 } 168 rc = mlx5_glue->devx_general_cmd(ctx, in, 169 MLX5_ST_SZ_BYTES(access_register_in) + 170 dw_cnt * sizeof(uint32_t), 171 out, sizeof(out)); 172 if (rc || MLX5_FW_STATUS(out)) { 173 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 174 return MLX5_DEVX_ERR_RC(rc); 175 } 176 return 0; 177 } 178 179 struct mlx5_devx_obj * 180 mlx5_devx_cmd_flow_counter_alloc_general(void *ctx, 181 struct mlx5_devx_counter_attr *attr) 182 { 183 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 184 0, SOCKET_ID_ANY); 185 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 186 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 187 188 if (!dcs) { 189 rte_errno = ENOMEM; 190 return NULL; 191 } 192 MLX5_SET(alloc_flow_counter_in, in, opcode, 193 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 194 if (attr->bulk_log_max_alloc) 195 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk_log_size, 196 attr->flow_counter_bulk_log_size); 197 else 198 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, 199 attr->bulk_n_128); 200 if (attr->pd_valid) 201 MLX5_SET(alloc_flow_counter_in, in, pd, attr->pd); 202 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 203 sizeof(in), out, sizeof(out)); 204 if (!dcs->obj) { 205 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 206 rte_errno = errno; 207 mlx5_free(dcs); 208 return NULL; 209 } 210 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 211 return dcs; 212 } 213 214 /** 215 * Allocate flow counters via devx interface. 216 * 217 * @param[in] ctx 218 * Context returned from mlx5 open_device() glue function. 219 * @param dcs 220 * Pointer to counters properties structure to be filled by the routine. 221 * @param bulk_n_128 222 * Bulk counter numbers in 128 counters units. 223 * 224 * @return 225 * Pointer to counter object on success, a negative value otherwise and 226 * rte_errno is set. 227 */ 228 struct mlx5_devx_obj * 229 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 230 { 231 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 232 0, SOCKET_ID_ANY); 233 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 234 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 235 236 if (!dcs) { 237 rte_errno = ENOMEM; 238 return NULL; 239 } 240 MLX5_SET(alloc_flow_counter_in, in, opcode, 241 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 242 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 243 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 244 sizeof(in), out, sizeof(out)); 245 if (!dcs->obj) { 246 DEVX_DRV_LOG(ERR, out, "allocate counters", NULL, 0); 247 mlx5_free(dcs); 248 return NULL; 249 } 250 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 251 return dcs; 252 } 253 254 /** 255 * Query flow counters values. 256 * 257 * @param[in] dcs 258 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 259 * @param[in] clear 260 * Whether hardware should clear the counters after the query or not. 261 * @param[in] n_counters 262 * 0 in case of 1 counter to read, otherwise the counter number to read. 263 * @param pkts 264 * The number of packets that matched the flow. 265 * @param bytes 266 * The number of bytes that matched the flow. 267 * @param mkey 268 * The mkey key for batch query. 269 * @param addr 270 * The address in the mkey range for batch query. 271 * @param cmd_comp 272 * The completion object for asynchronous batch query. 273 * @param async_id 274 * The ID to be returned in the asynchronous batch query response. 275 * 276 * @return 277 * 0 on success, a negative value otherwise. 278 */ 279 int 280 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 281 int clear, uint32_t n_counters, 282 uint64_t *pkts, uint64_t *bytes, 283 uint32_t mkey, void *addr, 284 void *cmd_comp, 285 uint64_t async_id) 286 { 287 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 288 MLX5_ST_SZ_BYTES(traffic_counter); 289 uint32_t out[out_len]; 290 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 291 void *stats; 292 int rc; 293 294 MLX5_SET(query_flow_counter_in, in, opcode, 295 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 296 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 297 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 298 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 299 300 if (n_counters) { 301 MLX5_SET(query_flow_counter_in, in, num_of_counters, 302 n_counters); 303 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 304 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 305 MLX5_SET64(query_flow_counter_in, in, address, 306 (uint64_t)(uintptr_t)addr); 307 } 308 if (!cmd_comp) 309 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 310 out_len); 311 else 312 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 313 out_len, async_id, 314 cmd_comp); 315 if (rc) { 316 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 317 rte_errno = rc; 318 return -rc; 319 } 320 if (!n_counters) { 321 stats = MLX5_ADDR_OF(query_flow_counter_out, 322 out, flow_statistics); 323 *pkts = MLX5_GET64(traffic_counter, stats, packets); 324 *bytes = MLX5_GET64(traffic_counter, stats, octets); 325 } 326 return 0; 327 } 328 329 /** 330 * Create a new mkey. 331 * 332 * @param[in] ctx 333 * Context returned from mlx5 open_device() glue function. 334 * @param[in] attr 335 * Attributes of the requested mkey. 336 * 337 * @return 338 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 339 * is set. 340 */ 341 struct mlx5_devx_obj * 342 mlx5_devx_cmd_mkey_create(void *ctx, 343 struct mlx5_devx_mkey_attr *attr) 344 { 345 struct mlx5_klm *klm_array = attr->klm_array; 346 int klm_num = attr->klm_num; 347 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 348 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 349 uint32_t in[in_size_dw]; 350 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 351 void *mkc; 352 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 353 0, SOCKET_ID_ANY); 354 size_t pgsize; 355 uint32_t translation_size; 356 357 if (!mkey) { 358 rte_errno = ENOMEM; 359 return NULL; 360 } 361 memset(in, 0, in_size_dw * 4); 362 pgsize = rte_mem_page_size(); 363 if (pgsize == (size_t)-1) { 364 mlx5_free(mkey); 365 DRV_LOG(ERR, "Failed to get page size"); 366 rte_errno = ENOMEM; 367 return NULL; 368 } 369 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 370 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 371 if (klm_num > 0) { 372 int i; 373 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 374 klm_pas_mtt); 375 translation_size = RTE_ALIGN(klm_num, 4); 376 for (i = 0; i < klm_num; i++) { 377 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 378 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 379 MLX5_SET64(klm, klm, address, klm_array[i].address); 380 klm += MLX5_ST_SZ_BYTES(klm); 381 } 382 for (; i < (int)translation_size; i++) { 383 MLX5_SET(klm, klm, mkey, 0x0); 384 MLX5_SET64(klm, klm, address, 0x0); 385 klm += MLX5_ST_SZ_BYTES(klm); 386 } 387 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 388 MLX5_MKC_ACCESS_MODE_KLM_FBS : 389 MLX5_MKC_ACCESS_MODE_KLM); 390 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 391 } else { 392 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 393 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 394 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 395 } 396 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 397 translation_size); 398 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 399 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 400 MLX5_SET(mkc, mkc, lw, 0x1); 401 MLX5_SET(mkc, mkc, lr, 0x1); 402 if (attr->set_remote_rw) { 403 MLX5_SET(mkc, mkc, rw, 0x1); 404 MLX5_SET(mkc, mkc, rr, 0x1); 405 } 406 MLX5_SET(mkc, mkc, qpn, 0xffffff); 407 MLX5_SET(mkc, mkc, pd, attr->pd); 408 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 409 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 410 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 411 MLX5_SET(mkc, mkc, relaxed_ordering_write, 412 attr->relaxed_ordering_write); 413 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 414 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 415 MLX5_SET64(mkc, mkc, len, attr->size); 416 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 417 if (attr->crypto_en) { 418 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 419 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 420 } 421 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 422 sizeof(out)); 423 if (!mkey->obj) { 424 DEVX_DRV_LOG(ERR, out, klm_num ? "create indirect mkey" 425 : "create direct key", NULL, 0); 426 mlx5_free(mkey); 427 return NULL; 428 } 429 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 430 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 431 return mkey; 432 } 433 434 /** 435 * Get status of devx command response. 436 * Mainly used for asynchronous commands. 437 * 438 * @param[in] out 439 * The out response buffer. 440 * 441 * @return 442 * 0 on success, non-zero value otherwise. 443 */ 444 int 445 mlx5_devx_get_out_command_status(void *out) 446 { 447 int status; 448 449 if (!out) 450 return -EINVAL; 451 status = MLX5_GET(query_flow_counter_out, out, status); 452 if (status) { 453 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 454 455 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 456 syndrome); 457 } 458 return status; 459 } 460 461 /** 462 * Destroy any object allocated by a Devx API. 463 * 464 * @param[in] obj 465 * Pointer to a general object. 466 * 467 * @return 468 * 0 on success, a negative value otherwise. 469 */ 470 int 471 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 472 { 473 int ret; 474 475 if (!obj) 476 return 0; 477 ret = mlx5_glue->devx_obj_destroy(obj->obj); 478 mlx5_free(obj); 479 return ret; 480 } 481 482 /** 483 * Query NIC vport context. 484 * Fills minimal inline attribute. 485 * 486 * @param[in] ctx 487 * ibv contexts returned from mlx5dv_open_device. 488 * @param[in] vport 489 * vport index 490 * @param[out] attr 491 * Attributes device values. 492 * 493 * @return 494 * 0 on success, a negative value otherwise. 495 */ 496 static int 497 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 498 unsigned int vport, 499 struct mlx5_hca_attr *attr) 500 { 501 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 502 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 503 void *vctx; 504 int rc; 505 506 /* Query NIC vport context to determine inline mode. */ 507 MLX5_SET(query_nic_vport_context_in, in, opcode, 508 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 509 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 510 if (vport) 511 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 512 rc = mlx5_glue->devx_general_cmd(ctx, 513 in, sizeof(in), 514 out, sizeof(out)); 515 if (rc || MLX5_FW_STATUS(out)) { 516 DEVX_DRV_LOG(ERR, out, "query NIC vport context", NULL, 0); 517 return MLX5_DEVX_ERR_RC(rc); 518 } 519 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 520 nic_vport_context); 521 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 522 min_wqe_inline_mode); 523 return 0; 524 } 525 526 /** 527 * Query NIC vDPA attributes. 528 * 529 * @param[in] ctx 530 * Context returned from mlx5 open_device() glue function. 531 * @param[out] vdpa_attr 532 * vDPA Attributes structure to fill. 533 */ 534 static void 535 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 536 struct mlx5_hca_vdpa_attr *vdpa_attr) 537 { 538 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 539 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 540 void *hcattr; 541 542 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, 543 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 544 MLX5_HCA_CAP_OPMOD_GET_CUR); 545 if (!hcattr) { 546 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities"); 547 vdpa_attr->valid = 0; 548 } else { 549 vdpa_attr->valid = 1; 550 vdpa_attr->desc_tunnel_offload_type = 551 MLX5_GET(virtio_emulation_cap, hcattr, 552 desc_tunnel_offload_type); 553 vdpa_attr->eth_frame_offload_type = 554 MLX5_GET(virtio_emulation_cap, hcattr, 555 eth_frame_offload_type); 556 vdpa_attr->virtio_version_1_0 = 557 MLX5_GET(virtio_emulation_cap, hcattr, 558 virtio_version_1_0); 559 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 560 tso_ipv4); 561 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 562 tso_ipv6); 563 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 564 tx_csum); 565 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 566 rx_csum); 567 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 568 event_mode); 569 vdpa_attr->virtio_queue_type = 570 MLX5_GET(virtio_emulation_cap, hcattr, 571 virtio_queue_type); 572 vdpa_attr->log_doorbell_stride = 573 MLX5_GET(virtio_emulation_cap, hcattr, 574 log_doorbell_stride); 575 vdpa_attr->vnet_modify_ext = 576 MLX5_GET(virtio_emulation_cap, hcattr, 577 vnet_modify_ext); 578 vdpa_attr->virtio_net_q_addr_modify = 579 MLX5_GET(virtio_emulation_cap, hcattr, 580 virtio_net_q_addr_modify); 581 vdpa_attr->virtio_q_index_modify = 582 MLX5_GET(virtio_emulation_cap, hcattr, 583 virtio_q_index_modify); 584 vdpa_attr->log_doorbell_bar_size = 585 MLX5_GET(virtio_emulation_cap, hcattr, 586 log_doorbell_bar_size); 587 vdpa_attr->doorbell_bar_offset = 588 MLX5_GET64(virtio_emulation_cap, hcattr, 589 doorbell_bar_offset); 590 vdpa_attr->max_num_virtio_queues = 591 MLX5_GET(virtio_emulation_cap, hcattr, 592 max_num_virtio_queues); 593 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 594 umem_1_buffer_param_a); 595 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 596 umem_1_buffer_param_b); 597 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 598 umem_2_buffer_param_a); 599 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 600 umem_2_buffer_param_b); 601 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 602 umem_3_buffer_param_a); 603 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 604 umem_3_buffer_param_b); 605 } 606 } 607 608 /** 609 * Query match sample handle parameters. 610 * 611 * This command allows translating a field sample handle returned by either 612 * PARSE_GRAPH_FLOW_MATCH_SAMPLE or by GENEVE TLV OPTION object into values 613 * used for header modification or header matching/hashing. 614 * 615 * @param[in] ctx 616 * Context used to create either GENEVE TLV option or FLEX PARSE GRAPH object. 617 * @param[in] sample_field_id 618 * Field sample handle returned by either PARSE_GRAPH_FLOW_MATCH_SAMPLE 619 * or by GENEVE TLV OPTION object. 620 * @param[out] attr 621 * Pointer to match sample info attributes structure. 622 * 623 * @return 624 * 0 on success, a negative errno otherwise and rte_errno is set. 625 */ 626 int 627 mlx5_devx_cmd_match_sample_info_query(void *ctx, uint32_t sample_field_id, 628 struct mlx5_devx_match_sample_info_query_attr *attr) 629 { 630 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 631 uint32_t out[MLX5_ST_SZ_DW(query_match_sample_info_out)] = {0}; 632 uint32_t in[MLX5_ST_SZ_DW(query_match_sample_info_in)] = {0}; 633 int rc; 634 635 MLX5_SET(query_match_sample_info_in, in, opcode, 636 MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO); 637 MLX5_SET(query_match_sample_info_in, in, op_mod, 0); 638 MLX5_SET(query_match_sample_info_in, in, sample_field_id, 639 sample_field_id); 640 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 641 if (rc) { 642 DRV_LOG(ERR, "Failed to query match sample info using DevX: %s", 643 strerror(rc)); 644 rte_errno = rc; 645 return -rc; 646 } 647 attr->modify_field_id = MLX5_GET(query_match_sample_info_out, out, 648 modify_field_id); 649 attr->sample_dw_data = MLX5_GET(query_match_sample_info_out, out, 650 field_format_select_dw); 651 attr->sample_dw_ok_bit = MLX5_GET(query_match_sample_info_out, out, 652 ok_bit_format_select_dw); 653 attr->sample_dw_ok_bit_offset = MLX5_GET(query_match_sample_info_out, 654 out, ok_bit_offset); 655 return 0; 656 #else 657 (void)ctx; 658 (void)sample_field_id; 659 (void)attr; 660 return -ENOTSUP; 661 #endif 662 } 663 664 int 665 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 666 uint32_t *ids, 667 uint32_t num, uint8_t *anchor) 668 { 669 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 670 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 671 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 672 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 673 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 674 int ret; 675 uint32_t idx = 0; 676 uint32_t i; 677 678 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 679 rte_errno = EINVAL; 680 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 681 return -rte_errno; 682 } 683 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 684 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 685 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 686 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 687 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 688 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 689 out, sizeof(out)); 690 if (ret) { 691 rte_errno = ret; 692 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 693 (void *)flex_obj); 694 return -rte_errno; 695 } 696 if (anchor) 697 *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id); 698 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx < num; i++) { 699 void *s_off = (void *)((char *)sample + i * 700 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 701 uint32_t en; 702 703 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 704 flow_match_sample_en); 705 if (!en) 706 continue; 707 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 708 flow_match_sample_field_id); 709 } 710 if (num != idx) { 711 rte_errno = EINVAL; 712 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 713 return -rte_errno; 714 } 715 return ret; 716 } 717 718 struct mlx5_devx_obj * 719 mlx5_devx_cmd_create_flex_parser(void *ctx, 720 struct mlx5_devx_graph_node_attr *data) 721 { 722 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 723 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 724 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 725 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 726 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 727 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 728 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 729 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 730 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 731 uint32_t i; 732 733 if (!parse_flex_obj) { 734 DRV_LOG(ERR, "Failed to allocate flex parser data."); 735 rte_errno = ENOMEM; 736 return NULL; 737 } 738 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 739 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 740 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 741 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 742 MLX5_SET(parse_graph_flex, flex, header_length_mode, 743 data->header_length_mode); 744 MLX5_SET64(parse_graph_flex, flex, modify_field_select, 745 data->modify_field_select); 746 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 747 data->header_length_base_value); 748 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 749 data->header_length_field_offset); 750 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 751 data->header_length_field_shift); 752 MLX5_SET(parse_graph_flex, flex, next_header_field_offset, 753 data->next_header_field_offset); 754 MLX5_SET(parse_graph_flex, flex, next_header_field_size, 755 data->next_header_field_size); 756 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 757 data->header_length_field_mask); 758 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 759 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 760 void *s_off = (void *)((char *)sample + i * 761 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 762 763 if (!s->flow_match_sample_en) 764 continue; 765 MLX5_SET(parse_graph_flow_match_sample, s_off, 766 flow_match_sample_en, !!s->flow_match_sample_en); 767 MLX5_SET(parse_graph_flow_match_sample, s_off, 768 flow_match_sample_field_offset, 769 s->flow_match_sample_field_offset); 770 MLX5_SET(parse_graph_flow_match_sample, s_off, 771 flow_match_sample_offset_mode, 772 s->flow_match_sample_offset_mode); 773 MLX5_SET(parse_graph_flow_match_sample, s_off, 774 flow_match_sample_field_offset_mask, 775 s->flow_match_sample_field_offset_mask); 776 MLX5_SET(parse_graph_flow_match_sample, s_off, 777 flow_match_sample_field_offset_shift, 778 s->flow_match_sample_field_offset_shift); 779 MLX5_SET(parse_graph_flow_match_sample, s_off, 780 flow_match_sample_field_base_offset, 781 s->flow_match_sample_field_base_offset); 782 MLX5_SET(parse_graph_flow_match_sample, s_off, 783 flow_match_sample_tunnel_mode, 784 s->flow_match_sample_tunnel_mode); 785 } 786 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 787 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 788 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 789 void *in_off = (void *)((char *)in_arc + i * 790 MLX5_ST_SZ_BYTES(parse_graph_arc)); 791 void *out_off = (void *)((char *)out_arc + i * 792 MLX5_ST_SZ_BYTES(parse_graph_arc)); 793 794 if (ia->arc_parse_graph_node != 0) { 795 MLX5_SET(parse_graph_arc, in_off, 796 compare_condition_value, 797 ia->compare_condition_value); 798 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 799 ia->start_inner_tunnel); 800 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 801 ia->arc_parse_graph_node); 802 MLX5_SET(parse_graph_arc, in_off, 803 parse_graph_node_handle, 804 ia->parse_graph_node_handle); 805 } 806 if (oa->arc_parse_graph_node != 0) { 807 MLX5_SET(parse_graph_arc, out_off, 808 compare_condition_value, 809 oa->compare_condition_value); 810 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 811 oa->start_inner_tunnel); 812 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 813 oa->arc_parse_graph_node); 814 MLX5_SET(parse_graph_arc, out_off, 815 parse_graph_node_handle, 816 oa->parse_graph_node_handle); 817 } 818 } 819 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 820 out, sizeof(out)); 821 if (!parse_flex_obj->obj) { 822 DEVX_DRV_LOG(ERR, out, "create FLEX PARSE GRAPH", NULL, 0); 823 mlx5_free(parse_flex_obj); 824 return NULL; 825 } 826 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 827 return parse_flex_obj; 828 } 829 830 static int 831 mlx5_devx_cmd_query_hca_parse_graph_node_cap 832 (void *ctx, struct mlx5_hca_flex_attr *attr) 833 { 834 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 835 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 836 void *hcattr; 837 int rc; 838 839 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 840 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | 841 MLX5_HCA_CAP_OPMOD_GET_CUR); 842 if (!hcattr) 843 return rc; 844 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); 845 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); 846 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, 847 header_length_mode); 848 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, 849 sample_offset_mode); 850 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, 851 max_num_arc_in); 852 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, 853 max_num_arc_out); 854 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, 855 max_num_sample); 856 attr->parse_graph_anchor = MLX5_GET(parse_graph_node_cap, hcattr, parse_graph_anchor); 857 attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr, 858 sample_tunnel_inner2); 859 attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr, 860 zero_size_supported); 861 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, 862 sample_id_in_out); 863 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, 864 max_base_header_length); 865 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, 866 max_sample_base_offset); 867 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, 868 max_next_header_offset); 869 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, 870 header_length_mask_width); 871 /* Get the max supported samples from HCA CAP 2 */ 872 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 873 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 874 MLX5_HCA_CAP_OPMOD_GET_CUR); 875 if (!hcattr) 876 return rc; 877 attr->max_num_prog_sample = 878 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); 879 return 0; 880 } 881 882 static int 883 mlx5_devx_query_pkt_integrity_match(void *hcattr) 884 { 885 return MLX5_GET(flow_table_nic_cap, hcattr, 886 ft_field_support_2_nic_receive.inner_l3_ok) && 887 MLX5_GET(flow_table_nic_cap, hcattr, 888 ft_field_support_2_nic_receive.inner_l4_ok) && 889 MLX5_GET(flow_table_nic_cap, hcattr, 890 ft_field_support_2_nic_receive.outer_l3_ok) && 891 MLX5_GET(flow_table_nic_cap, hcattr, 892 ft_field_support_2_nic_receive.outer_l4_ok) && 893 MLX5_GET(flow_table_nic_cap, hcattr, 894 ft_field_support_2_nic_receive 895 .inner_ipv4_checksum_ok) && 896 MLX5_GET(flow_table_nic_cap, hcattr, 897 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 898 MLX5_GET(flow_table_nic_cap, hcattr, 899 ft_field_support_2_nic_receive 900 .outer_ipv4_checksum_ok) && 901 MLX5_GET(flow_table_nic_cap, hcattr, 902 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 903 } 904 905 /** 906 * Query HCA attributes. 907 * Using those attributes we can check on run time if the device 908 * is having the required capabilities. 909 * 910 * @param[in] ctx 911 * Context returned from mlx5 open_device() glue function. 912 * @param[out] attr 913 * Attributes device values. 914 * 915 * @return 916 * 0 on success, a negative value otherwise. 917 */ 918 int 919 mlx5_devx_cmd_query_hca_attr(void *ctx, 920 struct mlx5_hca_attr *attr) 921 { 922 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 923 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 924 bool hca_cap_2_sup; 925 uint64_t general_obj_types_supported = 0; 926 void *hcattr; 927 int rc, i; 928 929 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 930 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 931 MLX5_HCA_CAP_OPMOD_GET_CUR); 932 if (!hcattr) 933 return rc; 934 hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2); 935 attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq); 936 attr->flow_counter_bulk_alloc_bitmap = 937 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 938 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 939 flow_counters_dump); 940 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp); 941 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp); 942 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 943 log_max_rqt_size); 944 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 945 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 946 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 947 log_max_hairpin_queues); 948 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 949 log_max_hairpin_wq_data_sz); 950 attr->log_max_hairpin_num_packets = MLX5_GET 951 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 952 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 953 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 954 relaxed_ordering_write); 955 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 956 relaxed_ordering_read); 957 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 958 access_register_user); 959 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 960 eth_net_offloads); 961 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 962 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 963 flex_parser_protocols); 964 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 965 max_geneve_tlv_options); 966 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 967 max_geneve_tlv_option_data_len); 968 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 969 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 970 general_obj_types) & 971 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 972 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 973 general_obj_types) & 974 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 975 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 976 general_obj_types) & 977 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 978 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 979 general_obj_types) & 980 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 981 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 982 wqe_index_ignore_cap); 983 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 984 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 985 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 986 log_max_static_sq_wq); 987 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 988 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 989 device_frequency_khz); 990 attr->scatter_fcs_w_decap_disable = 991 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 992 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 993 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 994 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 995 attr->steering_format_version = 996 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 997 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 998 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 999 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 1000 regexp_num_of_engines); 1001 /* Read the general_obj_types bitmap and extract the relevant bits. */ 1002 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 1003 general_obj_types); 1004 attr->vdpa.valid = !!(general_obj_types_supported & 1005 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 1006 attr->vdpa.queue_counters_valid = 1007 !!(general_obj_types_supported & 1008 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 1009 attr->parse_graph_flex_node = 1010 !!(general_obj_types_supported & 1011 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 1012 attr->flow_hit_aso = !!(general_obj_types_supported & 1013 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 1014 attr->geneve_tlv_opt = !!(general_obj_types_supported & 1015 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 1016 attr->dek = !!(general_obj_types_supported & 1017 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 1018 attr->import_kek = !!(general_obj_types_supported & 1019 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 1020 attr->credential = !!(general_obj_types_supported & 1021 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 1022 attr->crypto_login = !!(general_obj_types_supported & 1023 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 1024 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 1025 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 1026 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 1027 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 1028 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 1029 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 1030 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 1031 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 1032 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 1033 attr->reg_c_preserve = 1034 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 1035 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 1036 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 1037 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 1038 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 1039 compress_mmo_sq); 1040 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 1041 decompress_mmo_sq); 1042 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 1043 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 1044 compress_mmo_qp); 1045 attr->decomp_deflate_v1_en = MLX5_GET(cmd_hca_cap, hcattr, 1046 decompress_deflate_v1); 1047 attr->decomp_deflate_v2_en = MLX5_GET(cmd_hca_cap, hcattr, 1048 decompress_deflate_v2); 1049 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 1050 compress_min_block_size); 1051 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 1052 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 1053 log_compress_mmo_size); 1054 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 1055 log_decompress_mmo_size); 1056 attr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr, 1057 decompress_lz4_data_only_v2); 1058 attr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, 1059 decompress_lz4_no_checksum_v2); 1060 attr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, 1061 decompress_lz4_checksum_v2); 1062 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 1063 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 1064 mini_cqe_resp_flow_tag); 1065 attr->cqe_compression_128 = MLX5_GET(cmd_hca_cap, hcattr, 1066 cqe_compression_128); 1067 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 1068 mini_cqe_resp_l3_l4_tag); 1069 attr->enhanced_cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, 1070 enhanced_cqe_compression); 1071 attr->umr_indirect_mkey_disabled = 1072 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 1073 attr->umr_modify_entity_size_disabled = 1074 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 1075 attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time); 1076 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 1077 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 1078 general_obj_types) & 1079 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 1080 attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); 1081 attr->striding_rq = MLX5_GET(cmd_hca_cap, hcattr, striding_rq); 1082 attr->ext_stride_num_range = 1083 MLX5_GET(cmd_hca_cap, hcattr, ext_stride_num_range); 1084 attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr, 1085 max_flow_counter_15_0); 1086 attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr, 1087 max_flow_counter_31_16); 1088 attr->alloc_flow_counter_pd = MLX5_GET(cmd_hca_cap, hcattr, 1089 alloc_flow_counter_pd); 1090 attr->flow_counter_access_aso = MLX5_GET(cmd_hca_cap, hcattr, 1091 flow_counter_access_aso); 1092 attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr, 1093 flow_access_aso_opc_mod); 1094 attr->wqe_based_flow_table_sup = MLX5_GET(cmd_hca_cap, hcattr, 1095 wqe_based_flow_table_update_cap); 1096 /* 1097 * Flex item support needs max_num_prog_sample_field 1098 * from the Capabilities 2 table for PARSE_GRAPH_NODE 1099 */ 1100 if (attr->parse_graph_flex_node) { 1101 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap 1102 (ctx, &attr->flex); 1103 if (rc) 1104 return -1; 1105 attr->flex.query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr, 1106 query_match_sample_info); 1107 } 1108 if (attr->crypto) { 1109 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) || 1110 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_multi_block_be_tweak) || 1111 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_single_block_le_tweak); 1112 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1113 MLX5_GET_HCA_CAP_OP_MOD_CRYPTO | 1114 MLX5_HCA_CAP_OPMOD_GET_CUR); 1115 if (!hcattr) 1116 return -1; 1117 attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps, 1118 hcattr, wrapped_import_method) 1119 & 1 << 2); 1120 } 1121 if (hca_cap_2_sup) { 1122 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1123 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 1124 MLX5_HCA_CAP_OPMOD_GET_CUR); 1125 if (!hcattr) { 1126 DRV_LOG(DEBUG, 1127 "Failed to query DevX HCA capabilities 2."); 1128 return rc; 1129 } 1130 attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, 1131 log_min_stride_wqe_sz); 1132 attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr, 1133 hairpin_sq_wqe_bb_size); 1134 attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr, 1135 hairpin_sq_wq_in_host_mem); 1136 attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr, 1137 hairpin_data_buffer_locked); 1138 attr->flow_counter_bulk_log_max_alloc = MLX5_GET(cmd_hca_cap_2, 1139 hcattr, flow_counter_bulk_log_max_alloc); 1140 attr->flow_counter_bulk_log_granularity = 1141 MLX5_GET(cmd_hca_cap_2, hcattr, 1142 flow_counter_bulk_log_granularity); 1143 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1144 cross_vhca_object_to_object_supported); 1145 attr->cross_vhca = 1146 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR) && 1147 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT) && 1148 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT) && 1149 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC); 1150 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1151 allowed_object_for_other_vhca_access); 1152 attr->cross_vhca = attr->cross_vhca && 1153 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR) && 1154 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_FT) && 1155 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC); 1156 } 1157 if (attr->log_min_stride_wqe_sz == 0) 1158 attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 1159 if (attr->qos.sup) { 1160 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1161 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 1162 MLX5_HCA_CAP_OPMOD_GET_CUR); 1163 if (!hcattr) { 1164 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); 1165 return rc; 1166 } 1167 attr->qos.flow_meter_old = 1168 MLX5_GET(qos_cap, hcattr, flow_meter_old); 1169 attr->qos.log_max_flow_meter = 1170 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 1171 attr->qos.flow_meter_reg_c_ids = 1172 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 1173 attr->qos.flow_meter = 1174 MLX5_GET(qos_cap, hcattr, flow_meter); 1175 attr->qos.packet_pacing = 1176 MLX5_GET(qos_cap, hcattr, packet_pacing); 1177 attr->qos.wqe_rate_pp = 1178 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 1179 if (attr->qos.flow_meter_aso_sup) { 1180 attr->qos.log_meter_aso_granularity = 1181 MLX5_GET(qos_cap, hcattr, 1182 log_meter_aso_granularity); 1183 attr->qos.log_meter_aso_max_alloc = 1184 MLX5_GET(qos_cap, hcattr, 1185 log_meter_aso_max_alloc); 1186 attr->qos.log_max_num_meter_aso = 1187 MLX5_GET(qos_cap, hcattr, 1188 log_max_num_meter_aso); 1189 } 1190 } 1191 if (attr->vdpa.valid) 1192 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 1193 if (!attr->eth_net_offloads) 1194 return 0; 1195 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 1196 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1197 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 1198 MLX5_HCA_CAP_OPMOD_GET_CUR); 1199 if (!hcattr) { 1200 attr->log_max_ft_sampler_num = 0; 1201 return rc; 1202 } 1203 attr->log_max_ft_sampler_num = MLX5_GET 1204 (flow_table_nic_cap, hcattr, 1205 flow_table_properties_nic_receive.log_max_ft_sampler_num); 1206 attr->flow.tunnel_header_0_1 = MLX5_GET 1207 (flow_table_nic_cap, hcattr, 1208 ft_field_support_2_nic_receive.tunnel_header_0_1); 1209 attr->flow.tunnel_header_2_3 = MLX5_GET 1210 (flow_table_nic_cap, hcattr, 1211 ft_field_support_2_nic_receive.tunnel_header_2_3); 1212 attr->modify_outer_ip_ecn = MLX5_GET 1213 (flow_table_nic_cap, hcattr, 1214 ft_header_modify_nic_receive.outer_ip_ecn); 1215 attr->set_reg_c = 0xff; 1216 if (attr->nic_flow_table) { 1217 #define GET_RX_REG_X_BITS \ 1218 MLX5_GET(flow_table_nic_cap, hcattr, \ 1219 ft_header_modify_nic_receive.metadata_reg_c_x) 1220 #define GET_TX_REG_X_BITS \ 1221 MLX5_GET(flow_table_nic_cap, hcattr, \ 1222 ft_header_modify_nic_transmit.metadata_reg_c_x) 1223 1224 uint32_t tx_reg, rx_reg; 1225 1226 tx_reg = GET_TX_REG_X_BITS; 1227 rx_reg = GET_RX_REG_X_BITS; 1228 attr->set_reg_c &= (rx_reg & tx_reg); 1229 1230 #undef GET_RX_REG_X_BITS 1231 #undef GET_TX_REG_X_BITS 1232 } 1233 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 1234 attr->inner_ipv4_ihl = MLX5_GET 1235 (flow_table_nic_cap, hcattr, 1236 ft_field_support_2_nic_receive.inner_ipv4_ihl); 1237 attr->outer_ipv4_ihl = MLX5_GET 1238 (flow_table_nic_cap, hcattr, 1239 ft_field_support_2_nic_receive.outer_ipv4_ihl); 1240 attr->lag_rx_port_affinity = MLX5_GET 1241 (flow_table_nic_cap, hcattr, 1242 ft_field_support_2_nic_receive.lag_rx_port_affinity); 1243 /* Query HCA offloads for Ethernet protocol. */ 1244 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1245 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 1246 MLX5_HCA_CAP_OPMOD_GET_CUR); 1247 if (!hcattr) { 1248 attr->eth_net_offloads = 0; 1249 return rc; 1250 } 1251 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 1252 hcattr, wqe_vlan_insert); 1253 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 1254 hcattr, csum_cap); 1255 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 1256 hcattr, vlan_cap); 1257 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1258 lro_cap); 1259 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1260 hcattr, max_lso_cap); 1261 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1262 hcattr, scatter_fcs); 1263 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1264 hcattr, tunnel_lro_gre); 1265 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1266 hcattr, tunnel_lro_vxlan); 1267 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1268 hcattr, swp); 1269 attr->tunnel_stateless_gre = 1270 MLX5_GET(per_protocol_networking_offload_caps, 1271 hcattr, tunnel_stateless_gre); 1272 attr->tunnel_stateless_vxlan = 1273 MLX5_GET(per_protocol_networking_offload_caps, 1274 hcattr, tunnel_stateless_vxlan); 1275 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1276 hcattr, swp_csum); 1277 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1278 hcattr, swp_lso); 1279 attr->lro_max_msg_sz_mode = MLX5_GET 1280 (per_protocol_networking_offload_caps, 1281 hcattr, lro_max_msg_sz_mode); 1282 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1283 attr->lro_timer_supported_periods[i] = 1284 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1285 lro_timer_supported_periods[i]); 1286 } 1287 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1288 hcattr, lro_min_mss_size); 1289 attr->tunnel_stateless_geneve_rx = 1290 MLX5_GET(per_protocol_networking_offload_caps, 1291 hcattr, tunnel_stateless_geneve_rx); 1292 attr->geneve_max_opt_len = 1293 MLX5_GET(per_protocol_networking_offload_caps, 1294 hcattr, max_geneve_opt_len); 1295 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1296 hcattr, wqe_inline_mode); 1297 attr->tunnel_stateless_gtp = MLX5_GET 1298 (per_protocol_networking_offload_caps, 1299 hcattr, tunnel_stateless_gtp); 1300 attr->rss_ind_tbl_cap = MLX5_GET 1301 (per_protocol_networking_offload_caps, 1302 hcattr, rss_ind_tbl_cap); 1303 attr->multi_pkt_send_wqe = MLX5_GET 1304 (per_protocol_networking_offload_caps, 1305 hcattr, multi_pkt_send_wqe); 1306 attr->enhanced_multi_pkt_send_wqe = MLX5_GET 1307 (per_protocol_networking_offload_caps, 1308 hcattr, enhanced_multi_pkt_send_wqe); 1309 if (attr->wqe_based_flow_table_sup) { 1310 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1311 MLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE | 1312 MLX5_HCA_CAP_OPMOD_GET_CUR); 1313 if (!hcattr) { 1314 DRV_LOG(DEBUG, "Failed to query WQE Based Flow table capabilities"); 1315 return rc; 1316 } 1317 attr->max_header_modify_pattern_length = MLX5_GET(wqe_based_flow_table_cap, 1318 hcattr, 1319 max_header_modify_pattern_length); 1320 } 1321 /* Query HCA attribute for ROCE. */ 1322 if (attr->roce) { 1323 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1324 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1325 MLX5_HCA_CAP_OPMOD_GET_CUR); 1326 if (!hcattr) { 1327 DRV_LOG(DEBUG, 1328 "Failed to query devx HCA ROCE capabilities"); 1329 return rc; 1330 } 1331 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1332 } 1333 if (attr->eth_virt && 1334 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1335 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1336 if (rc) { 1337 attr->eth_virt = 0; 1338 goto error; 1339 } 1340 } 1341 if (attr->eswitch_manager) { 1342 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1343 MLX5_SET_HCA_CAP_OP_MOD_ESW | 1344 MLX5_HCA_CAP_OPMOD_GET_CUR); 1345 if (!hcattr) 1346 return rc; 1347 attr->esw_mgr_vport_id_valid = 1348 MLX5_GET(esw_cap, hcattr, 1349 esw_manager_vport_number_valid); 1350 attr->esw_mgr_vport_id = 1351 MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); 1352 } 1353 if (attr->eswitch_manager) { 1354 uint32_t esw_reg; 1355 1356 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1357 MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE | 1358 MLX5_HCA_CAP_OPMOD_GET_CUR); 1359 if (!hcattr) 1360 return rc; 1361 esw_reg = MLX5_GET(flow_table_esw_cap, hcattr, 1362 ft_header_modify_esw_fdb.metadata_reg_c_x); 1363 attr->set_reg_c &= esw_reg; 1364 } 1365 return 0; 1366 error: 1367 rc = (rc > 0) ? -rc : rc; 1368 return rc; 1369 } 1370 1371 /** 1372 * Query TIS transport domain from QP verbs object using DevX API. 1373 * 1374 * @param[in] qp 1375 * Pointer to verbs QP returned by ibv_create_qp . 1376 * @param[in] tis_num 1377 * TIS number of TIS to query. 1378 * @param[out] tis_td 1379 * Pointer to TIS transport domain variable, to be set by the routine. 1380 * 1381 * @return 1382 * 0 on success, a negative value otherwise. 1383 */ 1384 int 1385 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1386 uint32_t *tis_td) 1387 { 1388 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1389 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1390 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1391 int rc; 1392 void *tis_ctx; 1393 1394 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1395 MLX5_SET(query_tis_in, in, tisn, tis_num); 1396 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1397 if (rc) { 1398 DRV_LOG(ERR, "Failed to query QP using DevX"); 1399 return -rc; 1400 }; 1401 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1402 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1403 return 0; 1404 #else 1405 (void)qp; 1406 (void)tis_num; 1407 (void)tis_td; 1408 return -ENOTSUP; 1409 #endif 1410 } 1411 1412 /** 1413 * Fill WQ data for DevX API command. 1414 * Utility function for use when creating DevX objects containing a WQ. 1415 * 1416 * @param[in] wq_ctx 1417 * Pointer to WQ context to fill with data. 1418 * @param [in] wq_attr 1419 * Pointer to WQ attributes structure to fill in WQ context. 1420 */ 1421 static void 1422 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1423 { 1424 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1425 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1426 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1427 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1428 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1429 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1430 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1431 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1432 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1433 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1434 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1435 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1436 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1437 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1438 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1439 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1440 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1441 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1442 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1443 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1444 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1445 wq_attr->log_hairpin_num_packets); 1446 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1447 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1448 wq_attr->single_wqe_log_num_of_strides); 1449 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1450 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1451 wq_attr->single_stride_log_num_of_bytes); 1452 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1453 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1454 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1455 } 1456 1457 /** 1458 * Create RQ using DevX API. 1459 * 1460 * @param[in] ctx 1461 * Context returned from mlx5 open_device() glue function. 1462 * @param [in] rq_attr 1463 * Pointer to create RQ attributes structure. 1464 * @param [in] socket 1465 * CPU socket ID for allocations. 1466 * 1467 * @return 1468 * The DevX object created, NULL otherwise and rte_errno is set. 1469 */ 1470 struct mlx5_devx_obj * 1471 mlx5_devx_cmd_create_rq(void *ctx, 1472 struct mlx5_devx_create_rq_attr *rq_attr, 1473 int socket) 1474 { 1475 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1476 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1477 void *rq_ctx, *wq_ctx; 1478 struct mlx5_devx_wq_attr *wq_attr; 1479 struct mlx5_devx_obj *rq = NULL; 1480 1481 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1482 if (!rq) { 1483 DRV_LOG(ERR, "Failed to allocate RQ data"); 1484 rte_errno = ENOMEM; 1485 return NULL; 1486 } 1487 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1488 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1489 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1490 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1491 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1492 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1493 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1494 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1495 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1496 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1497 MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type); 1498 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1499 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1500 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1501 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1502 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1503 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1504 wq_attr = &rq_attr->wq_attr; 1505 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1506 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1507 out, sizeof(out)); 1508 if (!rq->obj) { 1509 DEVX_DRV_LOG(ERR, out, "create RQ", NULL, 0); 1510 mlx5_free(rq); 1511 return NULL; 1512 } 1513 rq->id = MLX5_GET(create_rq_out, out, rqn); 1514 return rq; 1515 } 1516 1517 /** 1518 * Modify RQ using DevX API. 1519 * 1520 * @param[in] rq 1521 * Pointer to RQ object structure. 1522 * @param [in] rq_attr 1523 * Pointer to modify RQ attributes structure. 1524 * 1525 * @return 1526 * 0 on success, a negative errno value otherwise and rte_errno is set. 1527 */ 1528 int 1529 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1530 struct mlx5_devx_modify_rq_attr *rq_attr) 1531 { 1532 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1533 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1534 void *rq_ctx, *wq_ctx; 1535 int ret; 1536 1537 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1538 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1539 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1540 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1541 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1542 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1543 if (rq_attr->modify_bitmask & 1544 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1545 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1546 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1547 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1548 if (rq_attr->modify_bitmask & 1549 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1550 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1551 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1552 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1553 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1554 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1555 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1556 } 1557 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1558 out, sizeof(out)); 1559 if (ret) { 1560 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1561 rte_errno = errno; 1562 return -errno; 1563 } 1564 return ret; 1565 } 1566 1567 /** 1568 * Create RMP using DevX API. 1569 * 1570 * @param[in] ctx 1571 * Context returned from mlx5 open_device() glue function. 1572 * @param [in] rmp_attr 1573 * Pointer to create RMP attributes structure. 1574 * @param [in] socket 1575 * CPU socket ID for allocations. 1576 * 1577 * @return 1578 * The DevX object created, NULL otherwise and rte_errno is set. 1579 */ 1580 struct mlx5_devx_obj * 1581 mlx5_devx_cmd_create_rmp(void *ctx, 1582 struct mlx5_devx_create_rmp_attr *rmp_attr, 1583 int socket) 1584 { 1585 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0}; 1586 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0}; 1587 void *rmp_ctx, *wq_ctx; 1588 struct mlx5_devx_wq_attr *wq_attr; 1589 struct mlx5_devx_obj *rmp = NULL; 1590 1591 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket); 1592 if (!rmp) { 1593 DRV_LOG(ERR, "Failed to allocate RMP data"); 1594 rte_errno = ENOMEM; 1595 return NULL; 1596 } 1597 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP); 1598 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx); 1599 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state); 1600 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe, 1601 rmp_attr->basic_cyclic_rcv_wqe); 1602 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq); 1603 wq_attr = &rmp_attr->wq_attr; 1604 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1605 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1606 sizeof(out)); 1607 if (!rmp->obj) { 1608 DEVX_DRV_LOG(ERR, out, "create RMP", NULL, 0); 1609 mlx5_free(rmp); 1610 return NULL; 1611 } 1612 rmp->id = MLX5_GET(create_rmp_out, out, rmpn); 1613 return rmp; 1614 } 1615 1616 /* 1617 * Create TIR using DevX API. 1618 * 1619 * @param[in] ctx 1620 * Context returned from mlx5 open_device() glue function. 1621 * @param [in] tir_attr 1622 * Pointer to TIR attributes structure. 1623 * 1624 * @return 1625 * The DevX object created, NULL otherwise and rte_errno is set. 1626 */ 1627 struct mlx5_devx_obj * 1628 mlx5_devx_cmd_create_tir(void *ctx, 1629 struct mlx5_devx_tir_attr *tir_attr) 1630 { 1631 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1632 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1633 void *tir_ctx, *outer, *inner, *rss_key; 1634 struct mlx5_devx_obj *tir = NULL; 1635 1636 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1637 if (!tir) { 1638 DRV_LOG(ERR, "Failed to allocate TIR data"); 1639 rte_errno = ENOMEM; 1640 return NULL; 1641 } 1642 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1643 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1644 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1645 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1646 tir_attr->lro_timeout_period_usecs); 1647 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1648 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1649 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1650 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1651 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1652 tir_attr->tunneled_offload_en); 1653 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1654 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1655 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1656 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1657 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1658 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1659 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1660 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1661 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1662 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1663 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1664 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1665 tir_attr->rx_hash_field_selector_outer.selected_fields); 1666 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1667 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1668 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1669 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1670 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1671 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1672 tir_attr->rx_hash_field_selector_inner.selected_fields); 1673 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1674 out, sizeof(out)); 1675 if (!tir->obj) { 1676 DEVX_DRV_LOG(ERR, out, "create TIR", NULL, 0); 1677 mlx5_free(tir); 1678 return NULL; 1679 } 1680 tir->id = MLX5_GET(create_tir_out, out, tirn); 1681 return tir; 1682 } 1683 1684 /** 1685 * Modify TIR using DevX API. 1686 * 1687 * @param[in] tir 1688 * Pointer to TIR DevX object structure. 1689 * @param [in] modify_tir_attr 1690 * Pointer to TIR modification attributes structure. 1691 * 1692 * @return 1693 * 0 on success, a negative errno value otherwise and rte_errno is set. 1694 */ 1695 int 1696 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1697 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1698 { 1699 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1700 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1701 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1702 void *tir_ctx; 1703 int ret; 1704 1705 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1706 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1707 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1708 modify_tir_attr->modify_bitmask); 1709 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1710 if (modify_tir_attr->modify_bitmask & 1711 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1712 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1713 tir_attr->lro_timeout_period_usecs); 1714 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1715 tir_attr->lro_enable_mask); 1716 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1717 tir_attr->lro_max_msg_sz); 1718 } 1719 if (modify_tir_attr->modify_bitmask & 1720 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1721 MLX5_SET(tirc, tir_ctx, indirect_table, 1722 tir_attr->indirect_table); 1723 if (modify_tir_attr->modify_bitmask & 1724 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1725 int i; 1726 void *outer, *inner; 1727 1728 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1729 tir_attr->rx_hash_symmetric); 1730 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1731 for (i = 0; i < 10; i++) { 1732 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1733 tir_attr->rx_hash_toeplitz_key[i]); 1734 } 1735 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1736 rx_hash_field_selector_outer); 1737 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1738 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1739 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1740 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1741 MLX5_SET 1742 (rx_hash_field_select, outer, selected_fields, 1743 tir_attr->rx_hash_field_selector_outer.selected_fields); 1744 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1745 rx_hash_field_selector_inner); 1746 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1747 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1748 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1749 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1750 MLX5_SET 1751 (rx_hash_field_select, inner, selected_fields, 1752 tir_attr->rx_hash_field_selector_inner.selected_fields); 1753 } 1754 if (modify_tir_attr->modify_bitmask & 1755 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1756 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1757 } 1758 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1759 out, sizeof(out)); 1760 if (ret) { 1761 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1762 rte_errno = errno; 1763 return -errno; 1764 } 1765 return ret; 1766 } 1767 1768 /** 1769 * Create RQT using DevX API. 1770 * 1771 * @param[in] ctx 1772 * Context returned from mlx5 open_device() glue function. 1773 * @param [in] rqt_attr 1774 * Pointer to RQT attributes structure. 1775 * 1776 * @return 1777 * The DevX object created, NULL otherwise and rte_errno is set. 1778 */ 1779 struct mlx5_devx_obj * 1780 mlx5_devx_cmd_create_rqt(void *ctx, 1781 struct mlx5_devx_rqt_attr *rqt_attr) 1782 { 1783 uint32_t *in = NULL; 1784 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1785 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1786 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1787 void *rqt_ctx; 1788 struct mlx5_devx_obj *rqt = NULL; 1789 int i; 1790 1791 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1792 if (!in) { 1793 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1794 rte_errno = ENOMEM; 1795 return NULL; 1796 } 1797 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1798 if (!rqt) { 1799 DRV_LOG(ERR, "Failed to allocate RQT data"); 1800 rte_errno = ENOMEM; 1801 mlx5_free(in); 1802 return NULL; 1803 } 1804 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1805 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1806 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1807 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1808 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1809 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1810 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1811 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1812 mlx5_free(in); 1813 if (!rqt->obj) { 1814 DEVX_DRV_LOG(ERR, out, "create RQT", NULL, 0); 1815 mlx5_free(rqt); 1816 return NULL; 1817 } 1818 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1819 return rqt; 1820 } 1821 1822 /** 1823 * Modify RQT using DevX API. 1824 * 1825 * @param[in] rqt 1826 * Pointer to RQT DevX object structure. 1827 * @param [in] rqt_attr 1828 * Pointer to RQT attributes structure. 1829 * 1830 * @return 1831 * 0 on success, a negative errno value otherwise and rte_errno is set. 1832 */ 1833 int 1834 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1835 struct mlx5_devx_rqt_attr *rqt_attr) 1836 { 1837 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1838 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1839 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1840 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1841 void *rqt_ctx; 1842 int i; 1843 int ret; 1844 1845 if (!in) { 1846 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1847 rte_errno = ENOMEM; 1848 return -ENOMEM; 1849 } 1850 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1851 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1852 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1853 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1854 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1855 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1856 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1857 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1858 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1859 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1860 mlx5_free(in); 1861 if (ret) { 1862 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1863 rte_errno = errno; 1864 return -rte_errno; 1865 } 1866 return ret; 1867 } 1868 1869 /** 1870 * Create SQ using DevX API. 1871 * 1872 * @param[in] ctx 1873 * Context returned from mlx5 open_device() glue function. 1874 * @param [in] sq_attr 1875 * Pointer to SQ attributes structure. 1876 * @param [in] socket 1877 * CPU socket ID for allocations. 1878 * 1879 * @return 1880 * The DevX object created, NULL otherwise and rte_errno is set. 1881 **/ 1882 struct mlx5_devx_obj * 1883 mlx5_devx_cmd_create_sq(void *ctx, 1884 struct mlx5_devx_create_sq_attr *sq_attr) 1885 { 1886 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1887 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1888 void *sq_ctx; 1889 void *wq_ctx; 1890 struct mlx5_devx_wq_attr *wq_attr; 1891 struct mlx5_devx_obj *sq = NULL; 1892 1893 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1894 if (!sq) { 1895 DRV_LOG(ERR, "Failed to allocate SQ data"); 1896 rte_errno = ENOMEM; 1897 return NULL; 1898 } 1899 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1900 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1901 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1902 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1903 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1904 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1905 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1906 sq_attr->allow_multi_pkt_send_wqe); 1907 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1908 sq_attr->min_wqe_inline_mode); 1909 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1910 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1911 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1912 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1913 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1914 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1915 MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type); 1916 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1917 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1918 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1919 sq_attr->packet_pacing_rate_limit_index); 1920 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1921 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1922 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1923 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1924 wq_attr = &sq_attr->wq_attr; 1925 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1926 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1927 out, sizeof(out)); 1928 if (!sq->obj) { 1929 DEVX_DRV_LOG(ERR, out, "create SQ", NULL, 0); 1930 mlx5_free(sq); 1931 return NULL; 1932 } 1933 sq->id = MLX5_GET(create_sq_out, out, sqn); 1934 return sq; 1935 } 1936 1937 /** 1938 * Modify SQ using DevX API. 1939 * 1940 * @param[in] sq 1941 * Pointer to SQ object structure. 1942 * @param [in] sq_attr 1943 * Pointer to SQ attributes structure. 1944 * 1945 * @return 1946 * 0 on success, a negative errno value otherwise and rte_errno is set. 1947 */ 1948 int 1949 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1950 struct mlx5_devx_modify_sq_attr *sq_attr) 1951 { 1952 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1953 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1954 void *sq_ctx; 1955 int ret; 1956 1957 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1958 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1959 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1960 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1961 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1962 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1963 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1964 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1965 out, sizeof(out)); 1966 if (ret) { 1967 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1968 rte_errno = errno; 1969 return -rte_errno; 1970 } 1971 return ret; 1972 } 1973 1974 /** 1975 * Create TIS using DevX API. 1976 * 1977 * @param[in] ctx 1978 * Context returned from mlx5 open_device() glue function. 1979 * @param [in] tis_attr 1980 * Pointer to TIS attributes structure. 1981 * 1982 * @return 1983 * The DevX object created, NULL otherwise and rte_errno is set. 1984 */ 1985 struct mlx5_devx_obj * 1986 mlx5_devx_cmd_create_tis(void *ctx, 1987 struct mlx5_devx_tis_attr *tis_attr) 1988 { 1989 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1990 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1991 struct mlx5_devx_obj *tis = NULL; 1992 void *tis_ctx; 1993 1994 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1995 if (!tis) { 1996 DRV_LOG(ERR, "Failed to allocate TIS object"); 1997 rte_errno = ENOMEM; 1998 return NULL; 1999 } 2000 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 2001 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 2002 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 2003 tis_attr->strict_lag_tx_port_affinity); 2004 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 2005 tis_attr->lag_tx_port_affinity); 2006 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 2007 MLX5_SET(tisc, tis_ctx, transport_domain, 2008 tis_attr->transport_domain); 2009 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2010 out, sizeof(out)); 2011 if (!tis->obj) { 2012 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 2013 mlx5_free(tis); 2014 return NULL; 2015 } 2016 tis->id = MLX5_GET(create_tis_out, out, tisn); 2017 return tis; 2018 } 2019 2020 /** 2021 * Create transport domain using DevX API. 2022 * 2023 * @param[in] ctx 2024 * Context returned from mlx5 open_device() glue function. 2025 * @return 2026 * The DevX object created, NULL otherwise and rte_errno is set. 2027 */ 2028 struct mlx5_devx_obj * 2029 mlx5_devx_cmd_create_td(void *ctx) 2030 { 2031 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 2032 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 2033 struct mlx5_devx_obj *td = NULL; 2034 2035 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 2036 if (!td) { 2037 DRV_LOG(ERR, "Failed to allocate TD object"); 2038 rte_errno = ENOMEM; 2039 return NULL; 2040 } 2041 MLX5_SET(alloc_transport_domain_in, in, opcode, 2042 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 2043 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2044 out, sizeof(out)); 2045 if (!td->obj) { 2046 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 2047 mlx5_free(td); 2048 return NULL; 2049 } 2050 td->id = MLX5_GET(alloc_transport_domain_out, out, 2051 transport_domain); 2052 return td; 2053 } 2054 2055 /** 2056 * Dump all flows to file. 2057 * 2058 * @param[in] fdb_domain 2059 * FDB domain. 2060 * @param[in] rx_domain 2061 * RX domain. 2062 * @param[in] tx_domain 2063 * TX domain. 2064 * @param[out] file 2065 * Pointer to file stream. 2066 * 2067 * @return 2068 * 0 on success, a negative value otherwise. 2069 */ 2070 int 2071 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 2072 void *rx_domain __rte_unused, 2073 void *tx_domain __rte_unused, FILE *file __rte_unused) 2074 { 2075 int ret = 0; 2076 2077 #ifdef HAVE_MLX5_DR_FLOW_DUMP 2078 if (fdb_domain) { 2079 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 2080 if (ret) 2081 return ret; 2082 } 2083 MLX5_ASSERT(rx_domain); 2084 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 2085 if (ret) 2086 return ret; 2087 MLX5_ASSERT(tx_domain); 2088 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 2089 #else 2090 ret = ENOTSUP; 2091 #endif 2092 return -ret; 2093 } 2094 2095 int 2096 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 2097 FILE *file __rte_unused) 2098 { 2099 int ret = 0; 2100 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 2101 if (rule_info) 2102 ret = mlx5_glue->dr_dump_rule(file, rule_info); 2103 #else 2104 ret = ENOTSUP; 2105 #endif 2106 return -ret; 2107 } 2108 2109 /* 2110 * Create CQ using DevX API. 2111 * 2112 * @param[in] ctx 2113 * Context returned from mlx5 open_device() glue function. 2114 * @param [in] attr 2115 * Pointer to CQ attributes structure. 2116 * 2117 * @return 2118 * The DevX object created, NULL otherwise and rte_errno is set. 2119 */ 2120 struct mlx5_devx_obj * 2121 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 2122 { 2123 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 2124 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 2125 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2126 sizeof(*cq_obj), 2127 0, SOCKET_ID_ANY); 2128 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 2129 2130 if (!cq_obj) { 2131 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 2132 rte_errno = ENOMEM; 2133 return NULL; 2134 } 2135 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 2136 if (attr->db_umem_valid) { 2137 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 2138 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 2139 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 2140 } else { 2141 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 2142 } 2143 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 2144 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 2145 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 2146 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 2147 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 2148 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2149 MLX5_SET(cqc, cqctx, log_page_size, 2150 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2151 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 2152 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 2153 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 2154 MLX5_SET(cqc, cqctx, cqe_comp_layout, !!attr->cqe_comp_layout); 2155 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 2156 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 2157 attr->mini_cqe_res_format_ext); 2158 if (attr->q_umem_valid) { 2159 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 2160 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 2161 MLX5_SET64(create_cq_in, in, cq_umem_offset, 2162 attr->q_umem_offset); 2163 } 2164 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2165 sizeof(out)); 2166 if (!cq_obj->obj) { 2167 DEVX_DRV_LOG(ERR, out, "create CQ", NULL, 0); 2168 mlx5_free(cq_obj); 2169 return NULL; 2170 } 2171 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 2172 return cq_obj; 2173 } 2174 2175 /** 2176 * Create VIRTQ using DevX API. 2177 * 2178 * @param[in] ctx 2179 * Context returned from mlx5 open_device() glue function. 2180 * @param [in] attr 2181 * Pointer to VIRTQ attributes structure. 2182 * 2183 * @return 2184 * The DevX object created, NULL otherwise and rte_errno is set. 2185 */ 2186 struct mlx5_devx_obj * 2187 mlx5_devx_cmd_create_virtq(void *ctx, 2188 struct mlx5_devx_virtq_attr *attr) 2189 { 2190 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2191 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2192 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2193 sizeof(*virtq_obj), 2194 0, SOCKET_ID_ANY); 2195 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2196 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2197 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2198 2199 if (!virtq_obj) { 2200 DRV_LOG(ERR, "Failed to allocate virtq data."); 2201 rte_errno = ENOMEM; 2202 return NULL; 2203 } 2204 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2205 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2206 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2207 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2208 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2209 attr->hw_available_index); 2210 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 2211 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2212 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2213 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2214 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2215 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2216 attr->virtio_version_1_0); 2217 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2218 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2219 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2220 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2221 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 2222 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2223 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 2224 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2225 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 2226 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 2227 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 2228 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 2229 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 2230 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 2231 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 2232 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 2233 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 2234 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 2235 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 2236 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 2237 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 2238 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 2239 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 2240 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2241 sizeof(out)); 2242 if (!virtq_obj->obj) { 2243 DEVX_DRV_LOG(ERR, out, "create VIRTQ", NULL, 0); 2244 mlx5_free(virtq_obj); 2245 return NULL; 2246 } 2247 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2248 return virtq_obj; 2249 } 2250 2251 /** 2252 * Modify VIRTQ using DevX API. 2253 * 2254 * @param[in] virtq_obj 2255 * Pointer to virtq object structure. 2256 * @param [in] attr 2257 * Pointer to modify virtq attributes structure. 2258 * 2259 * @return 2260 * 0 on success, a negative errno value otherwise and rte_errno is set. 2261 */ 2262 int 2263 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 2264 struct mlx5_devx_virtq_attr *attr) 2265 { 2266 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2267 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2268 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2269 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2270 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2271 int ret; 2272 2273 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2274 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 2275 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2276 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2277 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2278 MLX5_SET64(virtio_net_q, virtq, modify_field_select, 2279 attr->mod_fields_bitmap); 2280 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2281 if (!attr->mod_fields_bitmap) { 2282 DRV_LOG(ERR, "Failed to modify VIRTQ for no type set."); 2283 rte_errno = EINVAL; 2284 return -rte_errno; 2285 } 2286 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE) 2287 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 2288 if (attr->mod_fields_bitmap & 2289 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) { 2290 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 2291 attr->dirty_bitmap_mkey); 2292 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 2293 attr->dirty_bitmap_addr); 2294 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 2295 attr->dirty_bitmap_size); 2296 } 2297 if (attr->mod_fields_bitmap & 2298 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE) 2299 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 2300 attr->dirty_bitmap_dump_enable); 2301 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) { 2302 MLX5_SET(virtio_q, virtctx, queue_period_mode, 2303 attr->hw_latency_mode); 2304 MLX5_SET(virtio_q, virtctx, queue_period_us, 2305 attr->hw_max_latency_us); 2306 MLX5_SET(virtio_q, virtctx, queue_max_count, 2307 attr->hw_max_pending_comp); 2308 } 2309 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) { 2310 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2311 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2312 MLX5_SET64(virtio_q, virtctx, available_addr, 2313 attr->available_addr); 2314 } 2315 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX) 2316 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2317 attr->hw_available_index); 2318 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX) 2319 MLX5_SET16(virtio_net_q, virtq, hw_used_index, 2320 attr->hw_used_index); 2321 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE) 2322 MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type); 2323 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0) 2324 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2325 attr->virtio_version_1_0); 2326 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY) 2327 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2328 if (attr->mod_fields_bitmap & 2329 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) { 2330 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2331 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2332 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2333 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2334 } 2335 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) { 2336 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2337 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2338 } 2339 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 2340 out, sizeof(out)); 2341 if (ret) { 2342 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2343 rte_errno = errno; 2344 return -rte_errno; 2345 } 2346 return ret; 2347 } 2348 2349 /** 2350 * Query VIRTQ using DevX API. 2351 * 2352 * @param[in] virtq_obj 2353 * Pointer to virtq object structure. 2354 * @param [in/out] attr 2355 * Pointer to virtq attributes structure. 2356 * 2357 * @return 2358 * 0 on success, a negative errno value otherwise and rte_errno is set. 2359 */ 2360 int 2361 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 2362 struct mlx5_devx_virtq_attr *attr) 2363 { 2364 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2365 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 2366 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 2367 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 2368 int ret; 2369 2370 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2371 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2372 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2373 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2374 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2375 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2376 out, sizeof(out)); 2377 if (ret) { 2378 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2379 rte_errno = errno; 2380 return -errno; 2381 } 2382 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2383 hw_available_index); 2384 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2385 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2386 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2387 virtio_q_context.error_type); 2388 return ret; 2389 } 2390 2391 /** 2392 * Create QP using DevX API. 2393 * 2394 * @param[in] ctx 2395 * Context returned from mlx5 open_device() glue function. 2396 * @param [in] attr 2397 * Pointer to QP attributes structure. 2398 * 2399 * @return 2400 * The DevX object created, NULL otherwise and rte_errno is set. 2401 */ 2402 struct mlx5_devx_obj * 2403 mlx5_devx_cmd_create_qp(void *ctx, 2404 struct mlx5_devx_qp_attr *attr) 2405 { 2406 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2407 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2408 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2409 sizeof(*qp_obj), 2410 0, SOCKET_ID_ANY); 2411 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2412 2413 if (!qp_obj) { 2414 DRV_LOG(ERR, "Failed to allocate QP data."); 2415 rte_errno = ENOMEM; 2416 return NULL; 2417 } 2418 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2419 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2420 MLX5_SET(qpc, qpc, pd, attr->pd); 2421 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2422 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2423 if (attr->uar_index) { 2424 if (attr->mmo) { 2425 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2426 in, qpc_extension_and_pas_list); 2427 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2428 qpc_ext_and_pas_list, qpc_data_extension); 2429 2430 MLX5_SET(create_qp_in, in, qpc_ext, 1); 2431 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2432 } 2433 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2434 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2435 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2436 MLX5_SET(qpc, qpc, log_page_size, 2437 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2438 if (attr->num_of_send_wqbbs) { 2439 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs)); 2440 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2441 MLX5_SET(qpc, qpc, log_sq_size, 2442 rte_log2_u32(attr->num_of_send_wqbbs)); 2443 } else { 2444 MLX5_SET(qpc, qpc, no_sq, 1); 2445 } 2446 if (attr->num_of_receive_wqes) { 2447 MLX5_ASSERT(RTE_IS_POWER_OF_2( 2448 attr->num_of_receive_wqes)); 2449 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2450 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2451 MLX5_LOG_RQ_STRIDE_SHIFT); 2452 MLX5_SET(qpc, qpc, log_rq_size, 2453 rte_log2_u32(attr->num_of_receive_wqes)); 2454 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2455 } else { 2456 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2457 } 2458 if (attr->dbr_umem_valid) { 2459 MLX5_SET(qpc, qpc, dbr_umem_valid, 2460 attr->dbr_umem_valid); 2461 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2462 } 2463 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2464 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2465 attr->wq_umem_offset); 2466 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2467 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2468 } else { 2469 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2470 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2471 MLX5_SET(qpc, qpc, no_sq, 1); 2472 } 2473 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2474 sizeof(out)); 2475 if (!qp_obj->obj) { 2476 DEVX_DRV_LOG(ERR, out, "create QP", NULL, 0); 2477 mlx5_free(qp_obj); 2478 return NULL; 2479 } 2480 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2481 return qp_obj; 2482 } 2483 2484 /** 2485 * Modify QP using DevX API. 2486 * Currently supports only force loop-back QP. 2487 * 2488 * @param[in] qp 2489 * Pointer to QP object structure. 2490 * @param [in] qp_st_mod_op 2491 * The QP state modification operation. 2492 * @param [in] remote_qp_id 2493 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2494 * 2495 * @return 2496 * 0 on success, a negative errno value otherwise and rte_errno is set. 2497 */ 2498 int 2499 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2500 uint32_t remote_qp_id) 2501 { 2502 union { 2503 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2504 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2505 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2506 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)]; 2507 } in; 2508 union { 2509 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2510 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2511 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2512 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)]; 2513 } out; 2514 void *qpc; 2515 int ret; 2516 unsigned int inlen; 2517 unsigned int outlen; 2518 2519 memset(&in, 0, sizeof(in)); 2520 memset(&out, 0, sizeof(out)); 2521 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2522 switch (qp_st_mod_op) { 2523 case MLX5_CMD_OP_RST2INIT_QP: 2524 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2525 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2526 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2527 MLX5_SET(qpc, qpc, rre, 1); 2528 MLX5_SET(qpc, qpc, rwe, 1); 2529 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2530 inlen = sizeof(in.rst2init); 2531 outlen = sizeof(out.rst2init); 2532 break; 2533 case MLX5_CMD_OP_INIT2RTR_QP: 2534 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2535 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2536 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2537 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2538 MLX5_SET(qpc, qpc, mtu, 1); 2539 MLX5_SET(qpc, qpc, log_msg_max, 30); 2540 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2541 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2542 inlen = sizeof(in.init2rtr); 2543 outlen = sizeof(out.init2rtr); 2544 break; 2545 case MLX5_CMD_OP_RTR2RTS_QP: 2546 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2547 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2548 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16); 2549 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2550 MLX5_SET(qpc, qpc, retry_count, 7); 2551 MLX5_SET(qpc, qpc, rnr_retry, 7); 2552 inlen = sizeof(in.rtr2rts); 2553 outlen = sizeof(out.rtr2rts); 2554 break; 2555 case MLX5_CMD_OP_QP_2RST: 2556 MLX5_SET(2rst_qp_in, &in, qpn, qp->id); 2557 inlen = sizeof(in.qp2rst); 2558 outlen = sizeof(out.qp2rst); 2559 break; 2560 default: 2561 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2562 qp_st_mod_op); 2563 rte_errno = EINVAL; 2564 return -rte_errno; 2565 } 2566 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2567 if (ret) { 2568 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2569 rte_errno = errno; 2570 return -rte_errno; 2571 } 2572 return ret; 2573 } 2574 2575 struct mlx5_devx_obj * 2576 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2577 { 2578 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2579 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2580 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2581 sizeof(*couners_obj), 0, 2582 SOCKET_ID_ANY); 2583 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2584 2585 if (!couners_obj) { 2586 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2587 rte_errno = ENOMEM; 2588 return NULL; 2589 } 2590 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2591 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2592 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2593 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2594 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2595 sizeof(out)); 2596 if (!couners_obj->obj) { 2597 DEVX_DRV_LOG(ERR, out, "create virtio queue counters Obj", NULL, 2598 0); 2599 mlx5_free(couners_obj); 2600 return NULL; 2601 } 2602 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2603 return couners_obj; 2604 } 2605 2606 int 2607 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2608 struct mlx5_devx_virtio_q_couners_attr *attr) 2609 { 2610 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2611 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2612 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2613 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2614 virtio_q_counters); 2615 int ret; 2616 2617 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2618 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2619 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2620 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2621 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2622 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2623 sizeof(out)); 2624 if (ret) { 2625 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2626 rte_errno = errno; 2627 return -errno; 2628 } 2629 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2630 received_desc); 2631 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2632 completed_desc); 2633 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2634 error_cqes); 2635 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2636 bad_desc_errors); 2637 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2638 exceed_max_chain); 2639 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2640 invalid_buffer); 2641 return ret; 2642 } 2643 2644 /** 2645 * Create general object of type FLOW_HIT_ASO using DevX API. 2646 * 2647 * @param[in] ctx 2648 * Context returned from mlx5 open_device() glue function. 2649 * @param [in] pd 2650 * PD value to associate the FLOW_HIT_ASO object with. 2651 * 2652 * @return 2653 * The DevX object created, NULL otherwise and rte_errno is set. 2654 */ 2655 struct mlx5_devx_obj * 2656 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2657 { 2658 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2659 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2660 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2661 void *ptr = NULL; 2662 2663 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2664 0, SOCKET_ID_ANY); 2665 if (!flow_hit_aso_obj) { 2666 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2667 rte_errno = ENOMEM; 2668 return NULL; 2669 } 2670 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2671 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2672 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2673 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2674 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2675 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2676 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2677 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2678 out, sizeof(out)); 2679 if (!flow_hit_aso_obj->obj) { 2680 DEVX_DRV_LOG(ERR, out, "create FLOW_HIT_ASO", NULL, 0); 2681 mlx5_free(flow_hit_aso_obj); 2682 return NULL; 2683 } 2684 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2685 return flow_hit_aso_obj; 2686 } 2687 2688 /* 2689 * Create PD using DevX API. 2690 * 2691 * @param[in] ctx 2692 * Context returned from mlx5 open_device() glue function. 2693 * 2694 * @return 2695 * The DevX object created, NULL otherwise and rte_errno is set. 2696 */ 2697 struct mlx5_devx_obj * 2698 mlx5_devx_cmd_alloc_pd(void *ctx) 2699 { 2700 struct mlx5_devx_obj *ppd = 2701 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2702 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2703 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2704 2705 if (!ppd) { 2706 DRV_LOG(ERR, "Failed to allocate PD data."); 2707 rte_errno = ENOMEM; 2708 return NULL; 2709 } 2710 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2711 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2712 out, sizeof(out)); 2713 if (!ppd->obj) { 2714 mlx5_free(ppd); 2715 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2716 rte_errno = errno; 2717 return NULL; 2718 } 2719 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2720 return ppd; 2721 } 2722 2723 /** 2724 * Create general object of type FLOW_METER_ASO using DevX API. 2725 * 2726 * @param[in] ctx 2727 * Context returned from mlx5 open_device() glue function. 2728 * @param [in] pd 2729 * PD value to associate the FLOW_METER_ASO object with. 2730 * @param [in] log_obj_size 2731 * log_obj_size define to allocate number of 2 * meters 2732 * in one FLOW_METER_ASO object. 2733 * 2734 * @return 2735 * The DevX object created, NULL otherwise and rte_errno is set. 2736 */ 2737 struct mlx5_devx_obj * 2738 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2739 uint32_t log_obj_size) 2740 { 2741 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2742 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2743 struct mlx5_devx_obj *flow_meter_aso_obj; 2744 void *ptr; 2745 2746 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2747 sizeof(*flow_meter_aso_obj), 2748 0, SOCKET_ID_ANY); 2749 if (!flow_meter_aso_obj) { 2750 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2751 rte_errno = ENOMEM; 2752 return NULL; 2753 } 2754 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2755 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2756 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2757 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2758 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2759 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2760 log_obj_size); 2761 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2762 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2763 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2764 ctx, in, sizeof(in), 2765 out, sizeof(out)); 2766 if (!flow_meter_aso_obj->obj) { 2767 DEVX_DRV_LOG(ERR, out, "create FLOW_METTER_ASO", NULL, 0); 2768 mlx5_free(flow_meter_aso_obj); 2769 return NULL; 2770 } 2771 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2772 out, obj_id); 2773 return flow_meter_aso_obj; 2774 } 2775 2776 /* 2777 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2778 * 2779 * @param[in] ctx 2780 * Context returned from mlx5 open_device() glue function. 2781 * @param [in] pd 2782 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2783 * @param [in] log_obj_size 2784 * log_obj_size to allocate its power of 2 * objects 2785 * in one CONN_TRACK_OFFLOAD bulk allocation. 2786 * 2787 * @return 2788 * The DevX object created, NULL otherwise and rte_errno is set. 2789 */ 2790 struct mlx5_devx_obj * 2791 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2792 uint32_t log_obj_size) 2793 { 2794 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2795 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2796 struct mlx5_devx_obj *ct_aso_obj; 2797 void *ptr; 2798 2799 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2800 0, SOCKET_ID_ANY); 2801 if (!ct_aso_obj) { 2802 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2803 rte_errno = ENOMEM; 2804 return NULL; 2805 } 2806 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2807 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2808 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2809 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2810 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2811 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2812 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2813 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2814 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2815 out, sizeof(out)); 2816 if (!ct_aso_obj->obj) { 2817 DEVX_DRV_LOG(ERR, out, "create CONN_TRACK_OFFLOAD", NULL, 0); 2818 mlx5_free(ct_aso_obj); 2819 return NULL; 2820 } 2821 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2822 return ct_aso_obj; 2823 } 2824 2825 /** 2826 * Create general object of type GENEVE TLV option using DevX API. 2827 * 2828 * @param[in] ctx 2829 * Context returned from mlx5 open_device() glue function. 2830 * @param [in] class 2831 * TLV option variable value of class 2832 * @param [in] type 2833 * TLV option variable value of type 2834 * @param [in] len 2835 * TLV option variable value of len 2836 * 2837 * @return 2838 * The DevX object created, NULL otherwise and rte_errno is set. 2839 */ 2840 struct mlx5_devx_obj * 2841 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2842 uint16_t class, uint8_t type, uint8_t len) 2843 { 2844 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2845 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2846 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2847 sizeof(*geneve_tlv_opt_obj), 2848 0, SOCKET_ID_ANY); 2849 2850 if (!geneve_tlv_opt_obj) { 2851 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2852 rte_errno = ENOMEM; 2853 return NULL; 2854 } 2855 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2856 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2857 geneve_tlv_opt); 2858 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2859 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2860 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2861 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2862 MLX5_SET(geneve_tlv_option, opt, option_class, 2863 rte_be_to_cpu_16(class)); 2864 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2865 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2866 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2867 sizeof(in), out, sizeof(out)); 2868 if (!geneve_tlv_opt_obj->obj) { 2869 DEVX_DRV_LOG(ERR, out, "create GENEVE TLV", NULL, 0); 2870 mlx5_free(geneve_tlv_opt_obj); 2871 return NULL; 2872 } 2873 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2874 return geneve_tlv_opt_obj; 2875 } 2876 2877 int 2878 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2879 { 2880 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2881 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2882 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2883 int rc; 2884 void *rq_ctx; 2885 2886 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2887 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2888 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2889 if (rc) { 2890 rte_errno = errno; 2891 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2892 "rc = %d, errno = %d.", rc, errno); 2893 return -rc; 2894 }; 2895 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2896 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2897 return 0; 2898 #else 2899 (void)wq; 2900 (void)counter_set_id; 2901 return -ENOTSUP; 2902 #endif 2903 } 2904 2905 /* 2906 * Allocate queue counters via devx interface. 2907 * 2908 * @param[in] ctx 2909 * Context returned from mlx5 open_device() glue function. 2910 * 2911 * @return 2912 * Pointer to counter object on success, a NULL value otherwise and 2913 * rte_errno is set. 2914 */ 2915 struct mlx5_devx_obj * 2916 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2917 { 2918 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2919 SOCKET_ID_ANY); 2920 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2921 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2922 2923 if (!dcs) { 2924 rte_errno = ENOMEM; 2925 return NULL; 2926 } 2927 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2928 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2929 sizeof(out)); 2930 if (!dcs->obj) { 2931 DEVX_DRV_LOG(DEBUG, out, "create q counter set", NULL, 0); 2932 mlx5_free(dcs); 2933 return NULL; 2934 } 2935 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2936 return dcs; 2937 } 2938 2939 /** 2940 * Query queue counters values. 2941 * 2942 * @param[in] dcs 2943 * devx object of the queue counter set. 2944 * @param[in] clear 2945 * Whether hardware should clear the counters after the query or not. 2946 * @param[out] out_of_buffers 2947 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2948 * 2949 * @return 2950 * 0 on success, a negative value otherwise. 2951 */ 2952 int 2953 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2954 uint32_t *out_of_buffers) 2955 { 2956 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2957 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2958 int rc; 2959 2960 MLX5_SET(query_q_counter_in, in, opcode, 2961 MLX5_CMD_OP_QUERY_Q_COUNTER); 2962 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2963 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2964 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2965 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2966 sizeof(out)); 2967 if (rc) { 2968 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2969 rte_errno = rc; 2970 return -rc; 2971 } 2972 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2973 return 0; 2974 } 2975 2976 /** 2977 * Create general object of type DEK using DevX API. 2978 * 2979 * @param[in] ctx 2980 * Context returned from mlx5 open_device() glue function. 2981 * @param [in] attr 2982 * Pointer to DEK attributes structure. 2983 * 2984 * @return 2985 * The DevX object created, NULL otherwise and rte_errno is set. 2986 */ 2987 struct mlx5_devx_obj * 2988 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2989 { 2990 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2991 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2992 struct mlx5_devx_obj *dek_obj = NULL; 2993 void *ptr = NULL, *key_addr = NULL; 2994 2995 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2996 0, SOCKET_ID_ANY); 2997 if (dek_obj == NULL) { 2998 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2999 rte_errno = ENOMEM; 3000 return NULL; 3001 } 3002 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 3003 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3004 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3005 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3006 MLX5_GENERAL_OBJ_TYPE_DEK); 3007 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 3008 MLX5_SET(dek, ptr, key_size, attr->key_size); 3009 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 3010 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 3011 MLX5_SET(dek, ptr, pd, attr->pd); 3012 MLX5_SET64(dek, ptr, opaque, attr->opaque); 3013 key_addr = MLX5_ADDR_OF(dek, ptr, key); 3014 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 3015 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3016 out, sizeof(out)); 3017 if (dek_obj->obj == NULL) { 3018 DEVX_DRV_LOG(ERR, out, "create DEK", NULL, 0); 3019 mlx5_free(dek_obj); 3020 return NULL; 3021 } 3022 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3023 return dek_obj; 3024 } 3025 3026 /** 3027 * Create general object of type IMPORT_KEK using DevX API. 3028 * 3029 * @param[in] ctx 3030 * Context returned from mlx5 open_device() glue function. 3031 * @param [in] attr 3032 * Pointer to IMPORT_KEK attributes structure. 3033 * 3034 * @return 3035 * The DevX object created, NULL otherwise and rte_errno is set. 3036 */ 3037 struct mlx5_devx_obj * 3038 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 3039 struct mlx5_devx_import_kek_attr *attr) 3040 { 3041 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 3042 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3043 struct mlx5_devx_obj *import_kek_obj = NULL; 3044 void *ptr = NULL, *key_addr = NULL; 3045 3046 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 3047 0, SOCKET_ID_ANY); 3048 if (import_kek_obj == NULL) { 3049 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 3050 rte_errno = ENOMEM; 3051 return NULL; 3052 } 3053 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 3054 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3055 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3056 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3057 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 3058 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 3059 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 3060 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 3061 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 3062 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3063 out, sizeof(out)); 3064 if (import_kek_obj->obj == NULL) { 3065 DEVX_DRV_LOG(ERR, out, "create IMPORT_KEK", NULL, 0); 3066 mlx5_free(import_kek_obj); 3067 return NULL; 3068 } 3069 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3070 return import_kek_obj; 3071 } 3072 3073 /** 3074 * Create general object of type CREDENTIAL using DevX API. 3075 * 3076 * @param[in] ctx 3077 * Context returned from mlx5 open_device() glue function. 3078 * @param [in] attr 3079 * Pointer to CREDENTIAL attributes structure. 3080 * 3081 * @return 3082 * The DevX object created, NULL otherwise and rte_errno is set. 3083 */ 3084 struct mlx5_devx_obj * 3085 mlx5_devx_cmd_create_credential_obj(void *ctx, 3086 struct mlx5_devx_credential_attr *attr) 3087 { 3088 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 3089 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3090 struct mlx5_devx_obj *credential_obj = NULL; 3091 void *ptr = NULL, *credential_addr = NULL; 3092 3093 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 3094 0, SOCKET_ID_ANY); 3095 if (credential_obj == NULL) { 3096 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 3097 rte_errno = ENOMEM; 3098 return NULL; 3099 } 3100 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 3101 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3102 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3103 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3104 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 3105 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 3106 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 3107 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 3108 memcpy(credential_addr, (void *)(attr->credential), 3109 MLX5_CRYPTO_CREDENTIAL_SIZE); 3110 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3111 out, sizeof(out)); 3112 if (credential_obj->obj == NULL) { 3113 DEVX_DRV_LOG(ERR, out, "create CREDENTIAL", NULL, 0); 3114 mlx5_free(credential_obj); 3115 return NULL; 3116 } 3117 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3118 return credential_obj; 3119 } 3120 3121 /** 3122 * Create general object of type CRYPTO_LOGIN using DevX API. 3123 * 3124 * @param[in] ctx 3125 * Context returned from mlx5 open_device() glue function. 3126 * @param [in] attr 3127 * Pointer to CRYPTO_LOGIN attributes structure. 3128 * 3129 * @return 3130 * The DevX object created, NULL otherwise and rte_errno is set. 3131 */ 3132 struct mlx5_devx_obj * 3133 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 3134 struct mlx5_devx_crypto_login_attr *attr) 3135 { 3136 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 3137 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3138 struct mlx5_devx_obj *crypto_login_obj = NULL; 3139 void *ptr = NULL, *credential_addr = NULL; 3140 3141 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 3142 0, SOCKET_ID_ANY); 3143 if (crypto_login_obj == NULL) { 3144 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 3145 rte_errno = ENOMEM; 3146 return NULL; 3147 } 3148 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 3149 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3150 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3151 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3152 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 3153 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 3154 MLX5_SET(crypto_login, ptr, credential_pointer, 3155 attr->credential_pointer); 3156 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 3157 attr->session_import_kek_ptr); 3158 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 3159 memcpy(credential_addr, (void *)(attr->credential), 3160 MLX5_CRYPTO_CREDENTIAL_SIZE); 3161 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3162 out, sizeof(out)); 3163 if (crypto_login_obj->obj == NULL) { 3164 DEVX_DRV_LOG(ERR, out, "create CRYPTO_LOGIN", NULL, 0); 3165 mlx5_free(crypto_login_obj); 3166 return NULL; 3167 } 3168 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3169 return crypto_login_obj; 3170 } 3171 3172 /** 3173 * Query LAG context. 3174 * 3175 * @param[in] ctx 3176 * Pointer to ibv_context, returned from mlx5dv_open_device. 3177 * @param[out] lag_ctx 3178 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 3179 * 3180 * @return 3181 * 0 on success, a negative value otherwise. 3182 */ 3183 int 3184 mlx5_devx_cmd_query_lag(void *ctx, 3185 struct mlx5_devx_lag_context *lag_ctx) 3186 { 3187 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 3188 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 3189 void *lctx; 3190 int rc; 3191 3192 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 3193 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 3194 if (rc) 3195 goto error; 3196 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 3197 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 3198 fdb_selection_mode); 3199 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 3200 port_select_mode); 3201 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 3202 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 3203 tx_remap_affinity_2); 3204 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 3205 tx_remap_affinity_1); 3206 return 0; 3207 error: 3208 rc = (rc > 0) ? -rc : rc; 3209 return rc; 3210 } 3211