1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 static void * 17 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, 18 int *err, uint32_t flags) 19 { 20 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); 21 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); 22 int status, syndrome, rc; 23 24 if (err) 25 *err = 0; 26 memset(in, 0, size_in); 27 memset(out, 0, size_out); 28 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 29 MLX5_SET(query_hca_cap_in, in, op_mod, flags); 30 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); 31 if (rc) { 32 DRV_LOG(ERR, 33 "Failed to query devx HCA capabilities func %#02x", 34 flags >> 1); 35 if (err) 36 *err = rc > 0 ? -rc : rc; 37 return NULL; 38 } 39 status = MLX5_GET(query_hca_cap_out, out, status); 40 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 41 if (status) { 42 DRV_LOG(ERR, 43 "Failed to query devx HCA capabilities func %#02x status %x, syndrome = %x", 44 flags >> 1, status, syndrome); 45 if (err) 46 *err = -1; 47 return NULL; 48 } 49 return MLX5_ADDR_OF(query_hca_cap_out, out, capability); 50 } 51 52 /** 53 * Perform read access to the registers. Reads data from register 54 * and writes ones to the specified buffer. 55 * 56 * @param[in] ctx 57 * Context returned from mlx5 open_device() glue function. 58 * @param[in] reg_id 59 * Register identifier according to the PRM. 60 * @param[in] arg 61 * Register access auxiliary parameter according to the PRM. 62 * @param[out] data 63 * Pointer to the buffer to store read data. 64 * @param[in] dw_cnt 65 * Buffer size in double words. 66 * 67 * @return 68 * 0 on success, a negative value otherwise. 69 */ 70 int 71 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 72 uint32_t *data, uint32_t dw_cnt) 73 { 74 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 75 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 76 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 77 int status, rc; 78 79 MLX5_ASSERT(data && dw_cnt); 80 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 81 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 82 DRV_LOG(ERR, "Not enough buffer for register read data"); 83 return -1; 84 } 85 MLX5_SET(access_register_in, in, opcode, 86 MLX5_CMD_OP_ACCESS_REGISTER_USER); 87 MLX5_SET(access_register_in, in, op_mod, 88 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 89 MLX5_SET(access_register_in, in, register_id, reg_id); 90 MLX5_SET(access_register_in, in, argument, arg); 91 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 92 MLX5_ST_SZ_BYTES(access_register_out) + 93 sizeof(uint32_t) * dw_cnt); 94 if (rc) 95 goto error; 96 status = MLX5_GET(access_register_out, out, status); 97 if (status) { 98 int syndrome = MLX5_GET(access_register_out, out, syndrome); 99 100 DRV_LOG(DEBUG, "Failed to read access NIC register 0x%X, " 101 "status %x, syndrome = %x", 102 reg_id, status, syndrome); 103 return -1; 104 } 105 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 106 dw_cnt * sizeof(uint32_t)); 107 return 0; 108 error: 109 rc = (rc > 0) ? -rc : rc; 110 return rc; 111 } 112 113 /** 114 * Perform write access to the registers. 115 * 116 * @param[in] ctx 117 * Context returned from mlx5 open_device() glue function. 118 * @param[in] reg_id 119 * Register identifier according to the PRM. 120 * @param[in] arg 121 * Register access auxiliary parameter according to the PRM. 122 * @param[out] data 123 * Pointer to the buffer containing data to write. 124 * @param[in] dw_cnt 125 * Buffer size in double words (32bit units). 126 * 127 * @return 128 * 0 on success, a negative value otherwise. 129 */ 130 int 131 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 132 uint32_t *data, uint32_t dw_cnt) 133 { 134 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 135 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 136 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 137 int status, rc; 138 void *ptr; 139 140 MLX5_ASSERT(data && dw_cnt); 141 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 142 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 143 DRV_LOG(ERR, "Data to write exceeds max size"); 144 return -1; 145 } 146 MLX5_SET(access_register_in, in, opcode, 147 MLX5_CMD_OP_ACCESS_REGISTER_USER); 148 MLX5_SET(access_register_in, in, op_mod, 149 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 150 MLX5_SET(access_register_in, in, register_id, reg_id); 151 MLX5_SET(access_register_in, in, argument, arg); 152 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 153 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 154 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 155 156 rc = mlx5_glue->devx_general_cmd(ctx, in, 157 MLX5_ST_SZ_BYTES(access_register_in) + 158 dw_cnt * sizeof(uint32_t), 159 out, sizeof(out)); 160 if (rc) 161 goto error; 162 status = MLX5_GET(access_register_out, out, status); 163 if (status) { 164 int syndrome = MLX5_GET(access_register_out, out, syndrome); 165 166 DRV_LOG(DEBUG, "Failed to write access NIC register 0x%X, " 167 "status %x, syndrome = %x", 168 reg_id, status, syndrome); 169 return -1; 170 } 171 return 0; 172 error: 173 rc = (rc > 0) ? -rc : rc; 174 return rc; 175 } 176 177 /** 178 * Allocate flow counters via devx interface. 179 * 180 * @param[in] ctx 181 * Context returned from mlx5 open_device() glue function. 182 * @param dcs 183 * Pointer to counters properties structure to be filled by the routine. 184 * @param bulk_n_128 185 * Bulk counter numbers in 128 counters units. 186 * 187 * @return 188 * Pointer to counter object on success, a negative value otherwise and 189 * rte_errno is set. 190 */ 191 struct mlx5_devx_obj * 192 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 193 { 194 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 195 0, SOCKET_ID_ANY); 196 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 197 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 198 199 if (!dcs) { 200 rte_errno = ENOMEM; 201 return NULL; 202 } 203 MLX5_SET(alloc_flow_counter_in, in, opcode, 204 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 205 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 206 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 207 sizeof(in), out, sizeof(out)); 208 if (!dcs->obj) { 209 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 210 rte_errno = errno; 211 mlx5_free(dcs); 212 return NULL; 213 } 214 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 215 return dcs; 216 } 217 218 /** 219 * Query flow counters values. 220 * 221 * @param[in] dcs 222 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 223 * @param[in] clear 224 * Whether hardware should clear the counters after the query or not. 225 * @param[in] n_counters 226 * 0 in case of 1 counter to read, otherwise the counter number to read. 227 * @param pkts 228 * The number of packets that matched the flow. 229 * @param bytes 230 * The number of bytes that matched the flow. 231 * @param mkey 232 * The mkey key for batch query. 233 * @param addr 234 * The address in the mkey range for batch query. 235 * @param cmd_comp 236 * The completion object for asynchronous batch query. 237 * @param async_id 238 * The ID to be returned in the asynchronous batch query response. 239 * 240 * @return 241 * 0 on success, a negative value otherwise. 242 */ 243 int 244 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 245 int clear, uint32_t n_counters, 246 uint64_t *pkts, uint64_t *bytes, 247 uint32_t mkey, void *addr, 248 void *cmd_comp, 249 uint64_t async_id) 250 { 251 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 252 MLX5_ST_SZ_BYTES(traffic_counter); 253 uint32_t out[out_len]; 254 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 255 void *stats; 256 int rc; 257 258 MLX5_SET(query_flow_counter_in, in, opcode, 259 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 260 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 261 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 262 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 263 264 if (n_counters) { 265 MLX5_SET(query_flow_counter_in, in, num_of_counters, 266 n_counters); 267 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 268 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 269 MLX5_SET64(query_flow_counter_in, in, address, 270 (uint64_t)(uintptr_t)addr); 271 } 272 if (!cmd_comp) 273 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 274 out_len); 275 else 276 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 277 out_len, async_id, 278 cmd_comp); 279 if (rc) { 280 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 281 rte_errno = rc; 282 return -rc; 283 } 284 if (!n_counters) { 285 stats = MLX5_ADDR_OF(query_flow_counter_out, 286 out, flow_statistics); 287 *pkts = MLX5_GET64(traffic_counter, stats, packets); 288 *bytes = MLX5_GET64(traffic_counter, stats, octets); 289 } 290 return 0; 291 } 292 293 /** 294 * Create a new mkey. 295 * 296 * @param[in] ctx 297 * Context returned from mlx5 open_device() glue function. 298 * @param[in] attr 299 * Attributes of the requested mkey. 300 * 301 * @return 302 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 303 * is set. 304 */ 305 struct mlx5_devx_obj * 306 mlx5_devx_cmd_mkey_create(void *ctx, 307 struct mlx5_devx_mkey_attr *attr) 308 { 309 struct mlx5_klm *klm_array = attr->klm_array; 310 int klm_num = attr->klm_num; 311 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 312 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 313 uint32_t in[in_size_dw]; 314 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 315 void *mkc; 316 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 317 0, SOCKET_ID_ANY); 318 size_t pgsize; 319 uint32_t translation_size; 320 321 if (!mkey) { 322 rte_errno = ENOMEM; 323 return NULL; 324 } 325 memset(in, 0, in_size_dw * 4); 326 pgsize = rte_mem_page_size(); 327 if (pgsize == (size_t)-1) { 328 mlx5_free(mkey); 329 DRV_LOG(ERR, "Failed to get page size"); 330 rte_errno = ENOMEM; 331 return NULL; 332 } 333 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 334 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 335 if (klm_num > 0) { 336 int i; 337 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 338 klm_pas_mtt); 339 translation_size = RTE_ALIGN(klm_num, 4); 340 for (i = 0; i < klm_num; i++) { 341 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 342 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 343 MLX5_SET64(klm, klm, address, klm_array[i].address); 344 klm += MLX5_ST_SZ_BYTES(klm); 345 } 346 for (; i < (int)translation_size; i++) { 347 MLX5_SET(klm, klm, mkey, 0x0); 348 MLX5_SET64(klm, klm, address, 0x0); 349 klm += MLX5_ST_SZ_BYTES(klm); 350 } 351 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 352 MLX5_MKC_ACCESS_MODE_KLM_FBS : 353 MLX5_MKC_ACCESS_MODE_KLM); 354 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 355 } else { 356 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 357 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 358 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 359 } 360 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 361 translation_size); 362 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 363 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 364 MLX5_SET(mkc, mkc, lw, 0x1); 365 MLX5_SET(mkc, mkc, lr, 0x1); 366 if (attr->set_remote_rw) { 367 MLX5_SET(mkc, mkc, rw, 0x1); 368 MLX5_SET(mkc, mkc, rr, 0x1); 369 } 370 MLX5_SET(mkc, mkc, qpn, 0xffffff); 371 MLX5_SET(mkc, mkc, pd, attr->pd); 372 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 373 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 374 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 375 MLX5_SET(mkc, mkc, relaxed_ordering_write, 376 attr->relaxed_ordering_write); 377 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 378 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 379 MLX5_SET64(mkc, mkc, len, attr->size); 380 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 381 if (attr->crypto_en) { 382 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 383 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 384 } 385 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 386 sizeof(out)); 387 if (!mkey->obj) { 388 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d", 389 klm_num ? "an in" : "a ", errno); 390 rte_errno = errno; 391 mlx5_free(mkey); 392 return NULL; 393 } 394 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 395 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 396 return mkey; 397 } 398 399 /** 400 * Get status of devx command response. 401 * Mainly used for asynchronous commands. 402 * 403 * @param[in] out 404 * The out response buffer. 405 * 406 * @return 407 * 0 on success, non-zero value otherwise. 408 */ 409 int 410 mlx5_devx_get_out_command_status(void *out) 411 { 412 int status; 413 414 if (!out) 415 return -EINVAL; 416 status = MLX5_GET(query_flow_counter_out, out, status); 417 if (status) { 418 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 419 420 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 421 syndrome); 422 } 423 return status; 424 } 425 426 /** 427 * Destroy any object allocated by a Devx API. 428 * 429 * @param[in] obj 430 * Pointer to a general object. 431 * 432 * @return 433 * 0 on success, a negative value otherwise. 434 */ 435 int 436 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 437 { 438 int ret; 439 440 if (!obj) 441 return 0; 442 ret = mlx5_glue->devx_obj_destroy(obj->obj); 443 mlx5_free(obj); 444 return ret; 445 } 446 447 /** 448 * Query NIC vport context. 449 * Fills minimal inline attribute. 450 * 451 * @param[in] ctx 452 * ibv contexts returned from mlx5dv_open_device. 453 * @param[in] vport 454 * vport index 455 * @param[out] attr 456 * Attributes device values. 457 * 458 * @return 459 * 0 on success, a negative value otherwise. 460 */ 461 static int 462 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 463 unsigned int vport, 464 struct mlx5_hca_attr *attr) 465 { 466 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 467 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 468 void *vctx; 469 int status, syndrome, rc; 470 471 /* Query NIC vport context to determine inline mode. */ 472 MLX5_SET(query_nic_vport_context_in, in, opcode, 473 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 474 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 475 if (vport) 476 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 477 rc = mlx5_glue->devx_general_cmd(ctx, 478 in, sizeof(in), 479 out, sizeof(out)); 480 if (rc) 481 goto error; 482 status = MLX5_GET(query_nic_vport_context_out, out, status); 483 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 484 if (status) { 485 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 486 "status %x, syndrome = %x", status, syndrome); 487 return -1; 488 } 489 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 490 nic_vport_context); 491 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 492 min_wqe_inline_mode); 493 return 0; 494 error: 495 rc = (rc > 0) ? -rc : rc; 496 return rc; 497 } 498 499 /** 500 * Query NIC vDPA attributes. 501 * 502 * @param[in] ctx 503 * Context returned from mlx5 open_device() glue function. 504 * @param[out] vdpa_attr 505 * vDPA Attributes structure to fill. 506 */ 507 static void 508 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 509 struct mlx5_hca_vdpa_attr *vdpa_attr) 510 { 511 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 512 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 513 void *hcattr; 514 515 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, 516 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 517 MLX5_HCA_CAP_OPMOD_GET_CUR); 518 if (!hcattr) { 519 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities"); 520 vdpa_attr->valid = 0; 521 } else { 522 vdpa_attr->valid = 1; 523 vdpa_attr->desc_tunnel_offload_type = 524 MLX5_GET(virtio_emulation_cap, hcattr, 525 desc_tunnel_offload_type); 526 vdpa_attr->eth_frame_offload_type = 527 MLX5_GET(virtio_emulation_cap, hcattr, 528 eth_frame_offload_type); 529 vdpa_attr->virtio_version_1_0 = 530 MLX5_GET(virtio_emulation_cap, hcattr, 531 virtio_version_1_0); 532 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 533 tso_ipv4); 534 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 535 tso_ipv6); 536 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 537 tx_csum); 538 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 539 rx_csum); 540 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 541 event_mode); 542 vdpa_attr->virtio_queue_type = 543 MLX5_GET(virtio_emulation_cap, hcattr, 544 virtio_queue_type); 545 vdpa_attr->log_doorbell_stride = 546 MLX5_GET(virtio_emulation_cap, hcattr, 547 log_doorbell_stride); 548 vdpa_attr->vnet_modify_ext = 549 MLX5_GET(virtio_emulation_cap, hcattr, 550 vnet_modify_ext); 551 vdpa_attr->virtio_net_q_addr_modify = 552 MLX5_GET(virtio_emulation_cap, hcattr, 553 virtio_net_q_addr_modify); 554 vdpa_attr->virtio_q_index_modify = 555 MLX5_GET(virtio_emulation_cap, hcattr, 556 virtio_q_index_modify); 557 vdpa_attr->log_doorbell_bar_size = 558 MLX5_GET(virtio_emulation_cap, hcattr, 559 log_doorbell_bar_size); 560 vdpa_attr->doorbell_bar_offset = 561 MLX5_GET64(virtio_emulation_cap, hcattr, 562 doorbell_bar_offset); 563 vdpa_attr->max_num_virtio_queues = 564 MLX5_GET(virtio_emulation_cap, hcattr, 565 max_num_virtio_queues); 566 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 567 umem_1_buffer_param_a); 568 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 569 umem_1_buffer_param_b); 570 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 571 umem_2_buffer_param_a); 572 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 573 umem_2_buffer_param_b); 574 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 575 umem_3_buffer_param_a); 576 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 577 umem_3_buffer_param_b); 578 } 579 } 580 581 int 582 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 583 uint32_t ids[], uint32_t num) 584 { 585 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 586 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 587 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 588 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 589 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 590 int ret; 591 uint32_t idx = 0; 592 uint32_t i; 593 594 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 595 rte_errno = EINVAL; 596 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 597 return -rte_errno; 598 } 599 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 600 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 601 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 602 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 603 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 604 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 605 out, sizeof(out)); 606 if (ret) { 607 rte_errno = ret; 608 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 609 (void *)flex_obj); 610 return -rte_errno; 611 } 612 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 613 void *s_off = (void *)((char *)sample + i * 614 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 615 uint32_t en; 616 617 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 618 flow_match_sample_en); 619 if (!en) 620 continue; 621 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 622 flow_match_sample_field_id); 623 } 624 if (num != idx) { 625 rte_errno = EINVAL; 626 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 627 return -rte_errno; 628 } 629 return ret; 630 } 631 632 struct mlx5_devx_obj * 633 mlx5_devx_cmd_create_flex_parser(void *ctx, 634 struct mlx5_devx_graph_node_attr *data) 635 { 636 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 637 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 638 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 639 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 640 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 641 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 642 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 643 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 644 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 645 uint32_t i; 646 647 if (!parse_flex_obj) { 648 DRV_LOG(ERR, "Failed to allocate flex parser data."); 649 rte_errno = ENOMEM; 650 return NULL; 651 } 652 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 653 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 654 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 655 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 656 MLX5_SET(parse_graph_flex, flex, header_length_mode, 657 data->header_length_mode); 658 MLX5_SET64(parse_graph_flex, flex, modify_field_select, 659 data->modify_field_select); 660 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 661 data->header_length_base_value); 662 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 663 data->header_length_field_offset); 664 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 665 data->header_length_field_shift); 666 MLX5_SET(parse_graph_flex, flex, next_header_field_offset, 667 data->next_header_field_offset); 668 MLX5_SET(parse_graph_flex, flex, next_header_field_size, 669 data->next_header_field_size); 670 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 671 data->header_length_field_mask); 672 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 673 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 674 void *s_off = (void *)((char *)sample + i * 675 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 676 677 if (!s->flow_match_sample_en) 678 continue; 679 MLX5_SET(parse_graph_flow_match_sample, s_off, 680 flow_match_sample_en, !!s->flow_match_sample_en); 681 MLX5_SET(parse_graph_flow_match_sample, s_off, 682 flow_match_sample_field_offset, 683 s->flow_match_sample_field_offset); 684 MLX5_SET(parse_graph_flow_match_sample, s_off, 685 flow_match_sample_offset_mode, 686 s->flow_match_sample_offset_mode); 687 MLX5_SET(parse_graph_flow_match_sample, s_off, 688 flow_match_sample_field_offset_mask, 689 s->flow_match_sample_field_offset_mask); 690 MLX5_SET(parse_graph_flow_match_sample, s_off, 691 flow_match_sample_field_offset_shift, 692 s->flow_match_sample_field_offset_shift); 693 MLX5_SET(parse_graph_flow_match_sample, s_off, 694 flow_match_sample_field_base_offset, 695 s->flow_match_sample_field_base_offset); 696 MLX5_SET(parse_graph_flow_match_sample, s_off, 697 flow_match_sample_tunnel_mode, 698 s->flow_match_sample_tunnel_mode); 699 } 700 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 701 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 702 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 703 void *in_off = (void *)((char *)in_arc + i * 704 MLX5_ST_SZ_BYTES(parse_graph_arc)); 705 void *out_off = (void *)((char *)out_arc + i * 706 MLX5_ST_SZ_BYTES(parse_graph_arc)); 707 708 if (ia->arc_parse_graph_node != 0) { 709 MLX5_SET(parse_graph_arc, in_off, 710 compare_condition_value, 711 ia->compare_condition_value); 712 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 713 ia->start_inner_tunnel); 714 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 715 ia->arc_parse_graph_node); 716 MLX5_SET(parse_graph_arc, in_off, 717 parse_graph_node_handle, 718 ia->parse_graph_node_handle); 719 } 720 if (oa->arc_parse_graph_node != 0) { 721 MLX5_SET(parse_graph_arc, out_off, 722 compare_condition_value, 723 oa->compare_condition_value); 724 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 725 oa->start_inner_tunnel); 726 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 727 oa->arc_parse_graph_node); 728 MLX5_SET(parse_graph_arc, out_off, 729 parse_graph_node_handle, 730 oa->parse_graph_node_handle); 731 } 732 } 733 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 734 out, sizeof(out)); 735 if (!parse_flex_obj->obj) { 736 rte_errno = errno; 737 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 738 "by using DevX."); 739 mlx5_free(parse_flex_obj); 740 return NULL; 741 } 742 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 743 return parse_flex_obj; 744 } 745 746 static int 747 mlx5_devx_cmd_query_hca_parse_graph_node_cap 748 (void *ctx, struct mlx5_hca_flex_attr *attr) 749 { 750 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 751 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 752 void *hcattr; 753 int rc; 754 755 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 756 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | 757 MLX5_HCA_CAP_OPMOD_GET_CUR); 758 if (!hcattr) 759 return rc; 760 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); 761 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); 762 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, 763 header_length_mode); 764 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, 765 sample_offset_mode); 766 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, 767 max_num_arc_in); 768 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, 769 max_num_arc_out); 770 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, 771 max_num_sample); 772 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, 773 sample_id_in_out); 774 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, 775 max_base_header_length); 776 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, 777 max_sample_base_offset); 778 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, 779 max_next_header_offset); 780 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, 781 header_length_mask_width); 782 /* Get the max supported samples from HCA CAP 2 */ 783 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 784 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 785 MLX5_HCA_CAP_OPMOD_GET_CUR); 786 if (!hcattr) 787 return rc; 788 attr->max_num_prog_sample = 789 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); 790 return 0; 791 } 792 793 static int 794 mlx5_devx_query_pkt_integrity_match(void *hcattr) 795 { 796 return MLX5_GET(flow_table_nic_cap, hcattr, 797 ft_field_support_2_nic_receive.inner_l3_ok) && 798 MLX5_GET(flow_table_nic_cap, hcattr, 799 ft_field_support_2_nic_receive.inner_l4_ok) && 800 MLX5_GET(flow_table_nic_cap, hcattr, 801 ft_field_support_2_nic_receive.outer_l3_ok) && 802 MLX5_GET(flow_table_nic_cap, hcattr, 803 ft_field_support_2_nic_receive.outer_l4_ok) && 804 MLX5_GET(flow_table_nic_cap, hcattr, 805 ft_field_support_2_nic_receive 806 .inner_ipv4_checksum_ok) && 807 MLX5_GET(flow_table_nic_cap, hcattr, 808 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 809 MLX5_GET(flow_table_nic_cap, hcattr, 810 ft_field_support_2_nic_receive 811 .outer_ipv4_checksum_ok) && 812 MLX5_GET(flow_table_nic_cap, hcattr, 813 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 814 } 815 816 /** 817 * Query HCA attributes. 818 * Using those attributes we can check on run time if the device 819 * is having the required capabilities. 820 * 821 * @param[in] ctx 822 * Context returned from mlx5 open_device() glue function. 823 * @param[out] attr 824 * Attributes device values. 825 * 826 * @return 827 * 0 on success, a negative value otherwise. 828 */ 829 int 830 mlx5_devx_cmd_query_hca_attr(void *ctx, 831 struct mlx5_hca_attr *attr) 832 { 833 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 834 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 835 bool hca_cap_2_sup; 836 uint64_t general_obj_types_supported = 0; 837 void *hcattr; 838 int rc, i; 839 840 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 841 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 842 MLX5_HCA_CAP_OPMOD_GET_CUR); 843 if (!hcattr) 844 return rc; 845 hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2); 846 attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq); 847 attr->flow_counter_bulk_alloc_bitmap = 848 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 849 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 850 flow_counters_dump); 851 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp); 852 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp); 853 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 854 log_max_rqt_size); 855 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 856 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 857 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 858 log_max_hairpin_queues); 859 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 860 log_max_hairpin_wq_data_sz); 861 attr->log_max_hairpin_num_packets = MLX5_GET 862 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 863 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 864 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 865 relaxed_ordering_write); 866 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 867 relaxed_ordering_read); 868 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 869 access_register_user); 870 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 871 eth_net_offloads); 872 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 873 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 874 flex_parser_protocols); 875 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 876 max_geneve_tlv_options); 877 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 878 max_geneve_tlv_option_data_len); 879 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 880 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 881 general_obj_types) & 882 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 883 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 884 general_obj_types) & 885 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 886 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 887 general_obj_types) & 888 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 889 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 890 general_obj_types) & 891 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 892 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 893 wqe_index_ignore_cap); 894 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 895 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 896 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 897 log_max_static_sq_wq); 898 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 899 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 900 device_frequency_khz); 901 attr->scatter_fcs_w_decap_disable = 902 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 903 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 904 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 905 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 906 attr->steering_format_version = 907 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 908 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 909 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 910 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 911 regexp_num_of_engines); 912 /* Read the general_obj_types bitmap and extract the relevant bits. */ 913 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 914 general_obj_types); 915 attr->vdpa.valid = !!(general_obj_types_supported & 916 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 917 attr->vdpa.queue_counters_valid = 918 !!(general_obj_types_supported & 919 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 920 attr->parse_graph_flex_node = 921 !!(general_obj_types_supported & 922 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 923 attr->flow_hit_aso = !!(general_obj_types_supported & 924 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 925 attr->geneve_tlv_opt = !!(general_obj_types_supported & 926 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 927 attr->dek = !!(general_obj_types_supported & 928 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 929 attr->import_kek = !!(general_obj_types_supported & 930 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 931 attr->credential = !!(general_obj_types_supported & 932 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 933 attr->crypto_login = !!(general_obj_types_supported & 934 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 935 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 936 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 937 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 938 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 939 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 940 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 941 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 942 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 943 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 944 attr->reg_c_preserve = 945 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 946 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 947 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 948 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 949 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 950 compress_mmo_sq); 951 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 952 decompress_mmo_sq); 953 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 954 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 955 compress_mmo_qp); 956 attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 957 decompress_mmo_qp); 958 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 959 compress_min_block_size); 960 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 961 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 962 log_compress_mmo_size); 963 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 964 log_decompress_mmo_size); 965 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 966 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 967 mini_cqe_resp_flow_tag); 968 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 969 mini_cqe_resp_l3_l4_tag); 970 attr->umr_indirect_mkey_disabled = 971 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 972 attr->umr_modify_entity_size_disabled = 973 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 974 attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time); 975 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 976 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 977 general_obj_types) & 978 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 979 attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); 980 if (attr->crypto) { 981 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts); 982 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 983 MLX5_GET_HCA_CAP_OP_MOD_CRYPTO | 984 MLX5_HCA_CAP_OPMOD_GET_CUR); 985 if (!hcattr) 986 return -1; 987 attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps, 988 hcattr, wrapped_import_method) 989 & 1 << 2); 990 } 991 if (hca_cap_2_sup) { 992 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 993 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 994 MLX5_HCA_CAP_OPMOD_GET_CUR); 995 if (!hcattr) { 996 DRV_LOG(DEBUG, 997 "Failed to query DevX HCA capabilities 2."); 998 return rc; 999 } 1000 attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, 1001 log_min_stride_wqe_sz); 1002 } 1003 if (attr->log_min_stride_wqe_sz == 0) 1004 attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 1005 if (attr->qos.sup) { 1006 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1007 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 1008 MLX5_HCA_CAP_OPMOD_GET_CUR); 1009 if (!hcattr) { 1010 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); 1011 return rc; 1012 } 1013 attr->qos.flow_meter_old = 1014 MLX5_GET(qos_cap, hcattr, flow_meter_old); 1015 attr->qos.log_max_flow_meter = 1016 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 1017 attr->qos.flow_meter_reg_c_ids = 1018 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 1019 attr->qos.flow_meter = 1020 MLX5_GET(qos_cap, hcattr, flow_meter); 1021 attr->qos.packet_pacing = 1022 MLX5_GET(qos_cap, hcattr, packet_pacing); 1023 attr->qos.wqe_rate_pp = 1024 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 1025 if (attr->qos.flow_meter_aso_sup) { 1026 attr->qos.log_meter_aso_granularity = 1027 MLX5_GET(qos_cap, hcattr, 1028 log_meter_aso_granularity); 1029 attr->qos.log_meter_aso_max_alloc = 1030 MLX5_GET(qos_cap, hcattr, 1031 log_meter_aso_max_alloc); 1032 attr->qos.log_max_num_meter_aso = 1033 MLX5_GET(qos_cap, hcattr, 1034 log_max_num_meter_aso); 1035 } 1036 } 1037 /* 1038 * Flex item support needs max_num_prog_sample_field 1039 * from the Capabilities 2 table for PARSE_GRAPH_NODE 1040 */ 1041 if (attr->parse_graph_flex_node) { 1042 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap 1043 (ctx, &attr->flex); 1044 if (rc) 1045 return -1; 1046 } 1047 if (attr->vdpa.valid) 1048 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 1049 if (!attr->eth_net_offloads) 1050 return 0; 1051 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 1052 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1053 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 1054 MLX5_HCA_CAP_OPMOD_GET_CUR); 1055 if (!hcattr) { 1056 attr->log_max_ft_sampler_num = 0; 1057 return rc; 1058 } 1059 attr->log_max_ft_sampler_num = MLX5_GET 1060 (flow_table_nic_cap, hcattr, 1061 flow_table_properties_nic_receive.log_max_ft_sampler_num); 1062 attr->flow.tunnel_header_0_1 = MLX5_GET 1063 (flow_table_nic_cap, hcattr, 1064 ft_field_support_2_nic_receive.tunnel_header_0_1); 1065 attr->flow.tunnel_header_2_3 = MLX5_GET 1066 (flow_table_nic_cap, hcattr, 1067 ft_field_support_2_nic_receive.tunnel_header_2_3); 1068 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 1069 attr->inner_ipv4_ihl = MLX5_GET 1070 (flow_table_nic_cap, hcattr, 1071 ft_field_support_2_nic_receive.inner_ipv4_ihl); 1072 attr->outer_ipv4_ihl = MLX5_GET 1073 (flow_table_nic_cap, hcattr, 1074 ft_field_support_2_nic_receive.outer_ipv4_ihl); 1075 /* Query HCA offloads for Ethernet protocol. */ 1076 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1077 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 1078 MLX5_HCA_CAP_OPMOD_GET_CUR); 1079 if (!hcattr) { 1080 attr->eth_net_offloads = 0; 1081 return rc; 1082 } 1083 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 1084 hcattr, wqe_vlan_insert); 1085 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 1086 hcattr, csum_cap); 1087 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 1088 hcattr, vlan_cap); 1089 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1090 lro_cap); 1091 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1092 hcattr, max_lso_cap); 1093 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1094 hcattr, scatter_fcs); 1095 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1096 hcattr, tunnel_lro_gre); 1097 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1098 hcattr, tunnel_lro_vxlan); 1099 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1100 hcattr, swp); 1101 attr->tunnel_stateless_gre = 1102 MLX5_GET(per_protocol_networking_offload_caps, 1103 hcattr, tunnel_stateless_gre); 1104 attr->tunnel_stateless_vxlan = 1105 MLX5_GET(per_protocol_networking_offload_caps, 1106 hcattr, tunnel_stateless_vxlan); 1107 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1108 hcattr, swp_csum); 1109 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1110 hcattr, swp_lso); 1111 attr->lro_max_msg_sz_mode = MLX5_GET 1112 (per_protocol_networking_offload_caps, 1113 hcattr, lro_max_msg_sz_mode); 1114 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1115 attr->lro_timer_supported_periods[i] = 1116 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1117 lro_timer_supported_periods[i]); 1118 } 1119 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1120 hcattr, lro_min_mss_size); 1121 attr->tunnel_stateless_geneve_rx = 1122 MLX5_GET(per_protocol_networking_offload_caps, 1123 hcattr, tunnel_stateless_geneve_rx); 1124 attr->geneve_max_opt_len = 1125 MLX5_GET(per_protocol_networking_offload_caps, 1126 hcattr, max_geneve_opt_len); 1127 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1128 hcattr, wqe_inline_mode); 1129 attr->tunnel_stateless_gtp = MLX5_GET 1130 (per_protocol_networking_offload_caps, 1131 hcattr, tunnel_stateless_gtp); 1132 attr->rss_ind_tbl_cap = MLX5_GET 1133 (per_protocol_networking_offload_caps, 1134 hcattr, rss_ind_tbl_cap); 1135 /* Query HCA attribute for ROCE. */ 1136 if (attr->roce) { 1137 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1138 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1139 MLX5_HCA_CAP_OPMOD_GET_CUR); 1140 if (!hcattr) { 1141 DRV_LOG(DEBUG, 1142 "Failed to query devx HCA ROCE capabilities"); 1143 return rc; 1144 } 1145 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1146 } 1147 if (attr->eth_virt && 1148 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1149 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1150 if (rc) { 1151 attr->eth_virt = 0; 1152 goto error; 1153 } 1154 } 1155 if (attr->eswitch_manager) { 1156 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1157 MLX5_SET_HCA_CAP_OP_MOD_ESW | 1158 MLX5_HCA_CAP_OPMOD_GET_CUR); 1159 if (!hcattr) 1160 return rc; 1161 attr->esw_mgr_vport_id_valid = 1162 MLX5_GET(esw_cap, hcattr, 1163 esw_manager_vport_number_valid); 1164 attr->esw_mgr_vport_id = 1165 MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); 1166 } 1167 return 0; 1168 error: 1169 rc = (rc > 0) ? -rc : rc; 1170 return rc; 1171 } 1172 1173 /** 1174 * Query TIS transport domain from QP verbs object using DevX API. 1175 * 1176 * @param[in] qp 1177 * Pointer to verbs QP returned by ibv_create_qp . 1178 * @param[in] tis_num 1179 * TIS number of TIS to query. 1180 * @param[out] tis_td 1181 * Pointer to TIS transport domain variable, to be set by the routine. 1182 * 1183 * @return 1184 * 0 on success, a negative value otherwise. 1185 */ 1186 int 1187 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1188 uint32_t *tis_td) 1189 { 1190 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1191 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1192 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1193 int rc; 1194 void *tis_ctx; 1195 1196 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1197 MLX5_SET(query_tis_in, in, tisn, tis_num); 1198 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1199 if (rc) { 1200 DRV_LOG(ERR, "Failed to query QP using DevX"); 1201 return -rc; 1202 }; 1203 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1204 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1205 return 0; 1206 #else 1207 (void)qp; 1208 (void)tis_num; 1209 (void)tis_td; 1210 return -ENOTSUP; 1211 #endif 1212 } 1213 1214 /** 1215 * Fill WQ data for DevX API command. 1216 * Utility function for use when creating DevX objects containing a WQ. 1217 * 1218 * @param[in] wq_ctx 1219 * Pointer to WQ context to fill with data. 1220 * @param [in] wq_attr 1221 * Pointer to WQ attributes structure to fill in WQ context. 1222 */ 1223 static void 1224 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1225 { 1226 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1227 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1228 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1229 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1230 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1231 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1232 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1233 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1234 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1235 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1236 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1237 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1238 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1239 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1240 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1241 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1242 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1243 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1244 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1245 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1246 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1247 wq_attr->log_hairpin_num_packets); 1248 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1249 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1250 wq_attr->single_wqe_log_num_of_strides); 1251 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1252 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1253 wq_attr->single_stride_log_num_of_bytes); 1254 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1255 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1256 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1257 } 1258 1259 /** 1260 * Create RQ using DevX API. 1261 * 1262 * @param[in] ctx 1263 * Context returned from mlx5 open_device() glue function. 1264 * @param [in] rq_attr 1265 * Pointer to create RQ attributes structure. 1266 * @param [in] socket 1267 * CPU socket ID for allocations. 1268 * 1269 * @return 1270 * The DevX object created, NULL otherwise and rte_errno is set. 1271 */ 1272 struct mlx5_devx_obj * 1273 mlx5_devx_cmd_create_rq(void *ctx, 1274 struct mlx5_devx_create_rq_attr *rq_attr, 1275 int socket) 1276 { 1277 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1278 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1279 void *rq_ctx, *wq_ctx; 1280 struct mlx5_devx_wq_attr *wq_attr; 1281 struct mlx5_devx_obj *rq = NULL; 1282 1283 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1284 if (!rq) { 1285 DRV_LOG(ERR, "Failed to allocate RQ data"); 1286 rte_errno = ENOMEM; 1287 return NULL; 1288 } 1289 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1290 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1291 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1292 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1293 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1294 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1295 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1296 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1297 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1298 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1299 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1300 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1301 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1302 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1303 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1304 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1305 wq_attr = &rq_attr->wq_attr; 1306 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1307 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1308 out, sizeof(out)); 1309 if (!rq->obj) { 1310 DRV_LOG(ERR, "Failed to create RQ using DevX"); 1311 rte_errno = errno; 1312 mlx5_free(rq); 1313 return NULL; 1314 } 1315 rq->id = MLX5_GET(create_rq_out, out, rqn); 1316 return rq; 1317 } 1318 1319 /** 1320 * Modify RQ using DevX API. 1321 * 1322 * @param[in] rq 1323 * Pointer to RQ object structure. 1324 * @param [in] rq_attr 1325 * Pointer to modify RQ attributes structure. 1326 * 1327 * @return 1328 * 0 on success, a negative errno value otherwise and rte_errno is set. 1329 */ 1330 int 1331 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1332 struct mlx5_devx_modify_rq_attr *rq_attr) 1333 { 1334 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1335 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1336 void *rq_ctx, *wq_ctx; 1337 int ret; 1338 1339 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1340 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1341 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1342 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1343 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1344 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1345 if (rq_attr->modify_bitmask & 1346 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1347 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1348 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1349 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1350 if (rq_attr->modify_bitmask & 1351 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1352 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1353 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1354 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1355 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1356 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1357 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1358 } 1359 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1360 out, sizeof(out)); 1361 if (ret) { 1362 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1363 rte_errno = errno; 1364 return -errno; 1365 } 1366 return ret; 1367 } 1368 1369 /** 1370 * Create RMP using DevX API. 1371 * 1372 * @param[in] ctx 1373 * Context returned from mlx5 open_device() glue function. 1374 * @param [in] rmp_attr 1375 * Pointer to create RMP attributes structure. 1376 * @param [in] socket 1377 * CPU socket ID for allocations. 1378 * 1379 * @return 1380 * The DevX object created, NULL otherwise and rte_errno is set. 1381 */ 1382 struct mlx5_devx_obj * 1383 mlx5_devx_cmd_create_rmp(void *ctx, 1384 struct mlx5_devx_create_rmp_attr *rmp_attr, 1385 int socket) 1386 { 1387 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0}; 1388 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0}; 1389 void *rmp_ctx, *wq_ctx; 1390 struct mlx5_devx_wq_attr *wq_attr; 1391 struct mlx5_devx_obj *rmp = NULL; 1392 1393 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket); 1394 if (!rmp) { 1395 DRV_LOG(ERR, "Failed to allocate RMP data"); 1396 rte_errno = ENOMEM; 1397 return NULL; 1398 } 1399 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP); 1400 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx); 1401 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state); 1402 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe, 1403 rmp_attr->basic_cyclic_rcv_wqe); 1404 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq); 1405 wq_attr = &rmp_attr->wq_attr; 1406 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1407 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1408 sizeof(out)); 1409 if (!rmp->obj) { 1410 DRV_LOG(ERR, "Failed to create RMP using DevX"); 1411 rte_errno = errno; 1412 mlx5_free(rmp); 1413 return NULL; 1414 } 1415 rmp->id = MLX5_GET(create_rmp_out, out, rmpn); 1416 return rmp; 1417 } 1418 1419 /* 1420 * Create TIR using DevX API. 1421 * 1422 * @param[in] ctx 1423 * Context returned from mlx5 open_device() glue function. 1424 * @param [in] tir_attr 1425 * Pointer to TIR attributes structure. 1426 * 1427 * @return 1428 * The DevX object created, NULL otherwise and rte_errno is set. 1429 */ 1430 struct mlx5_devx_obj * 1431 mlx5_devx_cmd_create_tir(void *ctx, 1432 struct mlx5_devx_tir_attr *tir_attr) 1433 { 1434 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1435 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1436 void *tir_ctx, *outer, *inner, *rss_key; 1437 struct mlx5_devx_obj *tir = NULL; 1438 1439 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1440 if (!tir) { 1441 DRV_LOG(ERR, "Failed to allocate TIR data"); 1442 rte_errno = ENOMEM; 1443 return NULL; 1444 } 1445 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1446 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1447 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1448 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1449 tir_attr->lro_timeout_period_usecs); 1450 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1451 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1452 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1453 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1454 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1455 tir_attr->tunneled_offload_en); 1456 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1457 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1458 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1459 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1460 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1461 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1462 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1463 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1464 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1465 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1466 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1467 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1468 tir_attr->rx_hash_field_selector_outer.selected_fields); 1469 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1470 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1471 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1472 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1473 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1474 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1475 tir_attr->rx_hash_field_selector_inner.selected_fields); 1476 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1477 out, sizeof(out)); 1478 if (!tir->obj) { 1479 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1480 rte_errno = errno; 1481 mlx5_free(tir); 1482 return NULL; 1483 } 1484 tir->id = MLX5_GET(create_tir_out, out, tirn); 1485 return tir; 1486 } 1487 1488 /** 1489 * Modify TIR using DevX API. 1490 * 1491 * @param[in] tir 1492 * Pointer to TIR DevX object structure. 1493 * @param [in] modify_tir_attr 1494 * Pointer to TIR modification attributes structure. 1495 * 1496 * @return 1497 * 0 on success, a negative errno value otherwise and rte_errno is set. 1498 */ 1499 int 1500 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1501 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1502 { 1503 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1504 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1505 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1506 void *tir_ctx; 1507 int ret; 1508 1509 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1510 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1511 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1512 modify_tir_attr->modify_bitmask); 1513 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1514 if (modify_tir_attr->modify_bitmask & 1515 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1516 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1517 tir_attr->lro_timeout_period_usecs); 1518 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1519 tir_attr->lro_enable_mask); 1520 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1521 tir_attr->lro_max_msg_sz); 1522 } 1523 if (modify_tir_attr->modify_bitmask & 1524 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1525 MLX5_SET(tirc, tir_ctx, indirect_table, 1526 tir_attr->indirect_table); 1527 if (modify_tir_attr->modify_bitmask & 1528 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1529 int i; 1530 void *outer, *inner; 1531 1532 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1533 tir_attr->rx_hash_symmetric); 1534 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1535 for (i = 0; i < 10; i++) { 1536 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1537 tir_attr->rx_hash_toeplitz_key[i]); 1538 } 1539 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1540 rx_hash_field_selector_outer); 1541 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1542 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1543 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1544 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1545 MLX5_SET 1546 (rx_hash_field_select, outer, selected_fields, 1547 tir_attr->rx_hash_field_selector_outer.selected_fields); 1548 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1549 rx_hash_field_selector_inner); 1550 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1551 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1552 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1553 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1554 MLX5_SET 1555 (rx_hash_field_select, inner, selected_fields, 1556 tir_attr->rx_hash_field_selector_inner.selected_fields); 1557 } 1558 if (modify_tir_attr->modify_bitmask & 1559 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1560 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1561 } 1562 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1563 out, sizeof(out)); 1564 if (ret) { 1565 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1566 rte_errno = errno; 1567 return -errno; 1568 } 1569 return ret; 1570 } 1571 1572 /** 1573 * Create RQT using DevX API. 1574 * 1575 * @param[in] ctx 1576 * Context returned from mlx5 open_device() glue function. 1577 * @param [in] rqt_attr 1578 * Pointer to RQT attributes structure. 1579 * 1580 * @return 1581 * The DevX object created, NULL otherwise and rte_errno is set. 1582 */ 1583 struct mlx5_devx_obj * 1584 mlx5_devx_cmd_create_rqt(void *ctx, 1585 struct mlx5_devx_rqt_attr *rqt_attr) 1586 { 1587 uint32_t *in = NULL; 1588 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1589 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1590 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1591 void *rqt_ctx; 1592 struct mlx5_devx_obj *rqt = NULL; 1593 int i; 1594 1595 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1596 if (!in) { 1597 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1598 rte_errno = ENOMEM; 1599 return NULL; 1600 } 1601 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1602 if (!rqt) { 1603 DRV_LOG(ERR, "Failed to allocate RQT data"); 1604 rte_errno = ENOMEM; 1605 mlx5_free(in); 1606 return NULL; 1607 } 1608 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1609 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1610 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1611 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1612 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1613 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1614 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1615 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1616 mlx5_free(in); 1617 if (!rqt->obj) { 1618 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1619 rte_errno = errno; 1620 mlx5_free(rqt); 1621 return NULL; 1622 } 1623 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1624 return rqt; 1625 } 1626 1627 /** 1628 * Modify RQT using DevX API. 1629 * 1630 * @param[in] rqt 1631 * Pointer to RQT DevX object structure. 1632 * @param [in] rqt_attr 1633 * Pointer to RQT attributes structure. 1634 * 1635 * @return 1636 * 0 on success, a negative errno value otherwise and rte_errno is set. 1637 */ 1638 int 1639 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1640 struct mlx5_devx_rqt_attr *rqt_attr) 1641 { 1642 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1643 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1644 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1645 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1646 void *rqt_ctx; 1647 int i; 1648 int ret; 1649 1650 if (!in) { 1651 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1652 rte_errno = ENOMEM; 1653 return -ENOMEM; 1654 } 1655 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1656 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1657 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1658 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1659 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1660 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1661 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1662 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1663 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1664 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1665 mlx5_free(in); 1666 if (ret) { 1667 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1668 rte_errno = errno; 1669 return -rte_errno; 1670 } 1671 return ret; 1672 } 1673 1674 /** 1675 * Create SQ using DevX API. 1676 * 1677 * @param[in] ctx 1678 * Context returned from mlx5 open_device() glue function. 1679 * @param [in] sq_attr 1680 * Pointer to SQ attributes structure. 1681 * @param [in] socket 1682 * CPU socket ID for allocations. 1683 * 1684 * @return 1685 * The DevX object created, NULL otherwise and rte_errno is set. 1686 **/ 1687 struct mlx5_devx_obj * 1688 mlx5_devx_cmd_create_sq(void *ctx, 1689 struct mlx5_devx_create_sq_attr *sq_attr) 1690 { 1691 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1692 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1693 void *sq_ctx; 1694 void *wq_ctx; 1695 struct mlx5_devx_wq_attr *wq_attr; 1696 struct mlx5_devx_obj *sq = NULL; 1697 1698 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1699 if (!sq) { 1700 DRV_LOG(ERR, "Failed to allocate SQ data"); 1701 rte_errno = ENOMEM; 1702 return NULL; 1703 } 1704 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1705 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1706 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1707 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1708 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1709 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1710 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1711 sq_attr->allow_multi_pkt_send_wqe); 1712 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1713 sq_attr->min_wqe_inline_mode); 1714 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1715 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1716 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1717 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1718 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1719 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1720 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1721 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1722 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1723 sq_attr->packet_pacing_rate_limit_index); 1724 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1725 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1726 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1727 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1728 wq_attr = &sq_attr->wq_attr; 1729 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1730 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1731 out, sizeof(out)); 1732 if (!sq->obj) { 1733 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1734 rte_errno = errno; 1735 mlx5_free(sq); 1736 return NULL; 1737 } 1738 sq->id = MLX5_GET(create_sq_out, out, sqn); 1739 return sq; 1740 } 1741 1742 /** 1743 * Modify SQ using DevX API. 1744 * 1745 * @param[in] sq 1746 * Pointer to SQ object structure. 1747 * @param [in] sq_attr 1748 * Pointer to SQ attributes structure. 1749 * 1750 * @return 1751 * 0 on success, a negative errno value otherwise and rte_errno is set. 1752 */ 1753 int 1754 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1755 struct mlx5_devx_modify_sq_attr *sq_attr) 1756 { 1757 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1758 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1759 void *sq_ctx; 1760 int ret; 1761 1762 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1763 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1764 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1765 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1766 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1767 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1768 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1769 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1770 out, sizeof(out)); 1771 if (ret) { 1772 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1773 rte_errno = errno; 1774 return -rte_errno; 1775 } 1776 return ret; 1777 } 1778 1779 /** 1780 * Create TIS using DevX API. 1781 * 1782 * @param[in] ctx 1783 * Context returned from mlx5 open_device() glue function. 1784 * @param [in] tis_attr 1785 * Pointer to TIS attributes structure. 1786 * 1787 * @return 1788 * The DevX object created, NULL otherwise and rte_errno is set. 1789 */ 1790 struct mlx5_devx_obj * 1791 mlx5_devx_cmd_create_tis(void *ctx, 1792 struct mlx5_devx_tis_attr *tis_attr) 1793 { 1794 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1795 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1796 struct mlx5_devx_obj *tis = NULL; 1797 void *tis_ctx; 1798 1799 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1800 if (!tis) { 1801 DRV_LOG(ERR, "Failed to allocate TIS object"); 1802 rte_errno = ENOMEM; 1803 return NULL; 1804 } 1805 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1806 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1807 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1808 tis_attr->strict_lag_tx_port_affinity); 1809 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1810 tis_attr->lag_tx_port_affinity); 1811 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1812 MLX5_SET(tisc, tis_ctx, transport_domain, 1813 tis_attr->transport_domain); 1814 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1815 out, sizeof(out)); 1816 if (!tis->obj) { 1817 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1818 rte_errno = errno; 1819 mlx5_free(tis); 1820 return NULL; 1821 } 1822 tis->id = MLX5_GET(create_tis_out, out, tisn); 1823 return tis; 1824 } 1825 1826 /** 1827 * Create transport domain using DevX API. 1828 * 1829 * @param[in] ctx 1830 * Context returned from mlx5 open_device() glue function. 1831 * @return 1832 * The DevX object created, NULL otherwise and rte_errno is set. 1833 */ 1834 struct mlx5_devx_obj * 1835 mlx5_devx_cmd_create_td(void *ctx) 1836 { 1837 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1838 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1839 struct mlx5_devx_obj *td = NULL; 1840 1841 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1842 if (!td) { 1843 DRV_LOG(ERR, "Failed to allocate TD object"); 1844 rte_errno = ENOMEM; 1845 return NULL; 1846 } 1847 MLX5_SET(alloc_transport_domain_in, in, opcode, 1848 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1849 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1850 out, sizeof(out)); 1851 if (!td->obj) { 1852 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1853 rte_errno = errno; 1854 mlx5_free(td); 1855 return NULL; 1856 } 1857 td->id = MLX5_GET(alloc_transport_domain_out, out, 1858 transport_domain); 1859 return td; 1860 } 1861 1862 /** 1863 * Dump all flows to file. 1864 * 1865 * @param[in] fdb_domain 1866 * FDB domain. 1867 * @param[in] rx_domain 1868 * RX domain. 1869 * @param[in] tx_domain 1870 * TX domain. 1871 * @param[out] file 1872 * Pointer to file stream. 1873 * 1874 * @return 1875 * 0 on success, a negative value otherwise. 1876 */ 1877 int 1878 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1879 void *rx_domain __rte_unused, 1880 void *tx_domain __rte_unused, FILE *file __rte_unused) 1881 { 1882 int ret = 0; 1883 1884 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1885 if (fdb_domain) { 1886 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1887 if (ret) 1888 return ret; 1889 } 1890 MLX5_ASSERT(rx_domain); 1891 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1892 if (ret) 1893 return ret; 1894 MLX5_ASSERT(tx_domain); 1895 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1896 #else 1897 ret = ENOTSUP; 1898 #endif 1899 return -ret; 1900 } 1901 1902 int 1903 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 1904 FILE *file __rte_unused) 1905 { 1906 int ret = 0; 1907 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 1908 if (rule_info) 1909 ret = mlx5_glue->dr_dump_rule(file, rule_info); 1910 #else 1911 ret = ENOTSUP; 1912 #endif 1913 return -ret; 1914 } 1915 1916 /* 1917 * Create CQ using DevX API. 1918 * 1919 * @param[in] ctx 1920 * Context returned from mlx5 open_device() glue function. 1921 * @param [in] attr 1922 * Pointer to CQ attributes structure. 1923 * 1924 * @return 1925 * The DevX object created, NULL otherwise and rte_errno is set. 1926 */ 1927 struct mlx5_devx_obj * 1928 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1929 { 1930 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1931 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1932 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1933 sizeof(*cq_obj), 1934 0, SOCKET_ID_ANY); 1935 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1936 1937 if (!cq_obj) { 1938 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1939 rte_errno = ENOMEM; 1940 return NULL; 1941 } 1942 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1943 if (attr->db_umem_valid) { 1944 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1945 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1946 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1947 } else { 1948 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1949 } 1950 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1951 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1952 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1953 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1954 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1955 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1956 MLX5_SET(cqc, cqctx, log_page_size, 1957 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1958 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1959 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1960 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1961 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1962 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1963 attr->mini_cqe_res_format_ext); 1964 if (attr->q_umem_valid) { 1965 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1966 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1967 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1968 attr->q_umem_offset); 1969 } 1970 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1971 sizeof(out)); 1972 if (!cq_obj->obj) { 1973 rte_errno = errno; 1974 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1975 mlx5_free(cq_obj); 1976 return NULL; 1977 } 1978 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1979 return cq_obj; 1980 } 1981 1982 /** 1983 * Create VIRTQ using DevX API. 1984 * 1985 * @param[in] ctx 1986 * Context returned from mlx5 open_device() glue function. 1987 * @param [in] attr 1988 * Pointer to VIRTQ attributes structure. 1989 * 1990 * @return 1991 * The DevX object created, NULL otherwise and rte_errno is set. 1992 */ 1993 struct mlx5_devx_obj * 1994 mlx5_devx_cmd_create_virtq(void *ctx, 1995 struct mlx5_devx_virtq_attr *attr) 1996 { 1997 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1998 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1999 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2000 sizeof(*virtq_obj), 2001 0, SOCKET_ID_ANY); 2002 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2003 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2004 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2005 2006 if (!virtq_obj) { 2007 DRV_LOG(ERR, "Failed to allocate virtq data."); 2008 rte_errno = ENOMEM; 2009 return NULL; 2010 } 2011 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2012 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2013 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2014 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2015 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2016 attr->hw_available_index); 2017 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 2018 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2019 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2020 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2021 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2022 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2023 attr->virtio_version_1_0); 2024 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2025 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2026 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2027 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2028 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 2029 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2030 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 2031 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2032 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 2033 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 2034 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 2035 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 2036 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 2037 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 2038 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 2039 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 2040 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 2041 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 2042 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 2043 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 2044 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 2045 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 2046 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 2047 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2048 sizeof(out)); 2049 if (!virtq_obj->obj) { 2050 rte_errno = errno; 2051 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 2052 mlx5_free(virtq_obj); 2053 return NULL; 2054 } 2055 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2056 return virtq_obj; 2057 } 2058 2059 /** 2060 * Modify VIRTQ using DevX API. 2061 * 2062 * @param[in] virtq_obj 2063 * Pointer to virtq object structure. 2064 * @param [in] attr 2065 * Pointer to modify virtq attributes structure. 2066 * 2067 * @return 2068 * 0 on success, a negative errno value otherwise and rte_errno is set. 2069 */ 2070 int 2071 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 2072 struct mlx5_devx_virtq_attr *attr) 2073 { 2074 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2075 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2076 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2077 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2078 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2079 int ret; 2080 2081 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2082 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 2083 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2084 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2085 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2086 MLX5_SET64(virtio_net_q, virtq, modify_field_select, 2087 attr->mod_fields_bitmap); 2088 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2089 if (!attr->mod_fields_bitmap) { 2090 DRV_LOG(ERR, "Failed to modify VIRTQ for no type set."); 2091 rte_errno = EINVAL; 2092 return -rte_errno; 2093 } 2094 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE) 2095 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 2096 if (attr->mod_fields_bitmap & 2097 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) { 2098 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 2099 attr->dirty_bitmap_mkey); 2100 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 2101 attr->dirty_bitmap_addr); 2102 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 2103 attr->dirty_bitmap_size); 2104 } 2105 if (attr->mod_fields_bitmap & 2106 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE) 2107 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 2108 attr->dirty_bitmap_dump_enable); 2109 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) { 2110 MLX5_SET(virtio_q, virtctx, queue_period_mode, 2111 attr->hw_latency_mode); 2112 MLX5_SET(virtio_q, virtctx, queue_period_us, 2113 attr->hw_max_latency_us); 2114 MLX5_SET(virtio_q, virtctx, queue_max_count, 2115 attr->hw_max_pending_comp); 2116 } 2117 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) { 2118 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2119 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2120 MLX5_SET64(virtio_q, virtctx, available_addr, 2121 attr->available_addr); 2122 } 2123 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX) 2124 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2125 attr->hw_available_index); 2126 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX) 2127 MLX5_SET16(virtio_net_q, virtq, hw_used_index, 2128 attr->hw_used_index); 2129 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE) 2130 MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type); 2131 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0) 2132 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2133 attr->virtio_version_1_0); 2134 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY) 2135 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2136 if (attr->mod_fields_bitmap & 2137 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) { 2138 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2139 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2140 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2141 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2142 } 2143 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) { 2144 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2145 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2146 } 2147 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 2148 out, sizeof(out)); 2149 if (ret) { 2150 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2151 rte_errno = errno; 2152 return -rte_errno; 2153 } 2154 return ret; 2155 } 2156 2157 /** 2158 * Query VIRTQ using DevX API. 2159 * 2160 * @param[in] virtq_obj 2161 * Pointer to virtq object structure. 2162 * @param [in/out] attr 2163 * Pointer to virtq attributes structure. 2164 * 2165 * @return 2166 * 0 on success, a negative errno value otherwise and rte_errno is set. 2167 */ 2168 int 2169 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 2170 struct mlx5_devx_virtq_attr *attr) 2171 { 2172 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2173 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 2174 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 2175 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 2176 int ret; 2177 2178 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2179 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2180 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2181 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2182 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2183 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2184 out, sizeof(out)); 2185 if (ret) { 2186 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2187 rte_errno = errno; 2188 return -errno; 2189 } 2190 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2191 hw_available_index); 2192 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2193 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2194 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2195 virtio_q_context.error_type); 2196 return ret; 2197 } 2198 2199 /** 2200 * Create QP using DevX API. 2201 * 2202 * @param[in] ctx 2203 * Context returned from mlx5 open_device() glue function. 2204 * @param [in] attr 2205 * Pointer to QP attributes structure. 2206 * 2207 * @return 2208 * The DevX object created, NULL otherwise and rte_errno is set. 2209 */ 2210 struct mlx5_devx_obj * 2211 mlx5_devx_cmd_create_qp(void *ctx, 2212 struct mlx5_devx_qp_attr *attr) 2213 { 2214 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2215 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2216 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2217 sizeof(*qp_obj), 2218 0, SOCKET_ID_ANY); 2219 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2220 2221 if (!qp_obj) { 2222 DRV_LOG(ERR, "Failed to allocate QP data."); 2223 rte_errno = ENOMEM; 2224 return NULL; 2225 } 2226 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2227 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2228 MLX5_SET(qpc, qpc, pd, attr->pd); 2229 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2230 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2231 if (attr->uar_index) { 2232 if (attr->mmo) { 2233 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2234 in, qpc_extension_and_pas_list); 2235 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2236 qpc_ext_and_pas_list, qpc_data_extension); 2237 2238 MLX5_SET(create_qp_in, in, qpc_ext, 1); 2239 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2240 } 2241 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2242 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2243 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2244 MLX5_SET(qpc, qpc, log_page_size, 2245 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2246 if (attr->num_of_send_wqbbs) { 2247 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs)); 2248 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2249 MLX5_SET(qpc, qpc, log_sq_size, 2250 rte_log2_u32(attr->num_of_send_wqbbs)); 2251 } else { 2252 MLX5_SET(qpc, qpc, no_sq, 1); 2253 } 2254 if (attr->num_of_receive_wqes) { 2255 MLX5_ASSERT(RTE_IS_POWER_OF_2( 2256 attr->num_of_receive_wqes)); 2257 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2258 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2259 MLX5_LOG_RQ_STRIDE_SHIFT); 2260 MLX5_SET(qpc, qpc, log_rq_size, 2261 rte_log2_u32(attr->num_of_receive_wqes)); 2262 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2263 } else { 2264 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2265 } 2266 if (attr->dbr_umem_valid) { 2267 MLX5_SET(qpc, qpc, dbr_umem_valid, 2268 attr->dbr_umem_valid); 2269 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2270 } 2271 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2272 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2273 attr->wq_umem_offset); 2274 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2275 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2276 } else { 2277 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2278 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2279 MLX5_SET(qpc, qpc, no_sq, 1); 2280 } 2281 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2282 sizeof(out)); 2283 if (!qp_obj->obj) { 2284 rte_errno = errno; 2285 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 2286 mlx5_free(qp_obj); 2287 return NULL; 2288 } 2289 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2290 return qp_obj; 2291 } 2292 2293 /** 2294 * Modify QP using DevX API. 2295 * Currently supports only force loop-back QP. 2296 * 2297 * @param[in] qp 2298 * Pointer to QP object structure. 2299 * @param [in] qp_st_mod_op 2300 * The QP state modification operation. 2301 * @param [in] remote_qp_id 2302 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2303 * 2304 * @return 2305 * 0 on success, a negative errno value otherwise and rte_errno is set. 2306 */ 2307 int 2308 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2309 uint32_t remote_qp_id) 2310 { 2311 union { 2312 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2313 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2314 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2315 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)]; 2316 } in; 2317 union { 2318 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2319 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2320 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2321 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)]; 2322 } out; 2323 void *qpc; 2324 int ret; 2325 unsigned int inlen; 2326 unsigned int outlen; 2327 2328 memset(&in, 0, sizeof(in)); 2329 memset(&out, 0, sizeof(out)); 2330 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2331 switch (qp_st_mod_op) { 2332 case MLX5_CMD_OP_RST2INIT_QP: 2333 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2334 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2335 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2336 MLX5_SET(qpc, qpc, rre, 1); 2337 MLX5_SET(qpc, qpc, rwe, 1); 2338 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2339 inlen = sizeof(in.rst2init); 2340 outlen = sizeof(out.rst2init); 2341 break; 2342 case MLX5_CMD_OP_INIT2RTR_QP: 2343 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2344 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2345 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2346 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2347 MLX5_SET(qpc, qpc, mtu, 1); 2348 MLX5_SET(qpc, qpc, log_msg_max, 30); 2349 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2350 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2351 inlen = sizeof(in.init2rtr); 2352 outlen = sizeof(out.init2rtr); 2353 break; 2354 case MLX5_CMD_OP_RTR2RTS_QP: 2355 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2356 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2357 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16); 2358 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2359 MLX5_SET(qpc, qpc, retry_count, 7); 2360 MLX5_SET(qpc, qpc, rnr_retry, 7); 2361 inlen = sizeof(in.rtr2rts); 2362 outlen = sizeof(out.rtr2rts); 2363 break; 2364 case MLX5_CMD_OP_QP_2RST: 2365 MLX5_SET(2rst_qp_in, &in, qpn, qp->id); 2366 inlen = sizeof(in.qp2rst); 2367 outlen = sizeof(out.qp2rst); 2368 break; 2369 default: 2370 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2371 qp_st_mod_op); 2372 rte_errno = EINVAL; 2373 return -rte_errno; 2374 } 2375 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2376 if (ret) { 2377 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2378 rte_errno = errno; 2379 return -rte_errno; 2380 } 2381 return ret; 2382 } 2383 2384 struct mlx5_devx_obj * 2385 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2386 { 2387 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2388 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2389 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2390 sizeof(*couners_obj), 0, 2391 SOCKET_ID_ANY); 2392 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2393 2394 if (!couners_obj) { 2395 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2396 rte_errno = ENOMEM; 2397 return NULL; 2398 } 2399 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2400 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2401 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2402 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2403 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2404 sizeof(out)); 2405 if (!couners_obj->obj) { 2406 rte_errno = errno; 2407 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 2408 " DevX."); 2409 mlx5_free(couners_obj); 2410 return NULL; 2411 } 2412 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2413 return couners_obj; 2414 } 2415 2416 int 2417 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2418 struct mlx5_devx_virtio_q_couners_attr *attr) 2419 { 2420 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2421 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2422 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2423 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2424 virtio_q_counters); 2425 int ret; 2426 2427 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2428 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2429 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2430 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2431 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2432 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2433 sizeof(out)); 2434 if (ret) { 2435 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2436 rte_errno = errno; 2437 return -errno; 2438 } 2439 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2440 received_desc); 2441 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2442 completed_desc); 2443 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2444 error_cqes); 2445 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2446 bad_desc_errors); 2447 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2448 exceed_max_chain); 2449 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2450 invalid_buffer); 2451 return ret; 2452 } 2453 2454 /** 2455 * Create general object of type FLOW_HIT_ASO using DevX API. 2456 * 2457 * @param[in] ctx 2458 * Context returned from mlx5 open_device() glue function. 2459 * @param [in] pd 2460 * PD value to associate the FLOW_HIT_ASO object with. 2461 * 2462 * @return 2463 * The DevX object created, NULL otherwise and rte_errno is set. 2464 */ 2465 struct mlx5_devx_obj * 2466 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2467 { 2468 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2469 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2470 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2471 void *ptr = NULL; 2472 2473 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2474 0, SOCKET_ID_ANY); 2475 if (!flow_hit_aso_obj) { 2476 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2477 rte_errno = ENOMEM; 2478 return NULL; 2479 } 2480 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2481 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2482 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2483 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2484 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2485 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2486 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2487 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2488 out, sizeof(out)); 2489 if (!flow_hit_aso_obj->obj) { 2490 rte_errno = errno; 2491 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX."); 2492 mlx5_free(flow_hit_aso_obj); 2493 return NULL; 2494 } 2495 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2496 return flow_hit_aso_obj; 2497 } 2498 2499 /* 2500 * Create PD using DevX API. 2501 * 2502 * @param[in] ctx 2503 * Context returned from mlx5 open_device() glue function. 2504 * 2505 * @return 2506 * The DevX object created, NULL otherwise and rte_errno is set. 2507 */ 2508 struct mlx5_devx_obj * 2509 mlx5_devx_cmd_alloc_pd(void *ctx) 2510 { 2511 struct mlx5_devx_obj *ppd = 2512 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2513 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2514 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2515 2516 if (!ppd) { 2517 DRV_LOG(ERR, "Failed to allocate PD data."); 2518 rte_errno = ENOMEM; 2519 return NULL; 2520 } 2521 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2522 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2523 out, sizeof(out)); 2524 if (!ppd->obj) { 2525 mlx5_free(ppd); 2526 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2527 rte_errno = errno; 2528 return NULL; 2529 } 2530 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2531 return ppd; 2532 } 2533 2534 /** 2535 * Create general object of type FLOW_METER_ASO using DevX API. 2536 * 2537 * @param[in] ctx 2538 * Context returned from mlx5 open_device() glue function. 2539 * @param [in] pd 2540 * PD value to associate the FLOW_METER_ASO object with. 2541 * @param [in] log_obj_size 2542 * log_obj_size define to allocate number of 2 * meters 2543 * in one FLOW_METER_ASO object. 2544 * 2545 * @return 2546 * The DevX object created, NULL otherwise and rte_errno is set. 2547 */ 2548 struct mlx5_devx_obj * 2549 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2550 uint32_t log_obj_size) 2551 { 2552 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2553 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2554 struct mlx5_devx_obj *flow_meter_aso_obj; 2555 void *ptr; 2556 2557 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2558 sizeof(*flow_meter_aso_obj), 2559 0, SOCKET_ID_ANY); 2560 if (!flow_meter_aso_obj) { 2561 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2562 rte_errno = ENOMEM; 2563 return NULL; 2564 } 2565 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2566 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2567 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2568 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2569 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2570 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2571 log_obj_size); 2572 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2573 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2574 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2575 ctx, in, sizeof(in), 2576 out, sizeof(out)); 2577 if (!flow_meter_aso_obj->obj) { 2578 rte_errno = errno; 2579 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX."); 2580 mlx5_free(flow_meter_aso_obj); 2581 return NULL; 2582 } 2583 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2584 out, obj_id); 2585 return flow_meter_aso_obj; 2586 } 2587 2588 /* 2589 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2590 * 2591 * @param[in] ctx 2592 * Context returned from mlx5 open_device() glue function. 2593 * @param [in] pd 2594 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2595 * @param [in] log_obj_size 2596 * log_obj_size to allocate its power of 2 * objects 2597 * in one CONN_TRACK_OFFLOAD bulk allocation. 2598 * 2599 * @return 2600 * The DevX object created, NULL otherwise and rte_errno is set. 2601 */ 2602 struct mlx5_devx_obj * 2603 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2604 uint32_t log_obj_size) 2605 { 2606 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2607 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2608 struct mlx5_devx_obj *ct_aso_obj; 2609 void *ptr; 2610 2611 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2612 0, SOCKET_ID_ANY); 2613 if (!ct_aso_obj) { 2614 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2615 rte_errno = ENOMEM; 2616 return NULL; 2617 } 2618 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2619 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2620 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2621 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2622 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2623 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2624 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2625 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2626 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2627 out, sizeof(out)); 2628 if (!ct_aso_obj->obj) { 2629 rte_errno = errno; 2630 DRV_LOG(ERR, "Failed to create CONN_TRACK_OFFLOAD obj by using DevX."); 2631 mlx5_free(ct_aso_obj); 2632 return NULL; 2633 } 2634 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2635 return ct_aso_obj; 2636 } 2637 2638 /** 2639 * Create general object of type GENEVE TLV option using DevX API. 2640 * 2641 * @param[in] ctx 2642 * Context returned from mlx5 open_device() glue function. 2643 * @param [in] class 2644 * TLV option variable value of class 2645 * @param [in] type 2646 * TLV option variable value of type 2647 * @param [in] len 2648 * TLV option variable value of len 2649 * 2650 * @return 2651 * The DevX object created, NULL otherwise and rte_errno is set. 2652 */ 2653 struct mlx5_devx_obj * 2654 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2655 uint16_t class, uint8_t type, uint8_t len) 2656 { 2657 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2658 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2659 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2660 sizeof(*geneve_tlv_opt_obj), 2661 0, SOCKET_ID_ANY); 2662 2663 if (!geneve_tlv_opt_obj) { 2664 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2665 rte_errno = ENOMEM; 2666 return NULL; 2667 } 2668 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2669 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2670 geneve_tlv_opt); 2671 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2672 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2673 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2674 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2675 MLX5_SET(geneve_tlv_option, opt, option_class, 2676 rte_be_to_cpu_16(class)); 2677 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2678 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2679 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2680 sizeof(in), out, sizeof(out)); 2681 if (!geneve_tlv_opt_obj->obj) { 2682 rte_errno = errno; 2683 DRV_LOG(ERR, "Failed to create Geneve tlv option " 2684 "Obj using DevX."); 2685 mlx5_free(geneve_tlv_opt_obj); 2686 return NULL; 2687 } 2688 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2689 return geneve_tlv_opt_obj; 2690 } 2691 2692 int 2693 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2694 { 2695 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2696 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2697 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2698 int rc; 2699 void *rq_ctx; 2700 2701 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2702 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2703 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2704 if (rc) { 2705 rte_errno = errno; 2706 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2707 "rc = %d, errno = %d.", rc, errno); 2708 return -rc; 2709 }; 2710 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2711 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2712 return 0; 2713 #else 2714 (void)wq; 2715 (void)counter_set_id; 2716 return -ENOTSUP; 2717 #endif 2718 } 2719 2720 /* 2721 * Allocate queue counters via devx interface. 2722 * 2723 * @param[in] ctx 2724 * Context returned from mlx5 open_device() glue function. 2725 * 2726 * @return 2727 * Pointer to counter object on success, a NULL value otherwise and 2728 * rte_errno is set. 2729 */ 2730 struct mlx5_devx_obj * 2731 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2732 { 2733 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2734 SOCKET_ID_ANY); 2735 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2736 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2737 2738 if (!dcs) { 2739 rte_errno = ENOMEM; 2740 return NULL; 2741 } 2742 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2743 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2744 sizeof(out)); 2745 if (!dcs->obj) { 2746 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error " 2747 "%d.", errno); 2748 rte_errno = errno; 2749 mlx5_free(dcs); 2750 return NULL; 2751 } 2752 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2753 return dcs; 2754 } 2755 2756 /** 2757 * Query queue counters values. 2758 * 2759 * @param[in] dcs 2760 * devx object of the queue counter set. 2761 * @param[in] clear 2762 * Whether hardware should clear the counters after the query or not. 2763 * @param[out] out_of_buffers 2764 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2765 * 2766 * @return 2767 * 0 on success, a negative value otherwise. 2768 */ 2769 int 2770 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2771 uint32_t *out_of_buffers) 2772 { 2773 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2774 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2775 int rc; 2776 2777 MLX5_SET(query_q_counter_in, in, opcode, 2778 MLX5_CMD_OP_QUERY_Q_COUNTER); 2779 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2780 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2781 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2782 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2783 sizeof(out)); 2784 if (rc) { 2785 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2786 rte_errno = rc; 2787 return -rc; 2788 } 2789 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2790 return 0; 2791 } 2792 2793 /** 2794 * Create general object of type DEK using DevX API. 2795 * 2796 * @param[in] ctx 2797 * Context returned from mlx5 open_device() glue function. 2798 * @param [in] attr 2799 * Pointer to DEK attributes structure. 2800 * 2801 * @return 2802 * The DevX object created, NULL otherwise and rte_errno is set. 2803 */ 2804 struct mlx5_devx_obj * 2805 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2806 { 2807 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2808 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2809 struct mlx5_devx_obj *dek_obj = NULL; 2810 void *ptr = NULL, *key_addr = NULL; 2811 2812 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2813 0, SOCKET_ID_ANY); 2814 if (dek_obj == NULL) { 2815 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2816 rte_errno = ENOMEM; 2817 return NULL; 2818 } 2819 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2820 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2821 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2822 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2823 MLX5_GENERAL_OBJ_TYPE_DEK); 2824 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2825 MLX5_SET(dek, ptr, key_size, attr->key_size); 2826 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2827 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2828 MLX5_SET(dek, ptr, pd, attr->pd); 2829 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2830 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2831 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2832 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2833 out, sizeof(out)); 2834 if (dek_obj->obj == NULL) { 2835 rte_errno = errno; 2836 DRV_LOG(ERR, "Failed to create DEK obj using DevX."); 2837 mlx5_free(dek_obj); 2838 return NULL; 2839 } 2840 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2841 return dek_obj; 2842 } 2843 2844 /** 2845 * Create general object of type IMPORT_KEK using DevX API. 2846 * 2847 * @param[in] ctx 2848 * Context returned from mlx5 open_device() glue function. 2849 * @param [in] attr 2850 * Pointer to IMPORT_KEK attributes structure. 2851 * 2852 * @return 2853 * The DevX object created, NULL otherwise and rte_errno is set. 2854 */ 2855 struct mlx5_devx_obj * 2856 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 2857 struct mlx5_devx_import_kek_attr *attr) 2858 { 2859 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 2860 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2861 struct mlx5_devx_obj *import_kek_obj = NULL; 2862 void *ptr = NULL, *key_addr = NULL; 2863 2864 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 2865 0, SOCKET_ID_ANY); 2866 if (import_kek_obj == NULL) { 2867 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 2868 rte_errno = ENOMEM; 2869 return NULL; 2870 } 2871 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 2872 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2873 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2874 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2875 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 2876 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 2877 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 2878 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 2879 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2880 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2881 out, sizeof(out)); 2882 if (import_kek_obj->obj == NULL) { 2883 rte_errno = errno; 2884 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX."); 2885 mlx5_free(import_kek_obj); 2886 return NULL; 2887 } 2888 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2889 return import_kek_obj; 2890 } 2891 2892 /** 2893 * Create general object of type CREDENTIAL using DevX API. 2894 * 2895 * @param[in] ctx 2896 * Context returned from mlx5 open_device() glue function. 2897 * @param [in] attr 2898 * Pointer to CREDENTIAL attributes structure. 2899 * 2900 * @return 2901 * The DevX object created, NULL otherwise and rte_errno is set. 2902 */ 2903 struct mlx5_devx_obj * 2904 mlx5_devx_cmd_create_credential_obj(void *ctx, 2905 struct mlx5_devx_credential_attr *attr) 2906 { 2907 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 2908 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2909 struct mlx5_devx_obj *credential_obj = NULL; 2910 void *ptr = NULL, *credential_addr = NULL; 2911 2912 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 2913 0, SOCKET_ID_ANY); 2914 if (credential_obj == NULL) { 2915 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 2916 rte_errno = ENOMEM; 2917 return NULL; 2918 } 2919 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 2920 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2921 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2922 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2923 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 2924 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 2925 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 2926 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 2927 memcpy(credential_addr, (void *)(attr->credential), 2928 MLX5_CRYPTO_CREDENTIAL_SIZE); 2929 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2930 out, sizeof(out)); 2931 if (credential_obj->obj == NULL) { 2932 rte_errno = errno; 2933 DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX."); 2934 mlx5_free(credential_obj); 2935 return NULL; 2936 } 2937 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2938 return credential_obj; 2939 } 2940 2941 /** 2942 * Create general object of type CRYPTO_LOGIN using DevX API. 2943 * 2944 * @param[in] ctx 2945 * Context returned from mlx5 open_device() glue function. 2946 * @param [in] attr 2947 * Pointer to CRYPTO_LOGIN attributes structure. 2948 * 2949 * @return 2950 * The DevX object created, NULL otherwise and rte_errno is set. 2951 */ 2952 struct mlx5_devx_obj * 2953 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 2954 struct mlx5_devx_crypto_login_attr *attr) 2955 { 2956 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 2957 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2958 struct mlx5_devx_obj *crypto_login_obj = NULL; 2959 void *ptr = NULL, *credential_addr = NULL; 2960 2961 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 2962 0, SOCKET_ID_ANY); 2963 if (crypto_login_obj == NULL) { 2964 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 2965 rte_errno = ENOMEM; 2966 return NULL; 2967 } 2968 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 2969 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2970 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2971 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2972 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 2973 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 2974 MLX5_SET(crypto_login, ptr, credential_pointer, 2975 attr->credential_pointer); 2976 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 2977 attr->session_import_kek_ptr); 2978 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 2979 memcpy(credential_addr, (void *)(attr->credential), 2980 MLX5_CRYPTO_CREDENTIAL_SIZE); 2981 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2982 out, sizeof(out)); 2983 if (crypto_login_obj->obj == NULL) { 2984 rte_errno = errno; 2985 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX."); 2986 mlx5_free(crypto_login_obj); 2987 return NULL; 2988 } 2989 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2990 return crypto_login_obj; 2991 } 2992 2993 /** 2994 * Query LAG context. 2995 * 2996 * @param[in] ctx 2997 * Pointer to ibv_context, returned from mlx5dv_open_device. 2998 * @param[out] lag_ctx 2999 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 3000 * 3001 * @return 3002 * 0 on success, a negative value otherwise. 3003 */ 3004 int 3005 mlx5_devx_cmd_query_lag(void *ctx, 3006 struct mlx5_devx_lag_context *lag_ctx) 3007 { 3008 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 3009 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 3010 void *lctx; 3011 int rc; 3012 3013 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 3014 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 3015 if (rc) 3016 goto error; 3017 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 3018 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 3019 fdb_selection_mode); 3020 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 3021 port_select_mode); 3022 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 3023 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 3024 tx_remap_affinity_2); 3025 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 3026 tx_remap_affinity_1); 3027 return 0; 3028 error: 3029 rc = (rc > 0) ? -rc : rc; 3030 return rc; 3031 } 3032