1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /* FW writes status value to the OUT buffer at offset 00H */ 17 #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status) 18 /* FW writes syndrome value to the OUT buffer at offset 04H */ 19 #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome) 20 21 #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1)) 22 23 #define DEVX_DRV_LOG(level, out, reason, param, value) \ 24 do { \ 25 /* \ 26 * Some (old) GCC compilers like 7.5.0 and aarch64 GCC 7.1-2017.08 \ 27 * do not expand correctly when the macro invoked when the `param` \ 28 * is `NULL`. \ 29 * Use `local_param` to avoid direct `NULL` expansion. \ 30 */ \ 31 const char *local_param = (const char *)param; \ 32 \ 33 rte_errno = errno; \ 34 if (!local_param) { \ 35 DRV_LOG(level, \ 36 "DevX %s failed errno=%d status=%#x syndrome=%#x", \ 37 (reason), errno, MLX5_FW_STATUS((out)), \ 38 MLX5_FW_SYNDROME((out))); \ 39 } else { \ 40 DRV_LOG(level, \ 41 "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x",\ 42 (reason), local_param, (value), errno, \ 43 MLX5_FW_STATUS((out)), MLX5_FW_SYNDROME((out))); \ 44 } \ 45 } while (0) 46 47 static void * 48 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, 49 int *err, uint32_t flags) 50 { 51 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); 52 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); 53 int rc; 54 55 memset(in, 0, size_in); 56 memset(out, 0, size_out); 57 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 58 MLX5_SET(query_hca_cap_in, in, op_mod, flags); 59 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); 60 if (rc || MLX5_FW_STATUS(out)) { 61 DEVX_DRV_LOG(ERR, out, "HCA capabilities", "func", flags >> 1); 62 if (err) 63 *err = MLX5_DEVX_ERR_RC(rc); 64 return NULL; 65 } 66 if (err) 67 *err = 0; 68 return MLX5_ADDR_OF(query_hca_cap_out, out, capability); 69 } 70 71 /** 72 * Perform read access to the registers. Reads data from register 73 * and writes ones to the specified buffer. 74 * 75 * @param[in] ctx 76 * Context returned from mlx5 open_device() glue function. 77 * @param[in] reg_id 78 * Register identifier according to the PRM. 79 * @param[in] arg 80 * Register access auxiliary parameter according to the PRM. 81 * @param[out] data 82 * Pointer to the buffer to store read data. 83 * @param[in] dw_cnt 84 * Buffer size in double words. 85 * 86 * @return 87 * 0 on success, a negative value otherwise. 88 */ 89 int 90 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 91 uint32_t *data, uint32_t dw_cnt) 92 { 93 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 94 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 95 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 96 int rc; 97 98 MLX5_ASSERT(data && dw_cnt); 99 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 100 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 101 DRV_LOG(ERR, "Not enough buffer for register read data"); 102 return -1; 103 } 104 MLX5_SET(access_register_in, in, opcode, 105 MLX5_CMD_OP_ACCESS_REGISTER_USER); 106 MLX5_SET(access_register_in, in, op_mod, 107 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 108 MLX5_SET(access_register_in, in, register_id, reg_id); 109 MLX5_SET(access_register_in, in, argument, arg); 110 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 111 MLX5_ST_SZ_BYTES(access_register_out) + 112 sizeof(uint32_t) * dw_cnt); 113 if (rc || MLX5_FW_STATUS(out)) { 114 DEVX_DRV_LOG(DEBUG, out, "read access", "NIC register", reg_id); 115 return MLX5_DEVX_ERR_RC(rc); 116 } 117 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 118 dw_cnt * sizeof(uint32_t)); 119 return 0; 120 } 121 122 /** 123 * Perform write access to the registers. 124 * 125 * @param[in] ctx 126 * Context returned from mlx5 open_device() glue function. 127 * @param[in] reg_id 128 * Register identifier according to the PRM. 129 * @param[in] arg 130 * Register access auxiliary parameter according to the PRM. 131 * @param[out] data 132 * Pointer to the buffer containing data to write. 133 * @param[in] dw_cnt 134 * Buffer size in double words (32bit units). 135 * 136 * @return 137 * 0 on success, a negative value otherwise. 138 */ 139 int 140 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 141 uint32_t *data, uint32_t dw_cnt) 142 { 143 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 144 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 145 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 146 int rc; 147 void *ptr; 148 149 MLX5_ASSERT(data && dw_cnt); 150 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 151 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 152 DRV_LOG(ERR, "Data to write exceeds max size"); 153 return -1; 154 } 155 MLX5_SET(access_register_in, in, opcode, 156 MLX5_CMD_OP_ACCESS_REGISTER_USER); 157 MLX5_SET(access_register_in, in, op_mod, 158 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 159 MLX5_SET(access_register_in, in, register_id, reg_id); 160 MLX5_SET(access_register_in, in, argument, arg); 161 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 162 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 163 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 164 if (rc || MLX5_FW_STATUS(out)) { 165 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 166 return MLX5_DEVX_ERR_RC(rc); 167 } 168 rc = mlx5_glue->devx_general_cmd(ctx, in, 169 MLX5_ST_SZ_BYTES(access_register_in) + 170 dw_cnt * sizeof(uint32_t), 171 out, sizeof(out)); 172 if (rc || MLX5_FW_STATUS(out)) { 173 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 174 return MLX5_DEVX_ERR_RC(rc); 175 } 176 return 0; 177 } 178 179 struct mlx5_devx_obj * 180 mlx5_devx_cmd_flow_counter_alloc_general(void *ctx, 181 struct mlx5_devx_counter_attr *attr) 182 { 183 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 184 0, SOCKET_ID_ANY); 185 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 186 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 187 188 if (!dcs) { 189 rte_errno = ENOMEM; 190 return NULL; 191 } 192 MLX5_SET(alloc_flow_counter_in, in, opcode, 193 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 194 if (attr->bulk_log_max_alloc) 195 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk_log_size, 196 attr->flow_counter_bulk_log_size); 197 else 198 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, 199 attr->bulk_n_128); 200 if (attr->pd_valid) 201 MLX5_SET(alloc_flow_counter_in, in, pd, attr->pd); 202 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 203 sizeof(in), out, sizeof(out)); 204 if (!dcs->obj) { 205 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 206 rte_errno = errno; 207 mlx5_free(dcs); 208 return NULL; 209 } 210 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 211 return dcs; 212 } 213 214 /** 215 * Allocate flow counters via devx interface. 216 * 217 * @param[in] ctx 218 * Context returned from mlx5 open_device() glue function. 219 * @param dcs 220 * Pointer to counters properties structure to be filled by the routine. 221 * @param bulk_n_128 222 * Bulk counter numbers in 128 counters units. 223 * 224 * @return 225 * Pointer to counter object on success, a negative value otherwise and 226 * rte_errno is set. 227 */ 228 struct mlx5_devx_obj * 229 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 230 { 231 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 232 0, SOCKET_ID_ANY); 233 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 234 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 235 236 if (!dcs) { 237 rte_errno = ENOMEM; 238 return NULL; 239 } 240 MLX5_SET(alloc_flow_counter_in, in, opcode, 241 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 242 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 243 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 244 sizeof(in), out, sizeof(out)); 245 if (!dcs->obj) { 246 DEVX_DRV_LOG(ERR, out, "allocate counters", NULL, 0); 247 mlx5_free(dcs); 248 return NULL; 249 } 250 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 251 return dcs; 252 } 253 254 /** 255 * Query flow counters values. 256 * 257 * @param[in] dcs 258 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 259 * @param[in] clear 260 * Whether hardware should clear the counters after the query or not. 261 * @param[in] n_counters 262 * 0 in case of 1 counter to read, otherwise the counter number to read. 263 * @param pkts 264 * The number of packets that matched the flow. 265 * @param bytes 266 * The number of bytes that matched the flow. 267 * @param mkey 268 * The mkey key for batch query. 269 * @param addr 270 * The address in the mkey range for batch query. 271 * @param cmd_comp 272 * The completion object for asynchronous batch query. 273 * @param async_id 274 * The ID to be returned in the asynchronous batch query response. 275 * 276 * @return 277 * 0 on success, a negative value otherwise. 278 */ 279 int 280 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 281 int clear, uint32_t n_counters, 282 uint64_t *pkts, uint64_t *bytes, 283 uint32_t mkey, void *addr, 284 void *cmd_comp, 285 uint64_t async_id) 286 { 287 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 288 MLX5_ST_SZ_BYTES(traffic_counter); 289 uint32_t out[out_len]; 290 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 291 void *stats; 292 int rc; 293 294 MLX5_SET(query_flow_counter_in, in, opcode, 295 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 296 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 297 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 298 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 299 300 if (n_counters) { 301 MLX5_SET(query_flow_counter_in, in, num_of_counters, 302 n_counters); 303 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 304 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 305 MLX5_SET64(query_flow_counter_in, in, address, 306 (uint64_t)(uintptr_t)addr); 307 } 308 if (!cmd_comp) 309 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 310 out_len); 311 else 312 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 313 out_len, async_id, 314 cmd_comp); 315 if (rc) { 316 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 317 rte_errno = rc; 318 return -rc; 319 } 320 if (!n_counters) { 321 stats = MLX5_ADDR_OF(query_flow_counter_out, 322 out, flow_statistics); 323 *pkts = MLX5_GET64(traffic_counter, stats, packets); 324 *bytes = MLX5_GET64(traffic_counter, stats, octets); 325 } 326 return 0; 327 } 328 329 /** 330 * Create a new mkey. 331 * 332 * @param[in] ctx 333 * Context returned from mlx5 open_device() glue function. 334 * @param[in] attr 335 * Attributes of the requested mkey. 336 * 337 * @return 338 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 339 * is set. 340 */ 341 struct mlx5_devx_obj * 342 mlx5_devx_cmd_mkey_create(void *ctx, 343 struct mlx5_devx_mkey_attr *attr) 344 { 345 struct mlx5_klm *klm_array = attr->klm_array; 346 int klm_num = attr->klm_num; 347 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 348 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 349 uint32_t in[in_size_dw]; 350 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 351 void *mkc; 352 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 353 0, SOCKET_ID_ANY); 354 size_t pgsize; 355 uint32_t translation_size; 356 357 if (!mkey) { 358 rte_errno = ENOMEM; 359 return NULL; 360 } 361 memset(in, 0, in_size_dw * 4); 362 pgsize = rte_mem_page_size(); 363 if (pgsize == (size_t)-1) { 364 mlx5_free(mkey); 365 DRV_LOG(ERR, "Failed to get page size"); 366 rte_errno = ENOMEM; 367 return NULL; 368 } 369 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 370 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 371 if (klm_num > 0) { 372 int i; 373 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 374 klm_pas_mtt); 375 translation_size = RTE_ALIGN(klm_num, 4); 376 for (i = 0; i < klm_num; i++) { 377 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 378 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 379 MLX5_SET64(klm, klm, address, klm_array[i].address); 380 klm += MLX5_ST_SZ_BYTES(klm); 381 } 382 for (; i < (int)translation_size; i++) { 383 MLX5_SET(klm, klm, mkey, 0x0); 384 MLX5_SET64(klm, klm, address, 0x0); 385 klm += MLX5_ST_SZ_BYTES(klm); 386 } 387 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 388 MLX5_MKC_ACCESS_MODE_KLM_FBS : 389 MLX5_MKC_ACCESS_MODE_KLM); 390 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 391 } else { 392 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 393 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 394 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 395 } 396 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 397 translation_size); 398 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 399 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 400 MLX5_SET(mkc, mkc, lw, 0x1); 401 MLX5_SET(mkc, mkc, lr, 0x1); 402 if (attr->set_remote_rw) { 403 MLX5_SET(mkc, mkc, rw, 0x1); 404 MLX5_SET(mkc, mkc, rr, 0x1); 405 } 406 MLX5_SET(mkc, mkc, qpn, 0xffffff); 407 MLX5_SET(mkc, mkc, pd, attr->pd); 408 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 409 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 410 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 411 MLX5_SET(mkc, mkc, relaxed_ordering_write, 412 attr->relaxed_ordering_write); 413 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 414 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 415 MLX5_SET64(mkc, mkc, len, attr->size); 416 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 417 if (attr->crypto_en) { 418 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 419 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 420 } 421 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 422 sizeof(out)); 423 if (!mkey->obj) { 424 DEVX_DRV_LOG(ERR, out, klm_num ? "create indirect mkey" 425 : "create direct key", NULL, 0); 426 mlx5_free(mkey); 427 return NULL; 428 } 429 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 430 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 431 return mkey; 432 } 433 434 /** 435 * Get status of devx command response. 436 * Mainly used for asynchronous commands. 437 * 438 * @param[in] out 439 * The out response buffer. 440 * 441 * @return 442 * 0 on success, non-zero value otherwise. 443 */ 444 int 445 mlx5_devx_get_out_command_status(void *out) 446 { 447 int status; 448 449 if (!out) 450 return -EINVAL; 451 status = MLX5_GET(query_flow_counter_out, out, status); 452 if (status) { 453 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 454 455 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 456 syndrome); 457 } 458 return status; 459 } 460 461 /** 462 * Destroy any object allocated by a Devx API. 463 * 464 * @param[in] obj 465 * Pointer to a general object. 466 * 467 * @return 468 * 0 on success, a negative value otherwise. 469 */ 470 int 471 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 472 { 473 int ret; 474 475 if (!obj) 476 return 0; 477 ret = mlx5_glue->devx_obj_destroy(obj->obj); 478 mlx5_free(obj); 479 return ret; 480 } 481 482 /** 483 * Query NIC vport context. 484 * Fills minimal inline attribute. 485 * 486 * @param[in] ctx 487 * ibv contexts returned from mlx5dv_open_device. 488 * @param[in] vport 489 * vport index 490 * @param[out] attr 491 * Attributes device values. 492 * 493 * @return 494 * 0 on success, a negative value otherwise. 495 */ 496 static int 497 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 498 unsigned int vport, 499 struct mlx5_hca_attr *attr) 500 { 501 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 502 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 503 void *vctx; 504 int rc; 505 506 /* Query NIC vport context to determine inline mode. */ 507 MLX5_SET(query_nic_vport_context_in, in, opcode, 508 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 509 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 510 if (vport) 511 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 512 rc = mlx5_glue->devx_general_cmd(ctx, 513 in, sizeof(in), 514 out, sizeof(out)); 515 if (rc || MLX5_FW_STATUS(out)) { 516 DEVX_DRV_LOG(ERR, out, "query NIC vport context", NULL, 0); 517 return MLX5_DEVX_ERR_RC(rc); 518 } 519 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 520 nic_vport_context); 521 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 522 min_wqe_inline_mode); 523 return 0; 524 } 525 526 /** 527 * Query NIC vDPA attributes. 528 * 529 * @param[in] ctx 530 * Context returned from mlx5 open_device() glue function. 531 * @param[out] vdpa_attr 532 * vDPA Attributes structure to fill. 533 */ 534 static void 535 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 536 struct mlx5_hca_vdpa_attr *vdpa_attr) 537 { 538 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 539 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 540 void *hcattr; 541 542 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, 543 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 544 MLX5_HCA_CAP_OPMOD_GET_CUR); 545 if (!hcattr) { 546 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities"); 547 vdpa_attr->valid = 0; 548 } else { 549 vdpa_attr->valid = 1; 550 vdpa_attr->desc_tunnel_offload_type = 551 MLX5_GET(virtio_emulation_cap, hcattr, 552 desc_tunnel_offload_type); 553 vdpa_attr->eth_frame_offload_type = 554 MLX5_GET(virtio_emulation_cap, hcattr, 555 eth_frame_offload_type); 556 vdpa_attr->virtio_version_1_0 = 557 MLX5_GET(virtio_emulation_cap, hcattr, 558 virtio_version_1_0); 559 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 560 tso_ipv4); 561 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 562 tso_ipv6); 563 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 564 tx_csum); 565 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 566 rx_csum); 567 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 568 event_mode); 569 vdpa_attr->virtio_queue_type = 570 MLX5_GET(virtio_emulation_cap, hcattr, 571 virtio_queue_type); 572 vdpa_attr->log_doorbell_stride = 573 MLX5_GET(virtio_emulation_cap, hcattr, 574 log_doorbell_stride); 575 vdpa_attr->vnet_modify_ext = 576 MLX5_GET(virtio_emulation_cap, hcattr, 577 vnet_modify_ext); 578 vdpa_attr->virtio_net_q_addr_modify = 579 MLX5_GET(virtio_emulation_cap, hcattr, 580 virtio_net_q_addr_modify); 581 vdpa_attr->virtio_q_index_modify = 582 MLX5_GET(virtio_emulation_cap, hcattr, 583 virtio_q_index_modify); 584 vdpa_attr->log_doorbell_bar_size = 585 MLX5_GET(virtio_emulation_cap, hcattr, 586 log_doorbell_bar_size); 587 vdpa_attr->doorbell_bar_offset = 588 MLX5_GET64(virtio_emulation_cap, hcattr, 589 doorbell_bar_offset); 590 vdpa_attr->max_num_virtio_queues = 591 MLX5_GET(virtio_emulation_cap, hcattr, 592 max_num_virtio_queues); 593 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 594 umem_1_buffer_param_a); 595 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 596 umem_1_buffer_param_b); 597 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 598 umem_2_buffer_param_a); 599 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 600 umem_2_buffer_param_b); 601 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 602 umem_3_buffer_param_a); 603 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 604 umem_3_buffer_param_b); 605 } 606 } 607 608 int 609 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 610 struct mlx5_ext_sample_id *ids, 611 uint32_t num, uint8_t *anchor) 612 { 613 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 614 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 615 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 616 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 617 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 618 int ret; 619 uint32_t idx = 0; 620 uint32_t i; 621 622 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 623 rte_errno = EINVAL; 624 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 625 return -rte_errno; 626 } 627 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 628 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 629 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 630 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 631 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 632 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 633 out, sizeof(out)); 634 if (ret) { 635 rte_errno = ret; 636 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 637 (void *)flex_obj); 638 return -rte_errno; 639 } 640 if (anchor) 641 *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id); 642 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx <= num; i++) { 643 void *s_off = (void *)((char *)sample + i * 644 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 645 uint32_t en; 646 647 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 648 flow_match_sample_en); 649 if (!en) 650 continue; 651 ids[idx++].id = MLX5_GET(parse_graph_flow_match_sample, s_off, 652 flow_match_sample_field_id); 653 } 654 if (num != idx) { 655 rte_errno = EINVAL; 656 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 657 return -rte_errno; 658 } 659 return ret; 660 } 661 662 struct mlx5_devx_obj * 663 mlx5_devx_cmd_create_flex_parser(void *ctx, 664 struct mlx5_devx_graph_node_attr *data) 665 { 666 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 667 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 668 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 669 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 670 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 671 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 672 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 673 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 674 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 675 uint32_t i; 676 677 if (!parse_flex_obj) { 678 DRV_LOG(ERR, "Failed to allocate flex parser data."); 679 rte_errno = ENOMEM; 680 return NULL; 681 } 682 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 683 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 684 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 685 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 686 MLX5_SET(parse_graph_flex, flex, header_length_mode, 687 data->header_length_mode); 688 MLX5_SET64(parse_graph_flex, flex, modify_field_select, 689 data->modify_field_select); 690 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 691 data->header_length_base_value); 692 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 693 data->header_length_field_offset); 694 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 695 data->header_length_field_shift); 696 MLX5_SET(parse_graph_flex, flex, next_header_field_offset, 697 data->next_header_field_offset); 698 MLX5_SET(parse_graph_flex, flex, next_header_field_size, 699 data->next_header_field_size); 700 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 701 data->header_length_field_mask); 702 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 703 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 704 void *s_off = (void *)((char *)sample + i * 705 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 706 707 if (!s->flow_match_sample_en) 708 continue; 709 MLX5_SET(parse_graph_flow_match_sample, s_off, 710 flow_match_sample_en, !!s->flow_match_sample_en); 711 MLX5_SET(parse_graph_flow_match_sample, s_off, 712 flow_match_sample_field_offset, 713 s->flow_match_sample_field_offset); 714 MLX5_SET(parse_graph_flow_match_sample, s_off, 715 flow_match_sample_offset_mode, 716 s->flow_match_sample_offset_mode); 717 MLX5_SET(parse_graph_flow_match_sample, s_off, 718 flow_match_sample_field_offset_mask, 719 s->flow_match_sample_field_offset_mask); 720 MLX5_SET(parse_graph_flow_match_sample, s_off, 721 flow_match_sample_field_offset_shift, 722 s->flow_match_sample_field_offset_shift); 723 MLX5_SET(parse_graph_flow_match_sample, s_off, 724 flow_match_sample_field_base_offset, 725 s->flow_match_sample_field_base_offset); 726 MLX5_SET(parse_graph_flow_match_sample, s_off, 727 flow_match_sample_tunnel_mode, 728 s->flow_match_sample_tunnel_mode); 729 } 730 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 731 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 732 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 733 void *in_off = (void *)((char *)in_arc + i * 734 MLX5_ST_SZ_BYTES(parse_graph_arc)); 735 void *out_off = (void *)((char *)out_arc + i * 736 MLX5_ST_SZ_BYTES(parse_graph_arc)); 737 738 if (ia->arc_parse_graph_node != 0) { 739 MLX5_SET(parse_graph_arc, in_off, 740 compare_condition_value, 741 ia->compare_condition_value); 742 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 743 ia->start_inner_tunnel); 744 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 745 ia->arc_parse_graph_node); 746 MLX5_SET(parse_graph_arc, in_off, 747 parse_graph_node_handle, 748 ia->parse_graph_node_handle); 749 } 750 if (oa->arc_parse_graph_node != 0) { 751 MLX5_SET(parse_graph_arc, out_off, 752 compare_condition_value, 753 oa->compare_condition_value); 754 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 755 oa->start_inner_tunnel); 756 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 757 oa->arc_parse_graph_node); 758 MLX5_SET(parse_graph_arc, out_off, 759 parse_graph_node_handle, 760 oa->parse_graph_node_handle); 761 } 762 } 763 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 764 out, sizeof(out)); 765 if (!parse_flex_obj->obj) { 766 DEVX_DRV_LOG(ERR, out, "create FLEX PARSE GRAPH", NULL, 0); 767 mlx5_free(parse_flex_obj); 768 return NULL; 769 } 770 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 771 return parse_flex_obj; 772 } 773 774 static int 775 mlx5_devx_cmd_query_hca_parse_graph_node_cap 776 (void *ctx, struct mlx5_hca_flex_attr *attr) 777 { 778 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 779 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 780 void *hcattr; 781 int rc; 782 783 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 784 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | 785 MLX5_HCA_CAP_OPMOD_GET_CUR); 786 if (!hcattr) 787 return rc; 788 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); 789 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); 790 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, 791 header_length_mode); 792 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, 793 sample_offset_mode); 794 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, 795 max_num_arc_in); 796 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, 797 max_num_arc_out); 798 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, 799 max_num_sample); 800 attr->anchor_en = MLX5_GET(parse_graph_node_cap, hcattr, anchor_en); 801 attr->ext_sample_id = MLX5_GET(parse_graph_node_cap, hcattr, ext_sample_id); 802 attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr, 803 sample_tunnel_inner2); 804 attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr, 805 zero_size_supported); 806 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, 807 sample_id_in_out); 808 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, 809 max_base_header_length); 810 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, 811 max_sample_base_offset); 812 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, 813 max_next_header_offset); 814 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, 815 header_length_mask_width); 816 /* Get the max supported samples from HCA CAP 2 */ 817 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 818 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 819 MLX5_HCA_CAP_OPMOD_GET_CUR); 820 if (!hcattr) 821 return rc; 822 attr->max_num_prog_sample = 823 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); 824 return 0; 825 } 826 827 static int 828 mlx5_devx_query_pkt_integrity_match(void *hcattr) 829 { 830 return MLX5_GET(flow_table_nic_cap, hcattr, 831 ft_field_support_2_nic_receive.inner_l3_ok) && 832 MLX5_GET(flow_table_nic_cap, hcattr, 833 ft_field_support_2_nic_receive.inner_l4_ok) && 834 MLX5_GET(flow_table_nic_cap, hcattr, 835 ft_field_support_2_nic_receive.outer_l3_ok) && 836 MLX5_GET(flow_table_nic_cap, hcattr, 837 ft_field_support_2_nic_receive.outer_l4_ok) && 838 MLX5_GET(flow_table_nic_cap, hcattr, 839 ft_field_support_2_nic_receive 840 .inner_ipv4_checksum_ok) && 841 MLX5_GET(flow_table_nic_cap, hcattr, 842 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 843 MLX5_GET(flow_table_nic_cap, hcattr, 844 ft_field_support_2_nic_receive 845 .outer_ipv4_checksum_ok) && 846 MLX5_GET(flow_table_nic_cap, hcattr, 847 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 848 } 849 850 /** 851 * Query HCA attributes. 852 * Using those attributes we can check on run time if the device 853 * is having the required capabilities. 854 * 855 * @param[in] ctx 856 * Context returned from mlx5 open_device() glue function. 857 * @param[out] attr 858 * Attributes device values. 859 * 860 * @return 861 * 0 on success, a negative value otherwise. 862 */ 863 int 864 mlx5_devx_cmd_query_hca_attr(void *ctx, 865 struct mlx5_hca_attr *attr) 866 { 867 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 868 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 869 bool hca_cap_2_sup; 870 uint64_t general_obj_types_supported = 0; 871 void *hcattr; 872 int rc, i; 873 874 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 875 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 876 MLX5_HCA_CAP_OPMOD_GET_CUR); 877 if (!hcattr) 878 return rc; 879 hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2); 880 attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq); 881 attr->flow_counter_bulk_alloc_bitmap = 882 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 883 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 884 flow_counters_dump); 885 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp); 886 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp); 887 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 888 log_max_rqt_size); 889 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 890 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 891 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 892 log_max_hairpin_queues); 893 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 894 log_max_hairpin_wq_data_sz); 895 attr->log_max_hairpin_num_packets = MLX5_GET 896 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 897 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 898 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 899 relaxed_ordering_write); 900 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 901 relaxed_ordering_read); 902 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 903 access_register_user); 904 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 905 eth_net_offloads); 906 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 907 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 908 flex_parser_protocols); 909 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 910 max_geneve_tlv_options); 911 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 912 max_geneve_tlv_option_data_len); 913 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 914 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 915 general_obj_types) & 916 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 917 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 918 general_obj_types) & 919 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 920 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 921 general_obj_types) & 922 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 923 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 924 general_obj_types) & 925 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 926 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 927 wqe_index_ignore_cap); 928 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 929 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 930 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 931 log_max_static_sq_wq); 932 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 933 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 934 device_frequency_khz); 935 attr->scatter_fcs_w_decap_disable = 936 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 937 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 938 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 939 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 940 attr->steering_format_version = 941 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 942 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 943 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 944 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 945 regexp_num_of_engines); 946 /* Read the general_obj_types bitmap and extract the relevant bits. */ 947 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 948 general_obj_types); 949 attr->vdpa.valid = !!(general_obj_types_supported & 950 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 951 attr->vdpa.queue_counters_valid = 952 !!(general_obj_types_supported & 953 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 954 attr->parse_graph_flex_node = 955 !!(general_obj_types_supported & 956 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 957 attr->flow_hit_aso = !!(general_obj_types_supported & 958 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 959 attr->geneve_tlv_opt = !!(general_obj_types_supported & 960 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 961 attr->dek = !!(general_obj_types_supported & 962 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 963 attr->import_kek = !!(general_obj_types_supported & 964 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 965 attr->credential = !!(general_obj_types_supported & 966 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 967 attr->crypto_login = !!(general_obj_types_supported & 968 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 969 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 970 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 971 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 972 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 973 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 974 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 975 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 976 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 977 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 978 attr->reg_c_preserve = 979 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 980 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 981 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 982 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 983 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 984 compress_mmo_sq); 985 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 986 decompress_mmo_sq); 987 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 988 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 989 compress_mmo_qp); 990 attr->decomp_deflate_v1_en = MLX5_GET(cmd_hca_cap, hcattr, 991 decompress_deflate_v1); 992 attr->decomp_deflate_v2_en = MLX5_GET(cmd_hca_cap, hcattr, 993 decompress_deflate_v2); 994 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 995 compress_min_block_size); 996 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 997 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 998 log_compress_mmo_size); 999 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 1000 log_decompress_mmo_size); 1001 attr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr, 1002 decompress_lz4_data_only_v2); 1003 attr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, 1004 decompress_lz4_no_checksum_v2); 1005 attr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, 1006 decompress_lz4_checksum_v2); 1007 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 1008 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 1009 mini_cqe_resp_flow_tag); 1010 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 1011 mini_cqe_resp_l3_l4_tag); 1012 attr->umr_indirect_mkey_disabled = 1013 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 1014 attr->umr_modify_entity_size_disabled = 1015 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 1016 attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time); 1017 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 1018 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 1019 general_obj_types) & 1020 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 1021 attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); 1022 attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr, 1023 max_flow_counter_15_0); 1024 attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr, 1025 max_flow_counter_31_16); 1026 attr->alloc_flow_counter_pd = MLX5_GET(cmd_hca_cap, hcattr, 1027 alloc_flow_counter_pd); 1028 attr->flow_counter_access_aso = MLX5_GET(cmd_hca_cap, hcattr, 1029 flow_counter_access_aso); 1030 attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr, 1031 flow_access_aso_opc_mod); 1032 if (attr->crypto) { 1033 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) || 1034 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_multi_block_be_tweak) || 1035 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_single_block_le_tweak); 1036 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1037 MLX5_GET_HCA_CAP_OP_MOD_CRYPTO | 1038 MLX5_HCA_CAP_OPMOD_GET_CUR); 1039 if (!hcattr) 1040 return -1; 1041 attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps, 1042 hcattr, wrapped_import_method) 1043 & 1 << 2); 1044 } 1045 if (hca_cap_2_sup) { 1046 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1047 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 1048 MLX5_HCA_CAP_OPMOD_GET_CUR); 1049 if (!hcattr) { 1050 DRV_LOG(DEBUG, 1051 "Failed to query DevX HCA capabilities 2."); 1052 return rc; 1053 } 1054 attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, 1055 log_min_stride_wqe_sz); 1056 attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr, 1057 hairpin_sq_wqe_bb_size); 1058 attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr, 1059 hairpin_sq_wq_in_host_mem); 1060 attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr, 1061 hairpin_data_buffer_locked); 1062 attr->flow_counter_bulk_log_max_alloc = MLX5_GET(cmd_hca_cap_2, 1063 hcattr, flow_counter_bulk_log_max_alloc); 1064 attr->flow_counter_bulk_log_granularity = 1065 MLX5_GET(cmd_hca_cap_2, hcattr, 1066 flow_counter_bulk_log_granularity); 1067 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1068 cross_vhca_object_to_object_supported); 1069 attr->cross_vhca = 1070 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR) && 1071 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT) && 1072 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT) && 1073 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC); 1074 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1075 allowed_object_for_other_vhca_access); 1076 attr->cross_vhca = attr->cross_vhca && 1077 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR) && 1078 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_FT) && 1079 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC); 1080 } 1081 if (attr->log_min_stride_wqe_sz == 0) 1082 attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 1083 if (attr->qos.sup) { 1084 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1085 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 1086 MLX5_HCA_CAP_OPMOD_GET_CUR); 1087 if (!hcattr) { 1088 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); 1089 return rc; 1090 } 1091 attr->qos.flow_meter_old = 1092 MLX5_GET(qos_cap, hcattr, flow_meter_old); 1093 attr->qos.log_max_flow_meter = 1094 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 1095 attr->qos.flow_meter_reg_c_ids = 1096 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 1097 attr->qos.flow_meter = 1098 MLX5_GET(qos_cap, hcattr, flow_meter); 1099 attr->qos.packet_pacing = 1100 MLX5_GET(qos_cap, hcattr, packet_pacing); 1101 attr->qos.wqe_rate_pp = 1102 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 1103 if (attr->qos.flow_meter_aso_sup) { 1104 attr->qos.log_meter_aso_granularity = 1105 MLX5_GET(qos_cap, hcattr, 1106 log_meter_aso_granularity); 1107 attr->qos.log_meter_aso_max_alloc = 1108 MLX5_GET(qos_cap, hcattr, 1109 log_meter_aso_max_alloc); 1110 attr->qos.log_max_num_meter_aso = 1111 MLX5_GET(qos_cap, hcattr, 1112 log_max_num_meter_aso); 1113 } 1114 } 1115 /* 1116 * Flex item support needs max_num_prog_sample_field 1117 * from the Capabilities 2 table for PARSE_GRAPH_NODE 1118 */ 1119 if (attr->parse_graph_flex_node) { 1120 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap 1121 (ctx, &attr->flex); 1122 if (rc) 1123 return -1; 1124 } 1125 if (attr->vdpa.valid) 1126 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 1127 if (!attr->eth_net_offloads) 1128 return 0; 1129 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 1130 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1131 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 1132 MLX5_HCA_CAP_OPMOD_GET_CUR); 1133 if (!hcattr) { 1134 attr->log_max_ft_sampler_num = 0; 1135 return rc; 1136 } 1137 attr->log_max_ft_sampler_num = MLX5_GET 1138 (flow_table_nic_cap, hcattr, 1139 flow_table_properties_nic_receive.log_max_ft_sampler_num); 1140 attr->flow.tunnel_header_0_1 = MLX5_GET 1141 (flow_table_nic_cap, hcattr, 1142 ft_field_support_2_nic_receive.tunnel_header_0_1); 1143 attr->flow.tunnel_header_2_3 = MLX5_GET 1144 (flow_table_nic_cap, hcattr, 1145 ft_field_support_2_nic_receive.tunnel_header_2_3); 1146 attr->modify_outer_ip_ecn = MLX5_GET 1147 (flow_table_nic_cap, hcattr, 1148 ft_header_modify_nic_receive.outer_ip_ecn); 1149 attr->set_reg_c = 0xff; 1150 if (attr->nic_flow_table) { 1151 #define GET_RX_REG_X_BITS \ 1152 MLX5_GET(flow_table_nic_cap, hcattr, \ 1153 ft_header_modify_nic_receive.metadata_reg_c_x) 1154 #define GET_TX_REG_X_BITS \ 1155 MLX5_GET(flow_table_nic_cap, hcattr, \ 1156 ft_header_modify_nic_transmit.metadata_reg_c_x) 1157 1158 uint32_t tx_reg, rx_reg; 1159 1160 tx_reg = GET_TX_REG_X_BITS; 1161 rx_reg = GET_RX_REG_X_BITS; 1162 attr->set_reg_c &= (rx_reg & tx_reg); 1163 1164 #undef GET_RX_REG_X_BITS 1165 #undef GET_TX_REG_X_BITS 1166 } 1167 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 1168 attr->inner_ipv4_ihl = MLX5_GET 1169 (flow_table_nic_cap, hcattr, 1170 ft_field_support_2_nic_receive.inner_ipv4_ihl); 1171 attr->outer_ipv4_ihl = MLX5_GET 1172 (flow_table_nic_cap, hcattr, 1173 ft_field_support_2_nic_receive.outer_ipv4_ihl); 1174 /* Query HCA offloads for Ethernet protocol. */ 1175 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1176 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 1177 MLX5_HCA_CAP_OPMOD_GET_CUR); 1178 if (!hcattr) { 1179 attr->eth_net_offloads = 0; 1180 return rc; 1181 } 1182 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 1183 hcattr, wqe_vlan_insert); 1184 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 1185 hcattr, csum_cap); 1186 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 1187 hcattr, vlan_cap); 1188 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1189 lro_cap); 1190 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1191 hcattr, max_lso_cap); 1192 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1193 hcattr, scatter_fcs); 1194 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1195 hcattr, tunnel_lro_gre); 1196 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1197 hcattr, tunnel_lro_vxlan); 1198 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1199 hcattr, swp); 1200 attr->tunnel_stateless_gre = 1201 MLX5_GET(per_protocol_networking_offload_caps, 1202 hcattr, tunnel_stateless_gre); 1203 attr->tunnel_stateless_vxlan = 1204 MLX5_GET(per_protocol_networking_offload_caps, 1205 hcattr, tunnel_stateless_vxlan); 1206 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1207 hcattr, swp_csum); 1208 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1209 hcattr, swp_lso); 1210 attr->lro_max_msg_sz_mode = MLX5_GET 1211 (per_protocol_networking_offload_caps, 1212 hcattr, lro_max_msg_sz_mode); 1213 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1214 attr->lro_timer_supported_periods[i] = 1215 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1216 lro_timer_supported_periods[i]); 1217 } 1218 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1219 hcattr, lro_min_mss_size); 1220 attr->tunnel_stateless_geneve_rx = 1221 MLX5_GET(per_protocol_networking_offload_caps, 1222 hcattr, tunnel_stateless_geneve_rx); 1223 attr->geneve_max_opt_len = 1224 MLX5_GET(per_protocol_networking_offload_caps, 1225 hcattr, max_geneve_opt_len); 1226 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1227 hcattr, wqe_inline_mode); 1228 attr->tunnel_stateless_gtp = MLX5_GET 1229 (per_protocol_networking_offload_caps, 1230 hcattr, tunnel_stateless_gtp); 1231 attr->rss_ind_tbl_cap = MLX5_GET 1232 (per_protocol_networking_offload_caps, 1233 hcattr, rss_ind_tbl_cap); 1234 /* Query HCA attribute for ROCE. */ 1235 if (attr->roce) { 1236 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1237 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1238 MLX5_HCA_CAP_OPMOD_GET_CUR); 1239 if (!hcattr) { 1240 DRV_LOG(DEBUG, 1241 "Failed to query devx HCA ROCE capabilities"); 1242 return rc; 1243 } 1244 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1245 } 1246 if (attr->eth_virt && 1247 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1248 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1249 if (rc) { 1250 attr->eth_virt = 0; 1251 goto error; 1252 } 1253 } 1254 if (attr->eswitch_manager) { 1255 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1256 MLX5_SET_HCA_CAP_OP_MOD_ESW | 1257 MLX5_HCA_CAP_OPMOD_GET_CUR); 1258 if (!hcattr) 1259 return rc; 1260 attr->esw_mgr_vport_id_valid = 1261 MLX5_GET(esw_cap, hcattr, 1262 esw_manager_vport_number_valid); 1263 attr->esw_mgr_vport_id = 1264 MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); 1265 } 1266 if (attr->eswitch_manager) { 1267 uint32_t esw_reg; 1268 1269 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1270 MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE | 1271 MLX5_HCA_CAP_OPMOD_GET_CUR); 1272 if (!hcattr) 1273 return rc; 1274 esw_reg = MLX5_GET(flow_table_esw_cap, hcattr, 1275 ft_header_modify_esw_fdb.metadata_reg_c_x); 1276 attr->set_reg_c &= esw_reg; 1277 } 1278 return 0; 1279 error: 1280 rc = (rc > 0) ? -rc : rc; 1281 return rc; 1282 } 1283 1284 /** 1285 * Query TIS transport domain from QP verbs object using DevX API. 1286 * 1287 * @param[in] qp 1288 * Pointer to verbs QP returned by ibv_create_qp . 1289 * @param[in] tis_num 1290 * TIS number of TIS to query. 1291 * @param[out] tis_td 1292 * Pointer to TIS transport domain variable, to be set by the routine. 1293 * 1294 * @return 1295 * 0 on success, a negative value otherwise. 1296 */ 1297 int 1298 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1299 uint32_t *tis_td) 1300 { 1301 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1302 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1303 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1304 int rc; 1305 void *tis_ctx; 1306 1307 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1308 MLX5_SET(query_tis_in, in, tisn, tis_num); 1309 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1310 if (rc) { 1311 DRV_LOG(ERR, "Failed to query QP using DevX"); 1312 return -rc; 1313 }; 1314 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1315 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1316 return 0; 1317 #else 1318 (void)qp; 1319 (void)tis_num; 1320 (void)tis_td; 1321 return -ENOTSUP; 1322 #endif 1323 } 1324 1325 /** 1326 * Fill WQ data for DevX API command. 1327 * Utility function for use when creating DevX objects containing a WQ. 1328 * 1329 * @param[in] wq_ctx 1330 * Pointer to WQ context to fill with data. 1331 * @param [in] wq_attr 1332 * Pointer to WQ attributes structure to fill in WQ context. 1333 */ 1334 static void 1335 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1336 { 1337 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1338 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1339 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1340 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1341 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1342 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1343 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1344 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1345 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1346 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1347 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1348 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1349 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1350 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1351 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1352 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1353 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1354 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1355 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1356 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1357 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1358 wq_attr->log_hairpin_num_packets); 1359 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1360 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1361 wq_attr->single_wqe_log_num_of_strides); 1362 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1363 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1364 wq_attr->single_stride_log_num_of_bytes); 1365 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1366 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1367 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1368 } 1369 1370 /** 1371 * Create RQ using DevX API. 1372 * 1373 * @param[in] ctx 1374 * Context returned from mlx5 open_device() glue function. 1375 * @param [in] rq_attr 1376 * Pointer to create RQ attributes structure. 1377 * @param [in] socket 1378 * CPU socket ID for allocations. 1379 * 1380 * @return 1381 * The DevX object created, NULL otherwise and rte_errno is set. 1382 */ 1383 struct mlx5_devx_obj * 1384 mlx5_devx_cmd_create_rq(void *ctx, 1385 struct mlx5_devx_create_rq_attr *rq_attr, 1386 int socket) 1387 { 1388 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1389 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1390 void *rq_ctx, *wq_ctx; 1391 struct mlx5_devx_wq_attr *wq_attr; 1392 struct mlx5_devx_obj *rq = NULL; 1393 1394 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1395 if (!rq) { 1396 DRV_LOG(ERR, "Failed to allocate RQ data"); 1397 rte_errno = ENOMEM; 1398 return NULL; 1399 } 1400 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1401 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1402 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1403 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1404 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1405 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1406 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1407 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1408 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1409 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1410 MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type); 1411 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1412 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1413 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1414 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1415 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1416 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1417 wq_attr = &rq_attr->wq_attr; 1418 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1419 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1420 out, sizeof(out)); 1421 if (!rq->obj) { 1422 DEVX_DRV_LOG(ERR, out, "create RQ", NULL, 0); 1423 mlx5_free(rq); 1424 return NULL; 1425 } 1426 rq->id = MLX5_GET(create_rq_out, out, rqn); 1427 return rq; 1428 } 1429 1430 /** 1431 * Modify RQ using DevX API. 1432 * 1433 * @param[in] rq 1434 * Pointer to RQ object structure. 1435 * @param [in] rq_attr 1436 * Pointer to modify RQ attributes structure. 1437 * 1438 * @return 1439 * 0 on success, a negative errno value otherwise and rte_errno is set. 1440 */ 1441 int 1442 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1443 struct mlx5_devx_modify_rq_attr *rq_attr) 1444 { 1445 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1446 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1447 void *rq_ctx, *wq_ctx; 1448 int ret; 1449 1450 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1451 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1452 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1453 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1454 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1455 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1456 if (rq_attr->modify_bitmask & 1457 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1458 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1459 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1460 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1461 if (rq_attr->modify_bitmask & 1462 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1463 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1464 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1465 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1466 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1467 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1468 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1469 } 1470 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1471 out, sizeof(out)); 1472 if (ret) { 1473 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1474 rte_errno = errno; 1475 return -errno; 1476 } 1477 return ret; 1478 } 1479 1480 /** 1481 * Create RMP using DevX API. 1482 * 1483 * @param[in] ctx 1484 * Context returned from mlx5 open_device() glue function. 1485 * @param [in] rmp_attr 1486 * Pointer to create RMP attributes structure. 1487 * @param [in] socket 1488 * CPU socket ID for allocations. 1489 * 1490 * @return 1491 * The DevX object created, NULL otherwise and rte_errno is set. 1492 */ 1493 struct mlx5_devx_obj * 1494 mlx5_devx_cmd_create_rmp(void *ctx, 1495 struct mlx5_devx_create_rmp_attr *rmp_attr, 1496 int socket) 1497 { 1498 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0}; 1499 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0}; 1500 void *rmp_ctx, *wq_ctx; 1501 struct mlx5_devx_wq_attr *wq_attr; 1502 struct mlx5_devx_obj *rmp = NULL; 1503 1504 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket); 1505 if (!rmp) { 1506 DRV_LOG(ERR, "Failed to allocate RMP data"); 1507 rte_errno = ENOMEM; 1508 return NULL; 1509 } 1510 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP); 1511 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx); 1512 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state); 1513 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe, 1514 rmp_attr->basic_cyclic_rcv_wqe); 1515 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq); 1516 wq_attr = &rmp_attr->wq_attr; 1517 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1518 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1519 sizeof(out)); 1520 if (!rmp->obj) { 1521 DEVX_DRV_LOG(ERR, out, "create RMP", NULL, 0); 1522 mlx5_free(rmp); 1523 return NULL; 1524 } 1525 rmp->id = MLX5_GET(create_rmp_out, out, rmpn); 1526 return rmp; 1527 } 1528 1529 /* 1530 * Create TIR using DevX API. 1531 * 1532 * @param[in] ctx 1533 * Context returned from mlx5 open_device() glue function. 1534 * @param [in] tir_attr 1535 * Pointer to TIR attributes structure. 1536 * 1537 * @return 1538 * The DevX object created, NULL otherwise and rte_errno is set. 1539 */ 1540 struct mlx5_devx_obj * 1541 mlx5_devx_cmd_create_tir(void *ctx, 1542 struct mlx5_devx_tir_attr *tir_attr) 1543 { 1544 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1545 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1546 void *tir_ctx, *outer, *inner, *rss_key; 1547 struct mlx5_devx_obj *tir = NULL; 1548 1549 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1550 if (!tir) { 1551 DRV_LOG(ERR, "Failed to allocate TIR data"); 1552 rte_errno = ENOMEM; 1553 return NULL; 1554 } 1555 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1556 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1557 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1558 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1559 tir_attr->lro_timeout_period_usecs); 1560 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1561 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1562 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1563 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1564 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1565 tir_attr->tunneled_offload_en); 1566 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1567 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1568 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1569 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1570 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1571 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1572 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1573 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1574 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1575 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1576 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1577 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1578 tir_attr->rx_hash_field_selector_outer.selected_fields); 1579 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1580 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1581 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1582 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1583 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1584 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1585 tir_attr->rx_hash_field_selector_inner.selected_fields); 1586 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1587 out, sizeof(out)); 1588 if (!tir->obj) { 1589 DEVX_DRV_LOG(ERR, out, "create TIR", NULL, 0); 1590 mlx5_free(tir); 1591 return NULL; 1592 } 1593 tir->id = MLX5_GET(create_tir_out, out, tirn); 1594 return tir; 1595 } 1596 1597 /** 1598 * Modify TIR using DevX API. 1599 * 1600 * @param[in] tir 1601 * Pointer to TIR DevX object structure. 1602 * @param [in] modify_tir_attr 1603 * Pointer to TIR modification attributes structure. 1604 * 1605 * @return 1606 * 0 on success, a negative errno value otherwise and rte_errno is set. 1607 */ 1608 int 1609 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1610 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1611 { 1612 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1613 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1614 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1615 void *tir_ctx; 1616 int ret; 1617 1618 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1619 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1620 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1621 modify_tir_attr->modify_bitmask); 1622 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1623 if (modify_tir_attr->modify_bitmask & 1624 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1625 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1626 tir_attr->lro_timeout_period_usecs); 1627 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1628 tir_attr->lro_enable_mask); 1629 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1630 tir_attr->lro_max_msg_sz); 1631 } 1632 if (modify_tir_attr->modify_bitmask & 1633 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1634 MLX5_SET(tirc, tir_ctx, indirect_table, 1635 tir_attr->indirect_table); 1636 if (modify_tir_attr->modify_bitmask & 1637 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1638 int i; 1639 void *outer, *inner; 1640 1641 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1642 tir_attr->rx_hash_symmetric); 1643 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1644 for (i = 0; i < 10; i++) { 1645 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1646 tir_attr->rx_hash_toeplitz_key[i]); 1647 } 1648 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1649 rx_hash_field_selector_outer); 1650 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1651 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1652 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1653 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1654 MLX5_SET 1655 (rx_hash_field_select, outer, selected_fields, 1656 tir_attr->rx_hash_field_selector_outer.selected_fields); 1657 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1658 rx_hash_field_selector_inner); 1659 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1660 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1661 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1662 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1663 MLX5_SET 1664 (rx_hash_field_select, inner, selected_fields, 1665 tir_attr->rx_hash_field_selector_inner.selected_fields); 1666 } 1667 if (modify_tir_attr->modify_bitmask & 1668 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1669 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1670 } 1671 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1672 out, sizeof(out)); 1673 if (ret) { 1674 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1675 rte_errno = errno; 1676 return -errno; 1677 } 1678 return ret; 1679 } 1680 1681 /** 1682 * Create RQT using DevX API. 1683 * 1684 * @param[in] ctx 1685 * Context returned from mlx5 open_device() glue function. 1686 * @param [in] rqt_attr 1687 * Pointer to RQT attributes structure. 1688 * 1689 * @return 1690 * The DevX object created, NULL otherwise and rte_errno is set. 1691 */ 1692 struct mlx5_devx_obj * 1693 mlx5_devx_cmd_create_rqt(void *ctx, 1694 struct mlx5_devx_rqt_attr *rqt_attr) 1695 { 1696 uint32_t *in = NULL; 1697 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1698 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1699 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1700 void *rqt_ctx; 1701 struct mlx5_devx_obj *rqt = NULL; 1702 int i; 1703 1704 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1705 if (!in) { 1706 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1707 rte_errno = ENOMEM; 1708 return NULL; 1709 } 1710 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1711 if (!rqt) { 1712 DRV_LOG(ERR, "Failed to allocate RQT data"); 1713 rte_errno = ENOMEM; 1714 mlx5_free(in); 1715 return NULL; 1716 } 1717 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1718 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1719 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1720 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1721 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1722 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1723 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1724 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1725 mlx5_free(in); 1726 if (!rqt->obj) { 1727 DEVX_DRV_LOG(ERR, out, "create RQT", NULL, 0); 1728 mlx5_free(rqt); 1729 return NULL; 1730 } 1731 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1732 return rqt; 1733 } 1734 1735 /** 1736 * Modify RQT using DevX API. 1737 * 1738 * @param[in] rqt 1739 * Pointer to RQT DevX object structure. 1740 * @param [in] rqt_attr 1741 * Pointer to RQT attributes structure. 1742 * 1743 * @return 1744 * 0 on success, a negative errno value otherwise and rte_errno is set. 1745 */ 1746 int 1747 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1748 struct mlx5_devx_rqt_attr *rqt_attr) 1749 { 1750 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1751 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1752 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1753 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1754 void *rqt_ctx; 1755 int i; 1756 int ret; 1757 1758 if (!in) { 1759 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1760 rte_errno = ENOMEM; 1761 return -ENOMEM; 1762 } 1763 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1764 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1765 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1766 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1767 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1768 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1769 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1770 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1771 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1772 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1773 mlx5_free(in); 1774 if (ret) { 1775 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1776 rte_errno = errno; 1777 return -rte_errno; 1778 } 1779 return ret; 1780 } 1781 1782 /** 1783 * Create SQ using DevX API. 1784 * 1785 * @param[in] ctx 1786 * Context returned from mlx5 open_device() glue function. 1787 * @param [in] sq_attr 1788 * Pointer to SQ attributes structure. 1789 * @param [in] socket 1790 * CPU socket ID for allocations. 1791 * 1792 * @return 1793 * The DevX object created, NULL otherwise and rte_errno is set. 1794 **/ 1795 struct mlx5_devx_obj * 1796 mlx5_devx_cmd_create_sq(void *ctx, 1797 struct mlx5_devx_create_sq_attr *sq_attr) 1798 { 1799 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1800 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1801 void *sq_ctx; 1802 void *wq_ctx; 1803 struct mlx5_devx_wq_attr *wq_attr; 1804 struct mlx5_devx_obj *sq = NULL; 1805 1806 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1807 if (!sq) { 1808 DRV_LOG(ERR, "Failed to allocate SQ data"); 1809 rte_errno = ENOMEM; 1810 return NULL; 1811 } 1812 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1813 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1814 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1815 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1816 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1817 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1818 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1819 sq_attr->allow_multi_pkt_send_wqe); 1820 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1821 sq_attr->min_wqe_inline_mode); 1822 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1823 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1824 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1825 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1826 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1827 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1828 MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type); 1829 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1830 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1831 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1832 sq_attr->packet_pacing_rate_limit_index); 1833 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1834 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1835 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1836 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1837 wq_attr = &sq_attr->wq_attr; 1838 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1839 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1840 out, sizeof(out)); 1841 if (!sq->obj) { 1842 DEVX_DRV_LOG(ERR, out, "create SQ", NULL, 0); 1843 mlx5_free(sq); 1844 return NULL; 1845 } 1846 sq->id = MLX5_GET(create_sq_out, out, sqn); 1847 return sq; 1848 } 1849 1850 /** 1851 * Modify SQ using DevX API. 1852 * 1853 * @param[in] sq 1854 * Pointer to SQ object structure. 1855 * @param [in] sq_attr 1856 * Pointer to SQ attributes structure. 1857 * 1858 * @return 1859 * 0 on success, a negative errno value otherwise and rte_errno is set. 1860 */ 1861 int 1862 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1863 struct mlx5_devx_modify_sq_attr *sq_attr) 1864 { 1865 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1866 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1867 void *sq_ctx; 1868 int ret; 1869 1870 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1871 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1872 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1873 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1874 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1875 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1876 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1877 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1878 out, sizeof(out)); 1879 if (ret) { 1880 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1881 rte_errno = errno; 1882 return -rte_errno; 1883 } 1884 return ret; 1885 } 1886 1887 /** 1888 * Create TIS using DevX API. 1889 * 1890 * @param[in] ctx 1891 * Context returned from mlx5 open_device() glue function. 1892 * @param [in] tis_attr 1893 * Pointer to TIS attributes structure. 1894 * 1895 * @return 1896 * The DevX object created, NULL otherwise and rte_errno is set. 1897 */ 1898 struct mlx5_devx_obj * 1899 mlx5_devx_cmd_create_tis(void *ctx, 1900 struct mlx5_devx_tis_attr *tis_attr) 1901 { 1902 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1903 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1904 struct mlx5_devx_obj *tis = NULL; 1905 void *tis_ctx; 1906 1907 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1908 if (!tis) { 1909 DRV_LOG(ERR, "Failed to allocate TIS object"); 1910 rte_errno = ENOMEM; 1911 return NULL; 1912 } 1913 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1914 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1915 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1916 tis_attr->strict_lag_tx_port_affinity); 1917 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1918 tis_attr->lag_tx_port_affinity); 1919 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1920 MLX5_SET(tisc, tis_ctx, transport_domain, 1921 tis_attr->transport_domain); 1922 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1923 out, sizeof(out)); 1924 if (!tis->obj) { 1925 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 1926 mlx5_free(tis); 1927 return NULL; 1928 } 1929 tis->id = MLX5_GET(create_tis_out, out, tisn); 1930 return tis; 1931 } 1932 1933 /** 1934 * Create transport domain using DevX API. 1935 * 1936 * @param[in] ctx 1937 * Context returned from mlx5 open_device() glue function. 1938 * @return 1939 * The DevX object created, NULL otherwise and rte_errno is set. 1940 */ 1941 struct mlx5_devx_obj * 1942 mlx5_devx_cmd_create_td(void *ctx) 1943 { 1944 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1945 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1946 struct mlx5_devx_obj *td = NULL; 1947 1948 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1949 if (!td) { 1950 DRV_LOG(ERR, "Failed to allocate TD object"); 1951 rte_errno = ENOMEM; 1952 return NULL; 1953 } 1954 MLX5_SET(alloc_transport_domain_in, in, opcode, 1955 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1956 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1957 out, sizeof(out)); 1958 if (!td->obj) { 1959 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 1960 mlx5_free(td); 1961 return NULL; 1962 } 1963 td->id = MLX5_GET(alloc_transport_domain_out, out, 1964 transport_domain); 1965 return td; 1966 } 1967 1968 /** 1969 * Dump all flows to file. 1970 * 1971 * @param[in] fdb_domain 1972 * FDB domain. 1973 * @param[in] rx_domain 1974 * RX domain. 1975 * @param[in] tx_domain 1976 * TX domain. 1977 * @param[out] file 1978 * Pointer to file stream. 1979 * 1980 * @return 1981 * 0 on success, a negative value otherwise. 1982 */ 1983 int 1984 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1985 void *rx_domain __rte_unused, 1986 void *tx_domain __rte_unused, FILE *file __rte_unused) 1987 { 1988 int ret = 0; 1989 1990 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1991 if (fdb_domain) { 1992 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1993 if (ret) 1994 return ret; 1995 } 1996 MLX5_ASSERT(rx_domain); 1997 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1998 if (ret) 1999 return ret; 2000 MLX5_ASSERT(tx_domain); 2001 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 2002 #else 2003 ret = ENOTSUP; 2004 #endif 2005 return -ret; 2006 } 2007 2008 int 2009 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 2010 FILE *file __rte_unused) 2011 { 2012 int ret = 0; 2013 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 2014 if (rule_info) 2015 ret = mlx5_glue->dr_dump_rule(file, rule_info); 2016 #else 2017 ret = ENOTSUP; 2018 #endif 2019 return -ret; 2020 } 2021 2022 /* 2023 * Create CQ using DevX API. 2024 * 2025 * @param[in] ctx 2026 * Context returned from mlx5 open_device() glue function. 2027 * @param [in] attr 2028 * Pointer to CQ attributes structure. 2029 * 2030 * @return 2031 * The DevX object created, NULL otherwise and rte_errno is set. 2032 */ 2033 struct mlx5_devx_obj * 2034 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 2035 { 2036 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 2037 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 2038 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2039 sizeof(*cq_obj), 2040 0, SOCKET_ID_ANY); 2041 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 2042 2043 if (!cq_obj) { 2044 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 2045 rte_errno = ENOMEM; 2046 return NULL; 2047 } 2048 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 2049 if (attr->db_umem_valid) { 2050 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 2051 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 2052 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 2053 } else { 2054 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 2055 } 2056 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 2057 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 2058 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 2059 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 2060 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 2061 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2062 MLX5_SET(cqc, cqctx, log_page_size, 2063 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2064 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 2065 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 2066 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 2067 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 2068 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 2069 attr->mini_cqe_res_format_ext); 2070 if (attr->q_umem_valid) { 2071 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 2072 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 2073 MLX5_SET64(create_cq_in, in, cq_umem_offset, 2074 attr->q_umem_offset); 2075 } 2076 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2077 sizeof(out)); 2078 if (!cq_obj->obj) { 2079 DEVX_DRV_LOG(ERR, out, "create CQ", NULL, 0); 2080 mlx5_free(cq_obj); 2081 return NULL; 2082 } 2083 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 2084 return cq_obj; 2085 } 2086 2087 /** 2088 * Create VIRTQ using DevX API. 2089 * 2090 * @param[in] ctx 2091 * Context returned from mlx5 open_device() glue function. 2092 * @param [in] attr 2093 * Pointer to VIRTQ attributes structure. 2094 * 2095 * @return 2096 * The DevX object created, NULL otherwise and rte_errno is set. 2097 */ 2098 struct mlx5_devx_obj * 2099 mlx5_devx_cmd_create_virtq(void *ctx, 2100 struct mlx5_devx_virtq_attr *attr) 2101 { 2102 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2103 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2104 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2105 sizeof(*virtq_obj), 2106 0, SOCKET_ID_ANY); 2107 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2108 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2109 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2110 2111 if (!virtq_obj) { 2112 DRV_LOG(ERR, "Failed to allocate virtq data."); 2113 rte_errno = ENOMEM; 2114 return NULL; 2115 } 2116 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2117 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2118 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2119 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2120 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2121 attr->hw_available_index); 2122 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 2123 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2124 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2125 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2126 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2127 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2128 attr->virtio_version_1_0); 2129 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2130 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2131 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2132 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2133 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 2134 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2135 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 2136 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2137 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 2138 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 2139 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 2140 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 2141 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 2142 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 2143 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 2144 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 2145 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 2146 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 2147 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 2148 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 2149 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 2150 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 2151 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 2152 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2153 sizeof(out)); 2154 if (!virtq_obj->obj) { 2155 DEVX_DRV_LOG(ERR, out, "create VIRTQ", NULL, 0); 2156 mlx5_free(virtq_obj); 2157 return NULL; 2158 } 2159 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2160 return virtq_obj; 2161 } 2162 2163 /** 2164 * Modify VIRTQ using DevX API. 2165 * 2166 * @param[in] virtq_obj 2167 * Pointer to virtq object structure. 2168 * @param [in] attr 2169 * Pointer to modify virtq attributes structure. 2170 * 2171 * @return 2172 * 0 on success, a negative errno value otherwise and rte_errno is set. 2173 */ 2174 int 2175 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 2176 struct mlx5_devx_virtq_attr *attr) 2177 { 2178 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2179 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2180 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2181 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2182 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2183 int ret; 2184 2185 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2186 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 2187 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2188 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2189 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2190 MLX5_SET64(virtio_net_q, virtq, modify_field_select, 2191 attr->mod_fields_bitmap); 2192 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2193 if (!attr->mod_fields_bitmap) { 2194 DRV_LOG(ERR, "Failed to modify VIRTQ for no type set."); 2195 rte_errno = EINVAL; 2196 return -rte_errno; 2197 } 2198 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE) 2199 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 2200 if (attr->mod_fields_bitmap & 2201 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) { 2202 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 2203 attr->dirty_bitmap_mkey); 2204 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 2205 attr->dirty_bitmap_addr); 2206 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 2207 attr->dirty_bitmap_size); 2208 } 2209 if (attr->mod_fields_bitmap & 2210 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE) 2211 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 2212 attr->dirty_bitmap_dump_enable); 2213 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) { 2214 MLX5_SET(virtio_q, virtctx, queue_period_mode, 2215 attr->hw_latency_mode); 2216 MLX5_SET(virtio_q, virtctx, queue_period_us, 2217 attr->hw_max_latency_us); 2218 MLX5_SET(virtio_q, virtctx, queue_max_count, 2219 attr->hw_max_pending_comp); 2220 } 2221 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) { 2222 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2223 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2224 MLX5_SET64(virtio_q, virtctx, available_addr, 2225 attr->available_addr); 2226 } 2227 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX) 2228 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2229 attr->hw_available_index); 2230 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX) 2231 MLX5_SET16(virtio_net_q, virtq, hw_used_index, 2232 attr->hw_used_index); 2233 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE) 2234 MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type); 2235 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0) 2236 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2237 attr->virtio_version_1_0); 2238 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY) 2239 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2240 if (attr->mod_fields_bitmap & 2241 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) { 2242 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2243 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2244 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2245 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2246 } 2247 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) { 2248 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2249 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2250 } 2251 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 2252 out, sizeof(out)); 2253 if (ret) { 2254 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2255 rte_errno = errno; 2256 return -rte_errno; 2257 } 2258 return ret; 2259 } 2260 2261 /** 2262 * Query VIRTQ using DevX API. 2263 * 2264 * @param[in] virtq_obj 2265 * Pointer to virtq object structure. 2266 * @param [in/out] attr 2267 * Pointer to virtq attributes structure. 2268 * 2269 * @return 2270 * 0 on success, a negative errno value otherwise and rte_errno is set. 2271 */ 2272 int 2273 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 2274 struct mlx5_devx_virtq_attr *attr) 2275 { 2276 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2277 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 2278 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 2279 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 2280 int ret; 2281 2282 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2283 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2284 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2285 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2286 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2287 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2288 out, sizeof(out)); 2289 if (ret) { 2290 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2291 rte_errno = errno; 2292 return -errno; 2293 } 2294 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2295 hw_available_index); 2296 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2297 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2298 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2299 virtio_q_context.error_type); 2300 return ret; 2301 } 2302 2303 /** 2304 * Create QP using DevX API. 2305 * 2306 * @param[in] ctx 2307 * Context returned from mlx5 open_device() glue function. 2308 * @param [in] attr 2309 * Pointer to QP attributes structure. 2310 * 2311 * @return 2312 * The DevX object created, NULL otherwise and rte_errno is set. 2313 */ 2314 struct mlx5_devx_obj * 2315 mlx5_devx_cmd_create_qp(void *ctx, 2316 struct mlx5_devx_qp_attr *attr) 2317 { 2318 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2319 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2320 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2321 sizeof(*qp_obj), 2322 0, SOCKET_ID_ANY); 2323 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2324 2325 if (!qp_obj) { 2326 DRV_LOG(ERR, "Failed to allocate QP data."); 2327 rte_errno = ENOMEM; 2328 return NULL; 2329 } 2330 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2331 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2332 MLX5_SET(qpc, qpc, pd, attr->pd); 2333 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2334 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2335 if (attr->uar_index) { 2336 if (attr->mmo) { 2337 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2338 in, qpc_extension_and_pas_list); 2339 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2340 qpc_ext_and_pas_list, qpc_data_extension); 2341 2342 MLX5_SET(create_qp_in, in, qpc_ext, 1); 2343 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2344 } 2345 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2346 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2347 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2348 MLX5_SET(qpc, qpc, log_page_size, 2349 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2350 if (attr->num_of_send_wqbbs) { 2351 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs)); 2352 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2353 MLX5_SET(qpc, qpc, log_sq_size, 2354 rte_log2_u32(attr->num_of_send_wqbbs)); 2355 } else { 2356 MLX5_SET(qpc, qpc, no_sq, 1); 2357 } 2358 if (attr->num_of_receive_wqes) { 2359 MLX5_ASSERT(RTE_IS_POWER_OF_2( 2360 attr->num_of_receive_wqes)); 2361 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2362 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2363 MLX5_LOG_RQ_STRIDE_SHIFT); 2364 MLX5_SET(qpc, qpc, log_rq_size, 2365 rte_log2_u32(attr->num_of_receive_wqes)); 2366 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2367 } else { 2368 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2369 } 2370 if (attr->dbr_umem_valid) { 2371 MLX5_SET(qpc, qpc, dbr_umem_valid, 2372 attr->dbr_umem_valid); 2373 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2374 } 2375 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2376 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2377 attr->wq_umem_offset); 2378 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2379 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2380 } else { 2381 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2382 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2383 MLX5_SET(qpc, qpc, no_sq, 1); 2384 } 2385 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2386 sizeof(out)); 2387 if (!qp_obj->obj) { 2388 DEVX_DRV_LOG(ERR, out, "create QP", NULL, 0); 2389 mlx5_free(qp_obj); 2390 return NULL; 2391 } 2392 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2393 return qp_obj; 2394 } 2395 2396 /** 2397 * Modify QP using DevX API. 2398 * Currently supports only force loop-back QP. 2399 * 2400 * @param[in] qp 2401 * Pointer to QP object structure. 2402 * @param [in] qp_st_mod_op 2403 * The QP state modification operation. 2404 * @param [in] remote_qp_id 2405 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2406 * 2407 * @return 2408 * 0 on success, a negative errno value otherwise and rte_errno is set. 2409 */ 2410 int 2411 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2412 uint32_t remote_qp_id) 2413 { 2414 union { 2415 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2416 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2417 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2418 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)]; 2419 } in; 2420 union { 2421 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2422 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2423 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2424 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)]; 2425 } out; 2426 void *qpc; 2427 int ret; 2428 unsigned int inlen; 2429 unsigned int outlen; 2430 2431 memset(&in, 0, sizeof(in)); 2432 memset(&out, 0, sizeof(out)); 2433 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2434 switch (qp_st_mod_op) { 2435 case MLX5_CMD_OP_RST2INIT_QP: 2436 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2437 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2438 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2439 MLX5_SET(qpc, qpc, rre, 1); 2440 MLX5_SET(qpc, qpc, rwe, 1); 2441 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2442 inlen = sizeof(in.rst2init); 2443 outlen = sizeof(out.rst2init); 2444 break; 2445 case MLX5_CMD_OP_INIT2RTR_QP: 2446 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2447 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2448 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2449 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2450 MLX5_SET(qpc, qpc, mtu, 1); 2451 MLX5_SET(qpc, qpc, log_msg_max, 30); 2452 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2453 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2454 inlen = sizeof(in.init2rtr); 2455 outlen = sizeof(out.init2rtr); 2456 break; 2457 case MLX5_CMD_OP_RTR2RTS_QP: 2458 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2459 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2460 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16); 2461 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2462 MLX5_SET(qpc, qpc, retry_count, 7); 2463 MLX5_SET(qpc, qpc, rnr_retry, 7); 2464 inlen = sizeof(in.rtr2rts); 2465 outlen = sizeof(out.rtr2rts); 2466 break; 2467 case MLX5_CMD_OP_QP_2RST: 2468 MLX5_SET(2rst_qp_in, &in, qpn, qp->id); 2469 inlen = sizeof(in.qp2rst); 2470 outlen = sizeof(out.qp2rst); 2471 break; 2472 default: 2473 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2474 qp_st_mod_op); 2475 rte_errno = EINVAL; 2476 return -rte_errno; 2477 } 2478 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2479 if (ret) { 2480 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2481 rte_errno = errno; 2482 return -rte_errno; 2483 } 2484 return ret; 2485 } 2486 2487 struct mlx5_devx_obj * 2488 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2489 { 2490 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2491 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2492 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2493 sizeof(*couners_obj), 0, 2494 SOCKET_ID_ANY); 2495 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2496 2497 if (!couners_obj) { 2498 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2499 rte_errno = ENOMEM; 2500 return NULL; 2501 } 2502 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2503 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2504 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2505 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2506 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2507 sizeof(out)); 2508 if (!couners_obj->obj) { 2509 DEVX_DRV_LOG(ERR, out, "create virtio queue counters Obj", NULL, 2510 0); 2511 mlx5_free(couners_obj); 2512 return NULL; 2513 } 2514 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2515 return couners_obj; 2516 } 2517 2518 int 2519 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2520 struct mlx5_devx_virtio_q_couners_attr *attr) 2521 { 2522 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2523 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2524 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2525 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2526 virtio_q_counters); 2527 int ret; 2528 2529 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2530 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2531 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2532 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2533 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2534 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2535 sizeof(out)); 2536 if (ret) { 2537 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2538 rte_errno = errno; 2539 return -errno; 2540 } 2541 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2542 received_desc); 2543 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2544 completed_desc); 2545 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2546 error_cqes); 2547 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2548 bad_desc_errors); 2549 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2550 exceed_max_chain); 2551 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2552 invalid_buffer); 2553 return ret; 2554 } 2555 2556 /** 2557 * Create general object of type FLOW_HIT_ASO using DevX API. 2558 * 2559 * @param[in] ctx 2560 * Context returned from mlx5 open_device() glue function. 2561 * @param [in] pd 2562 * PD value to associate the FLOW_HIT_ASO object with. 2563 * 2564 * @return 2565 * The DevX object created, NULL otherwise and rte_errno is set. 2566 */ 2567 struct mlx5_devx_obj * 2568 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2569 { 2570 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2571 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2572 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2573 void *ptr = NULL; 2574 2575 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2576 0, SOCKET_ID_ANY); 2577 if (!flow_hit_aso_obj) { 2578 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2579 rte_errno = ENOMEM; 2580 return NULL; 2581 } 2582 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2583 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2584 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2585 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2586 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2587 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2588 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2589 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2590 out, sizeof(out)); 2591 if (!flow_hit_aso_obj->obj) { 2592 DEVX_DRV_LOG(ERR, out, "create FLOW_HIT_ASO", NULL, 0); 2593 mlx5_free(flow_hit_aso_obj); 2594 return NULL; 2595 } 2596 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2597 return flow_hit_aso_obj; 2598 } 2599 2600 /* 2601 * Create PD using DevX API. 2602 * 2603 * @param[in] ctx 2604 * Context returned from mlx5 open_device() glue function. 2605 * 2606 * @return 2607 * The DevX object created, NULL otherwise and rte_errno is set. 2608 */ 2609 struct mlx5_devx_obj * 2610 mlx5_devx_cmd_alloc_pd(void *ctx) 2611 { 2612 struct mlx5_devx_obj *ppd = 2613 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2614 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2615 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2616 2617 if (!ppd) { 2618 DRV_LOG(ERR, "Failed to allocate PD data."); 2619 rte_errno = ENOMEM; 2620 return NULL; 2621 } 2622 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2623 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2624 out, sizeof(out)); 2625 if (!ppd->obj) { 2626 mlx5_free(ppd); 2627 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2628 rte_errno = errno; 2629 return NULL; 2630 } 2631 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2632 return ppd; 2633 } 2634 2635 /** 2636 * Create general object of type FLOW_METER_ASO using DevX API. 2637 * 2638 * @param[in] ctx 2639 * Context returned from mlx5 open_device() glue function. 2640 * @param [in] pd 2641 * PD value to associate the FLOW_METER_ASO object with. 2642 * @param [in] log_obj_size 2643 * log_obj_size define to allocate number of 2 * meters 2644 * in one FLOW_METER_ASO object. 2645 * 2646 * @return 2647 * The DevX object created, NULL otherwise and rte_errno is set. 2648 */ 2649 struct mlx5_devx_obj * 2650 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2651 uint32_t log_obj_size) 2652 { 2653 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2654 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2655 struct mlx5_devx_obj *flow_meter_aso_obj; 2656 void *ptr; 2657 2658 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2659 sizeof(*flow_meter_aso_obj), 2660 0, SOCKET_ID_ANY); 2661 if (!flow_meter_aso_obj) { 2662 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2663 rte_errno = ENOMEM; 2664 return NULL; 2665 } 2666 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2667 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2668 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2669 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2670 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2671 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2672 log_obj_size); 2673 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2674 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2675 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2676 ctx, in, sizeof(in), 2677 out, sizeof(out)); 2678 if (!flow_meter_aso_obj->obj) { 2679 DEVX_DRV_LOG(ERR, out, "create FLOW_METTER_ASO", NULL, 0); 2680 mlx5_free(flow_meter_aso_obj); 2681 return NULL; 2682 } 2683 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2684 out, obj_id); 2685 return flow_meter_aso_obj; 2686 } 2687 2688 /* 2689 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2690 * 2691 * @param[in] ctx 2692 * Context returned from mlx5 open_device() glue function. 2693 * @param [in] pd 2694 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2695 * @param [in] log_obj_size 2696 * log_obj_size to allocate its power of 2 * objects 2697 * in one CONN_TRACK_OFFLOAD bulk allocation. 2698 * 2699 * @return 2700 * The DevX object created, NULL otherwise and rte_errno is set. 2701 */ 2702 struct mlx5_devx_obj * 2703 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2704 uint32_t log_obj_size) 2705 { 2706 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2707 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2708 struct mlx5_devx_obj *ct_aso_obj; 2709 void *ptr; 2710 2711 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2712 0, SOCKET_ID_ANY); 2713 if (!ct_aso_obj) { 2714 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2715 rte_errno = ENOMEM; 2716 return NULL; 2717 } 2718 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2719 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2720 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2721 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2722 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2723 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2724 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2725 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2726 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2727 out, sizeof(out)); 2728 if (!ct_aso_obj->obj) { 2729 DEVX_DRV_LOG(ERR, out, "create CONN_TRACK_OFFLOAD", NULL, 0); 2730 mlx5_free(ct_aso_obj); 2731 return NULL; 2732 } 2733 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2734 return ct_aso_obj; 2735 } 2736 2737 /** 2738 * Create general object of type GENEVE TLV option using DevX API. 2739 * 2740 * @param[in] ctx 2741 * Context returned from mlx5 open_device() glue function. 2742 * @param [in] class 2743 * TLV option variable value of class 2744 * @param [in] type 2745 * TLV option variable value of type 2746 * @param [in] len 2747 * TLV option variable value of len 2748 * 2749 * @return 2750 * The DevX object created, NULL otherwise and rte_errno is set. 2751 */ 2752 struct mlx5_devx_obj * 2753 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2754 uint16_t class, uint8_t type, uint8_t len) 2755 { 2756 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2757 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2758 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2759 sizeof(*geneve_tlv_opt_obj), 2760 0, SOCKET_ID_ANY); 2761 2762 if (!geneve_tlv_opt_obj) { 2763 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2764 rte_errno = ENOMEM; 2765 return NULL; 2766 } 2767 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2768 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2769 geneve_tlv_opt); 2770 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2771 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2772 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2773 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2774 MLX5_SET(geneve_tlv_option, opt, option_class, 2775 rte_be_to_cpu_16(class)); 2776 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2777 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2778 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2779 sizeof(in), out, sizeof(out)); 2780 if (!geneve_tlv_opt_obj->obj) { 2781 DEVX_DRV_LOG(ERR, out, "create GENEVE TLV", NULL, 0); 2782 mlx5_free(geneve_tlv_opt_obj); 2783 return NULL; 2784 } 2785 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2786 return geneve_tlv_opt_obj; 2787 } 2788 2789 int 2790 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2791 { 2792 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2793 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2794 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2795 int rc; 2796 void *rq_ctx; 2797 2798 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2799 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2800 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2801 if (rc) { 2802 rte_errno = errno; 2803 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2804 "rc = %d, errno = %d.", rc, errno); 2805 return -rc; 2806 }; 2807 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2808 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2809 return 0; 2810 #else 2811 (void)wq; 2812 (void)counter_set_id; 2813 return -ENOTSUP; 2814 #endif 2815 } 2816 2817 /* 2818 * Allocate queue counters via devx interface. 2819 * 2820 * @param[in] ctx 2821 * Context returned from mlx5 open_device() glue function. 2822 * 2823 * @return 2824 * Pointer to counter object on success, a NULL value otherwise and 2825 * rte_errno is set. 2826 */ 2827 struct mlx5_devx_obj * 2828 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2829 { 2830 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2831 SOCKET_ID_ANY); 2832 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2833 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2834 2835 if (!dcs) { 2836 rte_errno = ENOMEM; 2837 return NULL; 2838 } 2839 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2840 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2841 sizeof(out)); 2842 if (!dcs->obj) { 2843 DEVX_DRV_LOG(DEBUG, out, "create q counter set", NULL, 0); 2844 mlx5_free(dcs); 2845 return NULL; 2846 } 2847 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2848 return dcs; 2849 } 2850 2851 /** 2852 * Query queue counters values. 2853 * 2854 * @param[in] dcs 2855 * devx object of the queue counter set. 2856 * @param[in] clear 2857 * Whether hardware should clear the counters after the query or not. 2858 * @param[out] out_of_buffers 2859 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2860 * 2861 * @return 2862 * 0 on success, a negative value otherwise. 2863 */ 2864 int 2865 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2866 uint32_t *out_of_buffers) 2867 { 2868 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2869 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2870 int rc; 2871 2872 MLX5_SET(query_q_counter_in, in, opcode, 2873 MLX5_CMD_OP_QUERY_Q_COUNTER); 2874 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2875 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2876 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2877 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2878 sizeof(out)); 2879 if (rc) { 2880 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2881 rte_errno = rc; 2882 return -rc; 2883 } 2884 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2885 return 0; 2886 } 2887 2888 /** 2889 * Create general object of type DEK using DevX API. 2890 * 2891 * @param[in] ctx 2892 * Context returned from mlx5 open_device() glue function. 2893 * @param [in] attr 2894 * Pointer to DEK attributes structure. 2895 * 2896 * @return 2897 * The DevX object created, NULL otherwise and rte_errno is set. 2898 */ 2899 struct mlx5_devx_obj * 2900 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2901 { 2902 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2903 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2904 struct mlx5_devx_obj *dek_obj = NULL; 2905 void *ptr = NULL, *key_addr = NULL; 2906 2907 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2908 0, SOCKET_ID_ANY); 2909 if (dek_obj == NULL) { 2910 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2911 rte_errno = ENOMEM; 2912 return NULL; 2913 } 2914 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2915 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2916 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2917 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2918 MLX5_GENERAL_OBJ_TYPE_DEK); 2919 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2920 MLX5_SET(dek, ptr, key_size, attr->key_size); 2921 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2922 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2923 MLX5_SET(dek, ptr, pd, attr->pd); 2924 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2925 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2926 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2927 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2928 out, sizeof(out)); 2929 if (dek_obj->obj == NULL) { 2930 DEVX_DRV_LOG(ERR, out, "create DEK", NULL, 0); 2931 mlx5_free(dek_obj); 2932 return NULL; 2933 } 2934 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2935 return dek_obj; 2936 } 2937 2938 /** 2939 * Create general object of type IMPORT_KEK using DevX API. 2940 * 2941 * @param[in] ctx 2942 * Context returned from mlx5 open_device() glue function. 2943 * @param [in] attr 2944 * Pointer to IMPORT_KEK attributes structure. 2945 * 2946 * @return 2947 * The DevX object created, NULL otherwise and rte_errno is set. 2948 */ 2949 struct mlx5_devx_obj * 2950 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 2951 struct mlx5_devx_import_kek_attr *attr) 2952 { 2953 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 2954 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2955 struct mlx5_devx_obj *import_kek_obj = NULL; 2956 void *ptr = NULL, *key_addr = NULL; 2957 2958 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 2959 0, SOCKET_ID_ANY); 2960 if (import_kek_obj == NULL) { 2961 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 2962 rte_errno = ENOMEM; 2963 return NULL; 2964 } 2965 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 2966 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2967 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2968 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2969 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 2970 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 2971 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 2972 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 2973 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2974 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2975 out, sizeof(out)); 2976 if (import_kek_obj->obj == NULL) { 2977 DEVX_DRV_LOG(ERR, out, "create IMPORT_KEK", NULL, 0); 2978 mlx5_free(import_kek_obj); 2979 return NULL; 2980 } 2981 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2982 return import_kek_obj; 2983 } 2984 2985 /** 2986 * Create general object of type CREDENTIAL using DevX API. 2987 * 2988 * @param[in] ctx 2989 * Context returned from mlx5 open_device() glue function. 2990 * @param [in] attr 2991 * Pointer to CREDENTIAL attributes structure. 2992 * 2993 * @return 2994 * The DevX object created, NULL otherwise and rte_errno is set. 2995 */ 2996 struct mlx5_devx_obj * 2997 mlx5_devx_cmd_create_credential_obj(void *ctx, 2998 struct mlx5_devx_credential_attr *attr) 2999 { 3000 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 3001 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3002 struct mlx5_devx_obj *credential_obj = NULL; 3003 void *ptr = NULL, *credential_addr = NULL; 3004 3005 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 3006 0, SOCKET_ID_ANY); 3007 if (credential_obj == NULL) { 3008 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 3009 rte_errno = ENOMEM; 3010 return NULL; 3011 } 3012 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 3013 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3014 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3015 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3016 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 3017 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 3018 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 3019 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 3020 memcpy(credential_addr, (void *)(attr->credential), 3021 MLX5_CRYPTO_CREDENTIAL_SIZE); 3022 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3023 out, sizeof(out)); 3024 if (credential_obj->obj == NULL) { 3025 DEVX_DRV_LOG(ERR, out, "create CREDENTIAL", NULL, 0); 3026 mlx5_free(credential_obj); 3027 return NULL; 3028 } 3029 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3030 return credential_obj; 3031 } 3032 3033 /** 3034 * Create general object of type CRYPTO_LOGIN using DevX API. 3035 * 3036 * @param[in] ctx 3037 * Context returned from mlx5 open_device() glue function. 3038 * @param [in] attr 3039 * Pointer to CRYPTO_LOGIN attributes structure. 3040 * 3041 * @return 3042 * The DevX object created, NULL otherwise and rte_errno is set. 3043 */ 3044 struct mlx5_devx_obj * 3045 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 3046 struct mlx5_devx_crypto_login_attr *attr) 3047 { 3048 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 3049 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3050 struct mlx5_devx_obj *crypto_login_obj = NULL; 3051 void *ptr = NULL, *credential_addr = NULL; 3052 3053 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 3054 0, SOCKET_ID_ANY); 3055 if (crypto_login_obj == NULL) { 3056 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 3057 rte_errno = ENOMEM; 3058 return NULL; 3059 } 3060 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 3061 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3062 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3063 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3064 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 3065 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 3066 MLX5_SET(crypto_login, ptr, credential_pointer, 3067 attr->credential_pointer); 3068 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 3069 attr->session_import_kek_ptr); 3070 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 3071 memcpy(credential_addr, (void *)(attr->credential), 3072 MLX5_CRYPTO_CREDENTIAL_SIZE); 3073 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3074 out, sizeof(out)); 3075 if (crypto_login_obj->obj == NULL) { 3076 DEVX_DRV_LOG(ERR, out, "create CRYPTO_LOGIN", NULL, 0); 3077 mlx5_free(crypto_login_obj); 3078 return NULL; 3079 } 3080 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3081 return crypto_login_obj; 3082 } 3083 3084 /** 3085 * Query LAG context. 3086 * 3087 * @param[in] ctx 3088 * Pointer to ibv_context, returned from mlx5dv_open_device. 3089 * @param[out] lag_ctx 3090 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 3091 * 3092 * @return 3093 * 0 on success, a negative value otherwise. 3094 */ 3095 int 3096 mlx5_devx_cmd_query_lag(void *ctx, 3097 struct mlx5_devx_lag_context *lag_ctx) 3098 { 3099 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 3100 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 3101 void *lctx; 3102 int rc; 3103 3104 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 3105 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 3106 if (rc) 3107 goto error; 3108 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 3109 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 3110 fdb_selection_mode); 3111 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 3112 port_select_mode); 3113 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 3114 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 3115 tx_remap_affinity_2); 3116 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 3117 tx_remap_affinity_1); 3118 return 0; 3119 error: 3120 rc = (rc > 0) ? -rc : rc; 3121 return rc; 3122 } 3123