1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /** 17 * Perform read access to the registers. Reads data from register 18 * and writes ones to the specified buffer. 19 * 20 * @param[in] ctx 21 * Context returned from mlx5 open_device() glue function. 22 * @param[in] reg_id 23 * Register identifier according to the PRM. 24 * @param[in] arg 25 * Register access auxiliary parameter according to the PRM. 26 * @param[out] data 27 * Pointer to the buffer to store read data. 28 * @param[in] dw_cnt 29 * Buffer size in double words. 30 * 31 * @return 32 * 0 on success, a negative value otherwise. 33 */ 34 int 35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 36 uint32_t *data, uint32_t dw_cnt) 37 { 38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 41 int status, rc; 42 43 MLX5_ASSERT(data && dw_cnt); 44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 46 DRV_LOG(ERR, "Not enough buffer for register read data"); 47 return -1; 48 } 49 MLX5_SET(access_register_in, in, opcode, 50 MLX5_CMD_OP_ACCESS_REGISTER_USER); 51 MLX5_SET(access_register_in, in, op_mod, 52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 53 MLX5_SET(access_register_in, in, register_id, reg_id); 54 MLX5_SET(access_register_in, in, argument, arg); 55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 56 MLX5_ST_SZ_BYTES(access_register_out) + 57 sizeof(uint32_t) * dw_cnt); 58 if (rc) 59 goto error; 60 status = MLX5_GET(access_register_out, out, status); 61 if (status) { 62 int syndrome = MLX5_GET(access_register_out, out, syndrome); 63 64 DRV_LOG(DEBUG, "Failed to read access NIC register 0x%X, " 65 "status %x, syndrome = %x", 66 reg_id, status, syndrome); 67 return -1; 68 } 69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 70 dw_cnt * sizeof(uint32_t)); 71 return 0; 72 error: 73 rc = (rc > 0) ? -rc : rc; 74 return rc; 75 } 76 77 /** 78 * Perform write access to the registers. 79 * 80 * @param[in] ctx 81 * Context returned from mlx5 open_device() glue function. 82 * @param[in] reg_id 83 * Register identifier according to the PRM. 84 * @param[in] arg 85 * Register access auxiliary parameter according to the PRM. 86 * @param[out] data 87 * Pointer to the buffer containing data to write. 88 * @param[in] dw_cnt 89 * Buffer size in double words (32bit units). 90 * 91 * @return 92 * 0 on success, a negative value otherwise. 93 */ 94 int 95 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 96 uint32_t *data, uint32_t dw_cnt) 97 { 98 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 99 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 100 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 101 int status, rc; 102 void *ptr; 103 104 MLX5_ASSERT(data && dw_cnt); 105 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 106 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 107 DRV_LOG(ERR, "Data to write exceeds max size"); 108 return -1; 109 } 110 MLX5_SET(access_register_in, in, opcode, 111 MLX5_CMD_OP_ACCESS_REGISTER_USER); 112 MLX5_SET(access_register_in, in, op_mod, 113 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 114 MLX5_SET(access_register_in, in, register_id, reg_id); 115 MLX5_SET(access_register_in, in, argument, arg); 116 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 117 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 118 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 119 120 rc = mlx5_glue->devx_general_cmd(ctx, in, 121 MLX5_ST_SZ_BYTES(access_register_in) + 122 dw_cnt * sizeof(uint32_t), 123 out, sizeof(out)); 124 if (rc) 125 goto error; 126 status = MLX5_GET(access_register_out, out, status); 127 if (status) { 128 int syndrome = MLX5_GET(access_register_out, out, syndrome); 129 130 DRV_LOG(DEBUG, "Failed to write access NIC register 0x%X, " 131 "status %x, syndrome = %x", 132 reg_id, status, syndrome); 133 return -1; 134 } 135 return 0; 136 error: 137 rc = (rc > 0) ? -rc : rc; 138 return rc; 139 } 140 141 /** 142 * Allocate flow counters via devx interface. 143 * 144 * @param[in] ctx 145 * Context returned from mlx5 open_device() glue function. 146 * @param dcs 147 * Pointer to counters properties structure to be filled by the routine. 148 * @param bulk_n_128 149 * Bulk counter numbers in 128 counters units. 150 * 151 * @return 152 * Pointer to counter object on success, a negative value otherwise and 153 * rte_errno is set. 154 */ 155 struct mlx5_devx_obj * 156 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 157 { 158 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 159 0, SOCKET_ID_ANY); 160 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 161 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 162 163 if (!dcs) { 164 rte_errno = ENOMEM; 165 return NULL; 166 } 167 MLX5_SET(alloc_flow_counter_in, in, opcode, 168 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 169 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 170 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 171 sizeof(in), out, sizeof(out)); 172 if (!dcs->obj) { 173 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 174 rte_errno = errno; 175 mlx5_free(dcs); 176 return NULL; 177 } 178 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 179 return dcs; 180 } 181 182 /** 183 * Query flow counters values. 184 * 185 * @param[in] dcs 186 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 187 * @param[in] clear 188 * Whether hardware should clear the counters after the query or not. 189 * @param[in] n_counters 190 * 0 in case of 1 counter to read, otherwise the counter number to read. 191 * @param pkts 192 * The number of packets that matched the flow. 193 * @param bytes 194 * The number of bytes that matched the flow. 195 * @param mkey 196 * The mkey key for batch query. 197 * @param addr 198 * The address in the mkey range for batch query. 199 * @param cmd_comp 200 * The completion object for asynchronous batch query. 201 * @param async_id 202 * The ID to be returned in the asynchronous batch query response. 203 * 204 * @return 205 * 0 on success, a negative value otherwise. 206 */ 207 int 208 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 209 int clear, uint32_t n_counters, 210 uint64_t *pkts, uint64_t *bytes, 211 uint32_t mkey, void *addr, 212 void *cmd_comp, 213 uint64_t async_id) 214 { 215 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 216 MLX5_ST_SZ_BYTES(traffic_counter); 217 uint32_t out[out_len]; 218 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 219 void *stats; 220 int rc; 221 222 MLX5_SET(query_flow_counter_in, in, opcode, 223 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 224 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 225 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 226 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 227 228 if (n_counters) { 229 MLX5_SET(query_flow_counter_in, in, num_of_counters, 230 n_counters); 231 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 232 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 233 MLX5_SET64(query_flow_counter_in, in, address, 234 (uint64_t)(uintptr_t)addr); 235 } 236 if (!cmd_comp) 237 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 238 out_len); 239 else 240 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 241 out_len, async_id, 242 cmd_comp); 243 if (rc) { 244 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 245 rte_errno = rc; 246 return -rc; 247 } 248 if (!n_counters) { 249 stats = MLX5_ADDR_OF(query_flow_counter_out, 250 out, flow_statistics); 251 *pkts = MLX5_GET64(traffic_counter, stats, packets); 252 *bytes = MLX5_GET64(traffic_counter, stats, octets); 253 } 254 return 0; 255 } 256 257 /** 258 * Create a new mkey. 259 * 260 * @param[in] ctx 261 * Context returned from mlx5 open_device() glue function. 262 * @param[in] attr 263 * Attributes of the requested mkey. 264 * 265 * @return 266 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 267 * is set. 268 */ 269 struct mlx5_devx_obj * 270 mlx5_devx_cmd_mkey_create(void *ctx, 271 struct mlx5_devx_mkey_attr *attr) 272 { 273 struct mlx5_klm *klm_array = attr->klm_array; 274 int klm_num = attr->klm_num; 275 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 276 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 277 uint32_t in[in_size_dw]; 278 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 279 void *mkc; 280 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 281 0, SOCKET_ID_ANY); 282 size_t pgsize; 283 uint32_t translation_size; 284 285 if (!mkey) { 286 rte_errno = ENOMEM; 287 return NULL; 288 } 289 memset(in, 0, in_size_dw * 4); 290 pgsize = rte_mem_page_size(); 291 if (pgsize == (size_t)-1) { 292 mlx5_free(mkey); 293 DRV_LOG(ERR, "Failed to get page size"); 294 rte_errno = ENOMEM; 295 return NULL; 296 } 297 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 298 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 299 if (klm_num > 0) { 300 int i; 301 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 302 klm_pas_mtt); 303 translation_size = RTE_ALIGN(klm_num, 4); 304 for (i = 0; i < klm_num; i++) { 305 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 306 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 307 MLX5_SET64(klm, klm, address, klm_array[i].address); 308 klm += MLX5_ST_SZ_BYTES(klm); 309 } 310 for (; i < (int)translation_size; i++) { 311 MLX5_SET(klm, klm, mkey, 0x0); 312 MLX5_SET64(klm, klm, address, 0x0); 313 klm += MLX5_ST_SZ_BYTES(klm); 314 } 315 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 316 MLX5_MKC_ACCESS_MODE_KLM_FBS : 317 MLX5_MKC_ACCESS_MODE_KLM); 318 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 319 } else { 320 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 321 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 322 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 323 } 324 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 325 translation_size); 326 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 327 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 328 MLX5_SET(mkc, mkc, lw, 0x1); 329 MLX5_SET(mkc, mkc, lr, 0x1); 330 if (attr->set_remote_rw) { 331 MLX5_SET(mkc, mkc, rw, 0x1); 332 MLX5_SET(mkc, mkc, rr, 0x1); 333 } 334 MLX5_SET(mkc, mkc, qpn, 0xffffff); 335 MLX5_SET(mkc, mkc, pd, attr->pd); 336 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 337 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 338 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 339 MLX5_SET(mkc, mkc, relaxed_ordering_write, 340 attr->relaxed_ordering_write); 341 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 342 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 343 MLX5_SET64(mkc, mkc, len, attr->size); 344 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 345 if (attr->crypto_en) { 346 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 347 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 348 } 349 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 350 sizeof(out)); 351 if (!mkey->obj) { 352 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d", 353 klm_num ? "an in" : "a ", errno); 354 rte_errno = errno; 355 mlx5_free(mkey); 356 return NULL; 357 } 358 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 359 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 360 return mkey; 361 } 362 363 /** 364 * Get status of devx command response. 365 * Mainly used for asynchronous commands. 366 * 367 * @param[in] out 368 * The out response buffer. 369 * 370 * @return 371 * 0 on success, non-zero value otherwise. 372 */ 373 int 374 mlx5_devx_get_out_command_status(void *out) 375 { 376 int status; 377 378 if (!out) 379 return -EINVAL; 380 status = MLX5_GET(query_flow_counter_out, out, status); 381 if (status) { 382 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 383 384 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 385 syndrome); 386 } 387 return status; 388 } 389 390 /** 391 * Destroy any object allocated by a Devx API. 392 * 393 * @param[in] obj 394 * Pointer to a general object. 395 * 396 * @return 397 * 0 on success, a negative value otherwise. 398 */ 399 int 400 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 401 { 402 int ret; 403 404 if (!obj) 405 return 0; 406 ret = mlx5_glue->devx_obj_destroy(obj->obj); 407 mlx5_free(obj); 408 return ret; 409 } 410 411 /** 412 * Query NIC vport context. 413 * Fills minimal inline attribute. 414 * 415 * @param[in] ctx 416 * ibv contexts returned from mlx5dv_open_device. 417 * @param[in] vport 418 * vport index 419 * @param[out] attr 420 * Attributes device values. 421 * 422 * @return 423 * 0 on success, a negative value otherwise. 424 */ 425 static int 426 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 427 unsigned int vport, 428 struct mlx5_hca_attr *attr) 429 { 430 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 431 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 432 void *vctx; 433 int status, syndrome, rc; 434 435 /* Query NIC vport context to determine inline mode. */ 436 MLX5_SET(query_nic_vport_context_in, in, opcode, 437 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 438 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 439 if (vport) 440 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 441 rc = mlx5_glue->devx_general_cmd(ctx, 442 in, sizeof(in), 443 out, sizeof(out)); 444 if (rc) 445 goto error; 446 status = MLX5_GET(query_nic_vport_context_out, out, status); 447 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 448 if (status) { 449 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 450 "status %x, syndrome = %x", status, syndrome); 451 return -1; 452 } 453 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 454 nic_vport_context); 455 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 456 min_wqe_inline_mode); 457 return 0; 458 error: 459 rc = (rc > 0) ? -rc : rc; 460 return rc; 461 } 462 463 /** 464 * Query NIC vDPA attributes. 465 * 466 * @param[in] ctx 467 * Context returned from mlx5 open_device() glue function. 468 * @param[out] vdpa_attr 469 * vDPA Attributes structure to fill. 470 */ 471 static void 472 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 473 struct mlx5_hca_vdpa_attr *vdpa_attr) 474 { 475 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 476 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 477 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 478 int status, syndrome, rc; 479 480 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 481 MLX5_SET(query_hca_cap_in, in, op_mod, 482 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 483 MLX5_HCA_CAP_OPMOD_GET_CUR); 484 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 485 status = MLX5_GET(query_hca_cap_out, out, status); 486 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 487 if (rc || status) { 488 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities," 489 " status %x, syndrome = %x", status, syndrome); 490 vdpa_attr->valid = 0; 491 } else { 492 vdpa_attr->valid = 1; 493 vdpa_attr->desc_tunnel_offload_type = 494 MLX5_GET(virtio_emulation_cap, hcattr, 495 desc_tunnel_offload_type); 496 vdpa_attr->eth_frame_offload_type = 497 MLX5_GET(virtio_emulation_cap, hcattr, 498 eth_frame_offload_type); 499 vdpa_attr->virtio_version_1_0 = 500 MLX5_GET(virtio_emulation_cap, hcattr, 501 virtio_version_1_0); 502 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 503 tso_ipv4); 504 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 505 tso_ipv6); 506 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 507 tx_csum); 508 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 509 rx_csum); 510 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 511 event_mode); 512 vdpa_attr->virtio_queue_type = 513 MLX5_GET(virtio_emulation_cap, hcattr, 514 virtio_queue_type); 515 vdpa_attr->log_doorbell_stride = 516 MLX5_GET(virtio_emulation_cap, hcattr, 517 log_doorbell_stride); 518 vdpa_attr->log_doorbell_bar_size = 519 MLX5_GET(virtio_emulation_cap, hcattr, 520 log_doorbell_bar_size); 521 vdpa_attr->doorbell_bar_offset = 522 MLX5_GET64(virtio_emulation_cap, hcattr, 523 doorbell_bar_offset); 524 vdpa_attr->max_num_virtio_queues = 525 MLX5_GET(virtio_emulation_cap, hcattr, 526 max_num_virtio_queues); 527 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 528 umem_1_buffer_param_a); 529 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 530 umem_1_buffer_param_b); 531 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 532 umem_2_buffer_param_a); 533 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 534 umem_2_buffer_param_b); 535 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 536 umem_3_buffer_param_a); 537 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 538 umem_3_buffer_param_b); 539 } 540 } 541 542 int 543 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 544 uint32_t ids[], uint32_t num) 545 { 546 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 547 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 548 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 549 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 550 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 551 int ret; 552 uint32_t idx = 0; 553 uint32_t i; 554 555 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 556 rte_errno = EINVAL; 557 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 558 return -rte_errno; 559 } 560 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 561 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 562 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 563 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 564 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 565 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 566 out, sizeof(out)); 567 if (ret) { 568 rte_errno = ret; 569 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 570 (void *)flex_obj); 571 return -rte_errno; 572 } 573 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 574 void *s_off = (void *)((char *)sample + i * 575 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 576 uint32_t en; 577 578 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 579 flow_match_sample_en); 580 if (!en) 581 continue; 582 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 583 flow_match_sample_field_id); 584 } 585 if (num != idx) { 586 rte_errno = EINVAL; 587 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 588 return -rte_errno; 589 } 590 return ret; 591 } 592 593 594 struct mlx5_devx_obj * 595 mlx5_devx_cmd_create_flex_parser(void *ctx, 596 struct mlx5_devx_graph_node_attr *data) 597 { 598 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 599 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 600 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 601 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 602 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 603 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 604 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 605 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 606 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 607 uint32_t i; 608 609 if (!parse_flex_obj) { 610 DRV_LOG(ERR, "Failed to allocate flex parser data."); 611 rte_errno = ENOMEM; 612 return NULL; 613 } 614 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 615 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 616 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 617 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 618 MLX5_SET(parse_graph_flex, flex, header_length_mode, 619 data->header_length_mode); 620 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 621 data->header_length_base_value); 622 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 623 data->header_length_field_offset); 624 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 625 data->header_length_field_shift); 626 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 627 data->header_length_field_mask); 628 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 629 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 630 void *s_off = (void *)((char *)sample + i * 631 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 632 633 if (!s->flow_match_sample_en) 634 continue; 635 MLX5_SET(parse_graph_flow_match_sample, s_off, 636 flow_match_sample_en, !!s->flow_match_sample_en); 637 MLX5_SET(parse_graph_flow_match_sample, s_off, 638 flow_match_sample_field_offset, 639 s->flow_match_sample_field_offset); 640 MLX5_SET(parse_graph_flow_match_sample, s_off, 641 flow_match_sample_offset_mode, 642 s->flow_match_sample_offset_mode); 643 MLX5_SET(parse_graph_flow_match_sample, s_off, 644 flow_match_sample_field_offset_mask, 645 s->flow_match_sample_field_offset_mask); 646 MLX5_SET(parse_graph_flow_match_sample, s_off, 647 flow_match_sample_field_offset_shift, 648 s->flow_match_sample_field_offset_shift); 649 MLX5_SET(parse_graph_flow_match_sample, s_off, 650 flow_match_sample_field_base_offset, 651 s->flow_match_sample_field_base_offset); 652 MLX5_SET(parse_graph_flow_match_sample, s_off, 653 flow_match_sample_tunnel_mode, 654 s->flow_match_sample_tunnel_mode); 655 } 656 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 657 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 658 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 659 void *in_off = (void *)((char *)in_arc + i * 660 MLX5_ST_SZ_BYTES(parse_graph_arc)); 661 void *out_off = (void *)((char *)out_arc + i * 662 MLX5_ST_SZ_BYTES(parse_graph_arc)); 663 664 if (ia->arc_parse_graph_node != 0) { 665 MLX5_SET(parse_graph_arc, in_off, 666 compare_condition_value, 667 ia->compare_condition_value); 668 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 669 ia->start_inner_tunnel); 670 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 671 ia->arc_parse_graph_node); 672 MLX5_SET(parse_graph_arc, in_off, 673 parse_graph_node_handle, 674 ia->parse_graph_node_handle); 675 } 676 if (oa->arc_parse_graph_node != 0) { 677 MLX5_SET(parse_graph_arc, out_off, 678 compare_condition_value, 679 oa->compare_condition_value); 680 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 681 oa->start_inner_tunnel); 682 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 683 oa->arc_parse_graph_node); 684 MLX5_SET(parse_graph_arc, out_off, 685 parse_graph_node_handle, 686 oa->parse_graph_node_handle); 687 } 688 } 689 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 690 out, sizeof(out)); 691 if (!parse_flex_obj->obj) { 692 rte_errno = errno; 693 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 694 "by using DevX."); 695 mlx5_free(parse_flex_obj); 696 return NULL; 697 } 698 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 699 return parse_flex_obj; 700 } 701 702 static int 703 mlx5_devx_query_pkt_integrity_match(void *hcattr) 704 { 705 return MLX5_GET(flow_table_nic_cap, hcattr, 706 ft_field_support_2_nic_receive.inner_l3_ok) && 707 MLX5_GET(flow_table_nic_cap, hcattr, 708 ft_field_support_2_nic_receive.inner_l4_ok) && 709 MLX5_GET(flow_table_nic_cap, hcattr, 710 ft_field_support_2_nic_receive.outer_l3_ok) && 711 MLX5_GET(flow_table_nic_cap, hcattr, 712 ft_field_support_2_nic_receive.outer_l4_ok) && 713 MLX5_GET(flow_table_nic_cap, hcattr, 714 ft_field_support_2_nic_receive 715 .inner_ipv4_checksum_ok) && 716 MLX5_GET(flow_table_nic_cap, hcattr, 717 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 718 MLX5_GET(flow_table_nic_cap, hcattr, 719 ft_field_support_2_nic_receive 720 .outer_ipv4_checksum_ok) && 721 MLX5_GET(flow_table_nic_cap, hcattr, 722 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 723 } 724 725 /** 726 * Query HCA attributes. 727 * Using those attributes we can check on run time if the device 728 * is having the required capabilities. 729 * 730 * @param[in] ctx 731 * Context returned from mlx5 open_device() glue function. 732 * @param[out] attr 733 * Attributes device values. 734 * 735 * @return 736 * 0 on success, a negative value otherwise. 737 */ 738 int 739 mlx5_devx_cmd_query_hca_attr(void *ctx, 740 struct mlx5_hca_attr *attr) 741 { 742 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 743 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 744 void *hcattr; 745 int status, syndrome, rc, i; 746 uint64_t general_obj_types_supported = 0; 747 748 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 749 MLX5_SET(query_hca_cap_in, in, op_mod, 750 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 751 MLX5_HCA_CAP_OPMOD_GET_CUR); 752 753 rc = mlx5_glue->devx_general_cmd(ctx, 754 in, sizeof(in), out, sizeof(out)); 755 if (rc) 756 goto error; 757 status = MLX5_GET(query_hca_cap_out, out, status); 758 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 759 if (status) { 760 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 761 "status %x, syndrome = %x", status, syndrome); 762 return -1; 763 } 764 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 765 attr->flow_counter_bulk_alloc_bitmap = 766 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 767 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 768 flow_counters_dump); 769 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 770 log_max_rqt_size); 771 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 772 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 773 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 774 log_max_hairpin_queues); 775 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 776 log_max_hairpin_wq_data_sz); 777 attr->log_max_hairpin_num_packets = MLX5_GET 778 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 779 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 780 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 781 relaxed_ordering_write); 782 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 783 relaxed_ordering_read); 784 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 785 access_register_user); 786 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 787 eth_net_offloads); 788 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 789 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 790 flex_parser_protocols); 791 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 792 max_geneve_tlv_options); 793 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 794 max_geneve_tlv_option_data_len); 795 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 796 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 797 general_obj_types) & 798 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 799 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 800 general_obj_types) & 801 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 802 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 803 general_obj_types) & 804 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 805 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 806 general_obj_types) & 807 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 808 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 809 wqe_index_ignore_cap); 810 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 811 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 812 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 813 log_max_static_sq_wq); 814 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 815 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 816 device_frequency_khz); 817 attr->scatter_fcs_w_decap_disable = 818 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 819 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 820 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 821 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 822 attr->steering_format_version = 823 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 824 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 825 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 826 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 827 regexp_num_of_engines); 828 /* Read the general_obj_types bitmap and extract the relevant bits. */ 829 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 830 general_obj_types); 831 attr->vdpa.valid = !!(general_obj_types_supported & 832 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 833 attr->vdpa.queue_counters_valid = 834 !!(general_obj_types_supported & 835 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 836 attr->parse_graph_flex_node = 837 !!(general_obj_types_supported & 838 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 839 attr->flow_hit_aso = !!(general_obj_types_supported & 840 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 841 attr->geneve_tlv_opt = !!(general_obj_types_supported & 842 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 843 attr->dek = !!(general_obj_types_supported & 844 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 845 attr->import_kek = !!(general_obj_types_supported & 846 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 847 attr->credential = !!(general_obj_types_supported & 848 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 849 attr->crypto_login = !!(general_obj_types_supported & 850 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 851 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 852 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 853 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 854 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 855 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 856 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 857 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 858 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 859 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 860 attr->reg_c_preserve = 861 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 862 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 863 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 864 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 865 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 866 compress_mmo_sq); 867 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 868 decompress_mmo_sq); 869 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 870 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 871 compress_mmo_qp); 872 attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 873 decompress_mmo_qp); 874 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 875 compress_min_block_size); 876 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 877 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 878 log_compress_mmo_size); 879 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 880 log_decompress_mmo_size); 881 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 882 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 883 mini_cqe_resp_flow_tag); 884 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 885 mini_cqe_resp_l3_l4_tag); 886 attr->umr_indirect_mkey_disabled = 887 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 888 attr->umr_modify_entity_size_disabled = 889 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 890 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 891 if (attr->crypto) 892 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts); 893 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 894 general_obj_types) & 895 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 896 if (attr->qos.sup) { 897 MLX5_SET(query_hca_cap_in, in, op_mod, 898 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 899 MLX5_HCA_CAP_OPMOD_GET_CUR); 900 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 901 out, sizeof(out)); 902 if (rc) 903 goto error; 904 if (status) { 905 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities," 906 " status %x, syndrome = %x", status, syndrome); 907 return -1; 908 } 909 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 910 attr->qos.flow_meter_old = 911 MLX5_GET(qos_cap, hcattr, flow_meter_old); 912 attr->qos.log_max_flow_meter = 913 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 914 attr->qos.flow_meter_reg_c_ids = 915 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 916 attr->qos.flow_meter = 917 MLX5_GET(qos_cap, hcattr, flow_meter); 918 attr->qos.packet_pacing = 919 MLX5_GET(qos_cap, hcattr, packet_pacing); 920 attr->qos.wqe_rate_pp = 921 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 922 if (attr->qos.flow_meter_aso_sup) { 923 attr->qos.log_meter_aso_granularity = 924 MLX5_GET(qos_cap, hcattr, 925 log_meter_aso_granularity); 926 attr->qos.log_meter_aso_max_alloc = 927 MLX5_GET(qos_cap, hcattr, 928 log_meter_aso_max_alloc); 929 attr->qos.log_max_num_meter_aso = 930 MLX5_GET(qos_cap, hcattr, 931 log_max_num_meter_aso); 932 } 933 } 934 if (attr->vdpa.valid) 935 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 936 if (!attr->eth_net_offloads) 937 return 0; 938 939 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 940 memset(in, 0, sizeof(in)); 941 memset(out, 0, sizeof(out)); 942 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 943 MLX5_SET(query_hca_cap_in, in, op_mod, 944 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 945 MLX5_HCA_CAP_OPMOD_GET_CUR); 946 947 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 948 if (rc) 949 goto error; 950 status = MLX5_GET(query_hca_cap_out, out, status); 951 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 952 if (status) { 953 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 954 "status %x, syndrome = %x", status, syndrome); 955 attr->log_max_ft_sampler_num = 0; 956 return -1; 957 } 958 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 959 attr->log_max_ft_sampler_num = MLX5_GET 960 (flow_table_nic_cap, hcattr, 961 flow_table_properties_nic_receive.log_max_ft_sampler_num); 962 attr->flow.tunnel_header_0_1 = MLX5_GET 963 (flow_table_nic_cap, hcattr, 964 ft_field_support_2_nic_receive.tunnel_header_0_1); 965 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 966 attr->inner_ipv4_ihl = MLX5_GET 967 (flow_table_nic_cap, hcattr, 968 ft_field_support_2_nic_receive.inner_ipv4_ihl); 969 attr->outer_ipv4_ihl = MLX5_GET 970 (flow_table_nic_cap, hcattr, 971 ft_field_support_2_nic_receive.outer_ipv4_ihl); 972 /* Query HCA offloads for Ethernet protocol. */ 973 memset(in, 0, sizeof(in)); 974 memset(out, 0, sizeof(out)); 975 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 976 MLX5_SET(query_hca_cap_in, in, op_mod, 977 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 978 MLX5_HCA_CAP_OPMOD_GET_CUR); 979 980 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 981 if (rc) { 982 attr->eth_net_offloads = 0; 983 goto error; 984 } 985 status = MLX5_GET(query_hca_cap_out, out, status); 986 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 987 if (status) { 988 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 989 "status %x, syndrome = %x", status, syndrome); 990 attr->eth_net_offloads = 0; 991 return -1; 992 } 993 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 994 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 995 hcattr, wqe_vlan_insert); 996 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 997 hcattr, csum_cap); 998 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 999 hcattr, vlan_cap); 1000 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1001 lro_cap); 1002 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1003 hcattr, max_lso_cap); 1004 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1005 hcattr, scatter_fcs); 1006 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1007 hcattr, tunnel_lro_gre); 1008 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1009 hcattr, tunnel_lro_vxlan); 1010 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1011 hcattr, swp); 1012 attr->tunnel_stateless_gre = 1013 MLX5_GET(per_protocol_networking_offload_caps, 1014 hcattr, tunnel_stateless_gre); 1015 attr->tunnel_stateless_vxlan = 1016 MLX5_GET(per_protocol_networking_offload_caps, 1017 hcattr, tunnel_stateless_vxlan); 1018 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1019 hcattr, swp_csum); 1020 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1021 hcattr, swp_lso); 1022 attr->lro_max_msg_sz_mode = MLX5_GET 1023 (per_protocol_networking_offload_caps, 1024 hcattr, lro_max_msg_sz_mode); 1025 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1026 attr->lro_timer_supported_periods[i] = 1027 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1028 lro_timer_supported_periods[i]); 1029 } 1030 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1031 hcattr, lro_min_mss_size); 1032 attr->tunnel_stateless_geneve_rx = 1033 MLX5_GET(per_protocol_networking_offload_caps, 1034 hcattr, tunnel_stateless_geneve_rx); 1035 attr->geneve_max_opt_len = 1036 MLX5_GET(per_protocol_networking_offload_caps, 1037 hcattr, max_geneve_opt_len); 1038 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1039 hcattr, wqe_inline_mode); 1040 attr->tunnel_stateless_gtp = MLX5_GET 1041 (per_protocol_networking_offload_caps, 1042 hcattr, tunnel_stateless_gtp); 1043 attr->rss_ind_tbl_cap = MLX5_GET 1044 (per_protocol_networking_offload_caps, 1045 hcattr, rss_ind_tbl_cap); 1046 /* Query HCA attribute for ROCE. */ 1047 if (attr->roce) { 1048 memset(in, 0, sizeof(in)); 1049 memset(out, 0, sizeof(out)); 1050 MLX5_SET(query_hca_cap_in, in, opcode, 1051 MLX5_CMD_OP_QUERY_HCA_CAP); 1052 MLX5_SET(query_hca_cap_in, in, op_mod, 1053 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1054 MLX5_HCA_CAP_OPMOD_GET_CUR); 1055 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 1056 out, sizeof(out)); 1057 if (rc) 1058 goto error; 1059 status = MLX5_GET(query_hca_cap_out, out, status); 1060 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 1061 if (status) { 1062 DRV_LOG(DEBUG, 1063 "Failed to query devx HCA ROCE capabilities, " 1064 "status %x, syndrome = %x", status, syndrome); 1065 return -1; 1066 } 1067 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 1068 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1069 } 1070 if (attr->eth_virt && 1071 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1072 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1073 if (rc) { 1074 attr->eth_virt = 0; 1075 goto error; 1076 } 1077 } 1078 return 0; 1079 error: 1080 rc = (rc > 0) ? -rc : rc; 1081 return rc; 1082 } 1083 1084 /** 1085 * Query TIS transport domain from QP verbs object using DevX API. 1086 * 1087 * @param[in] qp 1088 * Pointer to verbs QP returned by ibv_create_qp . 1089 * @param[in] tis_num 1090 * TIS number of TIS to query. 1091 * @param[out] tis_td 1092 * Pointer to TIS transport domain variable, to be set by the routine. 1093 * 1094 * @return 1095 * 0 on success, a negative value otherwise. 1096 */ 1097 int 1098 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1099 uint32_t *tis_td) 1100 { 1101 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1102 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1103 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1104 int rc; 1105 void *tis_ctx; 1106 1107 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1108 MLX5_SET(query_tis_in, in, tisn, tis_num); 1109 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1110 if (rc) { 1111 DRV_LOG(ERR, "Failed to query QP using DevX"); 1112 return -rc; 1113 }; 1114 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1115 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1116 return 0; 1117 #else 1118 (void)qp; 1119 (void)tis_num; 1120 (void)tis_td; 1121 return -ENOTSUP; 1122 #endif 1123 } 1124 1125 /** 1126 * Fill WQ data for DevX API command. 1127 * Utility function for use when creating DevX objects containing a WQ. 1128 * 1129 * @param[in] wq_ctx 1130 * Pointer to WQ context to fill with data. 1131 * @param [in] wq_attr 1132 * Pointer to WQ attributes structure to fill in WQ context. 1133 */ 1134 static void 1135 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1136 { 1137 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1138 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1139 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1140 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1141 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1142 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1143 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1144 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1145 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1146 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1147 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1148 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1149 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1150 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1151 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1152 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1153 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1154 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1155 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1156 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1157 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1158 wq_attr->log_hairpin_num_packets); 1159 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1160 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1161 wq_attr->single_wqe_log_num_of_strides); 1162 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1163 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1164 wq_attr->single_stride_log_num_of_bytes); 1165 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1166 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1167 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1168 } 1169 1170 /** 1171 * Create RQ using DevX API. 1172 * 1173 * @param[in] ctx 1174 * Context returned from mlx5 open_device() glue function. 1175 * @param [in] rq_attr 1176 * Pointer to create RQ attributes structure. 1177 * @param [in] socket 1178 * CPU socket ID for allocations. 1179 * 1180 * @return 1181 * The DevX object created, NULL otherwise and rte_errno is set. 1182 */ 1183 struct mlx5_devx_obj * 1184 mlx5_devx_cmd_create_rq(void *ctx, 1185 struct mlx5_devx_create_rq_attr *rq_attr, 1186 int socket) 1187 { 1188 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1189 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1190 void *rq_ctx, *wq_ctx; 1191 struct mlx5_devx_wq_attr *wq_attr; 1192 struct mlx5_devx_obj *rq = NULL; 1193 1194 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1195 if (!rq) { 1196 DRV_LOG(ERR, "Failed to allocate RQ data"); 1197 rte_errno = ENOMEM; 1198 return NULL; 1199 } 1200 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1201 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1202 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1203 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1204 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1205 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1206 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1207 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1208 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1209 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1210 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1211 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1212 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1213 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1214 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1215 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1216 wq_attr = &rq_attr->wq_attr; 1217 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1218 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1219 out, sizeof(out)); 1220 if (!rq->obj) { 1221 DRV_LOG(ERR, "Failed to create RQ using DevX"); 1222 rte_errno = errno; 1223 mlx5_free(rq); 1224 return NULL; 1225 } 1226 rq->id = MLX5_GET(create_rq_out, out, rqn); 1227 return rq; 1228 } 1229 1230 /** 1231 * Modify RQ using DevX API. 1232 * 1233 * @param[in] rq 1234 * Pointer to RQ object structure. 1235 * @param [in] rq_attr 1236 * Pointer to modify RQ attributes structure. 1237 * 1238 * @return 1239 * 0 on success, a negative errno value otherwise and rte_errno is set. 1240 */ 1241 int 1242 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1243 struct mlx5_devx_modify_rq_attr *rq_attr) 1244 { 1245 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1246 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1247 void *rq_ctx, *wq_ctx; 1248 int ret; 1249 1250 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1251 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1252 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1253 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1254 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1255 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1256 if (rq_attr->modify_bitmask & 1257 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1258 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1259 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1260 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1261 if (rq_attr->modify_bitmask & 1262 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1263 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1264 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1265 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1266 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1267 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1268 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1269 } 1270 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1271 out, sizeof(out)); 1272 if (ret) { 1273 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1274 rte_errno = errno; 1275 return -errno; 1276 } 1277 return ret; 1278 } 1279 1280 /** 1281 * Create TIR using DevX API. 1282 * 1283 * @param[in] ctx 1284 * Context returned from mlx5 open_device() glue function. 1285 * @param [in] tir_attr 1286 * Pointer to TIR attributes structure. 1287 * 1288 * @return 1289 * The DevX object created, NULL otherwise and rte_errno is set. 1290 */ 1291 struct mlx5_devx_obj * 1292 mlx5_devx_cmd_create_tir(void *ctx, 1293 struct mlx5_devx_tir_attr *tir_attr) 1294 { 1295 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1296 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1297 void *tir_ctx, *outer, *inner, *rss_key; 1298 struct mlx5_devx_obj *tir = NULL; 1299 1300 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1301 if (!tir) { 1302 DRV_LOG(ERR, "Failed to allocate TIR data"); 1303 rte_errno = ENOMEM; 1304 return NULL; 1305 } 1306 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1307 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1308 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1309 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1310 tir_attr->lro_timeout_period_usecs); 1311 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1312 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1313 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1314 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1315 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1316 tir_attr->tunneled_offload_en); 1317 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1318 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1319 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1320 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1321 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1322 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1323 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1324 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1325 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1326 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1327 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1328 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1329 tir_attr->rx_hash_field_selector_outer.selected_fields); 1330 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1331 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1332 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1333 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1334 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1335 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1336 tir_attr->rx_hash_field_selector_inner.selected_fields); 1337 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1338 out, sizeof(out)); 1339 if (!tir->obj) { 1340 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1341 rte_errno = errno; 1342 mlx5_free(tir); 1343 return NULL; 1344 } 1345 tir->id = MLX5_GET(create_tir_out, out, tirn); 1346 return tir; 1347 } 1348 1349 /** 1350 * Modify TIR using DevX API. 1351 * 1352 * @param[in] tir 1353 * Pointer to TIR DevX object structure. 1354 * @param [in] modify_tir_attr 1355 * Pointer to TIR modification attributes structure. 1356 * 1357 * @return 1358 * 0 on success, a negative errno value otherwise and rte_errno is set. 1359 */ 1360 int 1361 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1362 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1363 { 1364 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1365 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1366 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1367 void *tir_ctx; 1368 int ret; 1369 1370 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1371 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1372 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1373 modify_tir_attr->modify_bitmask); 1374 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1375 if (modify_tir_attr->modify_bitmask & 1376 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1377 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1378 tir_attr->lro_timeout_period_usecs); 1379 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1380 tir_attr->lro_enable_mask); 1381 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1382 tir_attr->lro_max_msg_sz); 1383 } 1384 if (modify_tir_attr->modify_bitmask & 1385 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1386 MLX5_SET(tirc, tir_ctx, indirect_table, 1387 tir_attr->indirect_table); 1388 if (modify_tir_attr->modify_bitmask & 1389 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1390 int i; 1391 void *outer, *inner; 1392 1393 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1394 tir_attr->rx_hash_symmetric); 1395 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1396 for (i = 0; i < 10; i++) { 1397 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1398 tir_attr->rx_hash_toeplitz_key[i]); 1399 } 1400 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1401 rx_hash_field_selector_outer); 1402 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1403 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1404 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1405 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1406 MLX5_SET 1407 (rx_hash_field_select, outer, selected_fields, 1408 tir_attr->rx_hash_field_selector_outer.selected_fields); 1409 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1410 rx_hash_field_selector_inner); 1411 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1412 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1413 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1414 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1415 MLX5_SET 1416 (rx_hash_field_select, inner, selected_fields, 1417 tir_attr->rx_hash_field_selector_inner.selected_fields); 1418 } 1419 if (modify_tir_attr->modify_bitmask & 1420 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1421 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1422 } 1423 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1424 out, sizeof(out)); 1425 if (ret) { 1426 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1427 rte_errno = errno; 1428 return -errno; 1429 } 1430 return ret; 1431 } 1432 1433 /** 1434 * Create RQT using DevX API. 1435 * 1436 * @param[in] ctx 1437 * Context returned from mlx5 open_device() glue function. 1438 * @param [in] rqt_attr 1439 * Pointer to RQT attributes structure. 1440 * 1441 * @return 1442 * The DevX object created, NULL otherwise and rte_errno is set. 1443 */ 1444 struct mlx5_devx_obj * 1445 mlx5_devx_cmd_create_rqt(void *ctx, 1446 struct mlx5_devx_rqt_attr *rqt_attr) 1447 { 1448 uint32_t *in = NULL; 1449 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1450 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1451 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1452 void *rqt_ctx; 1453 struct mlx5_devx_obj *rqt = NULL; 1454 int i; 1455 1456 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1457 if (!in) { 1458 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1459 rte_errno = ENOMEM; 1460 return NULL; 1461 } 1462 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1463 if (!rqt) { 1464 DRV_LOG(ERR, "Failed to allocate RQT data"); 1465 rte_errno = ENOMEM; 1466 mlx5_free(in); 1467 return NULL; 1468 } 1469 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1470 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1471 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1472 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1473 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1474 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1475 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1476 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1477 mlx5_free(in); 1478 if (!rqt->obj) { 1479 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1480 rte_errno = errno; 1481 mlx5_free(rqt); 1482 return NULL; 1483 } 1484 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1485 return rqt; 1486 } 1487 1488 /** 1489 * Modify RQT using DevX API. 1490 * 1491 * @param[in] rqt 1492 * Pointer to RQT DevX object structure. 1493 * @param [in] rqt_attr 1494 * Pointer to RQT attributes structure. 1495 * 1496 * @return 1497 * 0 on success, a negative errno value otherwise and rte_errno is set. 1498 */ 1499 int 1500 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1501 struct mlx5_devx_rqt_attr *rqt_attr) 1502 { 1503 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1504 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1505 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1506 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1507 void *rqt_ctx; 1508 int i; 1509 int ret; 1510 1511 if (!in) { 1512 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1513 rte_errno = ENOMEM; 1514 return -ENOMEM; 1515 } 1516 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1517 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1518 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1519 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1520 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1521 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1522 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1523 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1524 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1525 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1526 mlx5_free(in); 1527 if (ret) { 1528 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1529 rte_errno = errno; 1530 return -rte_errno; 1531 } 1532 return ret; 1533 } 1534 1535 /** 1536 * Create SQ using DevX API. 1537 * 1538 * @param[in] ctx 1539 * Context returned from mlx5 open_device() glue function. 1540 * @param [in] sq_attr 1541 * Pointer to SQ attributes structure. 1542 * @param [in] socket 1543 * CPU socket ID for allocations. 1544 * 1545 * @return 1546 * The DevX object created, NULL otherwise and rte_errno is set. 1547 **/ 1548 struct mlx5_devx_obj * 1549 mlx5_devx_cmd_create_sq(void *ctx, 1550 struct mlx5_devx_create_sq_attr *sq_attr) 1551 { 1552 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1553 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1554 void *sq_ctx; 1555 void *wq_ctx; 1556 struct mlx5_devx_wq_attr *wq_attr; 1557 struct mlx5_devx_obj *sq = NULL; 1558 1559 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1560 if (!sq) { 1561 DRV_LOG(ERR, "Failed to allocate SQ data"); 1562 rte_errno = ENOMEM; 1563 return NULL; 1564 } 1565 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1566 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1567 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1568 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1569 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1570 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1571 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1572 sq_attr->allow_multi_pkt_send_wqe); 1573 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1574 sq_attr->min_wqe_inline_mode); 1575 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1576 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1577 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1578 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1579 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1580 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1581 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1582 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1583 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1584 sq_attr->packet_pacing_rate_limit_index); 1585 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1586 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1587 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1588 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1589 wq_attr = &sq_attr->wq_attr; 1590 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1591 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1592 out, sizeof(out)); 1593 if (!sq->obj) { 1594 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1595 rte_errno = errno; 1596 mlx5_free(sq); 1597 return NULL; 1598 } 1599 sq->id = MLX5_GET(create_sq_out, out, sqn); 1600 return sq; 1601 } 1602 1603 /** 1604 * Modify SQ using DevX API. 1605 * 1606 * @param[in] sq 1607 * Pointer to SQ object structure. 1608 * @param [in] sq_attr 1609 * Pointer to SQ attributes structure. 1610 * 1611 * @return 1612 * 0 on success, a negative errno value otherwise and rte_errno is set. 1613 */ 1614 int 1615 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1616 struct mlx5_devx_modify_sq_attr *sq_attr) 1617 { 1618 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1619 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1620 void *sq_ctx; 1621 int ret; 1622 1623 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1624 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1625 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1626 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1627 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1628 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1629 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1630 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1631 out, sizeof(out)); 1632 if (ret) { 1633 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1634 rte_errno = errno; 1635 return -rte_errno; 1636 } 1637 return ret; 1638 } 1639 1640 /** 1641 * Create TIS using DevX API. 1642 * 1643 * @param[in] ctx 1644 * Context returned from mlx5 open_device() glue function. 1645 * @param [in] tis_attr 1646 * Pointer to TIS attributes structure. 1647 * 1648 * @return 1649 * The DevX object created, NULL otherwise and rte_errno is set. 1650 */ 1651 struct mlx5_devx_obj * 1652 mlx5_devx_cmd_create_tis(void *ctx, 1653 struct mlx5_devx_tis_attr *tis_attr) 1654 { 1655 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1656 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1657 struct mlx5_devx_obj *tis = NULL; 1658 void *tis_ctx; 1659 1660 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1661 if (!tis) { 1662 DRV_LOG(ERR, "Failed to allocate TIS object"); 1663 rte_errno = ENOMEM; 1664 return NULL; 1665 } 1666 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1667 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1668 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1669 tis_attr->strict_lag_tx_port_affinity); 1670 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1671 tis_attr->lag_tx_port_affinity); 1672 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1673 MLX5_SET(tisc, tis_ctx, transport_domain, 1674 tis_attr->transport_domain); 1675 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1676 out, sizeof(out)); 1677 if (!tis->obj) { 1678 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1679 rte_errno = errno; 1680 mlx5_free(tis); 1681 return NULL; 1682 } 1683 tis->id = MLX5_GET(create_tis_out, out, tisn); 1684 return tis; 1685 } 1686 1687 /** 1688 * Create transport domain using DevX API. 1689 * 1690 * @param[in] ctx 1691 * Context returned from mlx5 open_device() glue function. 1692 * @return 1693 * The DevX object created, NULL otherwise and rte_errno is set. 1694 */ 1695 struct mlx5_devx_obj * 1696 mlx5_devx_cmd_create_td(void *ctx) 1697 { 1698 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1699 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1700 struct mlx5_devx_obj *td = NULL; 1701 1702 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1703 if (!td) { 1704 DRV_LOG(ERR, "Failed to allocate TD object"); 1705 rte_errno = ENOMEM; 1706 return NULL; 1707 } 1708 MLX5_SET(alloc_transport_domain_in, in, opcode, 1709 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1710 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1711 out, sizeof(out)); 1712 if (!td->obj) { 1713 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1714 rte_errno = errno; 1715 mlx5_free(td); 1716 return NULL; 1717 } 1718 td->id = MLX5_GET(alloc_transport_domain_out, out, 1719 transport_domain); 1720 return td; 1721 } 1722 1723 /** 1724 * Dump all flows to file. 1725 * 1726 * @param[in] fdb_domain 1727 * FDB domain. 1728 * @param[in] rx_domain 1729 * RX domain. 1730 * @param[in] tx_domain 1731 * TX domain. 1732 * @param[out] file 1733 * Pointer to file stream. 1734 * 1735 * @return 1736 * 0 on success, a nagative value otherwise. 1737 */ 1738 int 1739 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1740 void *rx_domain __rte_unused, 1741 void *tx_domain __rte_unused, FILE *file __rte_unused) 1742 { 1743 int ret = 0; 1744 1745 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1746 if (fdb_domain) { 1747 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1748 if (ret) 1749 return ret; 1750 } 1751 MLX5_ASSERT(rx_domain); 1752 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1753 if (ret) 1754 return ret; 1755 MLX5_ASSERT(tx_domain); 1756 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1757 #else 1758 ret = ENOTSUP; 1759 #endif 1760 return -ret; 1761 } 1762 1763 int 1764 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 1765 FILE *file __rte_unused) 1766 { 1767 int ret = 0; 1768 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 1769 if (rule_info) 1770 ret = mlx5_glue->dr_dump_rule(file, rule_info); 1771 #else 1772 ret = ENOTSUP; 1773 #endif 1774 return -ret; 1775 } 1776 1777 /* 1778 * Create CQ using DevX API. 1779 * 1780 * @param[in] ctx 1781 * Context returned from mlx5 open_device() glue function. 1782 * @param [in] attr 1783 * Pointer to CQ attributes structure. 1784 * 1785 * @return 1786 * The DevX object created, NULL otherwise and rte_errno is set. 1787 */ 1788 struct mlx5_devx_obj * 1789 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1790 { 1791 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1792 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1793 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1794 sizeof(*cq_obj), 1795 0, SOCKET_ID_ANY); 1796 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1797 1798 if (!cq_obj) { 1799 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1800 rte_errno = ENOMEM; 1801 return NULL; 1802 } 1803 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1804 if (attr->db_umem_valid) { 1805 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1806 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1807 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1808 } else { 1809 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1810 } 1811 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1812 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1813 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1814 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1815 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1816 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1817 MLX5_SET(cqc, cqctx, log_page_size, 1818 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1819 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1820 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1821 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1822 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1823 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1824 attr->mini_cqe_res_format_ext); 1825 if (attr->q_umem_valid) { 1826 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1827 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1828 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1829 attr->q_umem_offset); 1830 } 1831 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1832 sizeof(out)); 1833 if (!cq_obj->obj) { 1834 rte_errno = errno; 1835 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1836 mlx5_free(cq_obj); 1837 return NULL; 1838 } 1839 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1840 return cq_obj; 1841 } 1842 1843 /** 1844 * Create VIRTQ using DevX API. 1845 * 1846 * @param[in] ctx 1847 * Context returned from mlx5 open_device() glue function. 1848 * @param [in] attr 1849 * Pointer to VIRTQ attributes structure. 1850 * 1851 * @return 1852 * The DevX object created, NULL otherwise and rte_errno is set. 1853 */ 1854 struct mlx5_devx_obj * 1855 mlx5_devx_cmd_create_virtq(void *ctx, 1856 struct mlx5_devx_virtq_attr *attr) 1857 { 1858 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1859 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1860 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1861 sizeof(*virtq_obj), 1862 0, SOCKET_ID_ANY); 1863 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1864 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1865 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1866 1867 if (!virtq_obj) { 1868 DRV_LOG(ERR, "Failed to allocate virtq data."); 1869 rte_errno = ENOMEM; 1870 return NULL; 1871 } 1872 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1873 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1874 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1875 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1876 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1877 attr->hw_available_index); 1878 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1879 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1880 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1881 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1882 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1883 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1884 attr->virtio_version_1_0); 1885 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1886 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1887 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1888 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1889 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1890 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1891 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1892 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1893 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1894 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 1895 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 1896 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 1897 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 1898 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 1899 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 1900 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 1901 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 1902 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 1903 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 1904 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 1905 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 1906 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 1907 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 1908 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1909 sizeof(out)); 1910 if (!virtq_obj->obj) { 1911 rte_errno = errno; 1912 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 1913 mlx5_free(virtq_obj); 1914 return NULL; 1915 } 1916 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1917 return virtq_obj; 1918 } 1919 1920 /** 1921 * Modify VIRTQ using DevX API. 1922 * 1923 * @param[in] virtq_obj 1924 * Pointer to virtq object structure. 1925 * @param [in] attr 1926 * Pointer to modify virtq attributes structure. 1927 * 1928 * @return 1929 * 0 on success, a negative errno value otherwise and rte_errno is set. 1930 */ 1931 int 1932 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 1933 struct mlx5_devx_virtq_attr *attr) 1934 { 1935 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1936 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1937 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1938 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1939 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1940 int ret; 1941 1942 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1943 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 1944 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1945 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1946 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1947 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 1948 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1949 switch (attr->type) { 1950 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 1951 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 1952 break; 1953 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 1954 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 1955 attr->dirty_bitmap_mkey); 1956 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 1957 attr->dirty_bitmap_addr); 1958 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 1959 attr->dirty_bitmap_size); 1960 break; 1961 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 1962 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 1963 attr->dirty_bitmap_dump_enable); 1964 break; 1965 default: 1966 rte_errno = EINVAL; 1967 return -rte_errno; 1968 } 1969 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 1970 out, sizeof(out)); 1971 if (ret) { 1972 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1973 rte_errno = errno; 1974 return -rte_errno; 1975 } 1976 return ret; 1977 } 1978 1979 /** 1980 * Query VIRTQ using DevX API. 1981 * 1982 * @param[in] virtq_obj 1983 * Pointer to virtq object structure. 1984 * @param [in/out] attr 1985 * Pointer to virtq attributes structure. 1986 * 1987 * @return 1988 * 0 on success, a negative errno value otherwise and rte_errno is set. 1989 */ 1990 int 1991 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 1992 struct mlx5_devx_virtq_attr *attr) 1993 { 1994 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1995 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 1996 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 1997 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 1998 int ret; 1999 2000 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2001 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2002 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2003 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2004 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2005 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2006 out, sizeof(out)); 2007 if (ret) { 2008 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2009 rte_errno = errno; 2010 return -errno; 2011 } 2012 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2013 hw_available_index); 2014 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2015 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2016 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2017 virtio_q_context.error_type); 2018 return ret; 2019 } 2020 2021 /** 2022 * Create QP using DevX API. 2023 * 2024 * @param[in] ctx 2025 * Context returned from mlx5 open_device() glue function. 2026 * @param [in] attr 2027 * Pointer to QP attributes structure. 2028 * 2029 * @return 2030 * The DevX object created, NULL otherwise and rte_errno is set. 2031 */ 2032 struct mlx5_devx_obj * 2033 mlx5_devx_cmd_create_qp(void *ctx, 2034 struct mlx5_devx_qp_attr *attr) 2035 { 2036 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2037 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2038 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2039 sizeof(*qp_obj), 2040 0, SOCKET_ID_ANY); 2041 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2042 2043 if (!qp_obj) { 2044 DRV_LOG(ERR, "Failed to allocate QP data."); 2045 rte_errno = ENOMEM; 2046 return NULL; 2047 } 2048 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2049 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2050 MLX5_SET(qpc, qpc, pd, attr->pd); 2051 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2052 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2053 if (attr->uar_index) { 2054 if (attr->mmo) { 2055 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2056 in, qpc_extension_and_pas_list); 2057 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2058 qpc_ext_and_pas_list, qpc_data_extension); 2059 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2060 } 2061 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2062 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2063 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2064 MLX5_SET(qpc, qpc, log_page_size, 2065 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2066 if (attr->sq_size) { 2067 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); 2068 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2069 MLX5_SET(qpc, qpc, log_sq_size, 2070 rte_log2_u32(attr->sq_size)); 2071 } else { 2072 MLX5_SET(qpc, qpc, no_sq, 1); 2073 } 2074 if (attr->rq_size) { 2075 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); 2076 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2077 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2078 MLX5_LOG_RQ_STRIDE_SHIFT); 2079 MLX5_SET(qpc, qpc, log_rq_size, 2080 rte_log2_u32(attr->rq_size)); 2081 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2082 } else { 2083 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2084 } 2085 if (attr->dbr_umem_valid) { 2086 MLX5_SET(qpc, qpc, dbr_umem_valid, 2087 attr->dbr_umem_valid); 2088 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2089 } 2090 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2091 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2092 attr->wq_umem_offset); 2093 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2094 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2095 } else { 2096 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2097 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2098 MLX5_SET(qpc, qpc, no_sq, 1); 2099 } 2100 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2101 sizeof(out)); 2102 if (!qp_obj->obj) { 2103 rte_errno = errno; 2104 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 2105 mlx5_free(qp_obj); 2106 return NULL; 2107 } 2108 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2109 return qp_obj; 2110 } 2111 2112 /** 2113 * Modify QP using DevX API. 2114 * Currently supports only force loop-back QP. 2115 * 2116 * @param[in] qp 2117 * Pointer to QP object structure. 2118 * @param [in] qp_st_mod_op 2119 * The QP state modification operation. 2120 * @param [in] remote_qp_id 2121 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2122 * 2123 * @return 2124 * 0 on success, a negative errno value otherwise and rte_errno is set. 2125 */ 2126 int 2127 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2128 uint32_t remote_qp_id) 2129 { 2130 union { 2131 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2132 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2133 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2134 } in; 2135 union { 2136 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2137 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2138 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2139 } out; 2140 void *qpc; 2141 int ret; 2142 unsigned int inlen; 2143 unsigned int outlen; 2144 2145 memset(&in, 0, sizeof(in)); 2146 memset(&out, 0, sizeof(out)); 2147 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2148 switch (qp_st_mod_op) { 2149 case MLX5_CMD_OP_RST2INIT_QP: 2150 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2151 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2152 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2153 MLX5_SET(qpc, qpc, rre, 1); 2154 MLX5_SET(qpc, qpc, rwe, 1); 2155 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2156 inlen = sizeof(in.rst2init); 2157 outlen = sizeof(out.rst2init); 2158 break; 2159 case MLX5_CMD_OP_INIT2RTR_QP: 2160 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2161 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2162 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2163 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2164 MLX5_SET(qpc, qpc, mtu, 1); 2165 MLX5_SET(qpc, qpc, log_msg_max, 30); 2166 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2167 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2168 inlen = sizeof(in.init2rtr); 2169 outlen = sizeof(out.init2rtr); 2170 break; 2171 case MLX5_CMD_OP_RTR2RTS_QP: 2172 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2173 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2174 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 2175 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2176 MLX5_SET(qpc, qpc, retry_count, 7); 2177 MLX5_SET(qpc, qpc, rnr_retry, 7); 2178 inlen = sizeof(in.rtr2rts); 2179 outlen = sizeof(out.rtr2rts); 2180 break; 2181 default: 2182 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2183 qp_st_mod_op); 2184 rte_errno = EINVAL; 2185 return -rte_errno; 2186 } 2187 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2188 if (ret) { 2189 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2190 rte_errno = errno; 2191 return -rte_errno; 2192 } 2193 return ret; 2194 } 2195 2196 struct mlx5_devx_obj * 2197 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2198 { 2199 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2200 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2201 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2202 sizeof(*couners_obj), 0, 2203 SOCKET_ID_ANY); 2204 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2205 2206 if (!couners_obj) { 2207 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2208 rte_errno = ENOMEM; 2209 return NULL; 2210 } 2211 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2212 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2213 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2214 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2215 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2216 sizeof(out)); 2217 if (!couners_obj->obj) { 2218 rte_errno = errno; 2219 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 2220 " DevX."); 2221 mlx5_free(couners_obj); 2222 return NULL; 2223 } 2224 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2225 return couners_obj; 2226 } 2227 2228 int 2229 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2230 struct mlx5_devx_virtio_q_couners_attr *attr) 2231 { 2232 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2233 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2234 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2235 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2236 virtio_q_counters); 2237 int ret; 2238 2239 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2240 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2241 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2242 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2243 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2244 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2245 sizeof(out)); 2246 if (ret) { 2247 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2248 rte_errno = errno; 2249 return -errno; 2250 } 2251 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2252 received_desc); 2253 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2254 completed_desc); 2255 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2256 error_cqes); 2257 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2258 bad_desc_errors); 2259 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2260 exceed_max_chain); 2261 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2262 invalid_buffer); 2263 return ret; 2264 } 2265 2266 /** 2267 * Create general object of type FLOW_HIT_ASO using DevX API. 2268 * 2269 * @param[in] ctx 2270 * Context returned from mlx5 open_device() glue function. 2271 * @param [in] pd 2272 * PD value to associate the FLOW_HIT_ASO object with. 2273 * 2274 * @return 2275 * The DevX object created, NULL otherwise and rte_errno is set. 2276 */ 2277 struct mlx5_devx_obj * 2278 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2279 { 2280 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2281 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2282 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2283 void *ptr = NULL; 2284 2285 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2286 0, SOCKET_ID_ANY); 2287 if (!flow_hit_aso_obj) { 2288 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2289 rte_errno = ENOMEM; 2290 return NULL; 2291 } 2292 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2293 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2294 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2295 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2296 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2297 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2298 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2299 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2300 out, sizeof(out)); 2301 if (!flow_hit_aso_obj->obj) { 2302 rte_errno = errno; 2303 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX."); 2304 mlx5_free(flow_hit_aso_obj); 2305 return NULL; 2306 } 2307 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2308 return flow_hit_aso_obj; 2309 } 2310 2311 /* 2312 * Create PD using DevX API. 2313 * 2314 * @param[in] ctx 2315 * Context returned from mlx5 open_device() glue function. 2316 * 2317 * @return 2318 * The DevX object created, NULL otherwise and rte_errno is set. 2319 */ 2320 struct mlx5_devx_obj * 2321 mlx5_devx_cmd_alloc_pd(void *ctx) 2322 { 2323 struct mlx5_devx_obj *ppd = 2324 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2325 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2326 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2327 2328 if (!ppd) { 2329 DRV_LOG(ERR, "Failed to allocate PD data."); 2330 rte_errno = ENOMEM; 2331 return NULL; 2332 } 2333 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2334 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2335 out, sizeof(out)); 2336 if (!ppd->obj) { 2337 mlx5_free(ppd); 2338 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2339 rte_errno = errno; 2340 return NULL; 2341 } 2342 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2343 return ppd; 2344 } 2345 2346 /** 2347 * Create general object of type FLOW_METER_ASO using DevX API. 2348 * 2349 * @param[in] ctx 2350 * Context returned from mlx5 open_device() glue function. 2351 * @param [in] pd 2352 * PD value to associate the FLOW_METER_ASO object with. 2353 * @param [in] log_obj_size 2354 * log_obj_size define to allocate number of 2 * meters 2355 * in one FLOW_METER_ASO object. 2356 * 2357 * @return 2358 * The DevX object created, NULL otherwise and rte_errno is set. 2359 */ 2360 struct mlx5_devx_obj * 2361 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2362 uint32_t log_obj_size) 2363 { 2364 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2365 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2366 struct mlx5_devx_obj *flow_meter_aso_obj; 2367 void *ptr; 2368 2369 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2370 sizeof(*flow_meter_aso_obj), 2371 0, SOCKET_ID_ANY); 2372 if (!flow_meter_aso_obj) { 2373 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2374 rte_errno = ENOMEM; 2375 return NULL; 2376 } 2377 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2378 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2379 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2380 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2381 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2382 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2383 log_obj_size); 2384 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2385 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2386 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2387 ctx, in, sizeof(in), 2388 out, sizeof(out)); 2389 if (!flow_meter_aso_obj->obj) { 2390 rte_errno = errno; 2391 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX."); 2392 mlx5_free(flow_meter_aso_obj); 2393 return NULL; 2394 } 2395 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2396 out, obj_id); 2397 return flow_meter_aso_obj; 2398 } 2399 2400 /* 2401 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2402 * 2403 * @param[in] ctx 2404 * Context returned from mlx5 open_device() glue function. 2405 * @param [in] pd 2406 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2407 * @param [in] log_obj_size 2408 * log_obj_size to allocate its power of 2 * objects 2409 * in one CONN_TRACK_OFFLOAD bulk allocation. 2410 * 2411 * @return 2412 * The DevX object created, NULL otherwise and rte_errno is set. 2413 */ 2414 struct mlx5_devx_obj * 2415 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2416 uint32_t log_obj_size) 2417 { 2418 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2419 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2420 struct mlx5_devx_obj *ct_aso_obj; 2421 void *ptr; 2422 2423 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2424 0, SOCKET_ID_ANY); 2425 if (!ct_aso_obj) { 2426 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2427 rte_errno = ENOMEM; 2428 return NULL; 2429 } 2430 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2431 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2432 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2433 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2434 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2435 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2436 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2437 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2438 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2439 out, sizeof(out)); 2440 if (!ct_aso_obj->obj) { 2441 rte_errno = errno; 2442 DRV_LOG(ERR, "Failed to create CONN_TRACK_OFFLOAD obj by using DevX."); 2443 mlx5_free(ct_aso_obj); 2444 return NULL; 2445 } 2446 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2447 return ct_aso_obj; 2448 } 2449 2450 /** 2451 * Create general object of type GENEVE TLV option using DevX API. 2452 * 2453 * @param[in] ctx 2454 * Context returned from mlx5 open_device() glue function. 2455 * @param [in] class 2456 * TLV option variable value of class 2457 * @param [in] type 2458 * TLV option variable value of type 2459 * @param [in] len 2460 * TLV option variable value of len 2461 * 2462 * @return 2463 * The DevX object created, NULL otherwise and rte_errno is set. 2464 */ 2465 struct mlx5_devx_obj * 2466 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2467 uint16_t class, uint8_t type, uint8_t len) 2468 { 2469 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2470 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2471 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2472 sizeof(*geneve_tlv_opt_obj), 2473 0, SOCKET_ID_ANY); 2474 2475 if (!geneve_tlv_opt_obj) { 2476 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2477 rte_errno = ENOMEM; 2478 return NULL; 2479 } 2480 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2481 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2482 geneve_tlv_opt); 2483 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2484 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2485 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2486 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2487 MLX5_SET(geneve_tlv_option, opt, option_class, 2488 rte_be_to_cpu_16(class)); 2489 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2490 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2491 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2492 sizeof(in), out, sizeof(out)); 2493 if (!geneve_tlv_opt_obj->obj) { 2494 rte_errno = errno; 2495 DRV_LOG(ERR, "Failed to create Geneve tlv option " 2496 "Obj using DevX."); 2497 mlx5_free(geneve_tlv_opt_obj); 2498 return NULL; 2499 } 2500 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2501 return geneve_tlv_opt_obj; 2502 } 2503 2504 int 2505 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2506 { 2507 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2508 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2509 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2510 int rc; 2511 void *rq_ctx; 2512 2513 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2514 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2515 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2516 if (rc) { 2517 rte_errno = errno; 2518 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2519 "rc = %d, errno = %d.", rc, errno); 2520 return -rc; 2521 }; 2522 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2523 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2524 return 0; 2525 #else 2526 (void)wq; 2527 (void)counter_set_id; 2528 return -ENOTSUP; 2529 #endif 2530 } 2531 2532 /* 2533 * Allocate queue counters via devx interface. 2534 * 2535 * @param[in] ctx 2536 * Context returned from mlx5 open_device() glue function. 2537 * 2538 * @return 2539 * Pointer to counter object on success, a NULL value otherwise and 2540 * rte_errno is set. 2541 */ 2542 struct mlx5_devx_obj * 2543 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2544 { 2545 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2546 SOCKET_ID_ANY); 2547 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2548 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2549 2550 if (!dcs) { 2551 rte_errno = ENOMEM; 2552 return NULL; 2553 } 2554 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2555 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2556 sizeof(out)); 2557 if (!dcs->obj) { 2558 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error " 2559 "%d.", errno); 2560 rte_errno = errno; 2561 mlx5_free(dcs); 2562 return NULL; 2563 } 2564 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2565 return dcs; 2566 } 2567 2568 /** 2569 * Query queue counters values. 2570 * 2571 * @param[in] dcs 2572 * devx object of the queue counter set. 2573 * @param[in] clear 2574 * Whether hardware should clear the counters after the query or not. 2575 * @param[out] out_of_buffers 2576 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2577 * 2578 * @return 2579 * 0 on success, a negative value otherwise. 2580 */ 2581 int 2582 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2583 uint32_t *out_of_buffers) 2584 { 2585 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2586 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2587 int rc; 2588 2589 MLX5_SET(query_q_counter_in, in, opcode, 2590 MLX5_CMD_OP_QUERY_Q_COUNTER); 2591 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2592 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2593 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2594 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2595 sizeof(out)); 2596 if (rc) { 2597 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2598 rte_errno = rc; 2599 return -rc; 2600 } 2601 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2602 return 0; 2603 } 2604 2605 /** 2606 * Create general object of type DEK using DevX API. 2607 * 2608 * @param[in] ctx 2609 * Context returned from mlx5 open_device() glue function. 2610 * @param [in] attr 2611 * Pointer to DEK attributes structure. 2612 * 2613 * @return 2614 * The DevX object created, NULL otherwise and rte_errno is set. 2615 */ 2616 struct mlx5_devx_obj * 2617 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2618 { 2619 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2620 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2621 struct mlx5_devx_obj *dek_obj = NULL; 2622 void *ptr = NULL, *key_addr = NULL; 2623 2624 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2625 0, SOCKET_ID_ANY); 2626 if (dek_obj == NULL) { 2627 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2628 rte_errno = ENOMEM; 2629 return NULL; 2630 } 2631 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2632 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2633 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2634 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2635 MLX5_GENERAL_OBJ_TYPE_DEK); 2636 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2637 MLX5_SET(dek, ptr, key_size, attr->key_size); 2638 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2639 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2640 MLX5_SET(dek, ptr, pd, attr->pd); 2641 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2642 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2643 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2644 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2645 out, sizeof(out)); 2646 if (dek_obj->obj == NULL) { 2647 rte_errno = errno; 2648 DRV_LOG(ERR, "Failed to create DEK obj using DevX."); 2649 mlx5_free(dek_obj); 2650 return NULL; 2651 } 2652 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2653 return dek_obj; 2654 } 2655 2656 /** 2657 * Create general object of type IMPORT_KEK using DevX API. 2658 * 2659 * @param[in] ctx 2660 * Context returned from mlx5 open_device() glue function. 2661 * @param [in] attr 2662 * Pointer to IMPORT_KEK attributes structure. 2663 * 2664 * @return 2665 * The DevX object created, NULL otherwise and rte_errno is set. 2666 */ 2667 struct mlx5_devx_obj * 2668 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 2669 struct mlx5_devx_import_kek_attr *attr) 2670 { 2671 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 2672 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2673 struct mlx5_devx_obj *import_kek_obj = NULL; 2674 void *ptr = NULL, *key_addr = NULL; 2675 2676 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 2677 0, SOCKET_ID_ANY); 2678 if (import_kek_obj == NULL) { 2679 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 2680 rte_errno = ENOMEM; 2681 return NULL; 2682 } 2683 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 2684 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2685 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2686 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2687 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 2688 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 2689 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 2690 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 2691 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2692 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2693 out, sizeof(out)); 2694 if (import_kek_obj->obj == NULL) { 2695 rte_errno = errno; 2696 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX."); 2697 mlx5_free(import_kek_obj); 2698 return NULL; 2699 } 2700 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2701 return import_kek_obj; 2702 } 2703 2704 /** 2705 * Create general object of type CREDENTIAL using DevX API. 2706 * 2707 * @param[in] ctx 2708 * Context returned from mlx5 open_device() glue function. 2709 * @param [in] attr 2710 * Pointer to CREDENTIAL attributes structure. 2711 * 2712 * @return 2713 * The DevX object created, NULL otherwise and rte_errno is set. 2714 */ 2715 struct mlx5_devx_obj * 2716 mlx5_devx_cmd_create_credential_obj(void *ctx, 2717 struct mlx5_devx_credential_attr *attr) 2718 { 2719 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 2720 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2721 struct mlx5_devx_obj *credential_obj = NULL; 2722 void *ptr = NULL, *credential_addr = NULL; 2723 2724 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 2725 0, SOCKET_ID_ANY); 2726 if (credential_obj == NULL) { 2727 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 2728 rte_errno = ENOMEM; 2729 return NULL; 2730 } 2731 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 2732 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2733 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2734 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2735 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 2736 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 2737 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 2738 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 2739 memcpy(credential_addr, (void *)(attr->credential), 2740 MLX5_CRYPTO_CREDENTIAL_SIZE); 2741 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2742 out, sizeof(out)); 2743 if (credential_obj->obj == NULL) { 2744 rte_errno = errno; 2745 DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX."); 2746 mlx5_free(credential_obj); 2747 return NULL; 2748 } 2749 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2750 return credential_obj; 2751 } 2752 2753 /** 2754 * Create general object of type CRYPTO_LOGIN using DevX API. 2755 * 2756 * @param[in] ctx 2757 * Context returned from mlx5 open_device() glue function. 2758 * @param [in] attr 2759 * Pointer to CRYPTO_LOGIN attributes structure. 2760 * 2761 * @return 2762 * The DevX object created, NULL otherwise and rte_errno is set. 2763 */ 2764 struct mlx5_devx_obj * 2765 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 2766 struct mlx5_devx_crypto_login_attr *attr) 2767 { 2768 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 2769 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2770 struct mlx5_devx_obj *crypto_login_obj = NULL; 2771 void *ptr = NULL, *credential_addr = NULL; 2772 2773 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 2774 0, SOCKET_ID_ANY); 2775 if (crypto_login_obj == NULL) { 2776 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 2777 rte_errno = ENOMEM; 2778 return NULL; 2779 } 2780 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 2781 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2782 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2783 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2784 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 2785 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 2786 MLX5_SET(crypto_login, ptr, credential_pointer, 2787 attr->credential_pointer); 2788 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 2789 attr->session_import_kek_ptr); 2790 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 2791 memcpy(credential_addr, (void *)(attr->credential), 2792 MLX5_CRYPTO_CREDENTIAL_SIZE); 2793 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2794 out, sizeof(out)); 2795 if (crypto_login_obj->obj == NULL) { 2796 rte_errno = errno; 2797 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX."); 2798 mlx5_free(crypto_login_obj); 2799 return NULL; 2800 } 2801 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2802 return crypto_login_obj; 2803 } 2804 2805 /** 2806 * Query LAG context. 2807 * 2808 * @param[in] ctx 2809 * Pointer to ibv_context, returned from mlx5dv_open_device. 2810 * @param[out] lag_ctx 2811 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 2812 * 2813 * @return 2814 * 0 on success, a negative value otherwise. 2815 */ 2816 int 2817 mlx5_devx_cmd_query_lag(void *ctx, 2818 struct mlx5_devx_lag_context *lag_ctx) 2819 { 2820 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 2821 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 2822 void *lctx; 2823 int rc; 2824 2825 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 2826 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 2827 if (rc) 2828 goto error; 2829 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 2830 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 2831 fdb_selection_mode); 2832 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 2833 port_select_mode); 2834 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 2835 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 2836 tx_remap_affinity_2); 2837 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 2838 tx_remap_affinity_1); 2839 return 0; 2840 error: 2841 rc = (rc > 0) ? -rc : rc; 2842 return rc; 2843 } 2844