1 // SPDX-License-Identifier: BSD-3-Clause 2 /* Copyright 2018 Mellanox Technologies, Ltd */ 3 4 #include <unistd.h> 5 6 #include <rte_errno.h> 7 #include <rte_malloc.h> 8 #include <rte_eal_paging.h> 9 10 #include "mlx5_prm.h" 11 #include "mlx5_devx_cmds.h" 12 #include "mlx5_common_utils.h" 13 #include "mlx5_malloc.h" 14 15 16 /** 17 * Perform read access to the registers. Reads data from register 18 * and writes ones to the specified buffer. 19 * 20 * @param[in] ctx 21 * Context returned from mlx5 open_device() glue function. 22 * @param[in] reg_id 23 * Register identifier according to the PRM. 24 * @param[in] arg 25 * Register access auxiliary parameter according to the PRM. 26 * @param[out] data 27 * Pointer to the buffer to store read data. 28 * @param[in] dw_cnt 29 * Buffer size in double words. 30 * 31 * @return 32 * 0 on success, a negative value otherwise. 33 */ 34 int 35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 36 uint32_t *data, uint32_t dw_cnt) 37 { 38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 41 int status, rc; 42 43 MLX5_ASSERT(data && dw_cnt); 44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 46 DRV_LOG(ERR, "Not enough buffer for register read data"); 47 return -1; 48 } 49 MLX5_SET(access_register_in, in, opcode, 50 MLX5_CMD_OP_ACCESS_REGISTER_USER); 51 MLX5_SET(access_register_in, in, op_mod, 52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 53 MLX5_SET(access_register_in, in, register_id, reg_id); 54 MLX5_SET(access_register_in, in, argument, arg); 55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 56 MLX5_ST_SZ_DW(access_register_out) * 57 sizeof(uint32_t) + dw_cnt); 58 if (rc) 59 goto error; 60 status = MLX5_GET(access_register_out, out, status); 61 if (status) { 62 int syndrome = MLX5_GET(access_register_out, out, syndrome); 63 64 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, " 65 "status %x, syndrome = %x", 66 reg_id, status, syndrome); 67 return -1; 68 } 69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 70 dw_cnt * sizeof(uint32_t)); 71 return 0; 72 error: 73 rc = (rc > 0) ? -rc : rc; 74 return rc; 75 } 76 77 /** 78 * Allocate flow counters via devx interface. 79 * 80 * @param[in] ctx 81 * Context returned from mlx5 open_device() glue function. 82 * @param dcs 83 * Pointer to counters properties structure to be filled by the routine. 84 * @param bulk_n_128 85 * Bulk counter numbers in 128 counters units. 86 * 87 * @return 88 * Pointer to counter object on success, a negative value otherwise and 89 * rte_errno is set. 90 */ 91 struct mlx5_devx_obj * 92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 93 { 94 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 95 0, SOCKET_ID_ANY); 96 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 97 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 98 99 if (!dcs) { 100 rte_errno = ENOMEM; 101 return NULL; 102 } 103 MLX5_SET(alloc_flow_counter_in, in, opcode, 104 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 105 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 106 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 107 sizeof(in), out, sizeof(out)); 108 if (!dcs->obj) { 109 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 110 rte_errno = errno; 111 mlx5_free(dcs); 112 return NULL; 113 } 114 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 115 return dcs; 116 } 117 118 /** 119 * Query flow counters values. 120 * 121 * @param[in] dcs 122 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 123 * @param[in] clear 124 * Whether hardware should clear the counters after the query or not. 125 * @param[in] n_counters 126 * 0 in case of 1 counter to read, otherwise the counter number to read. 127 * @param pkts 128 * The number of packets that matched the flow. 129 * @param bytes 130 * The number of bytes that matched the flow. 131 * @param mkey 132 * The mkey key for batch query. 133 * @param addr 134 * The address in the mkey range for batch query. 135 * @param cmd_comp 136 * The completion object for asynchronous batch query. 137 * @param async_id 138 * The ID to be returned in the asynchronous batch query response. 139 * 140 * @return 141 * 0 on success, a negative value otherwise. 142 */ 143 int 144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 145 int clear, uint32_t n_counters, 146 uint64_t *pkts, uint64_t *bytes, 147 uint32_t mkey, void *addr, 148 void *cmd_comp, 149 uint64_t async_id) 150 { 151 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 152 MLX5_ST_SZ_BYTES(traffic_counter); 153 uint32_t out[out_len]; 154 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 155 void *stats; 156 int rc; 157 158 MLX5_SET(query_flow_counter_in, in, opcode, 159 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 160 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 161 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 162 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 163 164 if (n_counters) { 165 MLX5_SET(query_flow_counter_in, in, num_of_counters, 166 n_counters); 167 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 168 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 169 MLX5_SET64(query_flow_counter_in, in, address, 170 (uint64_t)(uintptr_t)addr); 171 } 172 if (!cmd_comp) 173 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 174 out_len); 175 else 176 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 177 out_len, async_id, 178 cmd_comp); 179 if (rc) { 180 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 181 rte_errno = rc; 182 return -rc; 183 } 184 if (!n_counters) { 185 stats = MLX5_ADDR_OF(query_flow_counter_out, 186 out, flow_statistics); 187 *pkts = MLX5_GET64(traffic_counter, stats, packets); 188 *bytes = MLX5_GET64(traffic_counter, stats, octets); 189 } 190 return 0; 191 } 192 193 /** 194 * Create a new mkey. 195 * 196 * @param[in] ctx 197 * Context returned from mlx5 open_device() glue function. 198 * @param[in] attr 199 * Attributes of the requested mkey. 200 * 201 * @return 202 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 203 * is set. 204 */ 205 struct mlx5_devx_obj * 206 mlx5_devx_cmd_mkey_create(void *ctx, 207 struct mlx5_devx_mkey_attr *attr) 208 { 209 struct mlx5_klm *klm_array = attr->klm_array; 210 int klm_num = attr->klm_num; 211 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 212 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 213 uint32_t in[in_size_dw]; 214 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 215 void *mkc; 216 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 217 0, SOCKET_ID_ANY); 218 size_t pgsize; 219 uint32_t translation_size; 220 221 if (!mkey) { 222 rte_errno = ENOMEM; 223 return NULL; 224 } 225 memset(in, 0, in_size_dw * 4); 226 pgsize = rte_mem_page_size(); 227 if (pgsize == (size_t)-1) { 228 mlx5_free(mkey); 229 DRV_LOG(ERR, "Failed to get page size"); 230 rte_errno = ENOMEM; 231 return NULL; 232 } 233 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 234 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 235 if (klm_num > 0) { 236 int i; 237 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 238 klm_pas_mtt); 239 translation_size = RTE_ALIGN(klm_num, 4); 240 for (i = 0; i < klm_num; i++) { 241 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 242 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 243 MLX5_SET64(klm, klm, address, klm_array[i].address); 244 klm += MLX5_ST_SZ_BYTES(klm); 245 } 246 for (; i < (int)translation_size; i++) { 247 MLX5_SET(klm, klm, mkey, 0x0); 248 MLX5_SET64(klm, klm, address, 0x0); 249 klm += MLX5_ST_SZ_BYTES(klm); 250 } 251 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 252 MLX5_MKC_ACCESS_MODE_KLM_FBS : 253 MLX5_MKC_ACCESS_MODE_KLM); 254 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 255 } else { 256 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 257 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 258 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 259 } 260 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 261 translation_size); 262 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 263 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 264 MLX5_SET(mkc, mkc, lw, 0x1); 265 MLX5_SET(mkc, mkc, lr, 0x1); 266 MLX5_SET(mkc, mkc, qpn, 0xffffff); 267 MLX5_SET(mkc, mkc, pd, attr->pd); 268 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 269 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 270 if (attr->relaxed_ordering == 1) { 271 MLX5_SET(mkc, mkc, relaxed_ordering_write, 0x1); 272 MLX5_SET(mkc, mkc, relaxed_ordering_read, 0x1); 273 } 274 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 275 MLX5_SET64(mkc, mkc, len, attr->size); 276 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 277 sizeof(out)); 278 if (!mkey->obj) { 279 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d\n", 280 klm_num ? "an in" : "a ", errno); 281 rte_errno = errno; 282 mlx5_free(mkey); 283 return NULL; 284 } 285 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 286 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 287 return mkey; 288 } 289 290 /** 291 * Get status of devx command response. 292 * Mainly used for asynchronous commands. 293 * 294 * @param[in] out 295 * The out response buffer. 296 * 297 * @return 298 * 0 on success, non-zero value otherwise. 299 */ 300 int 301 mlx5_devx_get_out_command_status(void *out) 302 { 303 int status; 304 305 if (!out) 306 return -EINVAL; 307 status = MLX5_GET(query_flow_counter_out, out, status); 308 if (status) { 309 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 310 311 DRV_LOG(ERR, "Bad devX status %x, syndrome = %x", status, 312 syndrome); 313 } 314 return status; 315 } 316 317 /** 318 * Destroy any object allocated by a Devx API. 319 * 320 * @param[in] obj 321 * Pointer to a general object. 322 * 323 * @return 324 * 0 on success, a negative value otherwise. 325 */ 326 int 327 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 328 { 329 int ret; 330 331 if (!obj) 332 return 0; 333 ret = mlx5_glue->devx_obj_destroy(obj->obj); 334 mlx5_free(obj); 335 return ret; 336 } 337 338 /** 339 * Query NIC vport context. 340 * Fills minimal inline attribute. 341 * 342 * @param[in] ctx 343 * ibv contexts returned from mlx5dv_open_device. 344 * @param[in] vport 345 * vport index 346 * @param[out] attr 347 * Attributes device values. 348 * 349 * @return 350 * 0 on success, a negative value otherwise. 351 */ 352 static int 353 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 354 unsigned int vport, 355 struct mlx5_hca_attr *attr) 356 { 357 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 358 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 359 void *vctx; 360 int status, syndrome, rc; 361 362 /* Query NIC vport context to determine inline mode. */ 363 MLX5_SET(query_nic_vport_context_in, in, opcode, 364 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 365 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 366 if (vport) 367 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 368 rc = mlx5_glue->devx_general_cmd(ctx, 369 in, sizeof(in), 370 out, sizeof(out)); 371 if (rc) 372 goto error; 373 status = MLX5_GET(query_nic_vport_context_out, out, status); 374 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 375 if (status) { 376 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 377 "status %x, syndrome = %x", 378 status, syndrome); 379 return -1; 380 } 381 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 382 nic_vport_context); 383 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 384 min_wqe_inline_mode); 385 return 0; 386 error: 387 rc = (rc > 0) ? -rc : rc; 388 return rc; 389 } 390 391 /** 392 * Query NIC vDPA attributes. 393 * 394 * @param[in] ctx 395 * Context returned from mlx5 open_device() glue function. 396 * @param[out] vdpa_attr 397 * vDPA Attributes structure to fill. 398 */ 399 static void 400 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 401 struct mlx5_hca_vdpa_attr *vdpa_attr) 402 { 403 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 404 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 405 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 406 int status, syndrome, rc; 407 408 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 409 MLX5_SET(query_hca_cap_in, in, op_mod, 410 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 411 MLX5_HCA_CAP_OPMOD_GET_CUR); 412 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 413 status = MLX5_GET(query_hca_cap_out, out, status); 414 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 415 if (rc || status) { 416 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities," 417 " status %x, syndrome = %x", status, syndrome); 418 vdpa_attr->valid = 0; 419 } else { 420 vdpa_attr->valid = 1; 421 vdpa_attr->desc_tunnel_offload_type = 422 MLX5_GET(virtio_emulation_cap, hcattr, 423 desc_tunnel_offload_type); 424 vdpa_attr->eth_frame_offload_type = 425 MLX5_GET(virtio_emulation_cap, hcattr, 426 eth_frame_offload_type); 427 vdpa_attr->virtio_version_1_0 = 428 MLX5_GET(virtio_emulation_cap, hcattr, 429 virtio_version_1_0); 430 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 431 tso_ipv4); 432 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 433 tso_ipv6); 434 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 435 tx_csum); 436 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 437 rx_csum); 438 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 439 event_mode); 440 vdpa_attr->virtio_queue_type = 441 MLX5_GET(virtio_emulation_cap, hcattr, 442 virtio_queue_type); 443 vdpa_attr->log_doorbell_stride = 444 MLX5_GET(virtio_emulation_cap, hcattr, 445 log_doorbell_stride); 446 vdpa_attr->log_doorbell_bar_size = 447 MLX5_GET(virtio_emulation_cap, hcattr, 448 log_doorbell_bar_size); 449 vdpa_attr->doorbell_bar_offset = 450 MLX5_GET64(virtio_emulation_cap, hcattr, 451 doorbell_bar_offset); 452 vdpa_attr->max_num_virtio_queues = 453 MLX5_GET(virtio_emulation_cap, hcattr, 454 max_num_virtio_queues); 455 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 456 umem_1_buffer_param_a); 457 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 458 umem_1_buffer_param_b); 459 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 460 umem_2_buffer_param_a); 461 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 462 umem_2_buffer_param_b); 463 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 464 umem_3_buffer_param_a); 465 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 466 umem_3_buffer_param_b); 467 } 468 } 469 470 int 471 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 472 uint32_t ids[], uint32_t num) 473 { 474 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 475 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 476 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 477 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 478 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 479 int ret; 480 uint32_t idx = 0; 481 uint32_t i; 482 483 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 484 rte_errno = EINVAL; 485 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 486 return -rte_errno; 487 } 488 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 489 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 490 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 491 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 492 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 493 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 494 out, sizeof(out)); 495 if (ret) { 496 rte_errno = ret; 497 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 498 (void *)flex_obj); 499 return -rte_errno; 500 } 501 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 502 void *s_off = (void *)((char *)sample + i * 503 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 504 uint32_t en; 505 506 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 507 flow_match_sample_en); 508 if (!en) 509 continue; 510 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 511 flow_match_sample_field_id); 512 } 513 if (num != idx) { 514 rte_errno = EINVAL; 515 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 516 return -rte_errno; 517 } 518 return ret; 519 } 520 521 522 struct mlx5_devx_obj * 523 mlx5_devx_cmd_create_flex_parser(void *ctx, 524 struct mlx5_devx_graph_node_attr *data) 525 { 526 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 527 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 528 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 529 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 530 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 531 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 532 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 533 struct mlx5_devx_obj *parse_flex_obj = NULL; 534 uint32_t i; 535 536 parse_flex_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, 537 SOCKET_ID_ANY); 538 if (!parse_flex_obj) { 539 DRV_LOG(ERR, "Failed to allocate flex parser data"); 540 rte_errno = ENOMEM; 541 mlx5_free(in); 542 return NULL; 543 } 544 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 545 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 546 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 547 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 548 MLX5_SET(parse_graph_flex, flex, header_length_mode, 549 data->header_length_mode); 550 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 551 data->header_length_base_value); 552 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 553 data->header_length_field_offset); 554 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 555 data->header_length_field_shift); 556 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 557 data->header_length_field_mask); 558 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 559 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 560 void *s_off = (void *)((char *)sample + i * 561 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 562 563 if (!s->flow_match_sample_en) 564 continue; 565 MLX5_SET(parse_graph_flow_match_sample, s_off, 566 flow_match_sample_en, !!s->flow_match_sample_en); 567 MLX5_SET(parse_graph_flow_match_sample, s_off, 568 flow_match_sample_field_offset, 569 s->flow_match_sample_field_offset); 570 MLX5_SET(parse_graph_flow_match_sample, s_off, 571 flow_match_sample_offset_mode, 572 s->flow_match_sample_offset_mode); 573 MLX5_SET(parse_graph_flow_match_sample, s_off, 574 flow_match_sample_field_offset_mask, 575 s->flow_match_sample_field_offset_mask); 576 MLX5_SET(parse_graph_flow_match_sample, s_off, 577 flow_match_sample_field_offset_shift, 578 s->flow_match_sample_field_offset_shift); 579 MLX5_SET(parse_graph_flow_match_sample, s_off, 580 flow_match_sample_field_base_offset, 581 s->flow_match_sample_field_base_offset); 582 MLX5_SET(parse_graph_flow_match_sample, s_off, 583 flow_match_sample_tunnel_mode, 584 s->flow_match_sample_tunnel_mode); 585 } 586 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 587 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 588 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 589 void *in_off = (void *)((char *)in_arc + i * 590 MLX5_ST_SZ_BYTES(parse_graph_arc)); 591 void *out_off = (void *)((char *)out_arc + i * 592 MLX5_ST_SZ_BYTES(parse_graph_arc)); 593 594 if (ia->arc_parse_graph_node != 0) { 595 MLX5_SET(parse_graph_arc, in_off, 596 compare_condition_value, 597 ia->compare_condition_value); 598 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 599 ia->start_inner_tunnel); 600 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 601 ia->arc_parse_graph_node); 602 MLX5_SET(parse_graph_arc, in_off, 603 parse_graph_node_handle, 604 ia->parse_graph_node_handle); 605 } 606 if (oa->arc_parse_graph_node != 0) { 607 MLX5_SET(parse_graph_arc, out_off, 608 compare_condition_value, 609 oa->compare_condition_value); 610 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 611 oa->start_inner_tunnel); 612 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 613 oa->arc_parse_graph_node); 614 MLX5_SET(parse_graph_arc, out_off, 615 parse_graph_node_handle, 616 oa->parse_graph_node_handle); 617 } 618 } 619 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 620 out, sizeof(out)); 621 if (!parse_flex_obj->obj) { 622 rte_errno = errno; 623 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 624 "by using DevX."); 625 mlx5_free(parse_flex_obj); 626 return NULL; 627 } 628 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 629 return parse_flex_obj; 630 } 631 632 /** 633 * Query HCA attributes. 634 * Using those attributes we can check on run time if the device 635 * is having the required capabilities. 636 * 637 * @param[in] ctx 638 * Context returned from mlx5 open_device() glue function. 639 * @param[out] attr 640 * Attributes device values. 641 * 642 * @return 643 * 0 on success, a negative value otherwise. 644 */ 645 int 646 mlx5_devx_cmd_query_hca_attr(void *ctx, 647 struct mlx5_hca_attr *attr) 648 { 649 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 650 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 651 void *hcattr; 652 int status, syndrome, rc, i; 653 654 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 655 MLX5_SET(query_hca_cap_in, in, op_mod, 656 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 657 MLX5_HCA_CAP_OPMOD_GET_CUR); 658 659 rc = mlx5_glue->devx_general_cmd(ctx, 660 in, sizeof(in), out, sizeof(out)); 661 if (rc) 662 goto error; 663 status = MLX5_GET(query_hca_cap_out, out, status); 664 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 665 if (status) { 666 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 667 "status %x, syndrome = %x", 668 status, syndrome); 669 return -1; 670 } 671 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 672 attr->flow_counter_bulk_alloc_bitmap = 673 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 674 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 675 flow_counters_dump); 676 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 677 log_max_rqt_size); 678 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 679 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 680 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 681 log_max_hairpin_queues); 682 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 683 log_max_hairpin_wq_data_sz); 684 attr->log_max_hairpin_num_packets = MLX5_GET 685 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 686 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 687 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 688 relaxed_ordering_write); 689 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 690 relaxed_ordering_read); 691 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 692 access_register_user); 693 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 694 eth_net_offloads); 695 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 696 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 697 flex_parser_protocols); 698 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 699 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 700 general_obj_types) & 701 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 702 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 703 general_obj_types) & 704 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 705 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 706 general_obj_types) & 707 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 708 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 709 wqe_index_ignore_cap); 710 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 711 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 712 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 713 log_max_static_sq_wq); 714 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 715 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 716 device_frequency_khz); 717 attr->scatter_fcs_w_decap_disable = 718 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 719 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp); 720 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 721 regexp_num_of_engines); 722 if (attr->qos.sup) { 723 MLX5_SET(query_hca_cap_in, in, op_mod, 724 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 725 MLX5_HCA_CAP_OPMOD_GET_CUR); 726 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 727 out, sizeof(out)); 728 if (rc) 729 goto error; 730 if (status) { 731 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities," 732 " status %x, syndrome = %x", 733 status, syndrome); 734 return -1; 735 } 736 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 737 attr->qos.srtcm_sup = 738 MLX5_GET(qos_cap, hcattr, flow_meter_srtcm); 739 attr->qos.log_max_flow_meter = 740 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 741 attr->qos.flow_meter_reg_c_ids = 742 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 743 attr->qos.flow_meter_reg_share = 744 MLX5_GET(qos_cap, hcattr, flow_meter_reg_share); 745 attr->qos.packet_pacing = 746 MLX5_GET(qos_cap, hcattr, packet_pacing); 747 attr->qos.wqe_rate_pp = 748 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 749 } 750 if (attr->vdpa.valid) 751 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 752 if (!attr->eth_net_offloads) 753 return 0; 754 755 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 756 memset(in, 0, sizeof(in)); 757 memset(out, 0, sizeof(out)); 758 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 759 MLX5_SET(query_hca_cap_in, in, op_mod, 760 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 761 MLX5_HCA_CAP_OPMOD_GET_CUR); 762 763 rc = mlx5_glue->devx_general_cmd(ctx, 764 in, sizeof(in), 765 out, sizeof(out)); 766 if (rc) 767 goto error; 768 status = MLX5_GET(query_hca_cap_out, out, status); 769 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 770 if (status) { 771 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 772 "status %x, syndrome = %x", 773 status, syndrome); 774 attr->log_max_ft_sampler_num = 0; 775 return -1; 776 } 777 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 778 attr->log_max_ft_sampler_num = 779 MLX5_GET(flow_table_nic_cap, 780 hcattr, flow_table_properties.log_max_ft_sampler_num); 781 782 /* Query HCA offloads for Ethernet protocol. */ 783 memset(in, 0, sizeof(in)); 784 memset(out, 0, sizeof(out)); 785 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 786 MLX5_SET(query_hca_cap_in, in, op_mod, 787 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 788 MLX5_HCA_CAP_OPMOD_GET_CUR); 789 790 rc = mlx5_glue->devx_general_cmd(ctx, 791 in, sizeof(in), 792 out, sizeof(out)); 793 if (rc) { 794 attr->eth_net_offloads = 0; 795 goto error; 796 } 797 status = MLX5_GET(query_hca_cap_out, out, status); 798 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 799 if (status) { 800 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 801 "status %x, syndrome = %x", 802 status, syndrome); 803 attr->eth_net_offloads = 0; 804 return -1; 805 } 806 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 807 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 808 hcattr, wqe_vlan_insert); 809 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 810 lro_cap); 811 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 812 hcattr, tunnel_lro_gre); 813 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 814 hcattr, tunnel_lro_vxlan); 815 attr->lro_max_msg_sz_mode = MLX5_GET 816 (per_protocol_networking_offload_caps, 817 hcattr, lro_max_msg_sz_mode); 818 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 819 attr->lro_timer_supported_periods[i] = 820 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 821 lro_timer_supported_periods[i]); 822 } 823 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 824 hcattr, lro_min_mss_size); 825 attr->tunnel_stateless_geneve_rx = 826 MLX5_GET(per_protocol_networking_offload_caps, 827 hcattr, tunnel_stateless_geneve_rx); 828 attr->geneve_max_opt_len = 829 MLX5_GET(per_protocol_networking_offload_caps, 830 hcattr, max_geneve_opt_len); 831 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 832 hcattr, wqe_inline_mode); 833 attr->tunnel_stateless_gtp = MLX5_GET 834 (per_protocol_networking_offload_caps, 835 hcattr, tunnel_stateless_gtp); 836 if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) 837 return 0; 838 if (attr->eth_virt) { 839 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 840 if (rc) { 841 attr->eth_virt = 0; 842 goto error; 843 } 844 } 845 return 0; 846 error: 847 rc = (rc > 0) ? -rc : rc; 848 return rc; 849 } 850 851 /** 852 * Query TIS transport domain from QP verbs object using DevX API. 853 * 854 * @param[in] qp 855 * Pointer to verbs QP returned by ibv_create_qp . 856 * @param[in] tis_num 857 * TIS number of TIS to query. 858 * @param[out] tis_td 859 * Pointer to TIS transport domain variable, to be set by the routine. 860 * 861 * @return 862 * 0 on success, a negative value otherwise. 863 */ 864 int 865 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 866 uint32_t *tis_td) 867 { 868 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 869 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 870 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 871 int rc; 872 void *tis_ctx; 873 874 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 875 MLX5_SET(query_tis_in, in, tisn, tis_num); 876 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 877 if (rc) { 878 DRV_LOG(ERR, "Failed to query QP using DevX"); 879 return -rc; 880 }; 881 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 882 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 883 return 0; 884 #else 885 (void)qp; 886 (void)tis_num; 887 (void)tis_td; 888 return -ENOTSUP; 889 #endif 890 } 891 892 /** 893 * Fill WQ data for DevX API command. 894 * Utility function for use when creating DevX objects containing a WQ. 895 * 896 * @param[in] wq_ctx 897 * Pointer to WQ context to fill with data. 898 * @param [in] wq_attr 899 * Pointer to WQ attributes structure to fill in WQ context. 900 */ 901 static void 902 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 903 { 904 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 905 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 906 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 907 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 908 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 909 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 910 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 911 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 912 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 913 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 914 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 915 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 916 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 917 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 918 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz); 919 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 920 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 921 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 922 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 923 wq_attr->log_hairpin_num_packets); 924 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 925 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 926 wq_attr->single_wqe_log_num_of_strides); 927 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 928 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 929 wq_attr->single_stride_log_num_of_bytes); 930 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 931 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 932 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 933 } 934 935 /** 936 * Create RQ using DevX API. 937 * 938 * @param[in] ctx 939 * Context returned from mlx5 open_device() glue function. 940 * @param [in] rq_attr 941 * Pointer to create RQ attributes structure. 942 * @param [in] socket 943 * CPU socket ID for allocations. 944 * 945 * @return 946 * The DevX object created, NULL otherwise and rte_errno is set. 947 */ 948 struct mlx5_devx_obj * 949 mlx5_devx_cmd_create_rq(void *ctx, 950 struct mlx5_devx_create_rq_attr *rq_attr, 951 int socket) 952 { 953 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 954 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 955 void *rq_ctx, *wq_ctx; 956 struct mlx5_devx_wq_attr *wq_attr; 957 struct mlx5_devx_obj *rq = NULL; 958 959 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 960 if (!rq) { 961 DRV_LOG(ERR, "Failed to allocate RQ data"); 962 rte_errno = ENOMEM; 963 return NULL; 964 } 965 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 966 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 967 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 968 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 969 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 970 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 971 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 972 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 973 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 974 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 975 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 976 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 977 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 978 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 979 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 980 wq_attr = &rq_attr->wq_attr; 981 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 982 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 983 out, sizeof(out)); 984 if (!rq->obj) { 985 DRV_LOG(ERR, "Failed to create RQ using DevX"); 986 rte_errno = errno; 987 mlx5_free(rq); 988 return NULL; 989 } 990 rq->id = MLX5_GET(create_rq_out, out, rqn); 991 return rq; 992 } 993 994 /** 995 * Modify RQ using DevX API. 996 * 997 * @param[in] rq 998 * Pointer to RQ object structure. 999 * @param [in] rq_attr 1000 * Pointer to modify RQ attributes structure. 1001 * 1002 * @return 1003 * 0 on success, a negative errno value otherwise and rte_errno is set. 1004 */ 1005 int 1006 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1007 struct mlx5_devx_modify_rq_attr *rq_attr) 1008 { 1009 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1010 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1011 void *rq_ctx, *wq_ctx; 1012 int ret; 1013 1014 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1015 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1016 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1017 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1018 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1019 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1020 if (rq_attr->modify_bitmask & 1021 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1022 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1023 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1024 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1025 if (rq_attr->modify_bitmask & 1026 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1027 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1028 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1029 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1030 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1031 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1032 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1033 } 1034 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1035 out, sizeof(out)); 1036 if (ret) { 1037 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1038 rte_errno = errno; 1039 return -errno; 1040 } 1041 return ret; 1042 } 1043 1044 /** 1045 * Create TIR using DevX API. 1046 * 1047 * @param[in] ctx 1048 * Context returned from mlx5 open_device() glue function. 1049 * @param [in] tir_attr 1050 * Pointer to TIR attributes structure. 1051 * 1052 * @return 1053 * The DevX object created, NULL otherwise and rte_errno is set. 1054 */ 1055 struct mlx5_devx_obj * 1056 mlx5_devx_cmd_create_tir(void *ctx, 1057 struct mlx5_devx_tir_attr *tir_attr) 1058 { 1059 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1060 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1061 void *tir_ctx, *outer, *inner, *rss_key; 1062 struct mlx5_devx_obj *tir = NULL; 1063 1064 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1065 if (!tir) { 1066 DRV_LOG(ERR, "Failed to allocate TIR data"); 1067 rte_errno = ENOMEM; 1068 return NULL; 1069 } 1070 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1071 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1072 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1073 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1074 tir_attr->lro_timeout_period_usecs); 1075 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1076 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1077 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1078 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1079 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1080 tir_attr->tunneled_offload_en); 1081 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1082 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1083 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1084 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1085 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1086 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1087 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1088 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1089 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1090 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1091 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1092 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1093 tir_attr->rx_hash_field_selector_outer.selected_fields); 1094 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1095 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1096 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1097 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1098 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1099 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1100 tir_attr->rx_hash_field_selector_inner.selected_fields); 1101 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1102 out, sizeof(out)); 1103 if (!tir->obj) { 1104 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1105 rte_errno = errno; 1106 mlx5_free(tir); 1107 return NULL; 1108 } 1109 tir->id = MLX5_GET(create_tir_out, out, tirn); 1110 return tir; 1111 } 1112 1113 /** 1114 * Modify TIR using DevX API. 1115 * 1116 * @param[in] tir 1117 * Pointer to TIR DevX object structure. 1118 * @param [in] modify_tir_attr 1119 * Pointer to TIR modification attributes structure. 1120 * 1121 * @return 1122 * 0 on success, a negative errno value otherwise and rte_errno is set. 1123 */ 1124 int 1125 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1126 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1127 { 1128 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1129 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1130 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1131 void *tir_ctx; 1132 int ret; 1133 1134 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1135 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1136 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1137 modify_tir_attr->modify_bitmask); 1138 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1139 if (modify_tir_attr->modify_bitmask & 1140 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1141 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1142 tir_attr->lro_timeout_period_usecs); 1143 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1144 tir_attr->lro_enable_mask); 1145 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1146 tir_attr->lro_max_msg_sz); 1147 } 1148 if (modify_tir_attr->modify_bitmask & 1149 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1150 MLX5_SET(tirc, tir_ctx, indirect_table, 1151 tir_attr->indirect_table); 1152 if (modify_tir_attr->modify_bitmask & 1153 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1154 int i; 1155 void *outer, *inner; 1156 1157 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1158 tir_attr->rx_hash_symmetric); 1159 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1160 for (i = 0; i < 10; i++) { 1161 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1162 tir_attr->rx_hash_toeplitz_key[i]); 1163 } 1164 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1165 rx_hash_field_selector_outer); 1166 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1167 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1168 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1169 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1170 MLX5_SET 1171 (rx_hash_field_select, outer, selected_fields, 1172 tir_attr->rx_hash_field_selector_outer.selected_fields); 1173 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1174 rx_hash_field_selector_inner); 1175 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1176 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1177 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1178 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1179 MLX5_SET 1180 (rx_hash_field_select, inner, selected_fields, 1181 tir_attr->rx_hash_field_selector_inner.selected_fields); 1182 } 1183 if (modify_tir_attr->modify_bitmask & 1184 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1185 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1186 } 1187 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1188 out, sizeof(out)); 1189 if (ret) { 1190 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1191 rte_errno = errno; 1192 return -errno; 1193 } 1194 return ret; 1195 } 1196 1197 /** 1198 * Create RQT using DevX API. 1199 * 1200 * @param[in] ctx 1201 * Context returned from mlx5 open_device() glue function. 1202 * @param [in] rqt_attr 1203 * Pointer to RQT attributes structure. 1204 * 1205 * @return 1206 * The DevX object created, NULL otherwise and rte_errno is set. 1207 */ 1208 struct mlx5_devx_obj * 1209 mlx5_devx_cmd_create_rqt(void *ctx, 1210 struct mlx5_devx_rqt_attr *rqt_attr) 1211 { 1212 uint32_t *in = NULL; 1213 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1214 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1215 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1216 void *rqt_ctx; 1217 struct mlx5_devx_obj *rqt = NULL; 1218 int i; 1219 1220 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1221 if (!in) { 1222 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1223 rte_errno = ENOMEM; 1224 return NULL; 1225 } 1226 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1227 if (!rqt) { 1228 DRV_LOG(ERR, "Failed to allocate RQT data"); 1229 rte_errno = ENOMEM; 1230 mlx5_free(in); 1231 return NULL; 1232 } 1233 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1234 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1235 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1236 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1237 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1238 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1239 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1240 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1241 mlx5_free(in); 1242 if (!rqt->obj) { 1243 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1244 rte_errno = errno; 1245 mlx5_free(rqt); 1246 return NULL; 1247 } 1248 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1249 return rqt; 1250 } 1251 1252 /** 1253 * Modify RQT using DevX API. 1254 * 1255 * @param[in] rqt 1256 * Pointer to RQT DevX object structure. 1257 * @param [in] rqt_attr 1258 * Pointer to RQT attributes structure. 1259 * 1260 * @return 1261 * 0 on success, a negative errno value otherwise and rte_errno is set. 1262 */ 1263 int 1264 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1265 struct mlx5_devx_rqt_attr *rqt_attr) 1266 { 1267 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1268 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1269 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1270 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1271 void *rqt_ctx; 1272 int i; 1273 int ret; 1274 1275 if (!in) { 1276 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1277 rte_errno = ENOMEM; 1278 return -ENOMEM; 1279 } 1280 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1281 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1282 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1283 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1284 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1285 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1286 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1287 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1288 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1289 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1290 mlx5_free(in); 1291 if (ret) { 1292 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1293 rte_errno = errno; 1294 return -rte_errno; 1295 } 1296 return ret; 1297 } 1298 1299 /** 1300 * Create SQ using DevX API. 1301 * 1302 * @param[in] ctx 1303 * Context returned from mlx5 open_device() glue function. 1304 * @param [in] sq_attr 1305 * Pointer to SQ attributes structure. 1306 * @param [in] socket 1307 * CPU socket ID for allocations. 1308 * 1309 * @return 1310 * The DevX object created, NULL otherwise and rte_errno is set. 1311 **/ 1312 struct mlx5_devx_obj * 1313 mlx5_devx_cmd_create_sq(void *ctx, 1314 struct mlx5_devx_create_sq_attr *sq_attr) 1315 { 1316 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1317 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1318 void *sq_ctx; 1319 void *wq_ctx; 1320 struct mlx5_devx_wq_attr *wq_attr; 1321 struct mlx5_devx_obj *sq = NULL; 1322 1323 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1324 if (!sq) { 1325 DRV_LOG(ERR, "Failed to allocate SQ data"); 1326 rte_errno = ENOMEM; 1327 return NULL; 1328 } 1329 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1330 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1331 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1332 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1333 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1334 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1335 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1336 sq_attr->flush_in_error_en); 1337 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1338 sq_attr->min_wqe_inline_mode); 1339 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1340 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1341 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1342 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1343 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1344 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1345 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1346 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1347 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1348 sq_attr->packet_pacing_rate_limit_index); 1349 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1350 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1351 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1352 wq_attr = &sq_attr->wq_attr; 1353 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1354 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1355 out, sizeof(out)); 1356 if (!sq->obj) { 1357 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1358 rte_errno = errno; 1359 mlx5_free(sq); 1360 return NULL; 1361 } 1362 sq->id = MLX5_GET(create_sq_out, out, sqn); 1363 return sq; 1364 } 1365 1366 /** 1367 * Modify SQ using DevX API. 1368 * 1369 * @param[in] sq 1370 * Pointer to SQ object structure. 1371 * @param [in] sq_attr 1372 * Pointer to SQ attributes structure. 1373 * 1374 * @return 1375 * 0 on success, a negative errno value otherwise and rte_errno is set. 1376 */ 1377 int 1378 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1379 struct mlx5_devx_modify_sq_attr *sq_attr) 1380 { 1381 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1382 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1383 void *sq_ctx; 1384 int ret; 1385 1386 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1387 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1388 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1389 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1390 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1391 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1392 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1393 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1394 out, sizeof(out)); 1395 if (ret) { 1396 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1397 rte_errno = errno; 1398 return -rte_errno; 1399 } 1400 return ret; 1401 } 1402 1403 /** 1404 * Create TIS using DevX API. 1405 * 1406 * @param[in] ctx 1407 * Context returned from mlx5 open_device() glue function. 1408 * @param [in] tis_attr 1409 * Pointer to TIS attributes structure. 1410 * 1411 * @return 1412 * The DevX object created, NULL otherwise and rte_errno is set. 1413 */ 1414 struct mlx5_devx_obj * 1415 mlx5_devx_cmd_create_tis(void *ctx, 1416 struct mlx5_devx_tis_attr *tis_attr) 1417 { 1418 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1419 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1420 struct mlx5_devx_obj *tis = NULL; 1421 void *tis_ctx; 1422 1423 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1424 if (!tis) { 1425 DRV_LOG(ERR, "Failed to allocate TIS object"); 1426 rte_errno = ENOMEM; 1427 return NULL; 1428 } 1429 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1430 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1431 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1432 tis_attr->strict_lag_tx_port_affinity); 1433 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1434 tis_attr->lag_tx_port_affinity); 1435 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1436 MLX5_SET(tisc, tis_ctx, transport_domain, 1437 tis_attr->transport_domain); 1438 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1439 out, sizeof(out)); 1440 if (!tis->obj) { 1441 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1442 rte_errno = errno; 1443 mlx5_free(tis); 1444 return NULL; 1445 } 1446 tis->id = MLX5_GET(create_tis_out, out, tisn); 1447 return tis; 1448 } 1449 1450 /** 1451 * Create transport domain using DevX API. 1452 * 1453 * @param[in] ctx 1454 * Context returned from mlx5 open_device() glue function. 1455 * @return 1456 * The DevX object created, NULL otherwise and rte_errno is set. 1457 */ 1458 struct mlx5_devx_obj * 1459 mlx5_devx_cmd_create_td(void *ctx) 1460 { 1461 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1462 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1463 struct mlx5_devx_obj *td = NULL; 1464 1465 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1466 if (!td) { 1467 DRV_LOG(ERR, "Failed to allocate TD object"); 1468 rte_errno = ENOMEM; 1469 return NULL; 1470 } 1471 MLX5_SET(alloc_transport_domain_in, in, opcode, 1472 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1473 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1474 out, sizeof(out)); 1475 if (!td->obj) { 1476 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1477 rte_errno = errno; 1478 mlx5_free(td); 1479 return NULL; 1480 } 1481 td->id = MLX5_GET(alloc_transport_domain_out, out, 1482 transport_domain); 1483 return td; 1484 } 1485 1486 /** 1487 * Dump all flows to file. 1488 * 1489 * @param[in] fdb_domain 1490 * FDB domain. 1491 * @param[in] rx_domain 1492 * RX domain. 1493 * @param[in] tx_domain 1494 * TX domain. 1495 * @param[out] file 1496 * Pointer to file stream. 1497 * 1498 * @return 1499 * 0 on success, a nagative value otherwise. 1500 */ 1501 int 1502 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1503 void *rx_domain __rte_unused, 1504 void *tx_domain __rte_unused, FILE *file __rte_unused) 1505 { 1506 int ret = 0; 1507 1508 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1509 if (fdb_domain) { 1510 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1511 if (ret) 1512 return ret; 1513 } 1514 MLX5_ASSERT(rx_domain); 1515 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1516 if (ret) 1517 return ret; 1518 MLX5_ASSERT(tx_domain); 1519 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1520 #else 1521 ret = ENOTSUP; 1522 #endif 1523 return -ret; 1524 } 1525 1526 /* 1527 * Create CQ using DevX API. 1528 * 1529 * @param[in] ctx 1530 * Context returned from mlx5 open_device() glue function. 1531 * @param [in] attr 1532 * Pointer to CQ attributes structure. 1533 * 1534 * @return 1535 * The DevX object created, NULL otherwise and rte_errno is set. 1536 */ 1537 struct mlx5_devx_obj * 1538 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1539 { 1540 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1541 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1542 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1543 sizeof(*cq_obj), 1544 0, SOCKET_ID_ANY); 1545 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1546 1547 if (!cq_obj) { 1548 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1549 rte_errno = ENOMEM; 1550 return NULL; 1551 } 1552 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1553 if (attr->db_umem_valid) { 1554 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1555 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1556 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1557 } else { 1558 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1559 } 1560 MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size); 1561 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1562 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1563 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1564 MLX5_SET(cqc, cqctx, log_page_size, attr->log_page_size - 1565 MLX5_ADAPTER_PAGE_SHIFT); 1566 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1567 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1568 MLX5_SET(cqc, cqctx, cqe_comp_en, attr->cqe_comp_en); 1569 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1570 MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size); 1571 if (attr->q_umem_valid) { 1572 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1573 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1574 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1575 attr->q_umem_offset); 1576 } 1577 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1578 sizeof(out)); 1579 if (!cq_obj->obj) { 1580 rte_errno = errno; 1581 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1582 mlx5_free(cq_obj); 1583 return NULL; 1584 } 1585 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1586 return cq_obj; 1587 } 1588 1589 /** 1590 * Create VIRTQ using DevX API. 1591 * 1592 * @param[in] ctx 1593 * Context returned from mlx5 open_device() glue function. 1594 * @param [in] attr 1595 * Pointer to VIRTQ attributes structure. 1596 * 1597 * @return 1598 * The DevX object created, NULL otherwise and rte_errno is set. 1599 */ 1600 struct mlx5_devx_obj * 1601 mlx5_devx_cmd_create_virtq(void *ctx, 1602 struct mlx5_devx_virtq_attr *attr) 1603 { 1604 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1605 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1606 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1607 sizeof(*virtq_obj), 1608 0, SOCKET_ID_ANY); 1609 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1610 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1611 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1612 1613 if (!virtq_obj) { 1614 DRV_LOG(ERR, "Failed to allocate virtq data."); 1615 rte_errno = ENOMEM; 1616 return NULL; 1617 } 1618 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1619 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1620 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1621 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1622 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1623 attr->hw_available_index); 1624 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1625 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1626 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1627 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1628 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1629 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1630 attr->virtio_version_1_0); 1631 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1632 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1633 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1634 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1635 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1636 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1637 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1638 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1639 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1640 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 1641 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 1642 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 1643 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 1644 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 1645 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 1646 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 1647 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 1648 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 1649 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 1650 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 1651 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1652 sizeof(out)); 1653 if (!virtq_obj->obj) { 1654 rte_errno = errno; 1655 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 1656 mlx5_free(virtq_obj); 1657 return NULL; 1658 } 1659 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1660 return virtq_obj; 1661 } 1662 1663 /** 1664 * Modify VIRTQ using DevX API. 1665 * 1666 * @param[in] virtq_obj 1667 * Pointer to virtq object structure. 1668 * @param [in] attr 1669 * Pointer to modify virtq attributes structure. 1670 * 1671 * @return 1672 * 0 on success, a negative errno value otherwise and rte_errno is set. 1673 */ 1674 int 1675 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 1676 struct mlx5_devx_virtq_attr *attr) 1677 { 1678 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1679 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1680 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1681 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1682 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1683 int ret; 1684 1685 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1686 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 1687 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1688 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1689 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1690 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 1691 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1692 switch (attr->type) { 1693 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 1694 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 1695 break; 1696 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 1697 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 1698 attr->dirty_bitmap_mkey); 1699 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 1700 attr->dirty_bitmap_addr); 1701 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 1702 attr->dirty_bitmap_size); 1703 break; 1704 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 1705 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 1706 attr->dirty_bitmap_dump_enable); 1707 break; 1708 default: 1709 rte_errno = EINVAL; 1710 return -rte_errno; 1711 } 1712 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 1713 out, sizeof(out)); 1714 if (ret) { 1715 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1716 rte_errno = errno; 1717 return -rte_errno; 1718 } 1719 return ret; 1720 } 1721 1722 /** 1723 * Query VIRTQ using DevX API. 1724 * 1725 * @param[in] virtq_obj 1726 * Pointer to virtq object structure. 1727 * @param [in/out] attr 1728 * Pointer to virtq attributes structure. 1729 * 1730 * @return 1731 * 0 on success, a negative errno value otherwise and rte_errno is set. 1732 */ 1733 int 1734 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 1735 struct mlx5_devx_virtq_attr *attr) 1736 { 1737 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1738 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 1739 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 1740 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 1741 int ret; 1742 1743 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1744 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1745 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1746 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1747 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1748 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 1749 out, sizeof(out)); 1750 if (ret) { 1751 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1752 rte_errno = errno; 1753 return -errno; 1754 } 1755 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 1756 hw_available_index); 1757 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 1758 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 1759 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 1760 virtio_q_context.error_type); 1761 return ret; 1762 } 1763 1764 /** 1765 * Create QP using DevX API. 1766 * 1767 * @param[in] ctx 1768 * Context returned from mlx5 open_device() glue function. 1769 * @param [in] attr 1770 * Pointer to QP attributes structure. 1771 * 1772 * @return 1773 * The DevX object created, NULL otherwise and rte_errno is set. 1774 */ 1775 struct mlx5_devx_obj * 1776 mlx5_devx_cmd_create_qp(void *ctx, 1777 struct mlx5_devx_qp_attr *attr) 1778 { 1779 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 1780 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 1781 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 1782 sizeof(*qp_obj), 1783 0, SOCKET_ID_ANY); 1784 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1785 1786 if (!qp_obj) { 1787 DRV_LOG(ERR, "Failed to allocate QP data."); 1788 rte_errno = ENOMEM; 1789 return NULL; 1790 } 1791 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 1792 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 1793 MLX5_SET(qpc, qpc, pd, attr->pd); 1794 if (attr->uar_index) { 1795 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1796 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 1797 MLX5_SET(qpc, qpc, log_page_size, attr->log_page_size - 1798 MLX5_ADAPTER_PAGE_SHIFT); 1799 if (attr->sq_size) { 1800 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); 1801 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 1802 MLX5_SET(qpc, qpc, log_sq_size, 1803 rte_log2_u32(attr->sq_size)); 1804 } else { 1805 MLX5_SET(qpc, qpc, no_sq, 1); 1806 } 1807 if (attr->rq_size) { 1808 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); 1809 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 1810 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 1811 MLX5_LOG_RQ_STRIDE_SHIFT); 1812 MLX5_SET(qpc, qpc, log_rq_size, 1813 rte_log2_u32(attr->rq_size)); 1814 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 1815 } else { 1816 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1817 } 1818 if (attr->dbr_umem_valid) { 1819 MLX5_SET(qpc, qpc, dbr_umem_valid, 1820 attr->dbr_umem_valid); 1821 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 1822 } 1823 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 1824 MLX5_SET64(create_qp_in, in, wq_umem_offset, 1825 attr->wq_umem_offset); 1826 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 1827 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 1828 } else { 1829 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 1830 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1831 MLX5_SET(qpc, qpc, no_sq, 1); 1832 } 1833 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1834 sizeof(out)); 1835 if (!qp_obj->obj) { 1836 rte_errno = errno; 1837 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 1838 mlx5_free(qp_obj); 1839 return NULL; 1840 } 1841 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 1842 return qp_obj; 1843 } 1844 1845 /** 1846 * Modify QP using DevX API. 1847 * Currently supports only force loop-back QP. 1848 * 1849 * @param[in] qp 1850 * Pointer to QP object structure. 1851 * @param [in] qp_st_mod_op 1852 * The QP state modification operation. 1853 * @param [in] remote_qp_id 1854 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 1855 * 1856 * @return 1857 * 0 on success, a negative errno value otherwise and rte_errno is set. 1858 */ 1859 int 1860 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 1861 uint32_t remote_qp_id) 1862 { 1863 union { 1864 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 1865 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 1866 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 1867 } in; 1868 union { 1869 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 1870 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 1871 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 1872 } out; 1873 void *qpc; 1874 int ret; 1875 unsigned int inlen; 1876 unsigned int outlen; 1877 1878 memset(&in, 0, sizeof(in)); 1879 memset(&out, 0, sizeof(out)); 1880 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 1881 switch (qp_st_mod_op) { 1882 case MLX5_CMD_OP_RST2INIT_QP: 1883 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 1884 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 1885 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1886 MLX5_SET(qpc, qpc, rre, 1); 1887 MLX5_SET(qpc, qpc, rwe, 1); 1888 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1889 inlen = sizeof(in.rst2init); 1890 outlen = sizeof(out.rst2init); 1891 break; 1892 case MLX5_CMD_OP_INIT2RTR_QP: 1893 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 1894 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 1895 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 1896 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1897 MLX5_SET(qpc, qpc, mtu, 1); 1898 MLX5_SET(qpc, qpc, log_msg_max, 30); 1899 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 1900 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 1901 inlen = sizeof(in.init2rtr); 1902 outlen = sizeof(out.init2rtr); 1903 break; 1904 case MLX5_CMD_OP_RTR2RTS_QP: 1905 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 1906 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 1907 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 1908 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 1909 MLX5_SET(qpc, qpc, retry_count, 7); 1910 MLX5_SET(qpc, qpc, rnr_retry, 7); 1911 inlen = sizeof(in.rtr2rts); 1912 outlen = sizeof(out.rtr2rts); 1913 break; 1914 default: 1915 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 1916 qp_st_mod_op); 1917 rte_errno = EINVAL; 1918 return -rte_errno; 1919 } 1920 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 1921 if (ret) { 1922 DRV_LOG(ERR, "Failed to modify QP using DevX."); 1923 rte_errno = errno; 1924 return -rte_errno; 1925 } 1926 return ret; 1927 } 1928 1929 struct mlx5_devx_obj * 1930 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 1931 { 1932 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 1933 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1934 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 1935 sizeof(*couners_obj), 0, 1936 SOCKET_ID_ANY); 1937 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 1938 1939 if (!couners_obj) { 1940 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 1941 rte_errno = ENOMEM; 1942 return NULL; 1943 } 1944 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1945 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1946 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1947 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 1948 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1949 sizeof(out)); 1950 if (!couners_obj->obj) { 1951 rte_errno = errno; 1952 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 1953 " DevX."); 1954 mlx5_free(couners_obj); 1955 return NULL; 1956 } 1957 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1958 return couners_obj; 1959 } 1960 1961 int 1962 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 1963 struct mlx5_devx_virtio_q_couners_attr *attr) 1964 { 1965 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1966 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 1967 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 1968 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 1969 virtio_q_counters); 1970 int ret; 1971 1972 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1973 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1974 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1975 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 1976 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 1977 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 1978 sizeof(out)); 1979 if (ret) { 1980 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 1981 rte_errno = errno; 1982 return -errno; 1983 } 1984 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 1985 received_desc); 1986 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 1987 completed_desc); 1988 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 1989 error_cqes); 1990 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 1991 bad_desc_errors); 1992 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 1993 exceed_max_chain); 1994 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 1995 invalid_buffer); 1996 return ret; 1997 } 1998