1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 static void * 17 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, 18 int *err, uint32_t flags) 19 { 20 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); 21 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); 22 int status, syndrome, rc; 23 24 if (err) 25 *err = 0; 26 memset(in, 0, size_in); 27 memset(out, 0, size_out); 28 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 29 MLX5_SET(query_hca_cap_in, in, op_mod, flags); 30 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); 31 if (rc) { 32 DRV_LOG(ERR, 33 "Failed to query devx HCA capabilities func %#02x", 34 flags >> 1); 35 if (err) 36 *err = rc > 0 ? -rc : rc; 37 return NULL; 38 } 39 status = MLX5_GET(query_hca_cap_out, out, status); 40 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 41 if (status) { 42 DRV_LOG(ERR, 43 "Failed to query devx HCA capabilities func %#02x status %x, syndrome = %x", 44 flags >> 1, status, syndrome); 45 if (err) 46 *err = -1; 47 return NULL; 48 } 49 return MLX5_ADDR_OF(query_hca_cap_out, out, capability); 50 } 51 52 /** 53 * Perform read access to the registers. Reads data from register 54 * and writes ones to the specified buffer. 55 * 56 * @param[in] ctx 57 * Context returned from mlx5 open_device() glue function. 58 * @param[in] reg_id 59 * Register identifier according to the PRM. 60 * @param[in] arg 61 * Register access auxiliary parameter according to the PRM. 62 * @param[out] data 63 * Pointer to the buffer to store read data. 64 * @param[in] dw_cnt 65 * Buffer size in double words. 66 * 67 * @return 68 * 0 on success, a negative value otherwise. 69 */ 70 int 71 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 72 uint32_t *data, uint32_t dw_cnt) 73 { 74 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 75 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 76 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 77 int status, rc; 78 79 MLX5_ASSERT(data && dw_cnt); 80 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 81 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 82 DRV_LOG(ERR, "Not enough buffer for register read data"); 83 return -1; 84 } 85 MLX5_SET(access_register_in, in, opcode, 86 MLX5_CMD_OP_ACCESS_REGISTER_USER); 87 MLX5_SET(access_register_in, in, op_mod, 88 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 89 MLX5_SET(access_register_in, in, register_id, reg_id); 90 MLX5_SET(access_register_in, in, argument, arg); 91 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 92 MLX5_ST_SZ_BYTES(access_register_out) + 93 sizeof(uint32_t) * dw_cnt); 94 if (rc) 95 goto error; 96 status = MLX5_GET(access_register_out, out, status); 97 if (status) { 98 int syndrome = MLX5_GET(access_register_out, out, syndrome); 99 100 DRV_LOG(DEBUG, "Failed to read access NIC register 0x%X, " 101 "status %x, syndrome = %x", 102 reg_id, status, syndrome); 103 return -1; 104 } 105 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 106 dw_cnt * sizeof(uint32_t)); 107 return 0; 108 error: 109 rc = (rc > 0) ? -rc : rc; 110 return rc; 111 } 112 113 /** 114 * Perform write access to the registers. 115 * 116 * @param[in] ctx 117 * Context returned from mlx5 open_device() glue function. 118 * @param[in] reg_id 119 * Register identifier according to the PRM. 120 * @param[in] arg 121 * Register access auxiliary parameter according to the PRM. 122 * @param[out] data 123 * Pointer to the buffer containing data to write. 124 * @param[in] dw_cnt 125 * Buffer size in double words (32bit units). 126 * 127 * @return 128 * 0 on success, a negative value otherwise. 129 */ 130 int 131 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 132 uint32_t *data, uint32_t dw_cnt) 133 { 134 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 135 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 136 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 137 int status, rc; 138 void *ptr; 139 140 MLX5_ASSERT(data && dw_cnt); 141 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 142 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 143 DRV_LOG(ERR, "Data to write exceeds max size"); 144 return -1; 145 } 146 MLX5_SET(access_register_in, in, opcode, 147 MLX5_CMD_OP_ACCESS_REGISTER_USER); 148 MLX5_SET(access_register_in, in, op_mod, 149 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 150 MLX5_SET(access_register_in, in, register_id, reg_id); 151 MLX5_SET(access_register_in, in, argument, arg); 152 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 153 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 154 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 155 156 rc = mlx5_glue->devx_general_cmd(ctx, in, 157 MLX5_ST_SZ_BYTES(access_register_in) + 158 dw_cnt * sizeof(uint32_t), 159 out, sizeof(out)); 160 if (rc) 161 goto error; 162 status = MLX5_GET(access_register_out, out, status); 163 if (status) { 164 int syndrome = MLX5_GET(access_register_out, out, syndrome); 165 166 DRV_LOG(DEBUG, "Failed to write access NIC register 0x%X, " 167 "status %x, syndrome = %x", 168 reg_id, status, syndrome); 169 return -1; 170 } 171 return 0; 172 error: 173 rc = (rc > 0) ? -rc : rc; 174 return rc; 175 } 176 177 /** 178 * Allocate flow counters via devx interface. 179 * 180 * @param[in] ctx 181 * Context returned from mlx5 open_device() glue function. 182 * @param dcs 183 * Pointer to counters properties structure to be filled by the routine. 184 * @param bulk_n_128 185 * Bulk counter numbers in 128 counters units. 186 * 187 * @return 188 * Pointer to counter object on success, a negative value otherwise and 189 * rte_errno is set. 190 */ 191 struct mlx5_devx_obj * 192 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 193 { 194 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 195 0, SOCKET_ID_ANY); 196 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 197 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 198 199 if (!dcs) { 200 rte_errno = ENOMEM; 201 return NULL; 202 } 203 MLX5_SET(alloc_flow_counter_in, in, opcode, 204 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 205 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 206 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 207 sizeof(in), out, sizeof(out)); 208 if (!dcs->obj) { 209 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 210 rte_errno = errno; 211 mlx5_free(dcs); 212 return NULL; 213 } 214 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 215 return dcs; 216 } 217 218 /** 219 * Query flow counters values. 220 * 221 * @param[in] dcs 222 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 223 * @param[in] clear 224 * Whether hardware should clear the counters after the query or not. 225 * @param[in] n_counters 226 * 0 in case of 1 counter to read, otherwise the counter number to read. 227 * @param pkts 228 * The number of packets that matched the flow. 229 * @param bytes 230 * The number of bytes that matched the flow. 231 * @param mkey 232 * The mkey key for batch query. 233 * @param addr 234 * The address in the mkey range for batch query. 235 * @param cmd_comp 236 * The completion object for asynchronous batch query. 237 * @param async_id 238 * The ID to be returned in the asynchronous batch query response. 239 * 240 * @return 241 * 0 on success, a negative value otherwise. 242 */ 243 int 244 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 245 int clear, uint32_t n_counters, 246 uint64_t *pkts, uint64_t *bytes, 247 uint32_t mkey, void *addr, 248 void *cmd_comp, 249 uint64_t async_id) 250 { 251 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 252 MLX5_ST_SZ_BYTES(traffic_counter); 253 uint32_t out[out_len]; 254 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 255 void *stats; 256 int rc; 257 258 MLX5_SET(query_flow_counter_in, in, opcode, 259 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 260 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 261 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 262 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 263 264 if (n_counters) { 265 MLX5_SET(query_flow_counter_in, in, num_of_counters, 266 n_counters); 267 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 268 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 269 MLX5_SET64(query_flow_counter_in, in, address, 270 (uint64_t)(uintptr_t)addr); 271 } 272 if (!cmd_comp) 273 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 274 out_len); 275 else 276 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 277 out_len, async_id, 278 cmd_comp); 279 if (rc) { 280 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 281 rte_errno = rc; 282 return -rc; 283 } 284 if (!n_counters) { 285 stats = MLX5_ADDR_OF(query_flow_counter_out, 286 out, flow_statistics); 287 *pkts = MLX5_GET64(traffic_counter, stats, packets); 288 *bytes = MLX5_GET64(traffic_counter, stats, octets); 289 } 290 return 0; 291 } 292 293 /** 294 * Create a new mkey. 295 * 296 * @param[in] ctx 297 * Context returned from mlx5 open_device() glue function. 298 * @param[in] attr 299 * Attributes of the requested mkey. 300 * 301 * @return 302 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 303 * is set. 304 */ 305 struct mlx5_devx_obj * 306 mlx5_devx_cmd_mkey_create(void *ctx, 307 struct mlx5_devx_mkey_attr *attr) 308 { 309 struct mlx5_klm *klm_array = attr->klm_array; 310 int klm_num = attr->klm_num; 311 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 312 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 313 uint32_t in[in_size_dw]; 314 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 315 void *mkc; 316 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 317 0, SOCKET_ID_ANY); 318 size_t pgsize; 319 uint32_t translation_size; 320 321 if (!mkey) { 322 rte_errno = ENOMEM; 323 return NULL; 324 } 325 memset(in, 0, in_size_dw * 4); 326 pgsize = rte_mem_page_size(); 327 if (pgsize == (size_t)-1) { 328 mlx5_free(mkey); 329 DRV_LOG(ERR, "Failed to get page size"); 330 rte_errno = ENOMEM; 331 return NULL; 332 } 333 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 334 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 335 if (klm_num > 0) { 336 int i; 337 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 338 klm_pas_mtt); 339 translation_size = RTE_ALIGN(klm_num, 4); 340 for (i = 0; i < klm_num; i++) { 341 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 342 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 343 MLX5_SET64(klm, klm, address, klm_array[i].address); 344 klm += MLX5_ST_SZ_BYTES(klm); 345 } 346 for (; i < (int)translation_size; i++) { 347 MLX5_SET(klm, klm, mkey, 0x0); 348 MLX5_SET64(klm, klm, address, 0x0); 349 klm += MLX5_ST_SZ_BYTES(klm); 350 } 351 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 352 MLX5_MKC_ACCESS_MODE_KLM_FBS : 353 MLX5_MKC_ACCESS_MODE_KLM); 354 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 355 } else { 356 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 357 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 358 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 359 } 360 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 361 translation_size); 362 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 363 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 364 MLX5_SET(mkc, mkc, lw, 0x1); 365 MLX5_SET(mkc, mkc, lr, 0x1); 366 if (attr->set_remote_rw) { 367 MLX5_SET(mkc, mkc, rw, 0x1); 368 MLX5_SET(mkc, mkc, rr, 0x1); 369 } 370 MLX5_SET(mkc, mkc, qpn, 0xffffff); 371 MLX5_SET(mkc, mkc, pd, attr->pd); 372 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 373 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 374 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 375 MLX5_SET(mkc, mkc, relaxed_ordering_write, 376 attr->relaxed_ordering_write); 377 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 378 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 379 MLX5_SET64(mkc, mkc, len, attr->size); 380 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 381 if (attr->crypto_en) { 382 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 383 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 384 } 385 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 386 sizeof(out)); 387 if (!mkey->obj) { 388 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d", 389 klm_num ? "an in" : "a ", errno); 390 rte_errno = errno; 391 mlx5_free(mkey); 392 return NULL; 393 } 394 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 395 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 396 return mkey; 397 } 398 399 /** 400 * Get status of devx command response. 401 * Mainly used for asynchronous commands. 402 * 403 * @param[in] out 404 * The out response buffer. 405 * 406 * @return 407 * 0 on success, non-zero value otherwise. 408 */ 409 int 410 mlx5_devx_get_out_command_status(void *out) 411 { 412 int status; 413 414 if (!out) 415 return -EINVAL; 416 status = MLX5_GET(query_flow_counter_out, out, status); 417 if (status) { 418 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 419 420 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 421 syndrome); 422 } 423 return status; 424 } 425 426 /** 427 * Destroy any object allocated by a Devx API. 428 * 429 * @param[in] obj 430 * Pointer to a general object. 431 * 432 * @return 433 * 0 on success, a negative value otherwise. 434 */ 435 int 436 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 437 { 438 int ret; 439 440 if (!obj) 441 return 0; 442 ret = mlx5_glue->devx_obj_destroy(obj->obj); 443 mlx5_free(obj); 444 return ret; 445 } 446 447 /** 448 * Query NIC vport context. 449 * Fills minimal inline attribute. 450 * 451 * @param[in] ctx 452 * ibv contexts returned from mlx5dv_open_device. 453 * @param[in] vport 454 * vport index 455 * @param[out] attr 456 * Attributes device values. 457 * 458 * @return 459 * 0 on success, a negative value otherwise. 460 */ 461 static int 462 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 463 unsigned int vport, 464 struct mlx5_hca_attr *attr) 465 { 466 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 467 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 468 void *vctx; 469 int status, syndrome, rc; 470 471 /* Query NIC vport context to determine inline mode. */ 472 MLX5_SET(query_nic_vport_context_in, in, opcode, 473 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 474 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 475 if (vport) 476 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 477 rc = mlx5_glue->devx_general_cmd(ctx, 478 in, sizeof(in), 479 out, sizeof(out)); 480 if (rc) 481 goto error; 482 status = MLX5_GET(query_nic_vport_context_out, out, status); 483 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 484 if (status) { 485 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 486 "status %x, syndrome = %x", status, syndrome); 487 return -1; 488 } 489 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 490 nic_vport_context); 491 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 492 min_wqe_inline_mode); 493 return 0; 494 error: 495 rc = (rc > 0) ? -rc : rc; 496 return rc; 497 } 498 499 /** 500 * Query NIC vDPA attributes. 501 * 502 * @param[in] ctx 503 * Context returned from mlx5 open_device() glue function. 504 * @param[out] vdpa_attr 505 * vDPA Attributes structure to fill. 506 */ 507 static void 508 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 509 struct mlx5_hca_vdpa_attr *vdpa_attr) 510 { 511 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 512 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 513 void *hcattr; 514 515 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, 516 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 517 MLX5_HCA_CAP_OPMOD_GET_CUR); 518 if (!hcattr) { 519 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities"); 520 vdpa_attr->valid = 0; 521 } else { 522 vdpa_attr->valid = 1; 523 vdpa_attr->desc_tunnel_offload_type = 524 MLX5_GET(virtio_emulation_cap, hcattr, 525 desc_tunnel_offload_type); 526 vdpa_attr->eth_frame_offload_type = 527 MLX5_GET(virtio_emulation_cap, hcattr, 528 eth_frame_offload_type); 529 vdpa_attr->virtio_version_1_0 = 530 MLX5_GET(virtio_emulation_cap, hcattr, 531 virtio_version_1_0); 532 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 533 tso_ipv4); 534 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 535 tso_ipv6); 536 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 537 tx_csum); 538 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 539 rx_csum); 540 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 541 event_mode); 542 vdpa_attr->virtio_queue_type = 543 MLX5_GET(virtio_emulation_cap, hcattr, 544 virtio_queue_type); 545 vdpa_attr->log_doorbell_stride = 546 MLX5_GET(virtio_emulation_cap, hcattr, 547 log_doorbell_stride); 548 vdpa_attr->log_doorbell_bar_size = 549 MLX5_GET(virtio_emulation_cap, hcattr, 550 log_doorbell_bar_size); 551 vdpa_attr->doorbell_bar_offset = 552 MLX5_GET64(virtio_emulation_cap, hcattr, 553 doorbell_bar_offset); 554 vdpa_attr->max_num_virtio_queues = 555 MLX5_GET(virtio_emulation_cap, hcattr, 556 max_num_virtio_queues); 557 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 558 umem_1_buffer_param_a); 559 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 560 umem_1_buffer_param_b); 561 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 562 umem_2_buffer_param_a); 563 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 564 umem_2_buffer_param_b); 565 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 566 umem_3_buffer_param_a); 567 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 568 umem_3_buffer_param_b); 569 } 570 } 571 572 int 573 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 574 uint32_t ids[], uint32_t num) 575 { 576 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 577 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 578 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 579 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 580 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 581 int ret; 582 uint32_t idx = 0; 583 uint32_t i; 584 585 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 586 rte_errno = EINVAL; 587 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 588 return -rte_errno; 589 } 590 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 591 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 592 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 593 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 594 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 595 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 596 out, sizeof(out)); 597 if (ret) { 598 rte_errno = ret; 599 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 600 (void *)flex_obj); 601 return -rte_errno; 602 } 603 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 604 void *s_off = (void *)((char *)sample + i * 605 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 606 uint32_t en; 607 608 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 609 flow_match_sample_en); 610 if (!en) 611 continue; 612 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 613 flow_match_sample_field_id); 614 } 615 if (num != idx) { 616 rte_errno = EINVAL; 617 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 618 return -rte_errno; 619 } 620 return ret; 621 } 622 623 struct mlx5_devx_obj * 624 mlx5_devx_cmd_create_flex_parser(void *ctx, 625 struct mlx5_devx_graph_node_attr *data) 626 { 627 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 628 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 629 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 630 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 631 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 632 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 633 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 634 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 635 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 636 uint32_t i; 637 638 if (!parse_flex_obj) { 639 DRV_LOG(ERR, "Failed to allocate flex parser data."); 640 rte_errno = ENOMEM; 641 return NULL; 642 } 643 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 644 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 645 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 646 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 647 MLX5_SET(parse_graph_flex, flex, header_length_mode, 648 data->header_length_mode); 649 MLX5_SET64(parse_graph_flex, flex, modify_field_select, 650 data->modify_field_select); 651 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 652 data->header_length_base_value); 653 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 654 data->header_length_field_offset); 655 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 656 data->header_length_field_shift); 657 MLX5_SET(parse_graph_flex, flex, next_header_field_offset, 658 data->next_header_field_offset); 659 MLX5_SET(parse_graph_flex, flex, next_header_field_size, 660 data->next_header_field_size); 661 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 662 data->header_length_field_mask); 663 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 664 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 665 void *s_off = (void *)((char *)sample + i * 666 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 667 668 if (!s->flow_match_sample_en) 669 continue; 670 MLX5_SET(parse_graph_flow_match_sample, s_off, 671 flow_match_sample_en, !!s->flow_match_sample_en); 672 MLX5_SET(parse_graph_flow_match_sample, s_off, 673 flow_match_sample_field_offset, 674 s->flow_match_sample_field_offset); 675 MLX5_SET(parse_graph_flow_match_sample, s_off, 676 flow_match_sample_offset_mode, 677 s->flow_match_sample_offset_mode); 678 MLX5_SET(parse_graph_flow_match_sample, s_off, 679 flow_match_sample_field_offset_mask, 680 s->flow_match_sample_field_offset_mask); 681 MLX5_SET(parse_graph_flow_match_sample, s_off, 682 flow_match_sample_field_offset_shift, 683 s->flow_match_sample_field_offset_shift); 684 MLX5_SET(parse_graph_flow_match_sample, s_off, 685 flow_match_sample_field_base_offset, 686 s->flow_match_sample_field_base_offset); 687 MLX5_SET(parse_graph_flow_match_sample, s_off, 688 flow_match_sample_tunnel_mode, 689 s->flow_match_sample_tunnel_mode); 690 } 691 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 692 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 693 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 694 void *in_off = (void *)((char *)in_arc + i * 695 MLX5_ST_SZ_BYTES(parse_graph_arc)); 696 void *out_off = (void *)((char *)out_arc + i * 697 MLX5_ST_SZ_BYTES(parse_graph_arc)); 698 699 if (ia->arc_parse_graph_node != 0) { 700 MLX5_SET(parse_graph_arc, in_off, 701 compare_condition_value, 702 ia->compare_condition_value); 703 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 704 ia->start_inner_tunnel); 705 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 706 ia->arc_parse_graph_node); 707 MLX5_SET(parse_graph_arc, in_off, 708 parse_graph_node_handle, 709 ia->parse_graph_node_handle); 710 } 711 if (oa->arc_parse_graph_node != 0) { 712 MLX5_SET(parse_graph_arc, out_off, 713 compare_condition_value, 714 oa->compare_condition_value); 715 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 716 oa->start_inner_tunnel); 717 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 718 oa->arc_parse_graph_node); 719 MLX5_SET(parse_graph_arc, out_off, 720 parse_graph_node_handle, 721 oa->parse_graph_node_handle); 722 } 723 } 724 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 725 out, sizeof(out)); 726 if (!parse_flex_obj->obj) { 727 rte_errno = errno; 728 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 729 "by using DevX."); 730 mlx5_free(parse_flex_obj); 731 return NULL; 732 } 733 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 734 return parse_flex_obj; 735 } 736 737 static int 738 mlx5_devx_cmd_query_hca_parse_graph_node_cap 739 (void *ctx, struct mlx5_hca_flex_attr *attr) 740 { 741 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 742 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 743 void *hcattr; 744 int rc; 745 746 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 747 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | 748 MLX5_HCA_CAP_OPMOD_GET_CUR); 749 if (!hcattr) 750 return rc; 751 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); 752 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); 753 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, 754 header_length_mode); 755 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, 756 sample_offset_mode); 757 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, 758 max_num_arc_in); 759 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, 760 max_num_arc_out); 761 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, 762 max_num_sample); 763 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, 764 sample_id_in_out); 765 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, 766 max_base_header_length); 767 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, 768 max_sample_base_offset); 769 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, 770 max_next_header_offset); 771 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, 772 header_length_mask_width); 773 /* Get the max supported samples from HCA CAP 2 */ 774 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 775 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 776 MLX5_HCA_CAP_OPMOD_GET_CUR); 777 if (!hcattr) 778 return rc; 779 attr->max_num_prog_sample = 780 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); 781 return 0; 782 } 783 784 static int 785 mlx5_devx_query_pkt_integrity_match(void *hcattr) 786 { 787 return MLX5_GET(flow_table_nic_cap, hcattr, 788 ft_field_support_2_nic_receive.inner_l3_ok) && 789 MLX5_GET(flow_table_nic_cap, hcattr, 790 ft_field_support_2_nic_receive.inner_l4_ok) && 791 MLX5_GET(flow_table_nic_cap, hcattr, 792 ft_field_support_2_nic_receive.outer_l3_ok) && 793 MLX5_GET(flow_table_nic_cap, hcattr, 794 ft_field_support_2_nic_receive.outer_l4_ok) && 795 MLX5_GET(flow_table_nic_cap, hcattr, 796 ft_field_support_2_nic_receive 797 .inner_ipv4_checksum_ok) && 798 MLX5_GET(flow_table_nic_cap, hcattr, 799 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 800 MLX5_GET(flow_table_nic_cap, hcattr, 801 ft_field_support_2_nic_receive 802 .outer_ipv4_checksum_ok) && 803 MLX5_GET(flow_table_nic_cap, hcattr, 804 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 805 } 806 807 /** 808 * Query HCA attributes. 809 * Using those attributes we can check on run time if the device 810 * is having the required capabilities. 811 * 812 * @param[in] ctx 813 * Context returned from mlx5 open_device() glue function. 814 * @param[out] attr 815 * Attributes device values. 816 * 817 * @return 818 * 0 on success, a negative value otherwise. 819 */ 820 int 821 mlx5_devx_cmd_query_hca_attr(void *ctx, 822 struct mlx5_hca_attr *attr) 823 { 824 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 825 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 826 bool hca_cap_2_sup; 827 uint64_t general_obj_types_supported = 0; 828 void *hcattr; 829 int rc, i; 830 831 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 832 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 833 MLX5_HCA_CAP_OPMOD_GET_CUR); 834 if (!hcattr) 835 return rc; 836 hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2); 837 attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq); 838 attr->flow_counter_bulk_alloc_bitmap = 839 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 840 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 841 flow_counters_dump); 842 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp); 843 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp); 844 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 845 log_max_rqt_size); 846 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 847 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 848 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 849 log_max_hairpin_queues); 850 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 851 log_max_hairpin_wq_data_sz); 852 attr->log_max_hairpin_num_packets = MLX5_GET 853 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 854 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 855 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 856 relaxed_ordering_write); 857 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 858 relaxed_ordering_read); 859 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 860 access_register_user); 861 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 862 eth_net_offloads); 863 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 864 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 865 flex_parser_protocols); 866 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 867 max_geneve_tlv_options); 868 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 869 max_geneve_tlv_option_data_len); 870 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 871 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 872 general_obj_types) & 873 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 874 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 875 general_obj_types) & 876 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 877 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 878 general_obj_types) & 879 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 880 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 881 general_obj_types) & 882 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 883 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 884 wqe_index_ignore_cap); 885 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 886 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 887 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 888 log_max_static_sq_wq); 889 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 890 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 891 device_frequency_khz); 892 attr->scatter_fcs_w_decap_disable = 893 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 894 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 895 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 896 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 897 attr->steering_format_version = 898 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 899 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 900 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 901 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 902 regexp_num_of_engines); 903 /* Read the general_obj_types bitmap and extract the relevant bits. */ 904 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 905 general_obj_types); 906 attr->vdpa.valid = !!(general_obj_types_supported & 907 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 908 attr->vdpa.queue_counters_valid = 909 !!(general_obj_types_supported & 910 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 911 attr->parse_graph_flex_node = 912 !!(general_obj_types_supported & 913 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 914 attr->flow_hit_aso = !!(general_obj_types_supported & 915 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 916 attr->geneve_tlv_opt = !!(general_obj_types_supported & 917 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 918 attr->dek = !!(general_obj_types_supported & 919 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 920 attr->import_kek = !!(general_obj_types_supported & 921 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 922 attr->credential = !!(general_obj_types_supported & 923 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 924 attr->crypto_login = !!(general_obj_types_supported & 925 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 926 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 927 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 928 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 929 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 930 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 931 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 932 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 933 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 934 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 935 attr->reg_c_preserve = 936 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 937 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 938 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 939 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 940 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 941 compress_mmo_sq); 942 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 943 decompress_mmo_sq); 944 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 945 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 946 compress_mmo_qp); 947 attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 948 decompress_mmo_qp); 949 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 950 compress_min_block_size); 951 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 952 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 953 log_compress_mmo_size); 954 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 955 log_decompress_mmo_size); 956 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 957 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 958 mini_cqe_resp_flow_tag); 959 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 960 mini_cqe_resp_l3_l4_tag); 961 attr->umr_indirect_mkey_disabled = 962 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 963 attr->umr_modify_entity_size_disabled = 964 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 965 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 966 if (attr->crypto) 967 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts); 968 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 969 general_obj_types) & 970 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 971 attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); 972 if (hca_cap_2_sup) { 973 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 974 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 975 MLX5_HCA_CAP_OPMOD_GET_CUR); 976 if (!hcattr) { 977 DRV_LOG(DEBUG, 978 "Failed to query DevX HCA capabilities 2."); 979 return rc; 980 } 981 attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, 982 log_min_stride_wqe_sz); 983 } 984 if (attr->log_min_stride_wqe_sz == 0) 985 attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 986 if (attr->qos.sup) { 987 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 988 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 989 MLX5_HCA_CAP_OPMOD_GET_CUR); 990 if (!hcattr) { 991 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); 992 return rc; 993 } 994 attr->qos.flow_meter_old = 995 MLX5_GET(qos_cap, hcattr, flow_meter_old); 996 attr->qos.log_max_flow_meter = 997 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 998 attr->qos.flow_meter_reg_c_ids = 999 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 1000 attr->qos.flow_meter = 1001 MLX5_GET(qos_cap, hcattr, flow_meter); 1002 attr->qos.packet_pacing = 1003 MLX5_GET(qos_cap, hcattr, packet_pacing); 1004 attr->qos.wqe_rate_pp = 1005 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 1006 if (attr->qos.flow_meter_aso_sup) { 1007 attr->qos.log_meter_aso_granularity = 1008 MLX5_GET(qos_cap, hcattr, 1009 log_meter_aso_granularity); 1010 attr->qos.log_meter_aso_max_alloc = 1011 MLX5_GET(qos_cap, hcattr, 1012 log_meter_aso_max_alloc); 1013 attr->qos.log_max_num_meter_aso = 1014 MLX5_GET(qos_cap, hcattr, 1015 log_max_num_meter_aso); 1016 } 1017 } 1018 /* 1019 * Flex item support needs max_num_prog_sample_field 1020 * from the Capabilities 2 table for PARSE_GRAPH_NODE 1021 */ 1022 if (attr->parse_graph_flex_node) { 1023 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap 1024 (ctx, &attr->flex); 1025 if (rc) 1026 return -1; 1027 } 1028 if (attr->vdpa.valid) 1029 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 1030 if (!attr->eth_net_offloads) 1031 return 0; 1032 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 1033 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1034 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 1035 MLX5_HCA_CAP_OPMOD_GET_CUR); 1036 if (!hcattr) { 1037 attr->log_max_ft_sampler_num = 0; 1038 return rc; 1039 } 1040 attr->log_max_ft_sampler_num = MLX5_GET 1041 (flow_table_nic_cap, hcattr, 1042 flow_table_properties_nic_receive.log_max_ft_sampler_num); 1043 attr->flow.tunnel_header_0_1 = MLX5_GET 1044 (flow_table_nic_cap, hcattr, 1045 ft_field_support_2_nic_receive.tunnel_header_0_1); 1046 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 1047 attr->inner_ipv4_ihl = MLX5_GET 1048 (flow_table_nic_cap, hcattr, 1049 ft_field_support_2_nic_receive.inner_ipv4_ihl); 1050 attr->outer_ipv4_ihl = MLX5_GET 1051 (flow_table_nic_cap, hcattr, 1052 ft_field_support_2_nic_receive.outer_ipv4_ihl); 1053 /* Query HCA offloads for Ethernet protocol. */ 1054 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1055 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 1056 MLX5_HCA_CAP_OPMOD_GET_CUR); 1057 if (!hcattr) { 1058 attr->eth_net_offloads = 0; 1059 return rc; 1060 } 1061 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 1062 hcattr, wqe_vlan_insert); 1063 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 1064 hcattr, csum_cap); 1065 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 1066 hcattr, vlan_cap); 1067 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1068 lro_cap); 1069 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1070 hcattr, max_lso_cap); 1071 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1072 hcattr, scatter_fcs); 1073 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1074 hcattr, tunnel_lro_gre); 1075 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1076 hcattr, tunnel_lro_vxlan); 1077 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1078 hcattr, swp); 1079 attr->tunnel_stateless_gre = 1080 MLX5_GET(per_protocol_networking_offload_caps, 1081 hcattr, tunnel_stateless_gre); 1082 attr->tunnel_stateless_vxlan = 1083 MLX5_GET(per_protocol_networking_offload_caps, 1084 hcattr, tunnel_stateless_vxlan); 1085 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1086 hcattr, swp_csum); 1087 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1088 hcattr, swp_lso); 1089 attr->lro_max_msg_sz_mode = MLX5_GET 1090 (per_protocol_networking_offload_caps, 1091 hcattr, lro_max_msg_sz_mode); 1092 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1093 attr->lro_timer_supported_periods[i] = 1094 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1095 lro_timer_supported_periods[i]); 1096 } 1097 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1098 hcattr, lro_min_mss_size); 1099 attr->tunnel_stateless_geneve_rx = 1100 MLX5_GET(per_protocol_networking_offload_caps, 1101 hcattr, tunnel_stateless_geneve_rx); 1102 attr->geneve_max_opt_len = 1103 MLX5_GET(per_protocol_networking_offload_caps, 1104 hcattr, max_geneve_opt_len); 1105 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1106 hcattr, wqe_inline_mode); 1107 attr->tunnel_stateless_gtp = MLX5_GET 1108 (per_protocol_networking_offload_caps, 1109 hcattr, tunnel_stateless_gtp); 1110 attr->rss_ind_tbl_cap = MLX5_GET 1111 (per_protocol_networking_offload_caps, 1112 hcattr, rss_ind_tbl_cap); 1113 /* Query HCA attribute for ROCE. */ 1114 if (attr->roce) { 1115 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1116 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1117 MLX5_HCA_CAP_OPMOD_GET_CUR); 1118 if (!hcattr) { 1119 DRV_LOG(DEBUG, 1120 "Failed to query devx HCA ROCE capabilities"); 1121 return rc; 1122 } 1123 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1124 } 1125 if (attr->eth_virt && 1126 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1127 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1128 if (rc) { 1129 attr->eth_virt = 0; 1130 goto error; 1131 } 1132 } 1133 if (attr->eswitch_manager) { 1134 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1135 MLX5_SET_HCA_CAP_OP_MOD_ESW | 1136 MLX5_HCA_CAP_OPMOD_GET_CUR); 1137 if (!hcattr) 1138 return rc; 1139 attr->esw_mgr_vport_id_valid = 1140 MLX5_GET(esw_cap, hcattr, 1141 esw_manager_vport_number_valid); 1142 attr->esw_mgr_vport_id = 1143 MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); 1144 } 1145 return 0; 1146 error: 1147 rc = (rc > 0) ? -rc : rc; 1148 return rc; 1149 } 1150 1151 /** 1152 * Query TIS transport domain from QP verbs object using DevX API. 1153 * 1154 * @param[in] qp 1155 * Pointer to verbs QP returned by ibv_create_qp . 1156 * @param[in] tis_num 1157 * TIS number of TIS to query. 1158 * @param[out] tis_td 1159 * Pointer to TIS transport domain variable, to be set by the routine. 1160 * 1161 * @return 1162 * 0 on success, a negative value otherwise. 1163 */ 1164 int 1165 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1166 uint32_t *tis_td) 1167 { 1168 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1169 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1170 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1171 int rc; 1172 void *tis_ctx; 1173 1174 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1175 MLX5_SET(query_tis_in, in, tisn, tis_num); 1176 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1177 if (rc) { 1178 DRV_LOG(ERR, "Failed to query QP using DevX"); 1179 return -rc; 1180 }; 1181 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1182 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1183 return 0; 1184 #else 1185 (void)qp; 1186 (void)tis_num; 1187 (void)tis_td; 1188 return -ENOTSUP; 1189 #endif 1190 } 1191 1192 /** 1193 * Fill WQ data for DevX API command. 1194 * Utility function for use when creating DevX objects containing a WQ. 1195 * 1196 * @param[in] wq_ctx 1197 * Pointer to WQ context to fill with data. 1198 * @param [in] wq_attr 1199 * Pointer to WQ attributes structure to fill in WQ context. 1200 */ 1201 static void 1202 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1203 { 1204 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1205 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1206 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1207 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1208 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1209 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1210 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1211 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1212 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1213 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1214 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1215 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1216 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1217 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1218 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1219 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1220 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1221 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1222 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1223 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1224 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1225 wq_attr->log_hairpin_num_packets); 1226 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1227 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1228 wq_attr->single_wqe_log_num_of_strides); 1229 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1230 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1231 wq_attr->single_stride_log_num_of_bytes); 1232 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1233 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1234 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1235 } 1236 1237 /** 1238 * Create RQ using DevX API. 1239 * 1240 * @param[in] ctx 1241 * Context returned from mlx5 open_device() glue function. 1242 * @param [in] rq_attr 1243 * Pointer to create RQ attributes structure. 1244 * @param [in] socket 1245 * CPU socket ID for allocations. 1246 * 1247 * @return 1248 * The DevX object created, NULL otherwise and rte_errno is set. 1249 */ 1250 struct mlx5_devx_obj * 1251 mlx5_devx_cmd_create_rq(void *ctx, 1252 struct mlx5_devx_create_rq_attr *rq_attr, 1253 int socket) 1254 { 1255 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1256 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1257 void *rq_ctx, *wq_ctx; 1258 struct mlx5_devx_wq_attr *wq_attr; 1259 struct mlx5_devx_obj *rq = NULL; 1260 1261 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1262 if (!rq) { 1263 DRV_LOG(ERR, "Failed to allocate RQ data"); 1264 rte_errno = ENOMEM; 1265 return NULL; 1266 } 1267 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1268 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1269 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1270 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1271 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1272 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1273 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1274 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1275 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1276 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1277 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1278 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1279 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1280 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1281 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1282 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1283 wq_attr = &rq_attr->wq_attr; 1284 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1285 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1286 out, sizeof(out)); 1287 if (!rq->obj) { 1288 DRV_LOG(ERR, "Failed to create RQ using DevX"); 1289 rte_errno = errno; 1290 mlx5_free(rq); 1291 return NULL; 1292 } 1293 rq->id = MLX5_GET(create_rq_out, out, rqn); 1294 return rq; 1295 } 1296 1297 /** 1298 * Modify RQ using DevX API. 1299 * 1300 * @param[in] rq 1301 * Pointer to RQ object structure. 1302 * @param [in] rq_attr 1303 * Pointer to modify RQ attributes structure. 1304 * 1305 * @return 1306 * 0 on success, a negative errno value otherwise and rte_errno is set. 1307 */ 1308 int 1309 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1310 struct mlx5_devx_modify_rq_attr *rq_attr) 1311 { 1312 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1313 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1314 void *rq_ctx, *wq_ctx; 1315 int ret; 1316 1317 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1318 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1319 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1320 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1321 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1322 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1323 if (rq_attr->modify_bitmask & 1324 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1325 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1326 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1327 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1328 if (rq_attr->modify_bitmask & 1329 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1330 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1331 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1332 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1333 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1334 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1335 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1336 } 1337 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1338 out, sizeof(out)); 1339 if (ret) { 1340 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1341 rte_errno = errno; 1342 return -errno; 1343 } 1344 return ret; 1345 } 1346 1347 /** 1348 * Create RMP using DevX API. 1349 * 1350 * @param[in] ctx 1351 * Context returned from mlx5 open_device() glue function. 1352 * @param [in] rmp_attr 1353 * Pointer to create RMP attributes structure. 1354 * @param [in] socket 1355 * CPU socket ID for allocations. 1356 * 1357 * @return 1358 * The DevX object created, NULL otherwise and rte_errno is set. 1359 */ 1360 struct mlx5_devx_obj * 1361 mlx5_devx_cmd_create_rmp(void *ctx, 1362 struct mlx5_devx_create_rmp_attr *rmp_attr, 1363 int socket) 1364 { 1365 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0}; 1366 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0}; 1367 void *rmp_ctx, *wq_ctx; 1368 struct mlx5_devx_wq_attr *wq_attr; 1369 struct mlx5_devx_obj *rmp = NULL; 1370 1371 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket); 1372 if (!rmp) { 1373 DRV_LOG(ERR, "Failed to allocate RMP data"); 1374 rte_errno = ENOMEM; 1375 return NULL; 1376 } 1377 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP); 1378 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx); 1379 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state); 1380 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe, 1381 rmp_attr->basic_cyclic_rcv_wqe); 1382 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq); 1383 wq_attr = &rmp_attr->wq_attr; 1384 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1385 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1386 sizeof(out)); 1387 if (!rmp->obj) { 1388 DRV_LOG(ERR, "Failed to create RMP using DevX"); 1389 rte_errno = errno; 1390 mlx5_free(rmp); 1391 return NULL; 1392 } 1393 rmp->id = MLX5_GET(create_rmp_out, out, rmpn); 1394 return rmp; 1395 } 1396 1397 /* 1398 * Create TIR using DevX API. 1399 * 1400 * @param[in] ctx 1401 * Context returned from mlx5 open_device() glue function. 1402 * @param [in] tir_attr 1403 * Pointer to TIR attributes structure. 1404 * 1405 * @return 1406 * The DevX object created, NULL otherwise and rte_errno is set. 1407 */ 1408 struct mlx5_devx_obj * 1409 mlx5_devx_cmd_create_tir(void *ctx, 1410 struct mlx5_devx_tir_attr *tir_attr) 1411 { 1412 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1413 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1414 void *tir_ctx, *outer, *inner, *rss_key; 1415 struct mlx5_devx_obj *tir = NULL; 1416 1417 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1418 if (!tir) { 1419 DRV_LOG(ERR, "Failed to allocate TIR data"); 1420 rte_errno = ENOMEM; 1421 return NULL; 1422 } 1423 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1424 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1425 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1426 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1427 tir_attr->lro_timeout_period_usecs); 1428 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1429 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1430 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1431 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1432 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1433 tir_attr->tunneled_offload_en); 1434 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1435 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1436 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1437 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1438 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1439 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1440 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1441 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1442 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1443 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1444 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1445 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1446 tir_attr->rx_hash_field_selector_outer.selected_fields); 1447 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1448 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1449 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1450 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1451 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1452 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1453 tir_attr->rx_hash_field_selector_inner.selected_fields); 1454 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1455 out, sizeof(out)); 1456 if (!tir->obj) { 1457 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1458 rte_errno = errno; 1459 mlx5_free(tir); 1460 return NULL; 1461 } 1462 tir->id = MLX5_GET(create_tir_out, out, tirn); 1463 return tir; 1464 } 1465 1466 /** 1467 * Modify TIR using DevX API. 1468 * 1469 * @param[in] tir 1470 * Pointer to TIR DevX object structure. 1471 * @param [in] modify_tir_attr 1472 * Pointer to TIR modification attributes structure. 1473 * 1474 * @return 1475 * 0 on success, a negative errno value otherwise and rte_errno is set. 1476 */ 1477 int 1478 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1479 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1480 { 1481 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1482 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1483 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1484 void *tir_ctx; 1485 int ret; 1486 1487 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1488 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1489 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1490 modify_tir_attr->modify_bitmask); 1491 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1492 if (modify_tir_attr->modify_bitmask & 1493 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1494 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1495 tir_attr->lro_timeout_period_usecs); 1496 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1497 tir_attr->lro_enable_mask); 1498 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1499 tir_attr->lro_max_msg_sz); 1500 } 1501 if (modify_tir_attr->modify_bitmask & 1502 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1503 MLX5_SET(tirc, tir_ctx, indirect_table, 1504 tir_attr->indirect_table); 1505 if (modify_tir_attr->modify_bitmask & 1506 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1507 int i; 1508 void *outer, *inner; 1509 1510 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1511 tir_attr->rx_hash_symmetric); 1512 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1513 for (i = 0; i < 10; i++) { 1514 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1515 tir_attr->rx_hash_toeplitz_key[i]); 1516 } 1517 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1518 rx_hash_field_selector_outer); 1519 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1520 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1521 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1522 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1523 MLX5_SET 1524 (rx_hash_field_select, outer, selected_fields, 1525 tir_attr->rx_hash_field_selector_outer.selected_fields); 1526 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1527 rx_hash_field_selector_inner); 1528 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1529 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1530 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1531 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1532 MLX5_SET 1533 (rx_hash_field_select, inner, selected_fields, 1534 tir_attr->rx_hash_field_selector_inner.selected_fields); 1535 } 1536 if (modify_tir_attr->modify_bitmask & 1537 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1538 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1539 } 1540 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1541 out, sizeof(out)); 1542 if (ret) { 1543 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1544 rte_errno = errno; 1545 return -errno; 1546 } 1547 return ret; 1548 } 1549 1550 /** 1551 * Create RQT using DevX API. 1552 * 1553 * @param[in] ctx 1554 * Context returned from mlx5 open_device() glue function. 1555 * @param [in] rqt_attr 1556 * Pointer to RQT attributes structure. 1557 * 1558 * @return 1559 * The DevX object created, NULL otherwise and rte_errno is set. 1560 */ 1561 struct mlx5_devx_obj * 1562 mlx5_devx_cmd_create_rqt(void *ctx, 1563 struct mlx5_devx_rqt_attr *rqt_attr) 1564 { 1565 uint32_t *in = NULL; 1566 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1567 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1568 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1569 void *rqt_ctx; 1570 struct mlx5_devx_obj *rqt = NULL; 1571 int i; 1572 1573 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1574 if (!in) { 1575 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1576 rte_errno = ENOMEM; 1577 return NULL; 1578 } 1579 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1580 if (!rqt) { 1581 DRV_LOG(ERR, "Failed to allocate RQT data"); 1582 rte_errno = ENOMEM; 1583 mlx5_free(in); 1584 return NULL; 1585 } 1586 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1587 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1588 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1589 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1590 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1591 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1592 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1593 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1594 mlx5_free(in); 1595 if (!rqt->obj) { 1596 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1597 rte_errno = errno; 1598 mlx5_free(rqt); 1599 return NULL; 1600 } 1601 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1602 return rqt; 1603 } 1604 1605 /** 1606 * Modify RQT using DevX API. 1607 * 1608 * @param[in] rqt 1609 * Pointer to RQT DevX object structure. 1610 * @param [in] rqt_attr 1611 * Pointer to RQT attributes structure. 1612 * 1613 * @return 1614 * 0 on success, a negative errno value otherwise and rte_errno is set. 1615 */ 1616 int 1617 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1618 struct mlx5_devx_rqt_attr *rqt_attr) 1619 { 1620 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1621 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1622 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1623 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1624 void *rqt_ctx; 1625 int i; 1626 int ret; 1627 1628 if (!in) { 1629 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1630 rte_errno = ENOMEM; 1631 return -ENOMEM; 1632 } 1633 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1634 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1635 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1636 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1637 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1638 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1639 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1640 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1641 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1642 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1643 mlx5_free(in); 1644 if (ret) { 1645 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1646 rte_errno = errno; 1647 return -rte_errno; 1648 } 1649 return ret; 1650 } 1651 1652 /** 1653 * Create SQ using DevX API. 1654 * 1655 * @param[in] ctx 1656 * Context returned from mlx5 open_device() glue function. 1657 * @param [in] sq_attr 1658 * Pointer to SQ attributes structure. 1659 * @param [in] socket 1660 * CPU socket ID for allocations. 1661 * 1662 * @return 1663 * The DevX object created, NULL otherwise and rte_errno is set. 1664 **/ 1665 struct mlx5_devx_obj * 1666 mlx5_devx_cmd_create_sq(void *ctx, 1667 struct mlx5_devx_create_sq_attr *sq_attr) 1668 { 1669 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1670 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1671 void *sq_ctx; 1672 void *wq_ctx; 1673 struct mlx5_devx_wq_attr *wq_attr; 1674 struct mlx5_devx_obj *sq = NULL; 1675 1676 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1677 if (!sq) { 1678 DRV_LOG(ERR, "Failed to allocate SQ data"); 1679 rte_errno = ENOMEM; 1680 return NULL; 1681 } 1682 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1683 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1684 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1685 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1686 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1687 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1688 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1689 sq_attr->allow_multi_pkt_send_wqe); 1690 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1691 sq_attr->min_wqe_inline_mode); 1692 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1693 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1694 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1695 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1696 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1697 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1698 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1699 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1700 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1701 sq_attr->packet_pacing_rate_limit_index); 1702 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1703 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1704 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1705 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1706 wq_attr = &sq_attr->wq_attr; 1707 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1708 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1709 out, sizeof(out)); 1710 if (!sq->obj) { 1711 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1712 rte_errno = errno; 1713 mlx5_free(sq); 1714 return NULL; 1715 } 1716 sq->id = MLX5_GET(create_sq_out, out, sqn); 1717 return sq; 1718 } 1719 1720 /** 1721 * Modify SQ using DevX API. 1722 * 1723 * @param[in] sq 1724 * Pointer to SQ object structure. 1725 * @param [in] sq_attr 1726 * Pointer to SQ attributes structure. 1727 * 1728 * @return 1729 * 0 on success, a negative errno value otherwise and rte_errno is set. 1730 */ 1731 int 1732 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1733 struct mlx5_devx_modify_sq_attr *sq_attr) 1734 { 1735 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1736 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1737 void *sq_ctx; 1738 int ret; 1739 1740 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1741 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1742 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1743 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1744 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1745 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1746 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1747 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1748 out, sizeof(out)); 1749 if (ret) { 1750 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1751 rte_errno = errno; 1752 return -rte_errno; 1753 } 1754 return ret; 1755 } 1756 1757 /** 1758 * Create TIS using DevX API. 1759 * 1760 * @param[in] ctx 1761 * Context returned from mlx5 open_device() glue function. 1762 * @param [in] tis_attr 1763 * Pointer to TIS attributes structure. 1764 * 1765 * @return 1766 * The DevX object created, NULL otherwise and rte_errno is set. 1767 */ 1768 struct mlx5_devx_obj * 1769 mlx5_devx_cmd_create_tis(void *ctx, 1770 struct mlx5_devx_tis_attr *tis_attr) 1771 { 1772 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1773 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1774 struct mlx5_devx_obj *tis = NULL; 1775 void *tis_ctx; 1776 1777 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1778 if (!tis) { 1779 DRV_LOG(ERR, "Failed to allocate TIS object"); 1780 rte_errno = ENOMEM; 1781 return NULL; 1782 } 1783 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1784 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1785 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1786 tis_attr->strict_lag_tx_port_affinity); 1787 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1788 tis_attr->lag_tx_port_affinity); 1789 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1790 MLX5_SET(tisc, tis_ctx, transport_domain, 1791 tis_attr->transport_domain); 1792 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1793 out, sizeof(out)); 1794 if (!tis->obj) { 1795 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1796 rte_errno = errno; 1797 mlx5_free(tis); 1798 return NULL; 1799 } 1800 tis->id = MLX5_GET(create_tis_out, out, tisn); 1801 return tis; 1802 } 1803 1804 /** 1805 * Create transport domain using DevX API. 1806 * 1807 * @param[in] ctx 1808 * Context returned from mlx5 open_device() glue function. 1809 * @return 1810 * The DevX object created, NULL otherwise and rte_errno is set. 1811 */ 1812 struct mlx5_devx_obj * 1813 mlx5_devx_cmd_create_td(void *ctx) 1814 { 1815 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1816 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1817 struct mlx5_devx_obj *td = NULL; 1818 1819 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1820 if (!td) { 1821 DRV_LOG(ERR, "Failed to allocate TD object"); 1822 rte_errno = ENOMEM; 1823 return NULL; 1824 } 1825 MLX5_SET(alloc_transport_domain_in, in, opcode, 1826 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1827 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1828 out, sizeof(out)); 1829 if (!td->obj) { 1830 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1831 rte_errno = errno; 1832 mlx5_free(td); 1833 return NULL; 1834 } 1835 td->id = MLX5_GET(alloc_transport_domain_out, out, 1836 transport_domain); 1837 return td; 1838 } 1839 1840 /** 1841 * Dump all flows to file. 1842 * 1843 * @param[in] fdb_domain 1844 * FDB domain. 1845 * @param[in] rx_domain 1846 * RX domain. 1847 * @param[in] tx_domain 1848 * TX domain. 1849 * @param[out] file 1850 * Pointer to file stream. 1851 * 1852 * @return 1853 * 0 on success, a negative value otherwise. 1854 */ 1855 int 1856 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1857 void *rx_domain __rte_unused, 1858 void *tx_domain __rte_unused, FILE *file __rte_unused) 1859 { 1860 int ret = 0; 1861 1862 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1863 if (fdb_domain) { 1864 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1865 if (ret) 1866 return ret; 1867 } 1868 MLX5_ASSERT(rx_domain); 1869 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1870 if (ret) 1871 return ret; 1872 MLX5_ASSERT(tx_domain); 1873 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1874 #else 1875 ret = ENOTSUP; 1876 #endif 1877 return -ret; 1878 } 1879 1880 int 1881 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 1882 FILE *file __rte_unused) 1883 { 1884 int ret = 0; 1885 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 1886 if (rule_info) 1887 ret = mlx5_glue->dr_dump_rule(file, rule_info); 1888 #else 1889 ret = ENOTSUP; 1890 #endif 1891 return -ret; 1892 } 1893 1894 /* 1895 * Create CQ using DevX API. 1896 * 1897 * @param[in] ctx 1898 * Context returned from mlx5 open_device() glue function. 1899 * @param [in] attr 1900 * Pointer to CQ attributes structure. 1901 * 1902 * @return 1903 * The DevX object created, NULL otherwise and rte_errno is set. 1904 */ 1905 struct mlx5_devx_obj * 1906 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1907 { 1908 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1909 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1910 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1911 sizeof(*cq_obj), 1912 0, SOCKET_ID_ANY); 1913 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1914 1915 if (!cq_obj) { 1916 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1917 rte_errno = ENOMEM; 1918 return NULL; 1919 } 1920 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1921 if (attr->db_umem_valid) { 1922 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1923 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1924 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1925 } else { 1926 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1927 } 1928 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1929 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1930 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1931 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1932 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1933 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1934 MLX5_SET(cqc, cqctx, log_page_size, 1935 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1936 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1937 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1938 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1939 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1940 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1941 attr->mini_cqe_res_format_ext); 1942 if (attr->q_umem_valid) { 1943 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1944 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1945 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1946 attr->q_umem_offset); 1947 } 1948 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1949 sizeof(out)); 1950 if (!cq_obj->obj) { 1951 rte_errno = errno; 1952 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1953 mlx5_free(cq_obj); 1954 return NULL; 1955 } 1956 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1957 return cq_obj; 1958 } 1959 1960 /** 1961 * Create VIRTQ using DevX API. 1962 * 1963 * @param[in] ctx 1964 * Context returned from mlx5 open_device() glue function. 1965 * @param [in] attr 1966 * Pointer to VIRTQ attributes structure. 1967 * 1968 * @return 1969 * The DevX object created, NULL otherwise and rte_errno is set. 1970 */ 1971 struct mlx5_devx_obj * 1972 mlx5_devx_cmd_create_virtq(void *ctx, 1973 struct mlx5_devx_virtq_attr *attr) 1974 { 1975 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1976 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1977 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1978 sizeof(*virtq_obj), 1979 0, SOCKET_ID_ANY); 1980 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1981 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1982 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1983 1984 if (!virtq_obj) { 1985 DRV_LOG(ERR, "Failed to allocate virtq data."); 1986 rte_errno = ENOMEM; 1987 return NULL; 1988 } 1989 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1990 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1991 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1992 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1993 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1994 attr->hw_available_index); 1995 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1996 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1997 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1998 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1999 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2000 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2001 attr->virtio_version_1_0); 2002 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2003 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2004 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2005 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2006 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 2007 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2008 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 2009 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2010 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 2011 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 2012 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 2013 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 2014 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 2015 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 2016 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 2017 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 2018 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 2019 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 2020 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 2021 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 2022 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 2023 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 2024 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 2025 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2026 sizeof(out)); 2027 if (!virtq_obj->obj) { 2028 rte_errno = errno; 2029 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 2030 mlx5_free(virtq_obj); 2031 return NULL; 2032 } 2033 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2034 return virtq_obj; 2035 } 2036 2037 /** 2038 * Modify VIRTQ using DevX API. 2039 * 2040 * @param[in] virtq_obj 2041 * Pointer to virtq object structure. 2042 * @param [in] attr 2043 * Pointer to modify virtq attributes structure. 2044 * 2045 * @return 2046 * 0 on success, a negative errno value otherwise and rte_errno is set. 2047 */ 2048 int 2049 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 2050 struct mlx5_devx_virtq_attr *attr) 2051 { 2052 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2053 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2054 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2055 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2056 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2057 int ret; 2058 2059 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2060 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 2061 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2062 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2063 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2064 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 2065 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2066 switch (attr->type) { 2067 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 2068 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 2069 break; 2070 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 2071 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 2072 attr->dirty_bitmap_mkey); 2073 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 2074 attr->dirty_bitmap_addr); 2075 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 2076 attr->dirty_bitmap_size); 2077 break; 2078 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 2079 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 2080 attr->dirty_bitmap_dump_enable); 2081 break; 2082 default: 2083 rte_errno = EINVAL; 2084 return -rte_errno; 2085 } 2086 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 2087 out, sizeof(out)); 2088 if (ret) { 2089 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2090 rte_errno = errno; 2091 return -rte_errno; 2092 } 2093 return ret; 2094 } 2095 2096 /** 2097 * Query VIRTQ using DevX API. 2098 * 2099 * @param[in] virtq_obj 2100 * Pointer to virtq object structure. 2101 * @param [in/out] attr 2102 * Pointer to virtq attributes structure. 2103 * 2104 * @return 2105 * 0 on success, a negative errno value otherwise and rte_errno is set. 2106 */ 2107 int 2108 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 2109 struct mlx5_devx_virtq_attr *attr) 2110 { 2111 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2112 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 2113 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 2114 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 2115 int ret; 2116 2117 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2118 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2119 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2120 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2121 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2122 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2123 out, sizeof(out)); 2124 if (ret) { 2125 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2126 rte_errno = errno; 2127 return -errno; 2128 } 2129 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2130 hw_available_index); 2131 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2132 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2133 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2134 virtio_q_context.error_type); 2135 return ret; 2136 } 2137 2138 /** 2139 * Create QP using DevX API. 2140 * 2141 * @param[in] ctx 2142 * Context returned from mlx5 open_device() glue function. 2143 * @param [in] attr 2144 * Pointer to QP attributes structure. 2145 * 2146 * @return 2147 * The DevX object created, NULL otherwise and rte_errno is set. 2148 */ 2149 struct mlx5_devx_obj * 2150 mlx5_devx_cmd_create_qp(void *ctx, 2151 struct mlx5_devx_qp_attr *attr) 2152 { 2153 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2154 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2155 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2156 sizeof(*qp_obj), 2157 0, SOCKET_ID_ANY); 2158 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2159 2160 if (!qp_obj) { 2161 DRV_LOG(ERR, "Failed to allocate QP data."); 2162 rte_errno = ENOMEM; 2163 return NULL; 2164 } 2165 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2166 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2167 MLX5_SET(qpc, qpc, pd, attr->pd); 2168 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2169 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2170 if (attr->uar_index) { 2171 if (attr->mmo) { 2172 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2173 in, qpc_extension_and_pas_list); 2174 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2175 qpc_ext_and_pas_list, qpc_data_extension); 2176 2177 MLX5_SET(create_qp_in, in, qpc_ext, 1); 2178 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2179 } 2180 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2181 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2182 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2183 MLX5_SET(qpc, qpc, log_page_size, 2184 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2185 if (attr->num_of_send_wqbbs) { 2186 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs)); 2187 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2188 MLX5_SET(qpc, qpc, log_sq_size, 2189 rte_log2_u32(attr->num_of_send_wqbbs)); 2190 } else { 2191 MLX5_SET(qpc, qpc, no_sq, 1); 2192 } 2193 if (attr->num_of_receive_wqes) { 2194 MLX5_ASSERT(RTE_IS_POWER_OF_2( 2195 attr->num_of_receive_wqes)); 2196 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2197 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2198 MLX5_LOG_RQ_STRIDE_SHIFT); 2199 MLX5_SET(qpc, qpc, log_rq_size, 2200 rte_log2_u32(attr->num_of_receive_wqes)); 2201 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2202 } else { 2203 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2204 } 2205 if (attr->dbr_umem_valid) { 2206 MLX5_SET(qpc, qpc, dbr_umem_valid, 2207 attr->dbr_umem_valid); 2208 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2209 } 2210 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2211 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2212 attr->wq_umem_offset); 2213 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2214 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2215 } else { 2216 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2217 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2218 MLX5_SET(qpc, qpc, no_sq, 1); 2219 } 2220 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2221 sizeof(out)); 2222 if (!qp_obj->obj) { 2223 rte_errno = errno; 2224 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 2225 mlx5_free(qp_obj); 2226 return NULL; 2227 } 2228 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2229 return qp_obj; 2230 } 2231 2232 /** 2233 * Modify QP using DevX API. 2234 * Currently supports only force loop-back QP. 2235 * 2236 * @param[in] qp 2237 * Pointer to QP object structure. 2238 * @param [in] qp_st_mod_op 2239 * The QP state modification operation. 2240 * @param [in] remote_qp_id 2241 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2242 * 2243 * @return 2244 * 0 on success, a negative errno value otherwise and rte_errno is set. 2245 */ 2246 int 2247 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2248 uint32_t remote_qp_id) 2249 { 2250 union { 2251 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2252 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2253 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2254 } in; 2255 union { 2256 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2257 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2258 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2259 } out; 2260 void *qpc; 2261 int ret; 2262 unsigned int inlen; 2263 unsigned int outlen; 2264 2265 memset(&in, 0, sizeof(in)); 2266 memset(&out, 0, sizeof(out)); 2267 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2268 switch (qp_st_mod_op) { 2269 case MLX5_CMD_OP_RST2INIT_QP: 2270 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2271 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2272 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2273 MLX5_SET(qpc, qpc, rre, 1); 2274 MLX5_SET(qpc, qpc, rwe, 1); 2275 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2276 inlen = sizeof(in.rst2init); 2277 outlen = sizeof(out.rst2init); 2278 break; 2279 case MLX5_CMD_OP_INIT2RTR_QP: 2280 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2281 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2282 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2283 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2284 MLX5_SET(qpc, qpc, mtu, 1); 2285 MLX5_SET(qpc, qpc, log_msg_max, 30); 2286 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2287 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2288 inlen = sizeof(in.init2rtr); 2289 outlen = sizeof(out.init2rtr); 2290 break; 2291 case MLX5_CMD_OP_RTR2RTS_QP: 2292 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2293 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2294 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16); 2295 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2296 MLX5_SET(qpc, qpc, retry_count, 7); 2297 MLX5_SET(qpc, qpc, rnr_retry, 7); 2298 inlen = sizeof(in.rtr2rts); 2299 outlen = sizeof(out.rtr2rts); 2300 break; 2301 default: 2302 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2303 qp_st_mod_op); 2304 rte_errno = EINVAL; 2305 return -rte_errno; 2306 } 2307 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2308 if (ret) { 2309 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2310 rte_errno = errno; 2311 return -rte_errno; 2312 } 2313 return ret; 2314 } 2315 2316 struct mlx5_devx_obj * 2317 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2318 { 2319 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2320 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2321 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2322 sizeof(*couners_obj), 0, 2323 SOCKET_ID_ANY); 2324 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2325 2326 if (!couners_obj) { 2327 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2328 rte_errno = ENOMEM; 2329 return NULL; 2330 } 2331 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2332 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2333 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2334 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2335 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2336 sizeof(out)); 2337 if (!couners_obj->obj) { 2338 rte_errno = errno; 2339 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 2340 " DevX."); 2341 mlx5_free(couners_obj); 2342 return NULL; 2343 } 2344 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2345 return couners_obj; 2346 } 2347 2348 int 2349 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2350 struct mlx5_devx_virtio_q_couners_attr *attr) 2351 { 2352 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2353 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2354 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2355 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2356 virtio_q_counters); 2357 int ret; 2358 2359 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2360 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2361 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2362 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2363 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2364 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2365 sizeof(out)); 2366 if (ret) { 2367 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2368 rte_errno = errno; 2369 return -errno; 2370 } 2371 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2372 received_desc); 2373 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2374 completed_desc); 2375 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2376 error_cqes); 2377 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2378 bad_desc_errors); 2379 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2380 exceed_max_chain); 2381 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2382 invalid_buffer); 2383 return ret; 2384 } 2385 2386 /** 2387 * Create general object of type FLOW_HIT_ASO using DevX API. 2388 * 2389 * @param[in] ctx 2390 * Context returned from mlx5 open_device() glue function. 2391 * @param [in] pd 2392 * PD value to associate the FLOW_HIT_ASO object with. 2393 * 2394 * @return 2395 * The DevX object created, NULL otherwise and rte_errno is set. 2396 */ 2397 struct mlx5_devx_obj * 2398 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2399 { 2400 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2401 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2402 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2403 void *ptr = NULL; 2404 2405 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2406 0, SOCKET_ID_ANY); 2407 if (!flow_hit_aso_obj) { 2408 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2409 rte_errno = ENOMEM; 2410 return NULL; 2411 } 2412 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2413 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2414 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2415 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2416 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2417 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2418 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2419 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2420 out, sizeof(out)); 2421 if (!flow_hit_aso_obj->obj) { 2422 rte_errno = errno; 2423 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX."); 2424 mlx5_free(flow_hit_aso_obj); 2425 return NULL; 2426 } 2427 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2428 return flow_hit_aso_obj; 2429 } 2430 2431 /* 2432 * Create PD using DevX API. 2433 * 2434 * @param[in] ctx 2435 * Context returned from mlx5 open_device() glue function. 2436 * 2437 * @return 2438 * The DevX object created, NULL otherwise and rte_errno is set. 2439 */ 2440 struct mlx5_devx_obj * 2441 mlx5_devx_cmd_alloc_pd(void *ctx) 2442 { 2443 struct mlx5_devx_obj *ppd = 2444 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2445 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2446 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2447 2448 if (!ppd) { 2449 DRV_LOG(ERR, "Failed to allocate PD data."); 2450 rte_errno = ENOMEM; 2451 return NULL; 2452 } 2453 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2454 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2455 out, sizeof(out)); 2456 if (!ppd->obj) { 2457 mlx5_free(ppd); 2458 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2459 rte_errno = errno; 2460 return NULL; 2461 } 2462 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2463 return ppd; 2464 } 2465 2466 /** 2467 * Create general object of type FLOW_METER_ASO using DevX API. 2468 * 2469 * @param[in] ctx 2470 * Context returned from mlx5 open_device() glue function. 2471 * @param [in] pd 2472 * PD value to associate the FLOW_METER_ASO object with. 2473 * @param [in] log_obj_size 2474 * log_obj_size define to allocate number of 2 * meters 2475 * in one FLOW_METER_ASO object. 2476 * 2477 * @return 2478 * The DevX object created, NULL otherwise and rte_errno is set. 2479 */ 2480 struct mlx5_devx_obj * 2481 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2482 uint32_t log_obj_size) 2483 { 2484 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2485 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2486 struct mlx5_devx_obj *flow_meter_aso_obj; 2487 void *ptr; 2488 2489 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2490 sizeof(*flow_meter_aso_obj), 2491 0, SOCKET_ID_ANY); 2492 if (!flow_meter_aso_obj) { 2493 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2494 rte_errno = ENOMEM; 2495 return NULL; 2496 } 2497 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2498 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2499 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2500 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2501 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2502 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2503 log_obj_size); 2504 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2505 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2506 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2507 ctx, in, sizeof(in), 2508 out, sizeof(out)); 2509 if (!flow_meter_aso_obj->obj) { 2510 rte_errno = errno; 2511 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX."); 2512 mlx5_free(flow_meter_aso_obj); 2513 return NULL; 2514 } 2515 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2516 out, obj_id); 2517 return flow_meter_aso_obj; 2518 } 2519 2520 /* 2521 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2522 * 2523 * @param[in] ctx 2524 * Context returned from mlx5 open_device() glue function. 2525 * @param [in] pd 2526 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2527 * @param [in] log_obj_size 2528 * log_obj_size to allocate its power of 2 * objects 2529 * in one CONN_TRACK_OFFLOAD bulk allocation. 2530 * 2531 * @return 2532 * The DevX object created, NULL otherwise and rte_errno is set. 2533 */ 2534 struct mlx5_devx_obj * 2535 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2536 uint32_t log_obj_size) 2537 { 2538 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2539 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2540 struct mlx5_devx_obj *ct_aso_obj; 2541 void *ptr; 2542 2543 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2544 0, SOCKET_ID_ANY); 2545 if (!ct_aso_obj) { 2546 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2547 rte_errno = ENOMEM; 2548 return NULL; 2549 } 2550 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2551 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2552 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2553 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2554 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2555 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2556 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2557 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2558 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2559 out, sizeof(out)); 2560 if (!ct_aso_obj->obj) { 2561 rte_errno = errno; 2562 DRV_LOG(ERR, "Failed to create CONN_TRACK_OFFLOAD obj by using DevX."); 2563 mlx5_free(ct_aso_obj); 2564 return NULL; 2565 } 2566 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2567 return ct_aso_obj; 2568 } 2569 2570 /** 2571 * Create general object of type GENEVE TLV option using DevX API. 2572 * 2573 * @param[in] ctx 2574 * Context returned from mlx5 open_device() glue function. 2575 * @param [in] class 2576 * TLV option variable value of class 2577 * @param [in] type 2578 * TLV option variable value of type 2579 * @param [in] len 2580 * TLV option variable value of len 2581 * 2582 * @return 2583 * The DevX object created, NULL otherwise and rte_errno is set. 2584 */ 2585 struct mlx5_devx_obj * 2586 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2587 uint16_t class, uint8_t type, uint8_t len) 2588 { 2589 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2590 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2591 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2592 sizeof(*geneve_tlv_opt_obj), 2593 0, SOCKET_ID_ANY); 2594 2595 if (!geneve_tlv_opt_obj) { 2596 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2597 rte_errno = ENOMEM; 2598 return NULL; 2599 } 2600 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2601 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2602 geneve_tlv_opt); 2603 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2604 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2605 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2606 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2607 MLX5_SET(geneve_tlv_option, opt, option_class, 2608 rte_be_to_cpu_16(class)); 2609 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2610 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2611 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2612 sizeof(in), out, sizeof(out)); 2613 if (!geneve_tlv_opt_obj->obj) { 2614 rte_errno = errno; 2615 DRV_LOG(ERR, "Failed to create Geneve tlv option " 2616 "Obj using DevX."); 2617 mlx5_free(geneve_tlv_opt_obj); 2618 return NULL; 2619 } 2620 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2621 return geneve_tlv_opt_obj; 2622 } 2623 2624 int 2625 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2626 { 2627 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2628 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2629 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2630 int rc; 2631 void *rq_ctx; 2632 2633 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2634 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2635 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2636 if (rc) { 2637 rte_errno = errno; 2638 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2639 "rc = %d, errno = %d.", rc, errno); 2640 return -rc; 2641 }; 2642 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2643 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2644 return 0; 2645 #else 2646 (void)wq; 2647 (void)counter_set_id; 2648 return -ENOTSUP; 2649 #endif 2650 } 2651 2652 /* 2653 * Allocate queue counters via devx interface. 2654 * 2655 * @param[in] ctx 2656 * Context returned from mlx5 open_device() glue function. 2657 * 2658 * @return 2659 * Pointer to counter object on success, a NULL value otherwise and 2660 * rte_errno is set. 2661 */ 2662 struct mlx5_devx_obj * 2663 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2664 { 2665 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2666 SOCKET_ID_ANY); 2667 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2668 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2669 2670 if (!dcs) { 2671 rte_errno = ENOMEM; 2672 return NULL; 2673 } 2674 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2675 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2676 sizeof(out)); 2677 if (!dcs->obj) { 2678 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error " 2679 "%d.", errno); 2680 rte_errno = errno; 2681 mlx5_free(dcs); 2682 return NULL; 2683 } 2684 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2685 return dcs; 2686 } 2687 2688 /** 2689 * Query queue counters values. 2690 * 2691 * @param[in] dcs 2692 * devx object of the queue counter set. 2693 * @param[in] clear 2694 * Whether hardware should clear the counters after the query or not. 2695 * @param[out] out_of_buffers 2696 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2697 * 2698 * @return 2699 * 0 on success, a negative value otherwise. 2700 */ 2701 int 2702 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2703 uint32_t *out_of_buffers) 2704 { 2705 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2706 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2707 int rc; 2708 2709 MLX5_SET(query_q_counter_in, in, opcode, 2710 MLX5_CMD_OP_QUERY_Q_COUNTER); 2711 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2712 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2713 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2714 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2715 sizeof(out)); 2716 if (rc) { 2717 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2718 rte_errno = rc; 2719 return -rc; 2720 } 2721 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2722 return 0; 2723 } 2724 2725 /** 2726 * Create general object of type DEK using DevX API. 2727 * 2728 * @param[in] ctx 2729 * Context returned from mlx5 open_device() glue function. 2730 * @param [in] attr 2731 * Pointer to DEK attributes structure. 2732 * 2733 * @return 2734 * The DevX object created, NULL otherwise and rte_errno is set. 2735 */ 2736 struct mlx5_devx_obj * 2737 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2738 { 2739 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2740 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2741 struct mlx5_devx_obj *dek_obj = NULL; 2742 void *ptr = NULL, *key_addr = NULL; 2743 2744 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2745 0, SOCKET_ID_ANY); 2746 if (dek_obj == NULL) { 2747 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2748 rte_errno = ENOMEM; 2749 return NULL; 2750 } 2751 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2752 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2753 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2754 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2755 MLX5_GENERAL_OBJ_TYPE_DEK); 2756 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2757 MLX5_SET(dek, ptr, key_size, attr->key_size); 2758 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2759 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2760 MLX5_SET(dek, ptr, pd, attr->pd); 2761 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2762 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2763 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2764 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2765 out, sizeof(out)); 2766 if (dek_obj->obj == NULL) { 2767 rte_errno = errno; 2768 DRV_LOG(ERR, "Failed to create DEK obj using DevX."); 2769 mlx5_free(dek_obj); 2770 return NULL; 2771 } 2772 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2773 return dek_obj; 2774 } 2775 2776 /** 2777 * Create general object of type IMPORT_KEK using DevX API. 2778 * 2779 * @param[in] ctx 2780 * Context returned from mlx5 open_device() glue function. 2781 * @param [in] attr 2782 * Pointer to IMPORT_KEK attributes structure. 2783 * 2784 * @return 2785 * The DevX object created, NULL otherwise and rte_errno is set. 2786 */ 2787 struct mlx5_devx_obj * 2788 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 2789 struct mlx5_devx_import_kek_attr *attr) 2790 { 2791 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 2792 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2793 struct mlx5_devx_obj *import_kek_obj = NULL; 2794 void *ptr = NULL, *key_addr = NULL; 2795 2796 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 2797 0, SOCKET_ID_ANY); 2798 if (import_kek_obj == NULL) { 2799 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 2800 rte_errno = ENOMEM; 2801 return NULL; 2802 } 2803 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 2804 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2805 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2806 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2807 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 2808 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 2809 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 2810 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 2811 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2812 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2813 out, sizeof(out)); 2814 if (import_kek_obj->obj == NULL) { 2815 rte_errno = errno; 2816 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX."); 2817 mlx5_free(import_kek_obj); 2818 return NULL; 2819 } 2820 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2821 return import_kek_obj; 2822 } 2823 2824 /** 2825 * Create general object of type CREDENTIAL using DevX API. 2826 * 2827 * @param[in] ctx 2828 * Context returned from mlx5 open_device() glue function. 2829 * @param [in] attr 2830 * Pointer to CREDENTIAL attributes structure. 2831 * 2832 * @return 2833 * The DevX object created, NULL otherwise and rte_errno is set. 2834 */ 2835 struct mlx5_devx_obj * 2836 mlx5_devx_cmd_create_credential_obj(void *ctx, 2837 struct mlx5_devx_credential_attr *attr) 2838 { 2839 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 2840 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2841 struct mlx5_devx_obj *credential_obj = NULL; 2842 void *ptr = NULL, *credential_addr = NULL; 2843 2844 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 2845 0, SOCKET_ID_ANY); 2846 if (credential_obj == NULL) { 2847 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 2848 rte_errno = ENOMEM; 2849 return NULL; 2850 } 2851 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 2852 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2853 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2854 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2855 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 2856 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 2857 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 2858 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 2859 memcpy(credential_addr, (void *)(attr->credential), 2860 MLX5_CRYPTO_CREDENTIAL_SIZE); 2861 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2862 out, sizeof(out)); 2863 if (credential_obj->obj == NULL) { 2864 rte_errno = errno; 2865 DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX."); 2866 mlx5_free(credential_obj); 2867 return NULL; 2868 } 2869 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2870 return credential_obj; 2871 } 2872 2873 /** 2874 * Create general object of type CRYPTO_LOGIN using DevX API. 2875 * 2876 * @param[in] ctx 2877 * Context returned from mlx5 open_device() glue function. 2878 * @param [in] attr 2879 * Pointer to CRYPTO_LOGIN attributes structure. 2880 * 2881 * @return 2882 * The DevX object created, NULL otherwise and rte_errno is set. 2883 */ 2884 struct mlx5_devx_obj * 2885 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 2886 struct mlx5_devx_crypto_login_attr *attr) 2887 { 2888 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 2889 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2890 struct mlx5_devx_obj *crypto_login_obj = NULL; 2891 void *ptr = NULL, *credential_addr = NULL; 2892 2893 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 2894 0, SOCKET_ID_ANY); 2895 if (crypto_login_obj == NULL) { 2896 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 2897 rte_errno = ENOMEM; 2898 return NULL; 2899 } 2900 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 2901 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2902 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2903 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2904 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 2905 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 2906 MLX5_SET(crypto_login, ptr, credential_pointer, 2907 attr->credential_pointer); 2908 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 2909 attr->session_import_kek_ptr); 2910 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 2911 memcpy(credential_addr, (void *)(attr->credential), 2912 MLX5_CRYPTO_CREDENTIAL_SIZE); 2913 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2914 out, sizeof(out)); 2915 if (crypto_login_obj->obj == NULL) { 2916 rte_errno = errno; 2917 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX."); 2918 mlx5_free(crypto_login_obj); 2919 return NULL; 2920 } 2921 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2922 return crypto_login_obj; 2923 } 2924 2925 /** 2926 * Query LAG context. 2927 * 2928 * @param[in] ctx 2929 * Pointer to ibv_context, returned from mlx5dv_open_device. 2930 * @param[out] lag_ctx 2931 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 2932 * 2933 * @return 2934 * 0 on success, a negative value otherwise. 2935 */ 2936 int 2937 mlx5_devx_cmd_query_lag(void *ctx, 2938 struct mlx5_devx_lag_context *lag_ctx) 2939 { 2940 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 2941 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 2942 void *lctx; 2943 int rc; 2944 2945 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 2946 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 2947 if (rc) 2948 goto error; 2949 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 2950 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 2951 fdb_selection_mode); 2952 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 2953 port_select_mode); 2954 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 2955 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 2956 tx_remap_affinity_2); 2957 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 2958 tx_remap_affinity_1); 2959 return 0; 2960 error: 2961 rc = (rc > 0) ? -rc : rc; 2962 return rc; 2963 } 2964