1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /** 17 * Perform read access to the registers. Reads data from register 18 * and writes ones to the specified buffer. 19 * 20 * @param[in] ctx 21 * Context returned from mlx5 open_device() glue function. 22 * @param[in] reg_id 23 * Register identifier according to the PRM. 24 * @param[in] arg 25 * Register access auxiliary parameter according to the PRM. 26 * @param[out] data 27 * Pointer to the buffer to store read data. 28 * @param[in] dw_cnt 29 * Buffer size in double words. 30 * 31 * @return 32 * 0 on success, a negative value otherwise. 33 */ 34 int 35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 36 uint32_t *data, uint32_t dw_cnt) 37 { 38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 41 int status, rc; 42 43 MLX5_ASSERT(data && dw_cnt); 44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 46 DRV_LOG(ERR, "Not enough buffer for register read data"); 47 return -1; 48 } 49 MLX5_SET(access_register_in, in, opcode, 50 MLX5_CMD_OP_ACCESS_REGISTER_USER); 51 MLX5_SET(access_register_in, in, op_mod, 52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 53 MLX5_SET(access_register_in, in, register_id, reg_id); 54 MLX5_SET(access_register_in, in, argument, arg); 55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 56 MLX5_ST_SZ_BYTES(access_register_out) + 57 sizeof(uint32_t) * dw_cnt); 58 if (rc) 59 goto error; 60 status = MLX5_GET(access_register_out, out, status); 61 if (status) { 62 int syndrome = MLX5_GET(access_register_out, out, syndrome); 63 64 DRV_LOG(DEBUG, "Failed to read access NIC register 0x%X, " 65 "status %x, syndrome = %x", 66 reg_id, status, syndrome); 67 return -1; 68 } 69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 70 dw_cnt * sizeof(uint32_t)); 71 return 0; 72 error: 73 rc = (rc > 0) ? -rc : rc; 74 return rc; 75 } 76 77 /** 78 * Perform write access to the registers. 79 * 80 * @param[in] ctx 81 * Context returned from mlx5 open_device() glue function. 82 * @param[in] reg_id 83 * Register identifier according to the PRM. 84 * @param[in] arg 85 * Register access auxiliary parameter according to the PRM. 86 * @param[out] data 87 * Pointer to the buffer containing data to write. 88 * @param[in] dw_cnt 89 * Buffer size in double words (32bit units). 90 * 91 * @return 92 * 0 on success, a negative value otherwise. 93 */ 94 int 95 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 96 uint32_t *data, uint32_t dw_cnt) 97 { 98 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 99 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 100 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 101 int status, rc; 102 void *ptr; 103 104 MLX5_ASSERT(data && dw_cnt); 105 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 106 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 107 DRV_LOG(ERR, "Data to write exceeds max size"); 108 return -1; 109 } 110 MLX5_SET(access_register_in, in, opcode, 111 MLX5_CMD_OP_ACCESS_REGISTER_USER); 112 MLX5_SET(access_register_in, in, op_mod, 113 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 114 MLX5_SET(access_register_in, in, register_id, reg_id); 115 MLX5_SET(access_register_in, in, argument, arg); 116 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 117 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 118 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 119 120 rc = mlx5_glue->devx_general_cmd(ctx, in, 121 MLX5_ST_SZ_BYTES(access_register_in) + 122 dw_cnt * sizeof(uint32_t), 123 out, sizeof(out)); 124 if (rc) 125 goto error; 126 status = MLX5_GET(access_register_out, out, status); 127 if (status) { 128 int syndrome = MLX5_GET(access_register_out, out, syndrome); 129 130 DRV_LOG(DEBUG, "Failed to write access NIC register 0x%X, " 131 "status %x, syndrome = %x", 132 reg_id, status, syndrome); 133 return -1; 134 } 135 return 0; 136 error: 137 rc = (rc > 0) ? -rc : rc; 138 return rc; 139 } 140 141 /** 142 * Allocate flow counters via devx interface. 143 * 144 * @param[in] ctx 145 * Context returned from mlx5 open_device() glue function. 146 * @param dcs 147 * Pointer to counters properties structure to be filled by the routine. 148 * @param bulk_n_128 149 * Bulk counter numbers in 128 counters units. 150 * 151 * @return 152 * Pointer to counter object on success, a negative value otherwise and 153 * rte_errno is set. 154 */ 155 struct mlx5_devx_obj * 156 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 157 { 158 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 159 0, SOCKET_ID_ANY); 160 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 161 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 162 163 if (!dcs) { 164 rte_errno = ENOMEM; 165 return NULL; 166 } 167 MLX5_SET(alloc_flow_counter_in, in, opcode, 168 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 169 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 170 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 171 sizeof(in), out, sizeof(out)); 172 if (!dcs->obj) { 173 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 174 rte_errno = errno; 175 mlx5_free(dcs); 176 return NULL; 177 } 178 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 179 return dcs; 180 } 181 182 /** 183 * Query flow counters values. 184 * 185 * @param[in] dcs 186 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 187 * @param[in] clear 188 * Whether hardware should clear the counters after the query or not. 189 * @param[in] n_counters 190 * 0 in case of 1 counter to read, otherwise the counter number to read. 191 * @param pkts 192 * The number of packets that matched the flow. 193 * @param bytes 194 * The number of bytes that matched the flow. 195 * @param mkey 196 * The mkey key for batch query. 197 * @param addr 198 * The address in the mkey range for batch query. 199 * @param cmd_comp 200 * The completion object for asynchronous batch query. 201 * @param async_id 202 * The ID to be returned in the asynchronous batch query response. 203 * 204 * @return 205 * 0 on success, a negative value otherwise. 206 */ 207 int 208 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 209 int clear, uint32_t n_counters, 210 uint64_t *pkts, uint64_t *bytes, 211 uint32_t mkey, void *addr, 212 void *cmd_comp, 213 uint64_t async_id) 214 { 215 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 216 MLX5_ST_SZ_BYTES(traffic_counter); 217 uint32_t out[out_len]; 218 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 219 void *stats; 220 int rc; 221 222 MLX5_SET(query_flow_counter_in, in, opcode, 223 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 224 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 225 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 226 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 227 228 if (n_counters) { 229 MLX5_SET(query_flow_counter_in, in, num_of_counters, 230 n_counters); 231 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 232 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 233 MLX5_SET64(query_flow_counter_in, in, address, 234 (uint64_t)(uintptr_t)addr); 235 } 236 if (!cmd_comp) 237 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 238 out_len); 239 else 240 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 241 out_len, async_id, 242 cmd_comp); 243 if (rc) { 244 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 245 rte_errno = rc; 246 return -rc; 247 } 248 if (!n_counters) { 249 stats = MLX5_ADDR_OF(query_flow_counter_out, 250 out, flow_statistics); 251 *pkts = MLX5_GET64(traffic_counter, stats, packets); 252 *bytes = MLX5_GET64(traffic_counter, stats, octets); 253 } 254 return 0; 255 } 256 257 /** 258 * Create a new mkey. 259 * 260 * @param[in] ctx 261 * Context returned from mlx5 open_device() glue function. 262 * @param[in] attr 263 * Attributes of the requested mkey. 264 * 265 * @return 266 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 267 * is set. 268 */ 269 struct mlx5_devx_obj * 270 mlx5_devx_cmd_mkey_create(void *ctx, 271 struct mlx5_devx_mkey_attr *attr) 272 { 273 struct mlx5_klm *klm_array = attr->klm_array; 274 int klm_num = attr->klm_num; 275 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 276 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 277 uint32_t in[in_size_dw]; 278 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 279 void *mkc; 280 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 281 0, SOCKET_ID_ANY); 282 size_t pgsize; 283 uint32_t translation_size; 284 285 if (!mkey) { 286 rte_errno = ENOMEM; 287 return NULL; 288 } 289 memset(in, 0, in_size_dw * 4); 290 pgsize = rte_mem_page_size(); 291 if (pgsize == (size_t)-1) { 292 mlx5_free(mkey); 293 DRV_LOG(ERR, "Failed to get page size"); 294 rte_errno = ENOMEM; 295 return NULL; 296 } 297 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 298 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 299 if (klm_num > 0) { 300 int i; 301 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 302 klm_pas_mtt); 303 translation_size = RTE_ALIGN(klm_num, 4); 304 for (i = 0; i < klm_num; i++) { 305 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 306 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 307 MLX5_SET64(klm, klm, address, klm_array[i].address); 308 klm += MLX5_ST_SZ_BYTES(klm); 309 } 310 for (; i < (int)translation_size; i++) { 311 MLX5_SET(klm, klm, mkey, 0x0); 312 MLX5_SET64(klm, klm, address, 0x0); 313 klm += MLX5_ST_SZ_BYTES(klm); 314 } 315 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 316 MLX5_MKC_ACCESS_MODE_KLM_FBS : 317 MLX5_MKC_ACCESS_MODE_KLM); 318 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 319 } else { 320 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 321 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 322 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 323 } 324 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 325 translation_size); 326 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 327 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 328 MLX5_SET(mkc, mkc, lw, 0x1); 329 MLX5_SET(mkc, mkc, lr, 0x1); 330 if (attr->set_remote_rw) { 331 MLX5_SET(mkc, mkc, rw, 0x1); 332 MLX5_SET(mkc, mkc, rr, 0x1); 333 } 334 MLX5_SET(mkc, mkc, qpn, 0xffffff); 335 MLX5_SET(mkc, mkc, pd, attr->pd); 336 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 337 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 338 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 339 MLX5_SET(mkc, mkc, relaxed_ordering_write, 340 attr->relaxed_ordering_write); 341 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 342 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 343 MLX5_SET64(mkc, mkc, len, attr->size); 344 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 345 if (attr->crypto_en) { 346 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 347 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 348 } 349 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 350 sizeof(out)); 351 if (!mkey->obj) { 352 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d", 353 klm_num ? "an in" : "a ", errno); 354 rte_errno = errno; 355 mlx5_free(mkey); 356 return NULL; 357 } 358 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 359 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 360 return mkey; 361 } 362 363 /** 364 * Get status of devx command response. 365 * Mainly used for asynchronous commands. 366 * 367 * @param[in] out 368 * The out response buffer. 369 * 370 * @return 371 * 0 on success, non-zero value otherwise. 372 */ 373 int 374 mlx5_devx_get_out_command_status(void *out) 375 { 376 int status; 377 378 if (!out) 379 return -EINVAL; 380 status = MLX5_GET(query_flow_counter_out, out, status); 381 if (status) { 382 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 383 384 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 385 syndrome); 386 } 387 return status; 388 } 389 390 /** 391 * Destroy any object allocated by a Devx API. 392 * 393 * @param[in] obj 394 * Pointer to a general object. 395 * 396 * @return 397 * 0 on success, a negative value otherwise. 398 */ 399 int 400 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 401 { 402 int ret; 403 404 if (!obj) 405 return 0; 406 ret = mlx5_glue->devx_obj_destroy(obj->obj); 407 mlx5_free(obj); 408 return ret; 409 } 410 411 /** 412 * Query NIC vport context. 413 * Fills minimal inline attribute. 414 * 415 * @param[in] ctx 416 * ibv contexts returned from mlx5dv_open_device. 417 * @param[in] vport 418 * vport index 419 * @param[out] attr 420 * Attributes device values. 421 * 422 * @return 423 * 0 on success, a negative value otherwise. 424 */ 425 static int 426 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 427 unsigned int vport, 428 struct mlx5_hca_attr *attr) 429 { 430 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 431 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 432 void *vctx; 433 int status, syndrome, rc; 434 435 /* Query NIC vport context to determine inline mode. */ 436 MLX5_SET(query_nic_vport_context_in, in, opcode, 437 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 438 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 439 if (vport) 440 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 441 rc = mlx5_glue->devx_general_cmd(ctx, 442 in, sizeof(in), 443 out, sizeof(out)); 444 if (rc) 445 goto error; 446 status = MLX5_GET(query_nic_vport_context_out, out, status); 447 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 448 if (status) { 449 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 450 "status %x, syndrome = %x", status, syndrome); 451 return -1; 452 } 453 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 454 nic_vport_context); 455 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 456 min_wqe_inline_mode); 457 return 0; 458 error: 459 rc = (rc > 0) ? -rc : rc; 460 return rc; 461 } 462 463 /** 464 * Query NIC vDPA attributes. 465 * 466 * @param[in] ctx 467 * Context returned from mlx5 open_device() glue function. 468 * @param[out] vdpa_attr 469 * vDPA Attributes structure to fill. 470 */ 471 static void 472 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 473 struct mlx5_hca_vdpa_attr *vdpa_attr) 474 { 475 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 476 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 477 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 478 int status, syndrome, rc; 479 480 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 481 MLX5_SET(query_hca_cap_in, in, op_mod, 482 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 483 MLX5_HCA_CAP_OPMOD_GET_CUR); 484 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 485 status = MLX5_GET(query_hca_cap_out, out, status); 486 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 487 if (rc || status) { 488 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities," 489 " status %x, syndrome = %x", status, syndrome); 490 vdpa_attr->valid = 0; 491 } else { 492 vdpa_attr->valid = 1; 493 vdpa_attr->desc_tunnel_offload_type = 494 MLX5_GET(virtio_emulation_cap, hcattr, 495 desc_tunnel_offload_type); 496 vdpa_attr->eth_frame_offload_type = 497 MLX5_GET(virtio_emulation_cap, hcattr, 498 eth_frame_offload_type); 499 vdpa_attr->virtio_version_1_0 = 500 MLX5_GET(virtio_emulation_cap, hcattr, 501 virtio_version_1_0); 502 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 503 tso_ipv4); 504 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 505 tso_ipv6); 506 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 507 tx_csum); 508 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 509 rx_csum); 510 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 511 event_mode); 512 vdpa_attr->virtio_queue_type = 513 MLX5_GET(virtio_emulation_cap, hcattr, 514 virtio_queue_type); 515 vdpa_attr->log_doorbell_stride = 516 MLX5_GET(virtio_emulation_cap, hcattr, 517 log_doorbell_stride); 518 vdpa_attr->log_doorbell_bar_size = 519 MLX5_GET(virtio_emulation_cap, hcattr, 520 log_doorbell_bar_size); 521 vdpa_attr->doorbell_bar_offset = 522 MLX5_GET64(virtio_emulation_cap, hcattr, 523 doorbell_bar_offset); 524 vdpa_attr->max_num_virtio_queues = 525 MLX5_GET(virtio_emulation_cap, hcattr, 526 max_num_virtio_queues); 527 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 528 umem_1_buffer_param_a); 529 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 530 umem_1_buffer_param_b); 531 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 532 umem_2_buffer_param_a); 533 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 534 umem_2_buffer_param_b); 535 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 536 umem_3_buffer_param_a); 537 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 538 umem_3_buffer_param_b); 539 } 540 } 541 542 int 543 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 544 uint32_t ids[], uint32_t num) 545 { 546 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 547 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 548 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 549 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 550 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 551 int ret; 552 uint32_t idx = 0; 553 uint32_t i; 554 555 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 556 rte_errno = EINVAL; 557 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 558 return -rte_errno; 559 } 560 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 561 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 562 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 563 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 564 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 565 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 566 out, sizeof(out)); 567 if (ret) { 568 rte_errno = ret; 569 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 570 (void *)flex_obj); 571 return -rte_errno; 572 } 573 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 574 void *s_off = (void *)((char *)sample + i * 575 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 576 uint32_t en; 577 578 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 579 flow_match_sample_en); 580 if (!en) 581 continue; 582 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 583 flow_match_sample_field_id); 584 } 585 if (num != idx) { 586 rte_errno = EINVAL; 587 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 588 return -rte_errno; 589 } 590 return ret; 591 } 592 593 594 struct mlx5_devx_obj * 595 mlx5_devx_cmd_create_flex_parser(void *ctx, 596 struct mlx5_devx_graph_node_attr *data) 597 { 598 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 599 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 600 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 601 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 602 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 603 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 604 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 605 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 606 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 607 uint32_t i; 608 609 if (!parse_flex_obj) { 610 DRV_LOG(ERR, "Failed to allocate flex parser data."); 611 rte_errno = ENOMEM; 612 return NULL; 613 } 614 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 615 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 616 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 617 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 618 MLX5_SET(parse_graph_flex, flex, header_length_mode, 619 data->header_length_mode); 620 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 621 data->header_length_base_value); 622 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 623 data->header_length_field_offset); 624 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 625 data->header_length_field_shift); 626 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 627 data->header_length_field_mask); 628 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 629 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 630 void *s_off = (void *)((char *)sample + i * 631 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 632 633 if (!s->flow_match_sample_en) 634 continue; 635 MLX5_SET(parse_graph_flow_match_sample, s_off, 636 flow_match_sample_en, !!s->flow_match_sample_en); 637 MLX5_SET(parse_graph_flow_match_sample, s_off, 638 flow_match_sample_field_offset, 639 s->flow_match_sample_field_offset); 640 MLX5_SET(parse_graph_flow_match_sample, s_off, 641 flow_match_sample_offset_mode, 642 s->flow_match_sample_offset_mode); 643 MLX5_SET(parse_graph_flow_match_sample, s_off, 644 flow_match_sample_field_offset_mask, 645 s->flow_match_sample_field_offset_mask); 646 MLX5_SET(parse_graph_flow_match_sample, s_off, 647 flow_match_sample_field_offset_shift, 648 s->flow_match_sample_field_offset_shift); 649 MLX5_SET(parse_graph_flow_match_sample, s_off, 650 flow_match_sample_field_base_offset, 651 s->flow_match_sample_field_base_offset); 652 MLX5_SET(parse_graph_flow_match_sample, s_off, 653 flow_match_sample_tunnel_mode, 654 s->flow_match_sample_tunnel_mode); 655 } 656 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 657 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 658 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 659 void *in_off = (void *)((char *)in_arc + i * 660 MLX5_ST_SZ_BYTES(parse_graph_arc)); 661 void *out_off = (void *)((char *)out_arc + i * 662 MLX5_ST_SZ_BYTES(parse_graph_arc)); 663 664 if (ia->arc_parse_graph_node != 0) { 665 MLX5_SET(parse_graph_arc, in_off, 666 compare_condition_value, 667 ia->compare_condition_value); 668 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 669 ia->start_inner_tunnel); 670 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 671 ia->arc_parse_graph_node); 672 MLX5_SET(parse_graph_arc, in_off, 673 parse_graph_node_handle, 674 ia->parse_graph_node_handle); 675 } 676 if (oa->arc_parse_graph_node != 0) { 677 MLX5_SET(parse_graph_arc, out_off, 678 compare_condition_value, 679 oa->compare_condition_value); 680 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 681 oa->start_inner_tunnel); 682 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 683 oa->arc_parse_graph_node); 684 MLX5_SET(parse_graph_arc, out_off, 685 parse_graph_node_handle, 686 oa->parse_graph_node_handle); 687 } 688 } 689 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 690 out, sizeof(out)); 691 if (!parse_flex_obj->obj) { 692 rte_errno = errno; 693 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 694 "by using DevX."); 695 mlx5_free(parse_flex_obj); 696 return NULL; 697 } 698 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 699 return parse_flex_obj; 700 } 701 702 static int 703 mlx5_devx_query_pkt_integrity_match(void *hcattr) 704 { 705 return MLX5_GET(flow_table_nic_cap, hcattr, 706 ft_field_support_2_nic_receive.inner_l3_ok) && 707 MLX5_GET(flow_table_nic_cap, hcattr, 708 ft_field_support_2_nic_receive.inner_l4_ok) && 709 MLX5_GET(flow_table_nic_cap, hcattr, 710 ft_field_support_2_nic_receive.outer_l3_ok) && 711 MLX5_GET(flow_table_nic_cap, hcattr, 712 ft_field_support_2_nic_receive.outer_l4_ok) && 713 MLX5_GET(flow_table_nic_cap, hcattr, 714 ft_field_support_2_nic_receive 715 .inner_ipv4_checksum_ok) && 716 MLX5_GET(flow_table_nic_cap, hcattr, 717 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 718 MLX5_GET(flow_table_nic_cap, hcattr, 719 ft_field_support_2_nic_receive 720 .outer_ipv4_checksum_ok) && 721 MLX5_GET(flow_table_nic_cap, hcattr, 722 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 723 } 724 725 /** 726 * Query HCA attributes. 727 * Using those attributes we can check on run time if the device 728 * is having the required capabilities. 729 * 730 * @param[in] ctx 731 * Context returned from mlx5 open_device() glue function. 732 * @param[out] attr 733 * Attributes device values. 734 * 735 * @return 736 * 0 on success, a negative value otherwise. 737 */ 738 int 739 mlx5_devx_cmd_query_hca_attr(void *ctx, 740 struct mlx5_hca_attr *attr) 741 { 742 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 743 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 744 void *hcattr; 745 int status, syndrome, rc, i; 746 uint64_t general_obj_types_supported = 0; 747 748 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 749 MLX5_SET(query_hca_cap_in, in, op_mod, 750 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 751 MLX5_HCA_CAP_OPMOD_GET_CUR); 752 753 rc = mlx5_glue->devx_general_cmd(ctx, 754 in, sizeof(in), out, sizeof(out)); 755 if (rc) 756 goto error; 757 status = MLX5_GET(query_hca_cap_out, out, status); 758 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 759 if (status) { 760 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 761 "status %x, syndrome = %x", status, syndrome); 762 return -1; 763 } 764 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 765 attr->flow_counter_bulk_alloc_bitmap = 766 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 767 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 768 flow_counters_dump); 769 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 770 log_max_rqt_size); 771 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 772 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 773 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 774 log_max_hairpin_queues); 775 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 776 log_max_hairpin_wq_data_sz); 777 attr->log_max_hairpin_num_packets = MLX5_GET 778 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 779 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 780 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 781 relaxed_ordering_write); 782 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 783 relaxed_ordering_read); 784 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 785 access_register_user); 786 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 787 eth_net_offloads); 788 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 789 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 790 flex_parser_protocols); 791 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 792 max_geneve_tlv_options); 793 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 794 max_geneve_tlv_option_data_len); 795 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 796 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 797 general_obj_types) & 798 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 799 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 800 general_obj_types) & 801 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 802 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 803 general_obj_types) & 804 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 805 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 806 general_obj_types) & 807 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 808 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 809 wqe_index_ignore_cap); 810 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 811 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 812 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 813 log_max_static_sq_wq); 814 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 815 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 816 device_frequency_khz); 817 attr->scatter_fcs_w_decap_disable = 818 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 819 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 820 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 821 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 822 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp); 823 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 824 regexp_num_of_engines); 825 /* Read the general_obj_types bitmap and extract the relevant bits. */ 826 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 827 general_obj_types); 828 attr->vdpa.valid = !!(general_obj_types_supported & 829 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 830 attr->vdpa.queue_counters_valid = 831 !!(general_obj_types_supported & 832 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 833 attr->parse_graph_flex_node = 834 !!(general_obj_types_supported & 835 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 836 attr->flow_hit_aso = !!(general_obj_types_supported & 837 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 838 attr->geneve_tlv_opt = !!(general_obj_types_supported & 839 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 840 attr->dek = !!(general_obj_types_supported & 841 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 842 attr->import_kek = !!(general_obj_types_supported & 843 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 844 attr->credential = !!(general_obj_types_supported & 845 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 846 attr->crypto_login = !!(general_obj_types_supported & 847 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 848 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 849 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 850 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 851 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 852 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 853 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 854 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 855 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 856 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 857 attr->reg_c_preserve = 858 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 859 attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo); 860 attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress); 861 attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress); 862 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 863 compress_min_block_size); 864 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 865 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 866 log_compress_mmo_size); 867 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 868 log_decompress_mmo_size); 869 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 870 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 871 mini_cqe_resp_flow_tag); 872 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 873 mini_cqe_resp_l3_l4_tag); 874 attr->umr_indirect_mkey_disabled = 875 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 876 attr->umr_modify_entity_size_disabled = 877 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 878 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 879 if (attr->crypto) 880 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts); 881 if (attr->qos.sup) { 882 MLX5_SET(query_hca_cap_in, in, op_mod, 883 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 884 MLX5_HCA_CAP_OPMOD_GET_CUR); 885 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 886 out, sizeof(out)); 887 if (rc) 888 goto error; 889 if (status) { 890 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities," 891 " status %x, syndrome = %x", status, syndrome); 892 return -1; 893 } 894 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 895 attr->qos.flow_meter_old = 896 MLX5_GET(qos_cap, hcattr, flow_meter_old); 897 attr->qos.log_max_flow_meter = 898 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 899 attr->qos.flow_meter_reg_c_ids = 900 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 901 attr->qos.flow_meter = 902 MLX5_GET(qos_cap, hcattr, flow_meter); 903 attr->qos.packet_pacing = 904 MLX5_GET(qos_cap, hcattr, packet_pacing); 905 attr->qos.wqe_rate_pp = 906 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 907 if (attr->qos.flow_meter_aso_sup) { 908 attr->qos.log_meter_aso_granularity = 909 MLX5_GET(qos_cap, hcattr, 910 log_meter_aso_granularity); 911 attr->qos.log_meter_aso_max_alloc = 912 MLX5_GET(qos_cap, hcattr, 913 log_meter_aso_max_alloc); 914 attr->qos.log_max_num_meter_aso = 915 MLX5_GET(qos_cap, hcattr, 916 log_max_num_meter_aso); 917 } 918 } 919 if (attr->vdpa.valid) 920 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 921 if (!attr->eth_net_offloads) 922 return 0; 923 924 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 925 memset(in, 0, sizeof(in)); 926 memset(out, 0, sizeof(out)); 927 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 928 MLX5_SET(query_hca_cap_in, in, op_mod, 929 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 930 MLX5_HCA_CAP_OPMOD_GET_CUR); 931 932 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 933 if (rc) 934 goto error; 935 status = MLX5_GET(query_hca_cap_out, out, status); 936 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 937 if (status) { 938 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 939 "status %x, syndrome = %x", status, syndrome); 940 attr->log_max_ft_sampler_num = 0; 941 return -1; 942 } 943 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 944 attr->log_max_ft_sampler_num = MLX5_GET 945 (flow_table_nic_cap, hcattr, 946 flow_table_properties_nic_receive.log_max_ft_sampler_num); 947 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 948 /* Query HCA offloads for Ethernet protocol. */ 949 memset(in, 0, sizeof(in)); 950 memset(out, 0, sizeof(out)); 951 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 952 MLX5_SET(query_hca_cap_in, in, op_mod, 953 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 954 MLX5_HCA_CAP_OPMOD_GET_CUR); 955 956 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 957 if (rc) { 958 attr->eth_net_offloads = 0; 959 goto error; 960 } 961 status = MLX5_GET(query_hca_cap_out, out, status); 962 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 963 if (status) { 964 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 965 "status %x, syndrome = %x", status, syndrome); 966 attr->eth_net_offloads = 0; 967 return -1; 968 } 969 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 970 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 971 hcattr, wqe_vlan_insert); 972 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 973 hcattr, csum_cap); 974 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 975 lro_cap); 976 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 977 hcattr, tunnel_lro_gre); 978 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 979 hcattr, tunnel_lro_vxlan); 980 attr->lro_max_msg_sz_mode = MLX5_GET 981 (per_protocol_networking_offload_caps, 982 hcattr, lro_max_msg_sz_mode); 983 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 984 attr->lro_timer_supported_periods[i] = 985 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 986 lro_timer_supported_periods[i]); 987 } 988 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 989 hcattr, lro_min_mss_size); 990 attr->tunnel_stateless_geneve_rx = 991 MLX5_GET(per_protocol_networking_offload_caps, 992 hcattr, tunnel_stateless_geneve_rx); 993 attr->geneve_max_opt_len = 994 MLX5_GET(per_protocol_networking_offload_caps, 995 hcattr, max_geneve_opt_len); 996 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 997 hcattr, wqe_inline_mode); 998 attr->tunnel_stateless_gtp = MLX5_GET 999 (per_protocol_networking_offload_caps, 1000 hcattr, tunnel_stateless_gtp); 1001 attr->rss_ind_tbl_cap = MLX5_GET 1002 (per_protocol_networking_offload_caps, 1003 hcattr, rss_ind_tbl_cap); 1004 /* Query HCA attribute for ROCE. */ 1005 if (attr->roce) { 1006 memset(in, 0, sizeof(in)); 1007 memset(out, 0, sizeof(out)); 1008 MLX5_SET(query_hca_cap_in, in, opcode, 1009 MLX5_CMD_OP_QUERY_HCA_CAP); 1010 MLX5_SET(query_hca_cap_in, in, op_mod, 1011 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1012 MLX5_HCA_CAP_OPMOD_GET_CUR); 1013 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 1014 out, sizeof(out)); 1015 if (rc) 1016 goto error; 1017 status = MLX5_GET(query_hca_cap_out, out, status); 1018 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 1019 if (status) { 1020 DRV_LOG(DEBUG, 1021 "Failed to query devx HCA ROCE capabilities, " 1022 "status %x, syndrome = %x", status, syndrome); 1023 return -1; 1024 } 1025 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 1026 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1027 } 1028 if (attr->eth_virt && 1029 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1030 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1031 if (rc) { 1032 attr->eth_virt = 0; 1033 goto error; 1034 } 1035 } 1036 return 0; 1037 error: 1038 rc = (rc > 0) ? -rc : rc; 1039 return rc; 1040 } 1041 1042 /** 1043 * Query TIS transport domain from QP verbs object using DevX API. 1044 * 1045 * @param[in] qp 1046 * Pointer to verbs QP returned by ibv_create_qp . 1047 * @param[in] tis_num 1048 * TIS number of TIS to query. 1049 * @param[out] tis_td 1050 * Pointer to TIS transport domain variable, to be set by the routine. 1051 * 1052 * @return 1053 * 0 on success, a negative value otherwise. 1054 */ 1055 int 1056 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1057 uint32_t *tis_td) 1058 { 1059 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1060 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1061 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1062 int rc; 1063 void *tis_ctx; 1064 1065 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1066 MLX5_SET(query_tis_in, in, tisn, tis_num); 1067 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1068 if (rc) { 1069 DRV_LOG(ERR, "Failed to query QP using DevX"); 1070 return -rc; 1071 }; 1072 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1073 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1074 return 0; 1075 #else 1076 (void)qp; 1077 (void)tis_num; 1078 (void)tis_td; 1079 return -ENOTSUP; 1080 #endif 1081 } 1082 1083 /** 1084 * Fill WQ data for DevX API command. 1085 * Utility function for use when creating DevX objects containing a WQ. 1086 * 1087 * @param[in] wq_ctx 1088 * Pointer to WQ context to fill with data. 1089 * @param [in] wq_attr 1090 * Pointer to WQ attributes structure to fill in WQ context. 1091 */ 1092 static void 1093 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1094 { 1095 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1096 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1097 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1098 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1099 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1100 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1101 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1102 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1103 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1104 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1105 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1106 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1107 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1108 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1109 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1110 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1111 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1112 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1113 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1114 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1115 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1116 wq_attr->log_hairpin_num_packets); 1117 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1118 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1119 wq_attr->single_wqe_log_num_of_strides); 1120 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1121 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1122 wq_attr->single_stride_log_num_of_bytes); 1123 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1124 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1125 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1126 } 1127 1128 /** 1129 * Create RQ using DevX API. 1130 * 1131 * @param[in] ctx 1132 * Context returned from mlx5 open_device() glue function. 1133 * @param [in] rq_attr 1134 * Pointer to create RQ attributes structure. 1135 * @param [in] socket 1136 * CPU socket ID for allocations. 1137 * 1138 * @return 1139 * The DevX object created, NULL otherwise and rte_errno is set. 1140 */ 1141 struct mlx5_devx_obj * 1142 mlx5_devx_cmd_create_rq(void *ctx, 1143 struct mlx5_devx_create_rq_attr *rq_attr, 1144 int socket) 1145 { 1146 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1147 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1148 void *rq_ctx, *wq_ctx; 1149 struct mlx5_devx_wq_attr *wq_attr; 1150 struct mlx5_devx_obj *rq = NULL; 1151 1152 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1153 if (!rq) { 1154 DRV_LOG(ERR, "Failed to allocate RQ data"); 1155 rte_errno = ENOMEM; 1156 return NULL; 1157 } 1158 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1159 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1160 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1161 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1162 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1163 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1164 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1165 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1166 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1167 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1168 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1169 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1170 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1171 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1172 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1173 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1174 wq_attr = &rq_attr->wq_attr; 1175 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1176 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1177 out, sizeof(out)); 1178 if (!rq->obj) { 1179 DRV_LOG(ERR, "Failed to create RQ using DevX"); 1180 rte_errno = errno; 1181 mlx5_free(rq); 1182 return NULL; 1183 } 1184 rq->id = MLX5_GET(create_rq_out, out, rqn); 1185 return rq; 1186 } 1187 1188 /** 1189 * Modify RQ using DevX API. 1190 * 1191 * @param[in] rq 1192 * Pointer to RQ object structure. 1193 * @param [in] rq_attr 1194 * Pointer to modify RQ attributes structure. 1195 * 1196 * @return 1197 * 0 on success, a negative errno value otherwise and rte_errno is set. 1198 */ 1199 int 1200 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1201 struct mlx5_devx_modify_rq_attr *rq_attr) 1202 { 1203 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1204 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1205 void *rq_ctx, *wq_ctx; 1206 int ret; 1207 1208 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1209 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1210 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1211 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1212 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1213 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1214 if (rq_attr->modify_bitmask & 1215 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1216 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1217 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1218 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1219 if (rq_attr->modify_bitmask & 1220 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1221 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1222 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1223 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1224 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1225 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1226 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1227 } 1228 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1229 out, sizeof(out)); 1230 if (ret) { 1231 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1232 rte_errno = errno; 1233 return -errno; 1234 } 1235 return ret; 1236 } 1237 1238 /** 1239 * Create TIR using DevX API. 1240 * 1241 * @param[in] ctx 1242 * Context returned from mlx5 open_device() glue function. 1243 * @param [in] tir_attr 1244 * Pointer to TIR attributes structure. 1245 * 1246 * @return 1247 * The DevX object created, NULL otherwise and rte_errno is set. 1248 */ 1249 struct mlx5_devx_obj * 1250 mlx5_devx_cmd_create_tir(void *ctx, 1251 struct mlx5_devx_tir_attr *tir_attr) 1252 { 1253 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1254 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1255 void *tir_ctx, *outer, *inner, *rss_key; 1256 struct mlx5_devx_obj *tir = NULL; 1257 1258 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1259 if (!tir) { 1260 DRV_LOG(ERR, "Failed to allocate TIR data"); 1261 rte_errno = ENOMEM; 1262 return NULL; 1263 } 1264 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1265 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1266 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1267 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1268 tir_attr->lro_timeout_period_usecs); 1269 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1270 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1271 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1272 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1273 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1274 tir_attr->tunneled_offload_en); 1275 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1276 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1277 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1278 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1279 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1280 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1281 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1282 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1283 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1284 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1285 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1286 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1287 tir_attr->rx_hash_field_selector_outer.selected_fields); 1288 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1289 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1290 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1291 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1292 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1293 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1294 tir_attr->rx_hash_field_selector_inner.selected_fields); 1295 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1296 out, sizeof(out)); 1297 if (!tir->obj) { 1298 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1299 rte_errno = errno; 1300 mlx5_free(tir); 1301 return NULL; 1302 } 1303 tir->id = MLX5_GET(create_tir_out, out, tirn); 1304 return tir; 1305 } 1306 1307 /** 1308 * Modify TIR using DevX API. 1309 * 1310 * @param[in] tir 1311 * Pointer to TIR DevX object structure. 1312 * @param [in] modify_tir_attr 1313 * Pointer to TIR modification attributes structure. 1314 * 1315 * @return 1316 * 0 on success, a negative errno value otherwise and rte_errno is set. 1317 */ 1318 int 1319 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1320 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1321 { 1322 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1323 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1324 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1325 void *tir_ctx; 1326 int ret; 1327 1328 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1329 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1330 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1331 modify_tir_attr->modify_bitmask); 1332 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1333 if (modify_tir_attr->modify_bitmask & 1334 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1335 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1336 tir_attr->lro_timeout_period_usecs); 1337 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1338 tir_attr->lro_enable_mask); 1339 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1340 tir_attr->lro_max_msg_sz); 1341 } 1342 if (modify_tir_attr->modify_bitmask & 1343 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1344 MLX5_SET(tirc, tir_ctx, indirect_table, 1345 tir_attr->indirect_table); 1346 if (modify_tir_attr->modify_bitmask & 1347 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1348 int i; 1349 void *outer, *inner; 1350 1351 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1352 tir_attr->rx_hash_symmetric); 1353 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1354 for (i = 0; i < 10; i++) { 1355 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1356 tir_attr->rx_hash_toeplitz_key[i]); 1357 } 1358 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1359 rx_hash_field_selector_outer); 1360 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1361 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1362 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1363 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1364 MLX5_SET 1365 (rx_hash_field_select, outer, selected_fields, 1366 tir_attr->rx_hash_field_selector_outer.selected_fields); 1367 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1368 rx_hash_field_selector_inner); 1369 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1370 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1371 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1372 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1373 MLX5_SET 1374 (rx_hash_field_select, inner, selected_fields, 1375 tir_attr->rx_hash_field_selector_inner.selected_fields); 1376 } 1377 if (modify_tir_attr->modify_bitmask & 1378 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1379 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1380 } 1381 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1382 out, sizeof(out)); 1383 if (ret) { 1384 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1385 rte_errno = errno; 1386 return -errno; 1387 } 1388 return ret; 1389 } 1390 1391 /** 1392 * Create RQT using DevX API. 1393 * 1394 * @param[in] ctx 1395 * Context returned from mlx5 open_device() glue function. 1396 * @param [in] rqt_attr 1397 * Pointer to RQT attributes structure. 1398 * 1399 * @return 1400 * The DevX object created, NULL otherwise and rte_errno is set. 1401 */ 1402 struct mlx5_devx_obj * 1403 mlx5_devx_cmd_create_rqt(void *ctx, 1404 struct mlx5_devx_rqt_attr *rqt_attr) 1405 { 1406 uint32_t *in = NULL; 1407 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1408 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1409 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1410 void *rqt_ctx; 1411 struct mlx5_devx_obj *rqt = NULL; 1412 int i; 1413 1414 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1415 if (!in) { 1416 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1417 rte_errno = ENOMEM; 1418 return NULL; 1419 } 1420 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1421 if (!rqt) { 1422 DRV_LOG(ERR, "Failed to allocate RQT data"); 1423 rte_errno = ENOMEM; 1424 mlx5_free(in); 1425 return NULL; 1426 } 1427 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1428 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1429 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1430 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1431 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1432 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1433 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1434 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1435 mlx5_free(in); 1436 if (!rqt->obj) { 1437 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1438 rte_errno = errno; 1439 mlx5_free(rqt); 1440 return NULL; 1441 } 1442 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1443 return rqt; 1444 } 1445 1446 /** 1447 * Modify RQT using DevX API. 1448 * 1449 * @param[in] rqt 1450 * Pointer to RQT DevX object structure. 1451 * @param [in] rqt_attr 1452 * Pointer to RQT attributes structure. 1453 * 1454 * @return 1455 * 0 on success, a negative errno value otherwise and rte_errno is set. 1456 */ 1457 int 1458 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1459 struct mlx5_devx_rqt_attr *rqt_attr) 1460 { 1461 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1462 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1463 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1464 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1465 void *rqt_ctx; 1466 int i; 1467 int ret; 1468 1469 if (!in) { 1470 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1471 rte_errno = ENOMEM; 1472 return -ENOMEM; 1473 } 1474 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1475 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1476 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1477 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1478 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1479 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1480 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1481 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1482 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1483 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1484 mlx5_free(in); 1485 if (ret) { 1486 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1487 rte_errno = errno; 1488 return -rte_errno; 1489 } 1490 return ret; 1491 } 1492 1493 /** 1494 * Create SQ using DevX API. 1495 * 1496 * @param[in] ctx 1497 * Context returned from mlx5 open_device() glue function. 1498 * @param [in] sq_attr 1499 * Pointer to SQ attributes structure. 1500 * @param [in] socket 1501 * CPU socket ID for allocations. 1502 * 1503 * @return 1504 * The DevX object created, NULL otherwise and rte_errno is set. 1505 **/ 1506 struct mlx5_devx_obj * 1507 mlx5_devx_cmd_create_sq(void *ctx, 1508 struct mlx5_devx_create_sq_attr *sq_attr) 1509 { 1510 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1511 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1512 void *sq_ctx; 1513 void *wq_ctx; 1514 struct mlx5_devx_wq_attr *wq_attr; 1515 struct mlx5_devx_obj *sq = NULL; 1516 1517 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1518 if (!sq) { 1519 DRV_LOG(ERR, "Failed to allocate SQ data"); 1520 rte_errno = ENOMEM; 1521 return NULL; 1522 } 1523 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1524 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1525 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1526 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1527 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1528 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1529 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1530 sq_attr->allow_multi_pkt_send_wqe); 1531 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1532 sq_attr->min_wqe_inline_mode); 1533 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1534 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1535 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1536 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1537 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1538 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1539 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1540 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1541 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1542 sq_attr->packet_pacing_rate_limit_index); 1543 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1544 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1545 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1546 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1547 wq_attr = &sq_attr->wq_attr; 1548 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1549 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1550 out, sizeof(out)); 1551 if (!sq->obj) { 1552 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1553 rte_errno = errno; 1554 mlx5_free(sq); 1555 return NULL; 1556 } 1557 sq->id = MLX5_GET(create_sq_out, out, sqn); 1558 return sq; 1559 } 1560 1561 /** 1562 * Modify SQ using DevX API. 1563 * 1564 * @param[in] sq 1565 * Pointer to SQ object structure. 1566 * @param [in] sq_attr 1567 * Pointer to SQ attributes structure. 1568 * 1569 * @return 1570 * 0 on success, a negative errno value otherwise and rte_errno is set. 1571 */ 1572 int 1573 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1574 struct mlx5_devx_modify_sq_attr *sq_attr) 1575 { 1576 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1577 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1578 void *sq_ctx; 1579 int ret; 1580 1581 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1582 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1583 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1584 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1585 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1586 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1587 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1588 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1589 out, sizeof(out)); 1590 if (ret) { 1591 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1592 rte_errno = errno; 1593 return -rte_errno; 1594 } 1595 return ret; 1596 } 1597 1598 /** 1599 * Create TIS using DevX API. 1600 * 1601 * @param[in] ctx 1602 * Context returned from mlx5 open_device() glue function. 1603 * @param [in] tis_attr 1604 * Pointer to TIS attributes structure. 1605 * 1606 * @return 1607 * The DevX object created, NULL otherwise and rte_errno is set. 1608 */ 1609 struct mlx5_devx_obj * 1610 mlx5_devx_cmd_create_tis(void *ctx, 1611 struct mlx5_devx_tis_attr *tis_attr) 1612 { 1613 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1614 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1615 struct mlx5_devx_obj *tis = NULL; 1616 void *tis_ctx; 1617 1618 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1619 if (!tis) { 1620 DRV_LOG(ERR, "Failed to allocate TIS object"); 1621 rte_errno = ENOMEM; 1622 return NULL; 1623 } 1624 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1625 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1626 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1627 tis_attr->strict_lag_tx_port_affinity); 1628 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1629 tis_attr->lag_tx_port_affinity); 1630 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1631 MLX5_SET(tisc, tis_ctx, transport_domain, 1632 tis_attr->transport_domain); 1633 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1634 out, sizeof(out)); 1635 if (!tis->obj) { 1636 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1637 rte_errno = errno; 1638 mlx5_free(tis); 1639 return NULL; 1640 } 1641 tis->id = MLX5_GET(create_tis_out, out, tisn); 1642 return tis; 1643 } 1644 1645 /** 1646 * Create transport domain using DevX API. 1647 * 1648 * @param[in] ctx 1649 * Context returned from mlx5 open_device() glue function. 1650 * @return 1651 * The DevX object created, NULL otherwise and rte_errno is set. 1652 */ 1653 struct mlx5_devx_obj * 1654 mlx5_devx_cmd_create_td(void *ctx) 1655 { 1656 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1657 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1658 struct mlx5_devx_obj *td = NULL; 1659 1660 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1661 if (!td) { 1662 DRV_LOG(ERR, "Failed to allocate TD object"); 1663 rte_errno = ENOMEM; 1664 return NULL; 1665 } 1666 MLX5_SET(alloc_transport_domain_in, in, opcode, 1667 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1668 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1669 out, sizeof(out)); 1670 if (!td->obj) { 1671 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1672 rte_errno = errno; 1673 mlx5_free(td); 1674 return NULL; 1675 } 1676 td->id = MLX5_GET(alloc_transport_domain_out, out, 1677 transport_domain); 1678 return td; 1679 } 1680 1681 /** 1682 * Dump all flows to file. 1683 * 1684 * @param[in] fdb_domain 1685 * FDB domain. 1686 * @param[in] rx_domain 1687 * RX domain. 1688 * @param[in] tx_domain 1689 * TX domain. 1690 * @param[out] file 1691 * Pointer to file stream. 1692 * 1693 * @return 1694 * 0 on success, a nagative value otherwise. 1695 */ 1696 int 1697 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1698 void *rx_domain __rte_unused, 1699 void *tx_domain __rte_unused, FILE *file __rte_unused) 1700 { 1701 int ret = 0; 1702 1703 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1704 if (fdb_domain) { 1705 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1706 if (ret) 1707 return ret; 1708 } 1709 MLX5_ASSERT(rx_domain); 1710 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1711 if (ret) 1712 return ret; 1713 MLX5_ASSERT(tx_domain); 1714 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1715 #else 1716 ret = ENOTSUP; 1717 #endif 1718 return -ret; 1719 } 1720 1721 int 1722 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 1723 FILE *file __rte_unused) 1724 { 1725 int ret = 0; 1726 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 1727 if (rule_info) 1728 ret = mlx5_glue->dr_dump_rule(file, rule_info); 1729 #else 1730 ret = ENOTSUP; 1731 #endif 1732 return -ret; 1733 } 1734 1735 /* 1736 * Create CQ using DevX API. 1737 * 1738 * @param[in] ctx 1739 * Context returned from mlx5 open_device() glue function. 1740 * @param [in] attr 1741 * Pointer to CQ attributes structure. 1742 * 1743 * @return 1744 * The DevX object created, NULL otherwise and rte_errno is set. 1745 */ 1746 struct mlx5_devx_obj * 1747 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1748 { 1749 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1750 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1751 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1752 sizeof(*cq_obj), 1753 0, SOCKET_ID_ANY); 1754 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1755 1756 if (!cq_obj) { 1757 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1758 rte_errno = ENOMEM; 1759 return NULL; 1760 } 1761 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1762 if (attr->db_umem_valid) { 1763 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1764 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1765 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1766 } else { 1767 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1768 } 1769 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1770 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1771 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1772 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1773 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1774 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1775 MLX5_SET(cqc, cqctx, log_page_size, 1776 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1777 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1778 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1779 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1780 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1781 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1782 attr->mini_cqe_res_format_ext); 1783 if (attr->q_umem_valid) { 1784 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1785 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1786 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1787 attr->q_umem_offset); 1788 } 1789 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1790 sizeof(out)); 1791 if (!cq_obj->obj) { 1792 rte_errno = errno; 1793 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1794 mlx5_free(cq_obj); 1795 return NULL; 1796 } 1797 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1798 return cq_obj; 1799 } 1800 1801 /** 1802 * Create VIRTQ using DevX API. 1803 * 1804 * @param[in] ctx 1805 * Context returned from mlx5 open_device() glue function. 1806 * @param [in] attr 1807 * Pointer to VIRTQ attributes structure. 1808 * 1809 * @return 1810 * The DevX object created, NULL otherwise and rte_errno is set. 1811 */ 1812 struct mlx5_devx_obj * 1813 mlx5_devx_cmd_create_virtq(void *ctx, 1814 struct mlx5_devx_virtq_attr *attr) 1815 { 1816 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1817 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1818 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1819 sizeof(*virtq_obj), 1820 0, SOCKET_ID_ANY); 1821 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1822 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1823 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1824 1825 if (!virtq_obj) { 1826 DRV_LOG(ERR, "Failed to allocate virtq data."); 1827 rte_errno = ENOMEM; 1828 return NULL; 1829 } 1830 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1831 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1832 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1833 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1834 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1835 attr->hw_available_index); 1836 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1837 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1838 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1839 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1840 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1841 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1842 attr->virtio_version_1_0); 1843 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1844 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1845 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1846 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1847 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1848 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1849 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1850 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1851 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1852 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 1853 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 1854 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 1855 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 1856 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 1857 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 1858 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 1859 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 1860 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 1861 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 1862 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 1863 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 1864 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 1865 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 1866 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1867 sizeof(out)); 1868 if (!virtq_obj->obj) { 1869 rte_errno = errno; 1870 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 1871 mlx5_free(virtq_obj); 1872 return NULL; 1873 } 1874 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1875 return virtq_obj; 1876 } 1877 1878 /** 1879 * Modify VIRTQ using DevX API. 1880 * 1881 * @param[in] virtq_obj 1882 * Pointer to virtq object structure. 1883 * @param [in] attr 1884 * Pointer to modify virtq attributes structure. 1885 * 1886 * @return 1887 * 0 on success, a negative errno value otherwise and rte_errno is set. 1888 */ 1889 int 1890 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 1891 struct mlx5_devx_virtq_attr *attr) 1892 { 1893 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1894 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1895 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1896 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1897 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1898 int ret; 1899 1900 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1901 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 1902 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1903 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1904 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1905 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 1906 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1907 switch (attr->type) { 1908 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 1909 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 1910 break; 1911 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 1912 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 1913 attr->dirty_bitmap_mkey); 1914 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 1915 attr->dirty_bitmap_addr); 1916 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 1917 attr->dirty_bitmap_size); 1918 break; 1919 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 1920 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 1921 attr->dirty_bitmap_dump_enable); 1922 break; 1923 default: 1924 rte_errno = EINVAL; 1925 return -rte_errno; 1926 } 1927 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 1928 out, sizeof(out)); 1929 if (ret) { 1930 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1931 rte_errno = errno; 1932 return -rte_errno; 1933 } 1934 return ret; 1935 } 1936 1937 /** 1938 * Query VIRTQ using DevX API. 1939 * 1940 * @param[in] virtq_obj 1941 * Pointer to virtq object structure. 1942 * @param [in/out] attr 1943 * Pointer to virtq attributes structure. 1944 * 1945 * @return 1946 * 0 on success, a negative errno value otherwise and rte_errno is set. 1947 */ 1948 int 1949 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 1950 struct mlx5_devx_virtq_attr *attr) 1951 { 1952 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1953 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 1954 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 1955 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 1956 int ret; 1957 1958 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1959 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1960 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1961 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1962 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1963 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 1964 out, sizeof(out)); 1965 if (ret) { 1966 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1967 rte_errno = errno; 1968 return -errno; 1969 } 1970 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 1971 hw_available_index); 1972 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 1973 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 1974 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 1975 virtio_q_context.error_type); 1976 return ret; 1977 } 1978 1979 /** 1980 * Create QP using DevX API. 1981 * 1982 * @param[in] ctx 1983 * Context returned from mlx5 open_device() glue function. 1984 * @param [in] attr 1985 * Pointer to QP attributes structure. 1986 * 1987 * @return 1988 * The DevX object created, NULL otherwise and rte_errno is set. 1989 */ 1990 struct mlx5_devx_obj * 1991 mlx5_devx_cmd_create_qp(void *ctx, 1992 struct mlx5_devx_qp_attr *attr) 1993 { 1994 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 1995 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 1996 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 1997 sizeof(*qp_obj), 1998 0, SOCKET_ID_ANY); 1999 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2000 2001 if (!qp_obj) { 2002 DRV_LOG(ERR, "Failed to allocate QP data."); 2003 rte_errno = ENOMEM; 2004 return NULL; 2005 } 2006 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2007 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2008 MLX5_SET(qpc, qpc, pd, attr->pd); 2009 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2010 if (attr->uar_index) { 2011 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2012 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2013 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2014 MLX5_SET(qpc, qpc, log_page_size, 2015 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2016 if (attr->sq_size) { 2017 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); 2018 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2019 MLX5_SET(qpc, qpc, log_sq_size, 2020 rte_log2_u32(attr->sq_size)); 2021 } else { 2022 MLX5_SET(qpc, qpc, no_sq, 1); 2023 } 2024 if (attr->rq_size) { 2025 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); 2026 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2027 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2028 MLX5_LOG_RQ_STRIDE_SHIFT); 2029 MLX5_SET(qpc, qpc, log_rq_size, 2030 rte_log2_u32(attr->rq_size)); 2031 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2032 } else { 2033 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2034 } 2035 if (attr->dbr_umem_valid) { 2036 MLX5_SET(qpc, qpc, dbr_umem_valid, 2037 attr->dbr_umem_valid); 2038 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2039 } 2040 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2041 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2042 attr->wq_umem_offset); 2043 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2044 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2045 } else { 2046 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2047 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2048 MLX5_SET(qpc, qpc, no_sq, 1); 2049 } 2050 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2051 sizeof(out)); 2052 if (!qp_obj->obj) { 2053 rte_errno = errno; 2054 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 2055 mlx5_free(qp_obj); 2056 return NULL; 2057 } 2058 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2059 return qp_obj; 2060 } 2061 2062 /** 2063 * Modify QP using DevX API. 2064 * Currently supports only force loop-back QP. 2065 * 2066 * @param[in] qp 2067 * Pointer to QP object structure. 2068 * @param [in] qp_st_mod_op 2069 * The QP state modification operation. 2070 * @param [in] remote_qp_id 2071 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2072 * 2073 * @return 2074 * 0 on success, a negative errno value otherwise and rte_errno is set. 2075 */ 2076 int 2077 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2078 uint32_t remote_qp_id) 2079 { 2080 union { 2081 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2082 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2083 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2084 } in; 2085 union { 2086 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2087 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2088 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2089 } out; 2090 void *qpc; 2091 int ret; 2092 unsigned int inlen; 2093 unsigned int outlen; 2094 2095 memset(&in, 0, sizeof(in)); 2096 memset(&out, 0, sizeof(out)); 2097 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2098 switch (qp_st_mod_op) { 2099 case MLX5_CMD_OP_RST2INIT_QP: 2100 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2101 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2102 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2103 MLX5_SET(qpc, qpc, rre, 1); 2104 MLX5_SET(qpc, qpc, rwe, 1); 2105 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2106 inlen = sizeof(in.rst2init); 2107 outlen = sizeof(out.rst2init); 2108 break; 2109 case MLX5_CMD_OP_INIT2RTR_QP: 2110 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2111 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2112 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2113 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2114 MLX5_SET(qpc, qpc, mtu, 1); 2115 MLX5_SET(qpc, qpc, log_msg_max, 30); 2116 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2117 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2118 inlen = sizeof(in.init2rtr); 2119 outlen = sizeof(out.init2rtr); 2120 break; 2121 case MLX5_CMD_OP_RTR2RTS_QP: 2122 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2123 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2124 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 2125 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2126 MLX5_SET(qpc, qpc, retry_count, 7); 2127 MLX5_SET(qpc, qpc, rnr_retry, 7); 2128 inlen = sizeof(in.rtr2rts); 2129 outlen = sizeof(out.rtr2rts); 2130 break; 2131 default: 2132 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2133 qp_st_mod_op); 2134 rte_errno = EINVAL; 2135 return -rte_errno; 2136 } 2137 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2138 if (ret) { 2139 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2140 rte_errno = errno; 2141 return -rte_errno; 2142 } 2143 return ret; 2144 } 2145 2146 struct mlx5_devx_obj * 2147 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2148 { 2149 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2150 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2151 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2152 sizeof(*couners_obj), 0, 2153 SOCKET_ID_ANY); 2154 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2155 2156 if (!couners_obj) { 2157 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2158 rte_errno = ENOMEM; 2159 return NULL; 2160 } 2161 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2162 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2163 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2164 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2165 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2166 sizeof(out)); 2167 if (!couners_obj->obj) { 2168 rte_errno = errno; 2169 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 2170 " DevX."); 2171 mlx5_free(couners_obj); 2172 return NULL; 2173 } 2174 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2175 return couners_obj; 2176 } 2177 2178 int 2179 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2180 struct mlx5_devx_virtio_q_couners_attr *attr) 2181 { 2182 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2183 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2184 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2185 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2186 virtio_q_counters); 2187 int ret; 2188 2189 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2190 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2191 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2192 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2193 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2194 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2195 sizeof(out)); 2196 if (ret) { 2197 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2198 rte_errno = errno; 2199 return -errno; 2200 } 2201 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2202 received_desc); 2203 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2204 completed_desc); 2205 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2206 error_cqes); 2207 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2208 bad_desc_errors); 2209 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2210 exceed_max_chain); 2211 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2212 invalid_buffer); 2213 return ret; 2214 } 2215 2216 /** 2217 * Create general object of type FLOW_HIT_ASO using DevX API. 2218 * 2219 * @param[in] ctx 2220 * Context returned from mlx5 open_device() glue function. 2221 * @param [in] pd 2222 * PD value to associate the FLOW_HIT_ASO object with. 2223 * 2224 * @return 2225 * The DevX object created, NULL otherwise and rte_errno is set. 2226 */ 2227 struct mlx5_devx_obj * 2228 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2229 { 2230 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2231 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2232 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2233 void *ptr = NULL; 2234 2235 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2236 0, SOCKET_ID_ANY); 2237 if (!flow_hit_aso_obj) { 2238 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2239 rte_errno = ENOMEM; 2240 return NULL; 2241 } 2242 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2243 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2244 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2245 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2246 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2247 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2248 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2249 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2250 out, sizeof(out)); 2251 if (!flow_hit_aso_obj->obj) { 2252 rte_errno = errno; 2253 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX."); 2254 mlx5_free(flow_hit_aso_obj); 2255 return NULL; 2256 } 2257 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2258 return flow_hit_aso_obj; 2259 } 2260 2261 /* 2262 * Create PD using DevX API. 2263 * 2264 * @param[in] ctx 2265 * Context returned from mlx5 open_device() glue function. 2266 * 2267 * @return 2268 * The DevX object created, NULL otherwise and rte_errno is set. 2269 */ 2270 struct mlx5_devx_obj * 2271 mlx5_devx_cmd_alloc_pd(void *ctx) 2272 { 2273 struct mlx5_devx_obj *ppd = 2274 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2275 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2276 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2277 2278 if (!ppd) { 2279 DRV_LOG(ERR, "Failed to allocate PD data."); 2280 rte_errno = ENOMEM; 2281 return NULL; 2282 } 2283 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2284 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2285 out, sizeof(out)); 2286 if (!ppd->obj) { 2287 mlx5_free(ppd); 2288 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2289 rte_errno = errno; 2290 return NULL; 2291 } 2292 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2293 return ppd; 2294 } 2295 2296 /** 2297 * Create general object of type FLOW_METER_ASO using DevX API. 2298 * 2299 * @param[in] ctx 2300 * Context returned from mlx5 open_device() glue function. 2301 * @param [in] pd 2302 * PD value to associate the FLOW_METER_ASO object with. 2303 * @param [in] log_obj_size 2304 * log_obj_size define to allocate number of 2 * meters 2305 * in one FLOW_METER_ASO object. 2306 * 2307 * @return 2308 * The DevX object created, NULL otherwise and rte_errno is set. 2309 */ 2310 struct mlx5_devx_obj * 2311 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2312 uint32_t log_obj_size) 2313 { 2314 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2315 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2316 struct mlx5_devx_obj *flow_meter_aso_obj; 2317 void *ptr; 2318 2319 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2320 sizeof(*flow_meter_aso_obj), 2321 0, SOCKET_ID_ANY); 2322 if (!flow_meter_aso_obj) { 2323 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2324 rte_errno = ENOMEM; 2325 return NULL; 2326 } 2327 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2328 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2329 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2330 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2331 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2332 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2333 log_obj_size); 2334 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2335 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2336 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2337 ctx, in, sizeof(in), 2338 out, sizeof(out)); 2339 if (!flow_meter_aso_obj->obj) { 2340 rte_errno = errno; 2341 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX."); 2342 mlx5_free(flow_meter_aso_obj); 2343 return NULL; 2344 } 2345 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2346 out, obj_id); 2347 return flow_meter_aso_obj; 2348 } 2349 2350 /** 2351 * Create general object of type GENEVE TLV option using DevX API. 2352 * 2353 * @param[in] ctx 2354 * Context returned from mlx5 open_device() glue function. 2355 * @param [in] class 2356 * TLV option variable value of class 2357 * @param [in] type 2358 * TLV option variable value of type 2359 * @param [in] len 2360 * TLV option variable value of len 2361 * 2362 * @return 2363 * The DevX object created, NULL otherwise and rte_errno is set. 2364 */ 2365 struct mlx5_devx_obj * 2366 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2367 uint16_t class, uint8_t type, uint8_t len) 2368 { 2369 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2370 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2371 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2372 sizeof(*geneve_tlv_opt_obj), 2373 0, SOCKET_ID_ANY); 2374 2375 if (!geneve_tlv_opt_obj) { 2376 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2377 rte_errno = ENOMEM; 2378 return NULL; 2379 } 2380 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2381 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2382 geneve_tlv_opt); 2383 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2384 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2385 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2386 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2387 MLX5_SET(geneve_tlv_option, opt, option_class, 2388 rte_be_to_cpu_16(class)); 2389 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2390 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2391 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2392 sizeof(in), out, sizeof(out)); 2393 if (!geneve_tlv_opt_obj->obj) { 2394 rte_errno = errno; 2395 DRV_LOG(ERR, "Failed to create Geneve tlv option " 2396 "Obj using DevX."); 2397 mlx5_free(geneve_tlv_opt_obj); 2398 return NULL; 2399 } 2400 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2401 return geneve_tlv_opt_obj; 2402 } 2403 2404 int 2405 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2406 { 2407 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2408 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2409 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2410 int rc; 2411 void *rq_ctx; 2412 2413 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2414 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2415 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2416 if (rc) { 2417 rte_errno = errno; 2418 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2419 "rc = %d, errno = %d.", rc, errno); 2420 return -rc; 2421 }; 2422 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2423 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2424 return 0; 2425 #else 2426 (void)wq; 2427 (void)counter_set_id; 2428 return -ENOTSUP; 2429 #endif 2430 } 2431 2432 /* 2433 * Allocate queue counters via devx interface. 2434 * 2435 * @param[in] ctx 2436 * Context returned from mlx5 open_device() glue function. 2437 * 2438 * @return 2439 * Pointer to counter object on success, a NULL value otherwise and 2440 * rte_errno is set. 2441 */ 2442 struct mlx5_devx_obj * 2443 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2444 { 2445 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2446 SOCKET_ID_ANY); 2447 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2448 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2449 2450 if (!dcs) { 2451 rte_errno = ENOMEM; 2452 return NULL; 2453 } 2454 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2455 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2456 sizeof(out)); 2457 if (!dcs->obj) { 2458 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error " 2459 "%d.", errno); 2460 rte_errno = errno; 2461 mlx5_free(dcs); 2462 return NULL; 2463 } 2464 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2465 return dcs; 2466 } 2467 2468 /** 2469 * Query queue counters values. 2470 * 2471 * @param[in] dcs 2472 * devx object of the queue counter set. 2473 * @param[in] clear 2474 * Whether hardware should clear the counters after the query or not. 2475 * @param[out] out_of_buffers 2476 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2477 * 2478 * @return 2479 * 0 on success, a negative value otherwise. 2480 */ 2481 int 2482 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2483 uint32_t *out_of_buffers) 2484 { 2485 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2486 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2487 int rc; 2488 2489 MLX5_SET(query_q_counter_in, in, opcode, 2490 MLX5_CMD_OP_QUERY_Q_COUNTER); 2491 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2492 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2493 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2494 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2495 sizeof(out)); 2496 if (rc) { 2497 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2498 rte_errno = rc; 2499 return -rc; 2500 } 2501 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2502 return 0; 2503 } 2504 2505 /** 2506 * Create general object of type DEK using DevX API. 2507 * 2508 * @param[in] ctx 2509 * Context returned from mlx5 open_device() glue function. 2510 * @param [in] attr 2511 * Pointer to DEK attributes structure. 2512 * 2513 * @return 2514 * The DevX object created, NULL otherwise and rte_errno is set. 2515 */ 2516 struct mlx5_devx_obj * 2517 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2518 { 2519 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2520 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2521 struct mlx5_devx_obj *dek_obj = NULL; 2522 void *ptr = NULL, *key_addr = NULL; 2523 2524 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2525 0, SOCKET_ID_ANY); 2526 if (dek_obj == NULL) { 2527 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2528 rte_errno = ENOMEM; 2529 return NULL; 2530 } 2531 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2532 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2533 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2534 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2535 MLX5_GENERAL_OBJ_TYPE_DEK); 2536 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2537 MLX5_SET(dek, ptr, key_size, attr->key_size); 2538 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2539 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2540 MLX5_SET(dek, ptr, pd, attr->pd); 2541 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2542 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2543 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2544 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2545 out, sizeof(out)); 2546 if (dek_obj->obj == NULL) { 2547 rte_errno = errno; 2548 DRV_LOG(ERR, "Failed to create DEK obj using DevX."); 2549 mlx5_free(dek_obj); 2550 return NULL; 2551 } 2552 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2553 return dek_obj; 2554 } 2555 2556 /** 2557 * Create general object of type IMPORT_KEK using DevX API. 2558 * 2559 * @param[in] ctx 2560 * Context returned from mlx5 open_device() glue function. 2561 * @param [in] attr 2562 * Pointer to IMPORT_KEK attributes structure. 2563 * 2564 * @return 2565 * The DevX object created, NULL otherwise and rte_errno is set. 2566 */ 2567 struct mlx5_devx_obj * 2568 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 2569 struct mlx5_devx_import_kek_attr *attr) 2570 { 2571 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 2572 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2573 struct mlx5_devx_obj *import_kek_obj = NULL; 2574 void *ptr = NULL, *key_addr = NULL; 2575 2576 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 2577 0, SOCKET_ID_ANY); 2578 if (import_kek_obj == NULL) { 2579 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 2580 rte_errno = ENOMEM; 2581 return NULL; 2582 } 2583 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 2584 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2585 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2586 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2587 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 2588 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 2589 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 2590 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 2591 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2592 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2593 out, sizeof(out)); 2594 if (import_kek_obj->obj == NULL) { 2595 rte_errno = errno; 2596 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX."); 2597 mlx5_free(import_kek_obj); 2598 return NULL; 2599 } 2600 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2601 return import_kek_obj; 2602 } 2603 2604 /** 2605 * Create general object of type CREDENTIAL using DevX API. 2606 * 2607 * @param[in] ctx 2608 * Context returned from mlx5 open_device() glue function. 2609 * @param [in] attr 2610 * Pointer to CREDENTIAL attributes structure. 2611 * 2612 * @return 2613 * The DevX object created, NULL otherwise and rte_errno is set. 2614 */ 2615 struct mlx5_devx_obj * 2616 mlx5_devx_cmd_create_credential_obj(void *ctx, 2617 struct mlx5_devx_credential_attr *attr) 2618 { 2619 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 2620 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2621 struct mlx5_devx_obj *credential_obj = NULL; 2622 void *ptr = NULL, *credential_addr = NULL; 2623 2624 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 2625 0, SOCKET_ID_ANY); 2626 if (credential_obj == NULL) { 2627 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 2628 rte_errno = ENOMEM; 2629 return NULL; 2630 } 2631 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 2632 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2633 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2634 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2635 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 2636 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 2637 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 2638 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 2639 memcpy(credential_addr, (void *)(attr->credential), 2640 MLX5_CRYPTO_CREDENTIAL_SIZE); 2641 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2642 out, sizeof(out)); 2643 if (credential_obj->obj == NULL) { 2644 rte_errno = errno; 2645 DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX."); 2646 mlx5_free(credential_obj); 2647 return NULL; 2648 } 2649 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2650 return credential_obj; 2651 } 2652 2653 /** 2654 * Create general object of type CRYPTO_LOGIN using DevX API. 2655 * 2656 * @param[in] ctx 2657 * Context returned from mlx5 open_device() glue function. 2658 * @param [in] attr 2659 * Pointer to CRYPTO_LOGIN attributes structure. 2660 * 2661 * @return 2662 * The DevX object created, NULL otherwise and rte_errno is set. 2663 */ 2664 struct mlx5_devx_obj * 2665 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 2666 struct mlx5_devx_crypto_login_attr *attr) 2667 { 2668 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 2669 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2670 struct mlx5_devx_obj *crypto_login_obj = NULL; 2671 void *ptr = NULL, *credential_addr = NULL; 2672 2673 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 2674 0, SOCKET_ID_ANY); 2675 if (crypto_login_obj == NULL) { 2676 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 2677 rte_errno = ENOMEM; 2678 return NULL; 2679 } 2680 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 2681 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2682 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2683 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2684 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 2685 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 2686 MLX5_SET(crypto_login, ptr, credential_pointer, 2687 attr->credential_pointer); 2688 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 2689 attr->session_import_kek_ptr); 2690 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 2691 memcpy(credential_addr, (void *)(attr->credential), 2692 MLX5_CRYPTO_CREDENTIAL_SIZE); 2693 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2694 out, sizeof(out)); 2695 if (crypto_login_obj->obj == NULL) { 2696 rte_errno = errno; 2697 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX."); 2698 mlx5_free(crypto_login_obj); 2699 return NULL; 2700 } 2701 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2702 return crypto_login_obj; 2703 } 2704