1 // SPDX-License-Identifier: BSD-3-Clause 2 /* Copyright 2018 Mellanox Technologies, Ltd */ 3 4 #include <unistd.h> 5 6 #include <rte_errno.h> 7 #include <rte_malloc.h> 8 #include <rte_eal_paging.h> 9 10 #include "mlx5_prm.h" 11 #include "mlx5_devx_cmds.h" 12 #include "mlx5_common_utils.h" 13 #include "mlx5_malloc.h" 14 15 16 /** 17 * Perform read access to the registers. Reads data from register 18 * and writes ones to the specified buffer. 19 * 20 * @param[in] ctx 21 * Context returned from mlx5 open_device() glue function. 22 * @param[in] reg_id 23 * Register identifier according to the PRM. 24 * @param[in] arg 25 * Register access auxiliary parameter according to the PRM. 26 * @param[out] data 27 * Pointer to the buffer to store read data. 28 * @param[in] dw_cnt 29 * Buffer size in double words. 30 * 31 * @return 32 * 0 on success, a negative value otherwise. 33 */ 34 int 35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 36 uint32_t *data, uint32_t dw_cnt) 37 { 38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 41 int status, rc; 42 43 MLX5_ASSERT(data && dw_cnt); 44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 46 DRV_LOG(ERR, "Not enough buffer for register read data"); 47 return -1; 48 } 49 MLX5_SET(access_register_in, in, opcode, 50 MLX5_CMD_OP_ACCESS_REGISTER_USER); 51 MLX5_SET(access_register_in, in, op_mod, 52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 53 MLX5_SET(access_register_in, in, register_id, reg_id); 54 MLX5_SET(access_register_in, in, argument, arg); 55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 56 MLX5_ST_SZ_DW(access_register_out) * 57 sizeof(uint32_t) + dw_cnt); 58 if (rc) 59 goto error; 60 status = MLX5_GET(access_register_out, out, status); 61 if (status) { 62 int syndrome = MLX5_GET(access_register_out, out, syndrome); 63 64 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, " 65 "status %x, syndrome = %x", 66 reg_id, status, syndrome); 67 return -1; 68 } 69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 70 dw_cnt * sizeof(uint32_t)); 71 return 0; 72 error: 73 rc = (rc > 0) ? -rc : rc; 74 return rc; 75 } 76 77 /** 78 * Allocate flow counters via devx interface. 79 * 80 * @param[in] ctx 81 * Context returned from mlx5 open_device() glue function. 82 * @param dcs 83 * Pointer to counters properties structure to be filled by the routine. 84 * @param bulk_n_128 85 * Bulk counter numbers in 128 counters units. 86 * 87 * @return 88 * Pointer to counter object on success, a negative value otherwise and 89 * rte_errno is set. 90 */ 91 struct mlx5_devx_obj * 92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 93 { 94 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 95 0, SOCKET_ID_ANY); 96 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 97 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 98 99 if (!dcs) { 100 rte_errno = ENOMEM; 101 return NULL; 102 } 103 MLX5_SET(alloc_flow_counter_in, in, opcode, 104 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 105 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 106 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 107 sizeof(in), out, sizeof(out)); 108 if (!dcs->obj) { 109 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 110 rte_errno = errno; 111 mlx5_free(dcs); 112 return NULL; 113 } 114 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 115 return dcs; 116 } 117 118 /** 119 * Query flow counters values. 120 * 121 * @param[in] dcs 122 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 123 * @param[in] clear 124 * Whether hardware should clear the counters after the query or not. 125 * @param[in] n_counters 126 * 0 in case of 1 counter to read, otherwise the counter number to read. 127 * @param pkts 128 * The number of packets that matched the flow. 129 * @param bytes 130 * The number of bytes that matched the flow. 131 * @param mkey 132 * The mkey key for batch query. 133 * @param addr 134 * The address in the mkey range for batch query. 135 * @param cmd_comp 136 * The completion object for asynchronous batch query. 137 * @param async_id 138 * The ID to be returned in the asynchronous batch query response. 139 * 140 * @return 141 * 0 on success, a negative value otherwise. 142 */ 143 int 144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 145 int clear, uint32_t n_counters, 146 uint64_t *pkts, uint64_t *bytes, 147 uint32_t mkey, void *addr, 148 void *cmd_comp, 149 uint64_t async_id) 150 { 151 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 152 MLX5_ST_SZ_BYTES(traffic_counter); 153 uint32_t out[out_len]; 154 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 155 void *stats; 156 int rc; 157 158 MLX5_SET(query_flow_counter_in, in, opcode, 159 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 160 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 161 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 162 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 163 164 if (n_counters) { 165 MLX5_SET(query_flow_counter_in, in, num_of_counters, 166 n_counters); 167 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 168 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 169 MLX5_SET64(query_flow_counter_in, in, address, 170 (uint64_t)(uintptr_t)addr); 171 } 172 if (!cmd_comp) 173 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 174 out_len); 175 else 176 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 177 out_len, async_id, 178 cmd_comp); 179 if (rc) { 180 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 181 rte_errno = rc; 182 return -rc; 183 } 184 if (!n_counters) { 185 stats = MLX5_ADDR_OF(query_flow_counter_out, 186 out, flow_statistics); 187 *pkts = MLX5_GET64(traffic_counter, stats, packets); 188 *bytes = MLX5_GET64(traffic_counter, stats, octets); 189 } 190 return 0; 191 } 192 193 /** 194 * Create a new mkey. 195 * 196 * @param[in] ctx 197 * Context returned from mlx5 open_device() glue function. 198 * @param[in] attr 199 * Attributes of the requested mkey. 200 * 201 * @return 202 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 203 * is set. 204 */ 205 struct mlx5_devx_obj * 206 mlx5_devx_cmd_mkey_create(void *ctx, 207 struct mlx5_devx_mkey_attr *attr) 208 { 209 struct mlx5_klm *klm_array = attr->klm_array; 210 int klm_num = attr->klm_num; 211 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 212 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 213 uint32_t in[in_size_dw]; 214 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 215 void *mkc; 216 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 217 0, SOCKET_ID_ANY); 218 size_t pgsize; 219 uint32_t translation_size; 220 221 if (!mkey) { 222 rte_errno = ENOMEM; 223 return NULL; 224 } 225 memset(in, 0, in_size_dw * 4); 226 pgsize = rte_mem_page_size(); 227 if (pgsize == (size_t)-1) { 228 mlx5_free(mkey); 229 DRV_LOG(ERR, "Failed to get page size"); 230 rte_errno = ENOMEM; 231 return NULL; 232 } 233 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 234 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 235 if (klm_num > 0) { 236 int i; 237 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 238 klm_pas_mtt); 239 translation_size = RTE_ALIGN(klm_num, 4); 240 for (i = 0; i < klm_num; i++) { 241 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 242 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 243 MLX5_SET64(klm, klm, address, klm_array[i].address); 244 klm += MLX5_ST_SZ_BYTES(klm); 245 } 246 for (; i < (int)translation_size; i++) { 247 MLX5_SET(klm, klm, mkey, 0x0); 248 MLX5_SET64(klm, klm, address, 0x0); 249 klm += MLX5_ST_SZ_BYTES(klm); 250 } 251 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 252 MLX5_MKC_ACCESS_MODE_KLM_FBS : 253 MLX5_MKC_ACCESS_MODE_KLM); 254 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 255 } else { 256 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 257 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 258 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 259 } 260 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 261 translation_size); 262 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 263 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 264 MLX5_SET(mkc, mkc, lw, 0x1); 265 MLX5_SET(mkc, mkc, lr, 0x1); 266 MLX5_SET(mkc, mkc, qpn, 0xffffff); 267 MLX5_SET(mkc, mkc, pd, attr->pd); 268 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 269 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 270 MLX5_SET(mkc, mkc, relaxed_ordering_write, 271 attr->relaxed_ordering_write); 272 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 273 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 274 MLX5_SET64(mkc, mkc, len, attr->size); 275 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 276 sizeof(out)); 277 if (!mkey->obj) { 278 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d\n", 279 klm_num ? "an in" : "a ", errno); 280 rte_errno = errno; 281 mlx5_free(mkey); 282 return NULL; 283 } 284 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 285 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 286 return mkey; 287 } 288 289 /** 290 * Get status of devx command response. 291 * Mainly used for asynchronous commands. 292 * 293 * @param[in] out 294 * The out response buffer. 295 * 296 * @return 297 * 0 on success, non-zero value otherwise. 298 */ 299 int 300 mlx5_devx_get_out_command_status(void *out) 301 { 302 int status; 303 304 if (!out) 305 return -EINVAL; 306 status = MLX5_GET(query_flow_counter_out, out, status); 307 if (status) { 308 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 309 310 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 311 syndrome); 312 } 313 return status; 314 } 315 316 /** 317 * Destroy any object allocated by a Devx API. 318 * 319 * @param[in] obj 320 * Pointer to a general object. 321 * 322 * @return 323 * 0 on success, a negative value otherwise. 324 */ 325 int 326 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 327 { 328 int ret; 329 330 if (!obj) 331 return 0; 332 ret = mlx5_glue->devx_obj_destroy(obj->obj); 333 mlx5_free(obj); 334 return ret; 335 } 336 337 /** 338 * Query NIC vport context. 339 * Fills minimal inline attribute. 340 * 341 * @param[in] ctx 342 * ibv contexts returned from mlx5dv_open_device. 343 * @param[in] vport 344 * vport index 345 * @param[out] attr 346 * Attributes device values. 347 * 348 * @return 349 * 0 on success, a negative value otherwise. 350 */ 351 static int 352 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 353 unsigned int vport, 354 struct mlx5_hca_attr *attr) 355 { 356 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 357 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 358 void *vctx; 359 int status, syndrome, rc; 360 361 /* Query NIC vport context to determine inline mode. */ 362 MLX5_SET(query_nic_vport_context_in, in, opcode, 363 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 364 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 365 if (vport) 366 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 367 rc = mlx5_glue->devx_general_cmd(ctx, 368 in, sizeof(in), 369 out, sizeof(out)); 370 if (rc) 371 goto error; 372 status = MLX5_GET(query_nic_vport_context_out, out, status); 373 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 374 if (status) { 375 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 376 "status %x, syndrome = %x", status, syndrome); 377 return -1; 378 } 379 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 380 nic_vport_context); 381 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 382 min_wqe_inline_mode); 383 return 0; 384 error: 385 rc = (rc > 0) ? -rc : rc; 386 return rc; 387 } 388 389 /** 390 * Query NIC vDPA attributes. 391 * 392 * @param[in] ctx 393 * Context returned from mlx5 open_device() glue function. 394 * @param[out] vdpa_attr 395 * vDPA Attributes structure to fill. 396 */ 397 static void 398 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 399 struct mlx5_hca_vdpa_attr *vdpa_attr) 400 { 401 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 402 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 403 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 404 int status, syndrome, rc; 405 406 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 407 MLX5_SET(query_hca_cap_in, in, op_mod, 408 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 409 MLX5_HCA_CAP_OPMOD_GET_CUR); 410 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 411 status = MLX5_GET(query_hca_cap_out, out, status); 412 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 413 if (rc || status) { 414 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities," 415 " status %x, syndrome = %x", status, syndrome); 416 vdpa_attr->valid = 0; 417 } else { 418 vdpa_attr->valid = 1; 419 vdpa_attr->desc_tunnel_offload_type = 420 MLX5_GET(virtio_emulation_cap, hcattr, 421 desc_tunnel_offload_type); 422 vdpa_attr->eth_frame_offload_type = 423 MLX5_GET(virtio_emulation_cap, hcattr, 424 eth_frame_offload_type); 425 vdpa_attr->virtio_version_1_0 = 426 MLX5_GET(virtio_emulation_cap, hcattr, 427 virtio_version_1_0); 428 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 429 tso_ipv4); 430 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 431 tso_ipv6); 432 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 433 tx_csum); 434 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 435 rx_csum); 436 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 437 event_mode); 438 vdpa_attr->virtio_queue_type = 439 MLX5_GET(virtio_emulation_cap, hcattr, 440 virtio_queue_type); 441 vdpa_attr->log_doorbell_stride = 442 MLX5_GET(virtio_emulation_cap, hcattr, 443 log_doorbell_stride); 444 vdpa_attr->log_doorbell_bar_size = 445 MLX5_GET(virtio_emulation_cap, hcattr, 446 log_doorbell_bar_size); 447 vdpa_attr->doorbell_bar_offset = 448 MLX5_GET64(virtio_emulation_cap, hcattr, 449 doorbell_bar_offset); 450 vdpa_attr->max_num_virtio_queues = 451 MLX5_GET(virtio_emulation_cap, hcattr, 452 max_num_virtio_queues); 453 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 454 umem_1_buffer_param_a); 455 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 456 umem_1_buffer_param_b); 457 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 458 umem_2_buffer_param_a); 459 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 460 umem_2_buffer_param_b); 461 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 462 umem_3_buffer_param_a); 463 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 464 umem_3_buffer_param_b); 465 } 466 } 467 468 int 469 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 470 uint32_t ids[], uint32_t num) 471 { 472 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 473 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 474 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 475 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 476 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 477 int ret; 478 uint32_t idx = 0; 479 uint32_t i; 480 481 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 482 rte_errno = EINVAL; 483 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 484 return -rte_errno; 485 } 486 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 487 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 488 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 489 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 490 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 491 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 492 out, sizeof(out)); 493 if (ret) { 494 rte_errno = ret; 495 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 496 (void *)flex_obj); 497 return -rte_errno; 498 } 499 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 500 void *s_off = (void *)((char *)sample + i * 501 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 502 uint32_t en; 503 504 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 505 flow_match_sample_en); 506 if (!en) 507 continue; 508 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 509 flow_match_sample_field_id); 510 } 511 if (num != idx) { 512 rte_errno = EINVAL; 513 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 514 return -rte_errno; 515 } 516 return ret; 517 } 518 519 520 struct mlx5_devx_obj * 521 mlx5_devx_cmd_create_flex_parser(void *ctx, 522 struct mlx5_devx_graph_node_attr *data) 523 { 524 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 525 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 526 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 527 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 528 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 529 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 530 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 531 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 532 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 533 uint32_t i; 534 535 if (!parse_flex_obj) { 536 DRV_LOG(ERR, "Failed to allocate flex parser data."); 537 rte_errno = ENOMEM; 538 return NULL; 539 } 540 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 541 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 542 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 543 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 544 MLX5_SET(parse_graph_flex, flex, header_length_mode, 545 data->header_length_mode); 546 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 547 data->header_length_base_value); 548 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 549 data->header_length_field_offset); 550 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 551 data->header_length_field_shift); 552 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 553 data->header_length_field_mask); 554 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 555 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 556 void *s_off = (void *)((char *)sample + i * 557 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 558 559 if (!s->flow_match_sample_en) 560 continue; 561 MLX5_SET(parse_graph_flow_match_sample, s_off, 562 flow_match_sample_en, !!s->flow_match_sample_en); 563 MLX5_SET(parse_graph_flow_match_sample, s_off, 564 flow_match_sample_field_offset, 565 s->flow_match_sample_field_offset); 566 MLX5_SET(parse_graph_flow_match_sample, s_off, 567 flow_match_sample_offset_mode, 568 s->flow_match_sample_offset_mode); 569 MLX5_SET(parse_graph_flow_match_sample, s_off, 570 flow_match_sample_field_offset_mask, 571 s->flow_match_sample_field_offset_mask); 572 MLX5_SET(parse_graph_flow_match_sample, s_off, 573 flow_match_sample_field_offset_shift, 574 s->flow_match_sample_field_offset_shift); 575 MLX5_SET(parse_graph_flow_match_sample, s_off, 576 flow_match_sample_field_base_offset, 577 s->flow_match_sample_field_base_offset); 578 MLX5_SET(parse_graph_flow_match_sample, s_off, 579 flow_match_sample_tunnel_mode, 580 s->flow_match_sample_tunnel_mode); 581 } 582 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 583 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 584 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 585 void *in_off = (void *)((char *)in_arc + i * 586 MLX5_ST_SZ_BYTES(parse_graph_arc)); 587 void *out_off = (void *)((char *)out_arc + i * 588 MLX5_ST_SZ_BYTES(parse_graph_arc)); 589 590 if (ia->arc_parse_graph_node != 0) { 591 MLX5_SET(parse_graph_arc, in_off, 592 compare_condition_value, 593 ia->compare_condition_value); 594 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 595 ia->start_inner_tunnel); 596 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 597 ia->arc_parse_graph_node); 598 MLX5_SET(parse_graph_arc, in_off, 599 parse_graph_node_handle, 600 ia->parse_graph_node_handle); 601 } 602 if (oa->arc_parse_graph_node != 0) { 603 MLX5_SET(parse_graph_arc, out_off, 604 compare_condition_value, 605 oa->compare_condition_value); 606 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 607 oa->start_inner_tunnel); 608 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 609 oa->arc_parse_graph_node); 610 MLX5_SET(parse_graph_arc, out_off, 611 parse_graph_node_handle, 612 oa->parse_graph_node_handle); 613 } 614 } 615 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 616 out, sizeof(out)); 617 if (!parse_flex_obj->obj) { 618 rte_errno = errno; 619 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 620 "by using DevX."); 621 mlx5_free(parse_flex_obj); 622 return NULL; 623 } 624 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 625 return parse_flex_obj; 626 } 627 628 /** 629 * Query HCA attributes. 630 * Using those attributes we can check on run time if the device 631 * is having the required capabilities. 632 * 633 * @param[in] ctx 634 * Context returned from mlx5 open_device() glue function. 635 * @param[out] attr 636 * Attributes device values. 637 * 638 * @return 639 * 0 on success, a negative value otherwise. 640 */ 641 int 642 mlx5_devx_cmd_query_hca_attr(void *ctx, 643 struct mlx5_hca_attr *attr) 644 { 645 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 646 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 647 void *hcattr; 648 int status, syndrome, rc, i; 649 650 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 651 MLX5_SET(query_hca_cap_in, in, op_mod, 652 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 653 MLX5_HCA_CAP_OPMOD_GET_CUR); 654 655 rc = mlx5_glue->devx_general_cmd(ctx, 656 in, sizeof(in), out, sizeof(out)); 657 if (rc) 658 goto error; 659 status = MLX5_GET(query_hca_cap_out, out, status); 660 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 661 if (status) { 662 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 663 "status %x, syndrome = %x", status, syndrome); 664 return -1; 665 } 666 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 667 attr->flow_counter_bulk_alloc_bitmap = 668 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 669 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 670 flow_counters_dump); 671 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 672 log_max_rqt_size); 673 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 674 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 675 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 676 log_max_hairpin_queues); 677 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 678 log_max_hairpin_wq_data_sz); 679 attr->log_max_hairpin_num_packets = MLX5_GET 680 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 681 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 682 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 683 relaxed_ordering_write); 684 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 685 relaxed_ordering_read); 686 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 687 access_register_user); 688 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 689 eth_net_offloads); 690 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 691 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 692 flex_parser_protocols); 693 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 694 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 695 general_obj_types) & 696 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 697 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 698 general_obj_types) & 699 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 700 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 701 general_obj_types) & 702 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 703 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 704 wqe_index_ignore_cap); 705 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 706 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 707 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 708 log_max_static_sq_wq); 709 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 710 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 711 device_frequency_khz); 712 attr->scatter_fcs_w_decap_disable = 713 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 714 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp); 715 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 716 regexp_num_of_engines); 717 attr->flow_hit_aso = !!(MLX5_GET64(cmd_hca_cap, hcattr, 718 general_obj_types) & 719 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 720 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 721 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 722 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 723 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 724 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 725 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 726 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 727 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 728 if (attr->qos.sup) { 729 MLX5_SET(query_hca_cap_in, in, op_mod, 730 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 731 MLX5_HCA_CAP_OPMOD_GET_CUR); 732 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 733 out, sizeof(out)); 734 if (rc) 735 goto error; 736 if (status) { 737 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities," 738 " status %x, syndrome = %x", status, syndrome); 739 return -1; 740 } 741 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 742 attr->qos.srtcm_sup = 743 MLX5_GET(qos_cap, hcattr, flow_meter_srtcm); 744 attr->qos.log_max_flow_meter = 745 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 746 attr->qos.flow_meter_reg_c_ids = 747 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 748 attr->qos.flow_meter_reg_share = 749 MLX5_GET(qos_cap, hcattr, flow_meter_reg_share); 750 attr->qos.packet_pacing = 751 MLX5_GET(qos_cap, hcattr, packet_pacing); 752 attr->qos.wqe_rate_pp = 753 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 754 } 755 if (attr->vdpa.valid) 756 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 757 if (!attr->eth_net_offloads) 758 return 0; 759 760 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 761 memset(in, 0, sizeof(in)); 762 memset(out, 0, sizeof(out)); 763 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 764 MLX5_SET(query_hca_cap_in, in, op_mod, 765 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 766 MLX5_HCA_CAP_OPMOD_GET_CUR); 767 768 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 769 if (rc) 770 goto error; 771 status = MLX5_GET(query_hca_cap_out, out, status); 772 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 773 if (status) { 774 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 775 "status %x, syndrome = %x", status, syndrome); 776 attr->log_max_ft_sampler_num = 0; 777 return -1; 778 } 779 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 780 attr->log_max_ft_sampler_num = 781 MLX5_GET(flow_table_nic_cap, 782 hcattr, flow_table_properties.log_max_ft_sampler_num); 783 784 /* Query HCA offloads for Ethernet protocol. */ 785 memset(in, 0, sizeof(in)); 786 memset(out, 0, sizeof(out)); 787 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 788 MLX5_SET(query_hca_cap_in, in, op_mod, 789 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 790 MLX5_HCA_CAP_OPMOD_GET_CUR); 791 792 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 793 if (rc) { 794 attr->eth_net_offloads = 0; 795 goto error; 796 } 797 status = MLX5_GET(query_hca_cap_out, out, status); 798 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 799 if (status) { 800 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 801 "status %x, syndrome = %x", status, syndrome); 802 attr->eth_net_offloads = 0; 803 return -1; 804 } 805 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 806 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 807 hcattr, wqe_vlan_insert); 808 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 809 lro_cap); 810 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 811 hcattr, tunnel_lro_gre); 812 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 813 hcattr, tunnel_lro_vxlan); 814 attr->lro_max_msg_sz_mode = MLX5_GET 815 (per_protocol_networking_offload_caps, 816 hcattr, lro_max_msg_sz_mode); 817 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 818 attr->lro_timer_supported_periods[i] = 819 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 820 lro_timer_supported_periods[i]); 821 } 822 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 823 hcattr, lro_min_mss_size); 824 attr->tunnel_stateless_geneve_rx = 825 MLX5_GET(per_protocol_networking_offload_caps, 826 hcattr, tunnel_stateless_geneve_rx); 827 attr->geneve_max_opt_len = 828 MLX5_GET(per_protocol_networking_offload_caps, 829 hcattr, max_geneve_opt_len); 830 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 831 hcattr, wqe_inline_mode); 832 attr->tunnel_stateless_gtp = MLX5_GET 833 (per_protocol_networking_offload_caps, 834 hcattr, tunnel_stateless_gtp); 835 attr->rss_ind_tbl_cap = MLX5_GET 836 (per_protocol_networking_offload_caps, 837 hcattr, rss_ind_tbl_cap); 838 if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) 839 return 0; 840 if (attr->eth_virt) { 841 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 842 if (rc) { 843 attr->eth_virt = 0; 844 goto error; 845 } 846 } 847 return 0; 848 error: 849 rc = (rc > 0) ? -rc : rc; 850 return rc; 851 } 852 853 /** 854 * Query TIS transport domain from QP verbs object using DevX API. 855 * 856 * @param[in] qp 857 * Pointer to verbs QP returned by ibv_create_qp . 858 * @param[in] tis_num 859 * TIS number of TIS to query. 860 * @param[out] tis_td 861 * Pointer to TIS transport domain variable, to be set by the routine. 862 * 863 * @return 864 * 0 on success, a negative value otherwise. 865 */ 866 int 867 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 868 uint32_t *tis_td) 869 { 870 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 871 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 872 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 873 int rc; 874 void *tis_ctx; 875 876 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 877 MLX5_SET(query_tis_in, in, tisn, tis_num); 878 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 879 if (rc) { 880 DRV_LOG(ERR, "Failed to query QP using DevX"); 881 return -rc; 882 }; 883 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 884 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 885 return 0; 886 #else 887 (void)qp; 888 (void)tis_num; 889 (void)tis_td; 890 return -ENOTSUP; 891 #endif 892 } 893 894 /** 895 * Fill WQ data for DevX API command. 896 * Utility function for use when creating DevX objects containing a WQ. 897 * 898 * @param[in] wq_ctx 899 * Pointer to WQ context to fill with data. 900 * @param [in] wq_attr 901 * Pointer to WQ attributes structure to fill in WQ context. 902 */ 903 static void 904 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 905 { 906 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 907 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 908 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 909 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 910 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 911 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 912 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 913 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 914 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 915 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 916 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 917 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 918 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 919 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 920 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 921 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 922 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 923 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 924 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 925 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 926 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 927 wq_attr->log_hairpin_num_packets); 928 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 929 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 930 wq_attr->single_wqe_log_num_of_strides); 931 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 932 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 933 wq_attr->single_stride_log_num_of_bytes); 934 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 935 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 936 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 937 } 938 939 /** 940 * Create RQ using DevX API. 941 * 942 * @param[in] ctx 943 * Context returned from mlx5 open_device() glue function. 944 * @param [in] rq_attr 945 * Pointer to create RQ attributes structure. 946 * @param [in] socket 947 * CPU socket ID for allocations. 948 * 949 * @return 950 * The DevX object created, NULL otherwise and rte_errno is set. 951 */ 952 struct mlx5_devx_obj * 953 mlx5_devx_cmd_create_rq(void *ctx, 954 struct mlx5_devx_create_rq_attr *rq_attr, 955 int socket) 956 { 957 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 958 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 959 void *rq_ctx, *wq_ctx; 960 struct mlx5_devx_wq_attr *wq_attr; 961 struct mlx5_devx_obj *rq = NULL; 962 963 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 964 if (!rq) { 965 DRV_LOG(ERR, "Failed to allocate RQ data"); 966 rte_errno = ENOMEM; 967 return NULL; 968 } 969 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 970 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 971 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 972 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 973 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 974 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 975 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 976 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 977 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 978 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 979 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 980 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 981 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 982 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 983 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 984 wq_attr = &rq_attr->wq_attr; 985 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 986 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 987 out, sizeof(out)); 988 if (!rq->obj) { 989 DRV_LOG(ERR, "Failed to create RQ using DevX"); 990 rte_errno = errno; 991 mlx5_free(rq); 992 return NULL; 993 } 994 rq->id = MLX5_GET(create_rq_out, out, rqn); 995 return rq; 996 } 997 998 /** 999 * Modify RQ using DevX API. 1000 * 1001 * @param[in] rq 1002 * Pointer to RQ object structure. 1003 * @param [in] rq_attr 1004 * Pointer to modify RQ attributes structure. 1005 * 1006 * @return 1007 * 0 on success, a negative errno value otherwise and rte_errno is set. 1008 */ 1009 int 1010 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1011 struct mlx5_devx_modify_rq_attr *rq_attr) 1012 { 1013 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1014 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1015 void *rq_ctx, *wq_ctx; 1016 int ret; 1017 1018 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1019 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1020 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1021 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1022 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1023 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1024 if (rq_attr->modify_bitmask & 1025 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1026 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1027 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1028 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1029 if (rq_attr->modify_bitmask & 1030 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1031 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1032 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1033 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1034 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1035 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1036 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1037 } 1038 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1039 out, sizeof(out)); 1040 if (ret) { 1041 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1042 rte_errno = errno; 1043 return -errno; 1044 } 1045 return ret; 1046 } 1047 1048 /** 1049 * Create TIR using DevX API. 1050 * 1051 * @param[in] ctx 1052 * Context returned from mlx5 open_device() glue function. 1053 * @param [in] tir_attr 1054 * Pointer to TIR attributes structure. 1055 * 1056 * @return 1057 * The DevX object created, NULL otherwise and rte_errno is set. 1058 */ 1059 struct mlx5_devx_obj * 1060 mlx5_devx_cmd_create_tir(void *ctx, 1061 struct mlx5_devx_tir_attr *tir_attr) 1062 { 1063 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1064 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1065 void *tir_ctx, *outer, *inner, *rss_key; 1066 struct mlx5_devx_obj *tir = NULL; 1067 1068 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1069 if (!tir) { 1070 DRV_LOG(ERR, "Failed to allocate TIR data"); 1071 rte_errno = ENOMEM; 1072 return NULL; 1073 } 1074 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1075 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1076 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1077 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1078 tir_attr->lro_timeout_period_usecs); 1079 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1080 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1081 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1082 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1083 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1084 tir_attr->tunneled_offload_en); 1085 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1086 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1087 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1088 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1089 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1090 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1091 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1092 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1093 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1094 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1095 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1096 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1097 tir_attr->rx_hash_field_selector_outer.selected_fields); 1098 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1099 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1100 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1101 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1102 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1103 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1104 tir_attr->rx_hash_field_selector_inner.selected_fields); 1105 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1106 out, sizeof(out)); 1107 if (!tir->obj) { 1108 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1109 rte_errno = errno; 1110 mlx5_free(tir); 1111 return NULL; 1112 } 1113 tir->id = MLX5_GET(create_tir_out, out, tirn); 1114 return tir; 1115 } 1116 1117 /** 1118 * Modify TIR using DevX API. 1119 * 1120 * @param[in] tir 1121 * Pointer to TIR DevX object structure. 1122 * @param [in] modify_tir_attr 1123 * Pointer to TIR modification attributes structure. 1124 * 1125 * @return 1126 * 0 on success, a negative errno value otherwise and rte_errno is set. 1127 */ 1128 int 1129 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1130 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1131 { 1132 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1133 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1134 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1135 void *tir_ctx; 1136 int ret; 1137 1138 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1139 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1140 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1141 modify_tir_attr->modify_bitmask); 1142 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1143 if (modify_tir_attr->modify_bitmask & 1144 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1145 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1146 tir_attr->lro_timeout_period_usecs); 1147 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1148 tir_attr->lro_enable_mask); 1149 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1150 tir_attr->lro_max_msg_sz); 1151 } 1152 if (modify_tir_attr->modify_bitmask & 1153 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1154 MLX5_SET(tirc, tir_ctx, indirect_table, 1155 tir_attr->indirect_table); 1156 if (modify_tir_attr->modify_bitmask & 1157 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1158 int i; 1159 void *outer, *inner; 1160 1161 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1162 tir_attr->rx_hash_symmetric); 1163 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1164 for (i = 0; i < 10; i++) { 1165 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1166 tir_attr->rx_hash_toeplitz_key[i]); 1167 } 1168 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1169 rx_hash_field_selector_outer); 1170 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1171 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1172 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1173 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1174 MLX5_SET 1175 (rx_hash_field_select, outer, selected_fields, 1176 tir_attr->rx_hash_field_selector_outer.selected_fields); 1177 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1178 rx_hash_field_selector_inner); 1179 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1180 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1181 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1182 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1183 MLX5_SET 1184 (rx_hash_field_select, inner, selected_fields, 1185 tir_attr->rx_hash_field_selector_inner.selected_fields); 1186 } 1187 if (modify_tir_attr->modify_bitmask & 1188 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1189 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1190 } 1191 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1192 out, sizeof(out)); 1193 if (ret) { 1194 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1195 rte_errno = errno; 1196 return -errno; 1197 } 1198 return ret; 1199 } 1200 1201 /** 1202 * Create RQT using DevX API. 1203 * 1204 * @param[in] ctx 1205 * Context returned from mlx5 open_device() glue function. 1206 * @param [in] rqt_attr 1207 * Pointer to RQT attributes structure. 1208 * 1209 * @return 1210 * The DevX object created, NULL otherwise and rte_errno is set. 1211 */ 1212 struct mlx5_devx_obj * 1213 mlx5_devx_cmd_create_rqt(void *ctx, 1214 struct mlx5_devx_rqt_attr *rqt_attr) 1215 { 1216 uint32_t *in = NULL; 1217 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1218 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1219 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1220 void *rqt_ctx; 1221 struct mlx5_devx_obj *rqt = NULL; 1222 int i; 1223 1224 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1225 if (!in) { 1226 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1227 rte_errno = ENOMEM; 1228 return NULL; 1229 } 1230 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1231 if (!rqt) { 1232 DRV_LOG(ERR, "Failed to allocate RQT data"); 1233 rte_errno = ENOMEM; 1234 mlx5_free(in); 1235 return NULL; 1236 } 1237 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1238 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1239 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1240 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1241 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1242 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1243 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1244 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1245 mlx5_free(in); 1246 if (!rqt->obj) { 1247 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1248 rte_errno = errno; 1249 mlx5_free(rqt); 1250 return NULL; 1251 } 1252 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1253 return rqt; 1254 } 1255 1256 /** 1257 * Modify RQT using DevX API. 1258 * 1259 * @param[in] rqt 1260 * Pointer to RQT DevX object structure. 1261 * @param [in] rqt_attr 1262 * Pointer to RQT attributes structure. 1263 * 1264 * @return 1265 * 0 on success, a negative errno value otherwise and rte_errno is set. 1266 */ 1267 int 1268 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1269 struct mlx5_devx_rqt_attr *rqt_attr) 1270 { 1271 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1272 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1273 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1274 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1275 void *rqt_ctx; 1276 int i; 1277 int ret; 1278 1279 if (!in) { 1280 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1281 rte_errno = ENOMEM; 1282 return -ENOMEM; 1283 } 1284 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1285 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1286 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1287 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1288 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1289 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1290 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1291 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1292 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1293 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1294 mlx5_free(in); 1295 if (ret) { 1296 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1297 rte_errno = errno; 1298 return -rte_errno; 1299 } 1300 return ret; 1301 } 1302 1303 /** 1304 * Create SQ using DevX API. 1305 * 1306 * @param[in] ctx 1307 * Context returned from mlx5 open_device() glue function. 1308 * @param [in] sq_attr 1309 * Pointer to SQ attributes structure. 1310 * @param [in] socket 1311 * CPU socket ID for allocations. 1312 * 1313 * @return 1314 * The DevX object created, NULL otherwise and rte_errno is set. 1315 **/ 1316 struct mlx5_devx_obj * 1317 mlx5_devx_cmd_create_sq(void *ctx, 1318 struct mlx5_devx_create_sq_attr *sq_attr) 1319 { 1320 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1321 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1322 void *sq_ctx; 1323 void *wq_ctx; 1324 struct mlx5_devx_wq_attr *wq_attr; 1325 struct mlx5_devx_obj *sq = NULL; 1326 1327 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1328 if (!sq) { 1329 DRV_LOG(ERR, "Failed to allocate SQ data"); 1330 rte_errno = ENOMEM; 1331 return NULL; 1332 } 1333 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1334 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1335 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1336 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1337 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1338 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1339 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1340 sq_attr->allow_multi_pkt_send_wqe); 1341 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1342 sq_attr->min_wqe_inline_mode); 1343 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1344 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1345 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1346 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1347 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1348 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1349 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1350 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1351 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1352 sq_attr->packet_pacing_rate_limit_index); 1353 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1354 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1355 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1356 wq_attr = &sq_attr->wq_attr; 1357 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1358 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1359 out, sizeof(out)); 1360 if (!sq->obj) { 1361 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1362 rte_errno = errno; 1363 mlx5_free(sq); 1364 return NULL; 1365 } 1366 sq->id = MLX5_GET(create_sq_out, out, sqn); 1367 return sq; 1368 } 1369 1370 /** 1371 * Modify SQ using DevX API. 1372 * 1373 * @param[in] sq 1374 * Pointer to SQ object structure. 1375 * @param [in] sq_attr 1376 * Pointer to SQ attributes structure. 1377 * 1378 * @return 1379 * 0 on success, a negative errno value otherwise and rte_errno is set. 1380 */ 1381 int 1382 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1383 struct mlx5_devx_modify_sq_attr *sq_attr) 1384 { 1385 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1386 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1387 void *sq_ctx; 1388 int ret; 1389 1390 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1391 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1392 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1393 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1394 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1395 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1396 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1397 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1398 out, sizeof(out)); 1399 if (ret) { 1400 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1401 rte_errno = errno; 1402 return -rte_errno; 1403 } 1404 return ret; 1405 } 1406 1407 /** 1408 * Create TIS using DevX API. 1409 * 1410 * @param[in] ctx 1411 * Context returned from mlx5 open_device() glue function. 1412 * @param [in] tis_attr 1413 * Pointer to TIS attributes structure. 1414 * 1415 * @return 1416 * The DevX object created, NULL otherwise and rte_errno is set. 1417 */ 1418 struct mlx5_devx_obj * 1419 mlx5_devx_cmd_create_tis(void *ctx, 1420 struct mlx5_devx_tis_attr *tis_attr) 1421 { 1422 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1423 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1424 struct mlx5_devx_obj *tis = NULL; 1425 void *tis_ctx; 1426 1427 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1428 if (!tis) { 1429 DRV_LOG(ERR, "Failed to allocate TIS object"); 1430 rte_errno = ENOMEM; 1431 return NULL; 1432 } 1433 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1434 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1435 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1436 tis_attr->strict_lag_tx_port_affinity); 1437 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1438 tis_attr->lag_tx_port_affinity); 1439 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1440 MLX5_SET(tisc, tis_ctx, transport_domain, 1441 tis_attr->transport_domain); 1442 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1443 out, sizeof(out)); 1444 if (!tis->obj) { 1445 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1446 rte_errno = errno; 1447 mlx5_free(tis); 1448 return NULL; 1449 } 1450 tis->id = MLX5_GET(create_tis_out, out, tisn); 1451 return tis; 1452 } 1453 1454 /** 1455 * Create transport domain using DevX API. 1456 * 1457 * @param[in] ctx 1458 * Context returned from mlx5 open_device() glue function. 1459 * @return 1460 * The DevX object created, NULL otherwise and rte_errno is set. 1461 */ 1462 struct mlx5_devx_obj * 1463 mlx5_devx_cmd_create_td(void *ctx) 1464 { 1465 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1466 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1467 struct mlx5_devx_obj *td = NULL; 1468 1469 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1470 if (!td) { 1471 DRV_LOG(ERR, "Failed to allocate TD object"); 1472 rte_errno = ENOMEM; 1473 return NULL; 1474 } 1475 MLX5_SET(alloc_transport_domain_in, in, opcode, 1476 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1477 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1478 out, sizeof(out)); 1479 if (!td->obj) { 1480 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1481 rte_errno = errno; 1482 mlx5_free(td); 1483 return NULL; 1484 } 1485 td->id = MLX5_GET(alloc_transport_domain_out, out, 1486 transport_domain); 1487 return td; 1488 } 1489 1490 /** 1491 * Dump all flows to file. 1492 * 1493 * @param[in] fdb_domain 1494 * FDB domain. 1495 * @param[in] rx_domain 1496 * RX domain. 1497 * @param[in] tx_domain 1498 * TX domain. 1499 * @param[out] file 1500 * Pointer to file stream. 1501 * 1502 * @return 1503 * 0 on success, a nagative value otherwise. 1504 */ 1505 int 1506 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1507 void *rx_domain __rte_unused, 1508 void *tx_domain __rte_unused, FILE *file __rte_unused) 1509 { 1510 int ret = 0; 1511 1512 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1513 if (fdb_domain) { 1514 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1515 if (ret) 1516 return ret; 1517 } 1518 MLX5_ASSERT(rx_domain); 1519 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1520 if (ret) 1521 return ret; 1522 MLX5_ASSERT(tx_domain); 1523 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1524 #else 1525 ret = ENOTSUP; 1526 #endif 1527 return -ret; 1528 } 1529 1530 /* 1531 * Create CQ using DevX API. 1532 * 1533 * @param[in] ctx 1534 * Context returned from mlx5 open_device() glue function. 1535 * @param [in] attr 1536 * Pointer to CQ attributes structure. 1537 * 1538 * @return 1539 * The DevX object created, NULL otherwise and rte_errno is set. 1540 */ 1541 struct mlx5_devx_obj * 1542 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1543 { 1544 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1545 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1546 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1547 sizeof(*cq_obj), 1548 0, SOCKET_ID_ANY); 1549 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1550 1551 if (!cq_obj) { 1552 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1553 rte_errno = ENOMEM; 1554 return NULL; 1555 } 1556 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1557 if (attr->db_umem_valid) { 1558 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1559 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1560 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1561 } else { 1562 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1563 } 1564 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1565 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1566 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1567 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1568 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1569 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1570 MLX5_SET(cqc, cqctx, log_page_size, 1571 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1572 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1573 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1574 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1575 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1576 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1577 attr->mini_cqe_res_format_ext); 1578 if (attr->q_umem_valid) { 1579 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1580 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1581 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1582 attr->q_umem_offset); 1583 } 1584 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1585 sizeof(out)); 1586 if (!cq_obj->obj) { 1587 rte_errno = errno; 1588 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1589 mlx5_free(cq_obj); 1590 return NULL; 1591 } 1592 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1593 return cq_obj; 1594 } 1595 1596 /** 1597 * Create VIRTQ using DevX API. 1598 * 1599 * @param[in] ctx 1600 * Context returned from mlx5 open_device() glue function. 1601 * @param [in] attr 1602 * Pointer to VIRTQ attributes structure. 1603 * 1604 * @return 1605 * The DevX object created, NULL otherwise and rte_errno is set. 1606 */ 1607 struct mlx5_devx_obj * 1608 mlx5_devx_cmd_create_virtq(void *ctx, 1609 struct mlx5_devx_virtq_attr *attr) 1610 { 1611 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1612 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1613 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1614 sizeof(*virtq_obj), 1615 0, SOCKET_ID_ANY); 1616 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1617 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1618 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1619 1620 if (!virtq_obj) { 1621 DRV_LOG(ERR, "Failed to allocate virtq data."); 1622 rte_errno = ENOMEM; 1623 return NULL; 1624 } 1625 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1626 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1627 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1628 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1629 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1630 attr->hw_available_index); 1631 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1632 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1633 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1634 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1635 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1636 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1637 attr->virtio_version_1_0); 1638 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1639 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1640 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1641 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1642 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1643 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1644 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1645 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1646 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1647 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 1648 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 1649 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 1650 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 1651 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 1652 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 1653 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 1654 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 1655 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 1656 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 1657 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 1658 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 1659 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 1660 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 1661 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1662 sizeof(out)); 1663 if (!virtq_obj->obj) { 1664 rte_errno = errno; 1665 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 1666 mlx5_free(virtq_obj); 1667 return NULL; 1668 } 1669 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1670 return virtq_obj; 1671 } 1672 1673 /** 1674 * Modify VIRTQ using DevX API. 1675 * 1676 * @param[in] virtq_obj 1677 * Pointer to virtq object structure. 1678 * @param [in] attr 1679 * Pointer to modify virtq attributes structure. 1680 * 1681 * @return 1682 * 0 on success, a negative errno value otherwise and rte_errno is set. 1683 */ 1684 int 1685 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 1686 struct mlx5_devx_virtq_attr *attr) 1687 { 1688 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1689 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1690 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1691 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1692 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1693 int ret; 1694 1695 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1696 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 1697 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1698 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1699 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1700 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 1701 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1702 switch (attr->type) { 1703 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 1704 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 1705 break; 1706 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 1707 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 1708 attr->dirty_bitmap_mkey); 1709 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 1710 attr->dirty_bitmap_addr); 1711 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 1712 attr->dirty_bitmap_size); 1713 break; 1714 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 1715 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 1716 attr->dirty_bitmap_dump_enable); 1717 break; 1718 default: 1719 rte_errno = EINVAL; 1720 return -rte_errno; 1721 } 1722 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 1723 out, sizeof(out)); 1724 if (ret) { 1725 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1726 rte_errno = errno; 1727 return -rte_errno; 1728 } 1729 return ret; 1730 } 1731 1732 /** 1733 * Query VIRTQ using DevX API. 1734 * 1735 * @param[in] virtq_obj 1736 * Pointer to virtq object structure. 1737 * @param [in/out] attr 1738 * Pointer to virtq attributes structure. 1739 * 1740 * @return 1741 * 0 on success, a negative errno value otherwise and rte_errno is set. 1742 */ 1743 int 1744 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 1745 struct mlx5_devx_virtq_attr *attr) 1746 { 1747 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1748 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 1749 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 1750 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 1751 int ret; 1752 1753 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1754 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1755 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1756 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1757 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1758 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 1759 out, sizeof(out)); 1760 if (ret) { 1761 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1762 rte_errno = errno; 1763 return -errno; 1764 } 1765 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 1766 hw_available_index); 1767 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 1768 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 1769 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 1770 virtio_q_context.error_type); 1771 return ret; 1772 } 1773 1774 /** 1775 * Create QP using DevX API. 1776 * 1777 * @param[in] ctx 1778 * Context returned from mlx5 open_device() glue function. 1779 * @param [in] attr 1780 * Pointer to QP attributes structure. 1781 * 1782 * @return 1783 * The DevX object created, NULL otherwise and rte_errno is set. 1784 */ 1785 struct mlx5_devx_obj * 1786 mlx5_devx_cmd_create_qp(void *ctx, 1787 struct mlx5_devx_qp_attr *attr) 1788 { 1789 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 1790 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 1791 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 1792 sizeof(*qp_obj), 1793 0, SOCKET_ID_ANY); 1794 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1795 1796 if (!qp_obj) { 1797 DRV_LOG(ERR, "Failed to allocate QP data."); 1798 rte_errno = ENOMEM; 1799 return NULL; 1800 } 1801 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 1802 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 1803 MLX5_SET(qpc, qpc, pd, attr->pd); 1804 if (attr->uar_index) { 1805 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1806 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 1807 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1808 MLX5_SET(qpc, qpc, log_page_size, 1809 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1810 if (attr->sq_size) { 1811 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); 1812 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 1813 MLX5_SET(qpc, qpc, log_sq_size, 1814 rte_log2_u32(attr->sq_size)); 1815 } else { 1816 MLX5_SET(qpc, qpc, no_sq, 1); 1817 } 1818 if (attr->rq_size) { 1819 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); 1820 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 1821 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 1822 MLX5_LOG_RQ_STRIDE_SHIFT); 1823 MLX5_SET(qpc, qpc, log_rq_size, 1824 rte_log2_u32(attr->rq_size)); 1825 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 1826 } else { 1827 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1828 } 1829 if (attr->dbr_umem_valid) { 1830 MLX5_SET(qpc, qpc, dbr_umem_valid, 1831 attr->dbr_umem_valid); 1832 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 1833 } 1834 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 1835 MLX5_SET64(create_qp_in, in, wq_umem_offset, 1836 attr->wq_umem_offset); 1837 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 1838 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 1839 } else { 1840 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 1841 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1842 MLX5_SET(qpc, qpc, no_sq, 1); 1843 } 1844 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1845 sizeof(out)); 1846 if (!qp_obj->obj) { 1847 rte_errno = errno; 1848 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 1849 mlx5_free(qp_obj); 1850 return NULL; 1851 } 1852 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 1853 return qp_obj; 1854 } 1855 1856 /** 1857 * Modify QP using DevX API. 1858 * Currently supports only force loop-back QP. 1859 * 1860 * @param[in] qp 1861 * Pointer to QP object structure. 1862 * @param [in] qp_st_mod_op 1863 * The QP state modification operation. 1864 * @param [in] remote_qp_id 1865 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 1866 * 1867 * @return 1868 * 0 on success, a negative errno value otherwise and rte_errno is set. 1869 */ 1870 int 1871 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 1872 uint32_t remote_qp_id) 1873 { 1874 union { 1875 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 1876 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 1877 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 1878 } in; 1879 union { 1880 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 1881 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 1882 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 1883 } out; 1884 void *qpc; 1885 int ret; 1886 unsigned int inlen; 1887 unsigned int outlen; 1888 1889 memset(&in, 0, sizeof(in)); 1890 memset(&out, 0, sizeof(out)); 1891 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 1892 switch (qp_st_mod_op) { 1893 case MLX5_CMD_OP_RST2INIT_QP: 1894 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 1895 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 1896 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1897 MLX5_SET(qpc, qpc, rre, 1); 1898 MLX5_SET(qpc, qpc, rwe, 1); 1899 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1900 inlen = sizeof(in.rst2init); 1901 outlen = sizeof(out.rst2init); 1902 break; 1903 case MLX5_CMD_OP_INIT2RTR_QP: 1904 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 1905 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 1906 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 1907 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1908 MLX5_SET(qpc, qpc, mtu, 1); 1909 MLX5_SET(qpc, qpc, log_msg_max, 30); 1910 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 1911 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 1912 inlen = sizeof(in.init2rtr); 1913 outlen = sizeof(out.init2rtr); 1914 break; 1915 case MLX5_CMD_OP_RTR2RTS_QP: 1916 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 1917 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 1918 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 1919 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 1920 MLX5_SET(qpc, qpc, retry_count, 7); 1921 MLX5_SET(qpc, qpc, rnr_retry, 7); 1922 inlen = sizeof(in.rtr2rts); 1923 outlen = sizeof(out.rtr2rts); 1924 break; 1925 default: 1926 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 1927 qp_st_mod_op); 1928 rte_errno = EINVAL; 1929 return -rte_errno; 1930 } 1931 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 1932 if (ret) { 1933 DRV_LOG(ERR, "Failed to modify QP using DevX."); 1934 rte_errno = errno; 1935 return -rte_errno; 1936 } 1937 return ret; 1938 } 1939 1940 struct mlx5_devx_obj * 1941 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 1942 { 1943 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 1944 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1945 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 1946 sizeof(*couners_obj), 0, 1947 SOCKET_ID_ANY); 1948 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 1949 1950 if (!couners_obj) { 1951 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 1952 rte_errno = ENOMEM; 1953 return NULL; 1954 } 1955 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1956 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1957 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1958 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 1959 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1960 sizeof(out)); 1961 if (!couners_obj->obj) { 1962 rte_errno = errno; 1963 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 1964 " DevX."); 1965 mlx5_free(couners_obj); 1966 return NULL; 1967 } 1968 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1969 return couners_obj; 1970 } 1971 1972 int 1973 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 1974 struct mlx5_devx_virtio_q_couners_attr *attr) 1975 { 1976 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1977 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 1978 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 1979 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 1980 virtio_q_counters); 1981 int ret; 1982 1983 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1984 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1985 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1986 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 1987 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 1988 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 1989 sizeof(out)); 1990 if (ret) { 1991 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 1992 rte_errno = errno; 1993 return -errno; 1994 } 1995 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 1996 received_desc); 1997 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 1998 completed_desc); 1999 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2000 error_cqes); 2001 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2002 bad_desc_errors); 2003 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2004 exceed_max_chain); 2005 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2006 invalid_buffer); 2007 return ret; 2008 } 2009 2010 /** 2011 * Create general object of type FLOW_HIT_ASO using DevX API. 2012 * 2013 * @param[in] ctx 2014 * Context returned from mlx5 open_device() glue function. 2015 * @param [in] pd 2016 * PD value to associate the FLOW_HIT_ASO object with. 2017 * 2018 * @return 2019 * The DevX object created, NULL otherwise and rte_errno is set. 2020 */ 2021 struct mlx5_devx_obj * 2022 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2023 { 2024 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2025 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2026 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2027 void *ptr = NULL; 2028 2029 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2030 0, SOCKET_ID_ANY); 2031 if (!flow_hit_aso_obj) { 2032 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2033 rte_errno = ENOMEM; 2034 return NULL; 2035 } 2036 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2037 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2038 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2039 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2040 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2041 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2042 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2043 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2044 out, sizeof(out)); 2045 if (!flow_hit_aso_obj->obj) { 2046 rte_errno = errno; 2047 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX."); 2048 mlx5_free(flow_hit_aso_obj); 2049 return NULL; 2050 } 2051 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2052 return flow_hit_aso_obj; 2053 } 2054 2055 /* 2056 * Create PD using DevX API. 2057 * 2058 * @param[in] ctx 2059 * Context returned from mlx5 open_device() glue function. 2060 * 2061 * @return 2062 * The DevX object created, NULL otherwise and rte_errno is set. 2063 */ 2064 struct mlx5_devx_obj * 2065 mlx5_devx_cmd_alloc_pd(void *ctx) 2066 { 2067 struct mlx5_devx_obj *ppd = 2068 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2069 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2070 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2071 2072 if (!ppd) { 2073 DRV_LOG(ERR, "Failed to allocate PD data."); 2074 rte_errno = ENOMEM; 2075 return NULL; 2076 } 2077 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2078 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2079 out, sizeof(out)); 2080 if (!ppd->obj) { 2081 mlx5_free(ppd); 2082 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2083 rte_errno = errno; 2084 return NULL; 2085 } 2086 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2087 return ppd; 2088 } 2089