1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /* FW writes status value to the OUT buffer at offset 00H */ 17 #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status) 18 /* FW writes syndrome value to the OUT buffer at offset 04H */ 19 #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome) 20 21 #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1)) 22 23 #define DEVX_DRV_LOG(level, out, reason, param, value) \ 24 do { \ 25 /* \ 26 * Some (old) GCC compilers like 7.5.0 and aarch64 GCC 7.1-2017.08 \ 27 * do not expand correctly when the macro invoked when the `param` \ 28 * is `NULL`. \ 29 * Use `local_param` to avoid direct `NULL` expansion. \ 30 */ \ 31 const char *local_param = (const char *)param; \ 32 \ 33 rte_errno = errno; \ 34 if (!local_param) { \ 35 DRV_LOG(level, \ 36 "DevX %s failed errno=%d status=%#x syndrome=%#x", \ 37 (reason), errno, MLX5_FW_STATUS((out)), \ 38 MLX5_FW_SYNDROME((out))); \ 39 } else { \ 40 DRV_LOG(level, \ 41 "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x",\ 42 (reason), local_param, (value), errno, \ 43 MLX5_FW_STATUS((out)), MLX5_FW_SYNDROME((out))); \ 44 } \ 45 } while (0) 46 47 static void * 48 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, 49 int *err, uint32_t flags) 50 { 51 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); 52 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); 53 int rc; 54 55 memset(in, 0, size_in); 56 memset(out, 0, size_out); 57 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 58 MLX5_SET(query_hca_cap_in, in, op_mod, flags); 59 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); 60 if (rc || MLX5_FW_STATUS(out)) { 61 DEVX_DRV_LOG(ERR, out, "HCA capabilities", "func", flags >> 1); 62 if (err) 63 *err = MLX5_DEVX_ERR_RC(rc); 64 return NULL; 65 } 66 if (err) 67 *err = 0; 68 return MLX5_ADDR_OF(query_hca_cap_out, out, capability); 69 } 70 71 /** 72 * Perform read access to the registers. Reads data from register 73 * and writes ones to the specified buffer. 74 * 75 * @param[in] ctx 76 * Context returned from mlx5 open_device() glue function. 77 * @param[in] reg_id 78 * Register identifier according to the PRM. 79 * @param[in] arg 80 * Register access auxiliary parameter according to the PRM. 81 * @param[out] data 82 * Pointer to the buffer to store read data. 83 * @param[in] dw_cnt 84 * Buffer size in double words. 85 * 86 * @return 87 * 0 on success, a negative value otherwise. 88 */ 89 int 90 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 91 uint32_t *data, uint32_t dw_cnt) 92 { 93 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 94 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 95 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 96 int rc; 97 98 MLX5_ASSERT(data && dw_cnt); 99 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 100 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 101 DRV_LOG(ERR, "Not enough buffer for register read data"); 102 return -1; 103 } 104 MLX5_SET(access_register_in, in, opcode, 105 MLX5_CMD_OP_ACCESS_REGISTER_USER); 106 MLX5_SET(access_register_in, in, op_mod, 107 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 108 MLX5_SET(access_register_in, in, register_id, reg_id); 109 MLX5_SET(access_register_in, in, argument, arg); 110 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 111 MLX5_ST_SZ_BYTES(access_register_out) + 112 sizeof(uint32_t) * dw_cnt); 113 if (rc || MLX5_FW_STATUS(out)) { 114 DEVX_DRV_LOG(DEBUG, out, "read access", "NIC register", reg_id); 115 return MLX5_DEVX_ERR_RC(rc); 116 } 117 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 118 dw_cnt * sizeof(uint32_t)); 119 return 0; 120 } 121 122 /** 123 * Perform write access to the registers. 124 * 125 * @param[in] ctx 126 * Context returned from mlx5 open_device() glue function. 127 * @param[in] reg_id 128 * Register identifier according to the PRM. 129 * @param[in] arg 130 * Register access auxiliary parameter according to the PRM. 131 * @param[out] data 132 * Pointer to the buffer containing data to write. 133 * @param[in] dw_cnt 134 * Buffer size in double words (32bit units). 135 * 136 * @return 137 * 0 on success, a negative value otherwise. 138 */ 139 int 140 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 141 uint32_t *data, uint32_t dw_cnt) 142 { 143 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 144 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 145 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 146 int rc; 147 void *ptr; 148 149 MLX5_ASSERT(data && dw_cnt); 150 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 151 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 152 DRV_LOG(ERR, "Data to write exceeds max size"); 153 return -1; 154 } 155 MLX5_SET(access_register_in, in, opcode, 156 MLX5_CMD_OP_ACCESS_REGISTER_USER); 157 MLX5_SET(access_register_in, in, op_mod, 158 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 159 MLX5_SET(access_register_in, in, register_id, reg_id); 160 MLX5_SET(access_register_in, in, argument, arg); 161 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 162 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 163 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 164 if (rc || MLX5_FW_STATUS(out)) { 165 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 166 return MLX5_DEVX_ERR_RC(rc); 167 } 168 rc = mlx5_glue->devx_general_cmd(ctx, in, 169 MLX5_ST_SZ_BYTES(access_register_in) + 170 dw_cnt * sizeof(uint32_t), 171 out, sizeof(out)); 172 if (rc || MLX5_FW_STATUS(out)) { 173 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 174 return MLX5_DEVX_ERR_RC(rc); 175 } 176 return 0; 177 } 178 179 struct mlx5_devx_obj * 180 mlx5_devx_cmd_flow_counter_alloc_general(void *ctx, 181 struct mlx5_devx_counter_attr *attr) 182 { 183 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 184 0, SOCKET_ID_ANY); 185 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 186 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 187 188 if (!dcs) { 189 rte_errno = ENOMEM; 190 return NULL; 191 } 192 MLX5_SET(alloc_flow_counter_in, in, opcode, 193 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 194 if (attr->bulk_log_max_alloc) 195 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk_log_size, 196 attr->flow_counter_bulk_log_size); 197 else 198 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, 199 attr->bulk_n_128); 200 if (attr->pd_valid) 201 MLX5_SET(alloc_flow_counter_in, in, pd, attr->pd); 202 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 203 sizeof(in), out, sizeof(out)); 204 if (!dcs->obj) { 205 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 206 rte_errno = errno; 207 mlx5_free(dcs); 208 return NULL; 209 } 210 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 211 return dcs; 212 } 213 214 /** 215 * Allocate flow counters via devx interface. 216 * 217 * @param[in] ctx 218 * Context returned from mlx5 open_device() glue function. 219 * @param dcs 220 * Pointer to counters properties structure to be filled by the routine. 221 * @param bulk_n_128 222 * Bulk counter numbers in 128 counters units. 223 * 224 * @return 225 * Pointer to counter object on success, a negative value otherwise and 226 * rte_errno is set. 227 */ 228 struct mlx5_devx_obj * 229 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 230 { 231 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 232 0, SOCKET_ID_ANY); 233 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 234 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 235 236 if (!dcs) { 237 rte_errno = ENOMEM; 238 return NULL; 239 } 240 MLX5_SET(alloc_flow_counter_in, in, opcode, 241 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 242 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 243 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 244 sizeof(in), out, sizeof(out)); 245 if (!dcs->obj) { 246 DEVX_DRV_LOG(ERR, out, "allocate counters", NULL, 0); 247 mlx5_free(dcs); 248 return NULL; 249 } 250 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 251 return dcs; 252 } 253 254 /** 255 * Query flow counters values. 256 * 257 * @param[in] dcs 258 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 259 * @param[in] clear 260 * Whether hardware should clear the counters after the query or not. 261 * @param[in] n_counters 262 * 0 in case of 1 counter to read, otherwise the counter number to read. 263 * @param pkts 264 * The number of packets that matched the flow. 265 * @param bytes 266 * The number of bytes that matched the flow. 267 * @param mkey 268 * The mkey key for batch query. 269 * @param addr 270 * The address in the mkey range for batch query. 271 * @param cmd_comp 272 * The completion object for asynchronous batch query. 273 * @param async_id 274 * The ID to be returned in the asynchronous batch query response. 275 * 276 * @return 277 * 0 on success, a negative value otherwise. 278 */ 279 int 280 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 281 int clear, uint32_t n_counters, 282 uint64_t *pkts, uint64_t *bytes, 283 uint32_t mkey, void *addr, 284 void *cmd_comp, 285 uint64_t async_id) 286 { 287 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 288 MLX5_ST_SZ_BYTES(traffic_counter); 289 uint32_t out[out_len]; 290 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 291 void *stats; 292 int rc; 293 294 MLX5_SET(query_flow_counter_in, in, opcode, 295 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 296 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 297 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 298 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 299 300 if (n_counters) { 301 MLX5_SET(query_flow_counter_in, in, num_of_counters, 302 n_counters); 303 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 304 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 305 MLX5_SET64(query_flow_counter_in, in, address, 306 (uint64_t)(uintptr_t)addr); 307 } 308 if (!cmd_comp) 309 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 310 out_len); 311 else 312 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 313 out_len, async_id, 314 cmd_comp); 315 if (rc) { 316 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 317 rte_errno = rc; 318 return -rc; 319 } 320 if (!n_counters) { 321 stats = MLX5_ADDR_OF(query_flow_counter_out, 322 out, flow_statistics); 323 *pkts = MLX5_GET64(traffic_counter, stats, packets); 324 *bytes = MLX5_GET64(traffic_counter, stats, octets); 325 } 326 return 0; 327 } 328 329 /** 330 * Create a new mkey. 331 * 332 * @param[in] ctx 333 * Context returned from mlx5 open_device() glue function. 334 * @param[in] attr 335 * Attributes of the requested mkey. 336 * 337 * @return 338 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 339 * is set. 340 */ 341 struct mlx5_devx_obj * 342 mlx5_devx_cmd_mkey_create(void *ctx, 343 struct mlx5_devx_mkey_attr *attr) 344 { 345 struct mlx5_klm *klm_array = attr->klm_array; 346 int klm_num = attr->klm_num; 347 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 348 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 349 uint32_t in[in_size_dw]; 350 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 351 void *mkc; 352 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 353 0, SOCKET_ID_ANY); 354 size_t pgsize; 355 uint32_t translation_size; 356 357 if (!mkey) { 358 rte_errno = ENOMEM; 359 return NULL; 360 } 361 memset(in, 0, in_size_dw * 4); 362 pgsize = rte_mem_page_size(); 363 if (pgsize == (size_t)-1) { 364 mlx5_free(mkey); 365 DRV_LOG(ERR, "Failed to get page size"); 366 rte_errno = ENOMEM; 367 return NULL; 368 } 369 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 370 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 371 if (klm_num > 0) { 372 int i; 373 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 374 klm_pas_mtt); 375 translation_size = RTE_ALIGN(klm_num, 4); 376 for (i = 0; i < klm_num; i++) { 377 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 378 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 379 MLX5_SET64(klm, klm, address, klm_array[i].address); 380 klm += MLX5_ST_SZ_BYTES(klm); 381 } 382 for (; i < (int)translation_size; i++) { 383 MLX5_SET(klm, klm, mkey, 0x0); 384 MLX5_SET64(klm, klm, address, 0x0); 385 klm += MLX5_ST_SZ_BYTES(klm); 386 } 387 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 388 MLX5_MKC_ACCESS_MODE_KLM_FBS : 389 MLX5_MKC_ACCESS_MODE_KLM); 390 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 391 } else { 392 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 393 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 394 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 395 } 396 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 397 translation_size); 398 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 399 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 400 MLX5_SET(mkc, mkc, lw, 0x1); 401 MLX5_SET(mkc, mkc, lr, 0x1); 402 if (attr->set_remote_rw) { 403 MLX5_SET(mkc, mkc, rw, 0x1); 404 MLX5_SET(mkc, mkc, rr, 0x1); 405 } 406 MLX5_SET(mkc, mkc, qpn, 0xffffff); 407 MLX5_SET(mkc, mkc, pd, attr->pd); 408 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 409 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 410 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 411 MLX5_SET(mkc, mkc, relaxed_ordering_write, 412 attr->relaxed_ordering_write); 413 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 414 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 415 MLX5_SET64(mkc, mkc, len, attr->size); 416 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 417 if (attr->crypto_en) { 418 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 419 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 420 } 421 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 422 sizeof(out)); 423 if (!mkey->obj) { 424 DEVX_DRV_LOG(ERR, out, klm_num ? "create indirect mkey" 425 : "create direct key", NULL, 0); 426 mlx5_free(mkey); 427 return NULL; 428 } 429 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 430 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 431 return mkey; 432 } 433 434 /** 435 * Get status of devx command response. 436 * Mainly used for asynchronous commands. 437 * 438 * @param[in] out 439 * The out response buffer. 440 * 441 * @return 442 * 0 on success, non-zero value otherwise. 443 */ 444 int 445 mlx5_devx_get_out_command_status(void *out) 446 { 447 int status; 448 449 if (!out) 450 return -EINVAL; 451 status = MLX5_GET(query_flow_counter_out, out, status); 452 if (status) { 453 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 454 455 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 456 syndrome); 457 } 458 return status; 459 } 460 461 /** 462 * Destroy any object allocated by a Devx API. 463 * 464 * @param[in] obj 465 * Pointer to a general object. 466 * 467 * @return 468 * 0 on success, a negative value otherwise. 469 */ 470 int 471 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 472 { 473 int ret; 474 475 if (!obj) 476 return 0; 477 ret = mlx5_glue->devx_obj_destroy(obj->obj); 478 mlx5_free(obj); 479 return ret; 480 } 481 482 /** 483 * Query NIC vport context. 484 * Fills minimal inline attribute. 485 * 486 * @param[in] ctx 487 * ibv contexts returned from mlx5dv_open_device. 488 * @param[in] vport 489 * vport index 490 * @param[out] attr 491 * Attributes device values. 492 * 493 * @return 494 * 0 on success, a negative value otherwise. 495 */ 496 static int 497 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 498 unsigned int vport, 499 struct mlx5_hca_attr *attr) 500 { 501 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 502 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 503 void *vctx; 504 int rc; 505 506 /* Query NIC vport context to determine inline mode. */ 507 MLX5_SET(query_nic_vport_context_in, in, opcode, 508 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 509 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 510 if (vport) 511 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 512 rc = mlx5_glue->devx_general_cmd(ctx, 513 in, sizeof(in), 514 out, sizeof(out)); 515 if (rc || MLX5_FW_STATUS(out)) { 516 DEVX_DRV_LOG(ERR, out, "query NIC vport context", NULL, 0); 517 return MLX5_DEVX_ERR_RC(rc); 518 } 519 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 520 nic_vport_context); 521 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 522 min_wqe_inline_mode); 523 return 0; 524 } 525 526 /** 527 * Query NIC vDPA attributes. 528 * 529 * @param[in] ctx 530 * Context returned from mlx5 open_device() glue function. 531 * @param[out] vdpa_attr 532 * vDPA Attributes structure to fill. 533 */ 534 static void 535 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 536 struct mlx5_hca_vdpa_attr *vdpa_attr) 537 { 538 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 539 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 540 void *hcattr; 541 542 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, 543 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 544 MLX5_HCA_CAP_OPMOD_GET_CUR); 545 if (!hcattr) { 546 DRV_LOG(DEBUG, "Failed to query devx VDPA capabilities"); 547 vdpa_attr->valid = 0; 548 } else { 549 vdpa_attr->valid = 1; 550 vdpa_attr->desc_tunnel_offload_type = 551 MLX5_GET(virtio_emulation_cap, hcattr, 552 desc_tunnel_offload_type); 553 vdpa_attr->eth_frame_offload_type = 554 MLX5_GET(virtio_emulation_cap, hcattr, 555 eth_frame_offload_type); 556 vdpa_attr->virtio_version_1_0 = 557 MLX5_GET(virtio_emulation_cap, hcattr, 558 virtio_version_1_0); 559 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 560 tso_ipv4); 561 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 562 tso_ipv6); 563 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 564 tx_csum); 565 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 566 rx_csum); 567 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 568 event_mode); 569 vdpa_attr->virtio_queue_type = 570 MLX5_GET(virtio_emulation_cap, hcattr, 571 virtio_queue_type); 572 vdpa_attr->log_doorbell_stride = 573 MLX5_GET(virtio_emulation_cap, hcattr, 574 log_doorbell_stride); 575 vdpa_attr->vnet_modify_ext = 576 MLX5_GET(virtio_emulation_cap, hcattr, 577 vnet_modify_ext); 578 vdpa_attr->virtio_net_q_addr_modify = 579 MLX5_GET(virtio_emulation_cap, hcattr, 580 virtio_net_q_addr_modify); 581 vdpa_attr->virtio_q_index_modify = 582 MLX5_GET(virtio_emulation_cap, hcattr, 583 virtio_q_index_modify); 584 vdpa_attr->log_doorbell_bar_size = 585 MLX5_GET(virtio_emulation_cap, hcattr, 586 log_doorbell_bar_size); 587 vdpa_attr->doorbell_bar_offset = 588 MLX5_GET64(virtio_emulation_cap, hcattr, 589 doorbell_bar_offset); 590 vdpa_attr->max_num_virtio_queues = 591 MLX5_GET(virtio_emulation_cap, hcattr, 592 max_num_virtio_queues); 593 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 594 umem_1_buffer_param_a); 595 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 596 umem_1_buffer_param_b); 597 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 598 umem_2_buffer_param_a); 599 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 600 umem_2_buffer_param_b); 601 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 602 umem_3_buffer_param_a); 603 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 604 umem_3_buffer_param_b); 605 } 606 } 607 608 /** 609 * Query match sample handle parameters. 610 * 611 * This command allows translating a field sample handle returned by either 612 * PARSE_GRAPH_FLOW_MATCH_SAMPLE or by GENEVE TLV OPTION object into values 613 * used for header modification or header matching/hashing. 614 * 615 * @param[in] ctx 616 * Context used to create either GENEVE TLV option or FLEX PARSE GRAPH object. 617 * @param[in] sample_field_id 618 * Field sample handle returned by either PARSE_GRAPH_FLOW_MATCH_SAMPLE 619 * or by GENEVE TLV OPTION object. 620 * @param[out] attr 621 * Pointer to match sample info attributes structure. 622 * 623 * @return 624 * 0 on success, a negative errno otherwise and rte_errno is set. 625 */ 626 int 627 mlx5_devx_cmd_match_sample_info_query(void *ctx, uint32_t sample_field_id, 628 struct mlx5_devx_match_sample_info_query_attr *attr) 629 { 630 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 631 uint32_t out[MLX5_ST_SZ_DW(query_match_sample_info_out)] = {0}; 632 uint32_t in[MLX5_ST_SZ_DW(query_match_sample_info_in)] = {0}; 633 int rc; 634 635 MLX5_SET(query_match_sample_info_in, in, opcode, 636 MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO); 637 MLX5_SET(query_match_sample_info_in, in, op_mod, 0); 638 MLX5_SET(query_match_sample_info_in, in, sample_field_id, 639 sample_field_id); 640 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 641 if (rc) { 642 DRV_LOG(ERR, "Failed to query match sample info using DevX: %s", 643 strerror(rc)); 644 rte_errno = rc; 645 return -rc; 646 } 647 attr->modify_field_id = MLX5_GET(query_match_sample_info_out, out, 648 modify_field_id); 649 attr->sample_dw_data = MLX5_GET(query_match_sample_info_out, out, 650 field_format_select_dw); 651 attr->sample_dw_ok_bit = MLX5_GET(query_match_sample_info_out, out, 652 ok_bit_format_select_dw); 653 attr->sample_dw_ok_bit_offset = MLX5_GET(query_match_sample_info_out, 654 out, ok_bit_offset); 655 return 0; 656 #else 657 (void)ctx; 658 (void)sample_field_id; 659 (void)attr; 660 return -ENOTSUP; 661 #endif 662 } 663 664 int 665 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 666 uint32_t *ids, 667 uint32_t num, uint8_t *anchor) 668 { 669 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 670 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 671 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 672 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 673 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 674 int ret; 675 uint32_t idx = 0; 676 uint32_t i; 677 678 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 679 rte_errno = EINVAL; 680 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 681 return -rte_errno; 682 } 683 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 684 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 685 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 686 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 687 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 688 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 689 out, sizeof(out)); 690 if (ret) { 691 rte_errno = ret; 692 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 693 (void *)flex_obj); 694 return -rte_errno; 695 } 696 if (anchor) 697 *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id); 698 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx < num; i++) { 699 void *s_off = (void *)((char *)sample + i * 700 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 701 uint32_t en; 702 703 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 704 flow_match_sample_en); 705 if (!en) 706 continue; 707 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 708 flow_match_sample_field_id); 709 } 710 if (num != idx) { 711 rte_errno = EINVAL; 712 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 713 return -rte_errno; 714 } 715 return ret; 716 } 717 718 struct mlx5_devx_obj * 719 mlx5_devx_cmd_create_flex_parser(void *ctx, 720 struct mlx5_devx_graph_node_attr *data) 721 { 722 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 723 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 724 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 725 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 726 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 727 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 728 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 729 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 730 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 731 uint32_t i; 732 733 if (!parse_flex_obj) { 734 DRV_LOG(ERR, "Failed to allocate flex parser data."); 735 rte_errno = ENOMEM; 736 return NULL; 737 } 738 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 739 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 740 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 741 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 742 MLX5_SET(parse_graph_flex, flex, header_length_mode, 743 data->header_length_mode); 744 MLX5_SET64(parse_graph_flex, flex, modify_field_select, 745 data->modify_field_select); 746 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 747 data->header_length_base_value); 748 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 749 data->header_length_field_offset); 750 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 751 data->header_length_field_shift); 752 MLX5_SET(parse_graph_flex, flex, next_header_field_offset, 753 data->next_header_field_offset); 754 MLX5_SET(parse_graph_flex, flex, next_header_field_size, 755 data->next_header_field_size); 756 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 757 data->header_length_field_mask); 758 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 759 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 760 void *s_off = (void *)((char *)sample + i * 761 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 762 763 if (!s->flow_match_sample_en) 764 continue; 765 MLX5_SET(parse_graph_flow_match_sample, s_off, 766 flow_match_sample_en, !!s->flow_match_sample_en); 767 MLX5_SET(parse_graph_flow_match_sample, s_off, 768 flow_match_sample_field_offset, 769 s->flow_match_sample_field_offset); 770 MLX5_SET(parse_graph_flow_match_sample, s_off, 771 flow_match_sample_offset_mode, 772 s->flow_match_sample_offset_mode); 773 MLX5_SET(parse_graph_flow_match_sample, s_off, 774 flow_match_sample_field_offset_mask, 775 s->flow_match_sample_field_offset_mask); 776 MLX5_SET(parse_graph_flow_match_sample, s_off, 777 flow_match_sample_field_offset_shift, 778 s->flow_match_sample_field_offset_shift); 779 MLX5_SET(parse_graph_flow_match_sample, s_off, 780 flow_match_sample_field_base_offset, 781 s->flow_match_sample_field_base_offset); 782 MLX5_SET(parse_graph_flow_match_sample, s_off, 783 flow_match_sample_tunnel_mode, 784 s->flow_match_sample_tunnel_mode); 785 } 786 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 787 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 788 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 789 void *in_off = (void *)((char *)in_arc + i * 790 MLX5_ST_SZ_BYTES(parse_graph_arc)); 791 void *out_off = (void *)((char *)out_arc + i * 792 MLX5_ST_SZ_BYTES(parse_graph_arc)); 793 794 if (ia->arc_parse_graph_node != 0) { 795 MLX5_SET(parse_graph_arc, in_off, 796 compare_condition_value, 797 ia->compare_condition_value); 798 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 799 ia->start_inner_tunnel); 800 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 801 ia->arc_parse_graph_node); 802 MLX5_SET(parse_graph_arc, in_off, 803 parse_graph_node_handle, 804 ia->parse_graph_node_handle); 805 } 806 if (oa->arc_parse_graph_node != 0) { 807 MLX5_SET(parse_graph_arc, out_off, 808 compare_condition_value, 809 oa->compare_condition_value); 810 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 811 oa->start_inner_tunnel); 812 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 813 oa->arc_parse_graph_node); 814 MLX5_SET(parse_graph_arc, out_off, 815 parse_graph_node_handle, 816 oa->parse_graph_node_handle); 817 } 818 } 819 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 820 out, sizeof(out)); 821 if (!parse_flex_obj->obj) { 822 DEVX_DRV_LOG(ERR, out, "create FLEX PARSE GRAPH", NULL, 0); 823 mlx5_free(parse_flex_obj); 824 return NULL; 825 } 826 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 827 return parse_flex_obj; 828 } 829 830 static int 831 mlx5_devx_cmd_query_hca_parse_graph_node_cap 832 (void *ctx, struct mlx5_hca_flex_attr *attr) 833 { 834 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 835 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 836 void *hcattr; 837 int rc; 838 839 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 840 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | 841 MLX5_HCA_CAP_OPMOD_GET_CUR); 842 if (!hcattr) 843 return rc; 844 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); 845 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); 846 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, 847 header_length_mode); 848 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, 849 sample_offset_mode); 850 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, 851 max_num_arc_in); 852 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, 853 max_num_arc_out); 854 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, 855 max_num_sample); 856 attr->parse_graph_anchor = MLX5_GET(parse_graph_node_cap, hcattr, parse_graph_anchor); 857 attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr, 858 sample_tunnel_inner2); 859 attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr, 860 zero_size_supported); 861 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, 862 sample_id_in_out); 863 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, 864 max_base_header_length); 865 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, 866 max_sample_base_offset); 867 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, 868 max_next_header_offset); 869 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, 870 header_length_mask_width); 871 /* Get the max supported samples from HCA CAP 2 */ 872 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 873 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 874 MLX5_HCA_CAP_OPMOD_GET_CUR); 875 if (!hcattr) 876 return rc; 877 attr->max_num_prog_sample = 878 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); 879 return 0; 880 } 881 882 static int 883 mlx5_devx_query_pkt_integrity_match(void *hcattr) 884 { 885 return MLX5_GET(flow_table_nic_cap, hcattr, 886 ft_field_support_2_nic_receive.inner_l3_ok) && 887 MLX5_GET(flow_table_nic_cap, hcattr, 888 ft_field_support_2_nic_receive.inner_l4_ok) && 889 MLX5_GET(flow_table_nic_cap, hcattr, 890 ft_field_support_2_nic_receive.outer_l3_ok) && 891 MLX5_GET(flow_table_nic_cap, hcattr, 892 ft_field_support_2_nic_receive.outer_l4_ok) && 893 MLX5_GET(flow_table_nic_cap, hcattr, 894 ft_field_support_2_nic_receive 895 .inner_ipv4_checksum_ok) && 896 MLX5_GET(flow_table_nic_cap, hcattr, 897 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 898 MLX5_GET(flow_table_nic_cap, hcattr, 899 ft_field_support_2_nic_receive 900 .outer_ipv4_checksum_ok) && 901 MLX5_GET(flow_table_nic_cap, hcattr, 902 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 903 } 904 905 /** 906 * Query HCA attributes. 907 * Using those attributes we can check on run time if the device 908 * is having the required capabilities. 909 * 910 * @param[in] ctx 911 * Context returned from mlx5 open_device() glue function. 912 * @param[out] attr 913 * Attributes device values. 914 * 915 * @return 916 * 0 on success, a negative value otherwise. 917 */ 918 int 919 mlx5_devx_cmd_query_hca_attr(void *ctx, 920 struct mlx5_hca_attr *attr) 921 { 922 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 923 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 924 bool hca_cap_2_sup; 925 uint64_t general_obj_types_supported = 0; 926 void *hcattr; 927 int rc, i; 928 929 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 930 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 931 MLX5_HCA_CAP_OPMOD_GET_CUR); 932 if (!hcattr) 933 return rc; 934 hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2); 935 attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq); 936 attr->flow_counter_bulk_alloc_bitmap = 937 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 938 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 939 flow_counters_dump); 940 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp); 941 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp); 942 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 943 log_max_rqt_size); 944 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 945 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 946 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 947 log_max_hairpin_queues); 948 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 949 log_max_hairpin_wq_data_sz); 950 attr->log_max_hairpin_num_packets = MLX5_GET 951 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 952 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 953 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 954 relaxed_ordering_write); 955 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 956 relaxed_ordering_read); 957 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 958 access_register_user); 959 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 960 eth_net_offloads); 961 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 962 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 963 flex_parser_protocols); 964 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 965 max_geneve_tlv_options); 966 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 967 max_geneve_tlv_option_data_len); 968 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 969 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 970 general_obj_types) & 971 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 972 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 973 general_obj_types) & 974 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 975 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 976 general_obj_types) & 977 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 978 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 979 general_obj_types) & 980 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 981 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 982 wqe_index_ignore_cap); 983 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 984 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 985 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 986 log_max_static_sq_wq); 987 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 988 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 989 device_frequency_khz); 990 attr->scatter_fcs_w_decap_disable = 991 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 992 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 993 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 994 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 995 attr->steering_format_version = 996 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 997 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 998 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 999 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 1000 regexp_num_of_engines); 1001 /* Read the general_obj_types bitmap and extract the relevant bits. */ 1002 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 1003 general_obj_types); 1004 attr->vdpa.valid = !!(general_obj_types_supported & 1005 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 1006 attr->vdpa.queue_counters_valid = 1007 !!(general_obj_types_supported & 1008 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 1009 attr->parse_graph_flex_node = 1010 !!(general_obj_types_supported & 1011 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 1012 attr->flow_hit_aso = !!(general_obj_types_supported & 1013 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 1014 attr->geneve_tlv_opt = !!(general_obj_types_supported & 1015 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 1016 attr->dek = !!(general_obj_types_supported & 1017 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 1018 attr->import_kek = !!(general_obj_types_supported & 1019 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 1020 attr->credential = !!(general_obj_types_supported & 1021 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 1022 attr->crypto_login = !!(general_obj_types_supported & 1023 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 1024 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 1025 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 1026 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 1027 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 1028 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 1029 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 1030 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 1031 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 1032 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 1033 attr->reg_c_preserve = 1034 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 1035 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 1036 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 1037 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 1038 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 1039 compress_mmo_sq); 1040 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 1041 decompress_mmo_sq); 1042 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 1043 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 1044 compress_mmo_qp); 1045 attr->decomp_deflate_v1_en = MLX5_GET(cmd_hca_cap, hcattr, 1046 decompress_deflate_v1); 1047 attr->decomp_deflate_v2_en = MLX5_GET(cmd_hca_cap, hcattr, 1048 decompress_deflate_v2); 1049 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 1050 compress_min_block_size); 1051 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 1052 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 1053 log_compress_mmo_size); 1054 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 1055 log_decompress_mmo_size); 1056 attr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr, 1057 decompress_lz4_data_only_v2); 1058 attr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, 1059 decompress_lz4_no_checksum_v2); 1060 attr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, 1061 decompress_lz4_checksum_v2); 1062 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 1063 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 1064 mini_cqe_resp_flow_tag); 1065 attr->cqe_compression_128 = MLX5_GET(cmd_hca_cap, hcattr, 1066 cqe_compression_128); 1067 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 1068 mini_cqe_resp_l3_l4_tag); 1069 attr->enhanced_cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, 1070 enhanced_cqe_compression); 1071 attr->umr_indirect_mkey_disabled = 1072 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 1073 attr->umr_modify_entity_size_disabled = 1074 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 1075 attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time); 1076 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 1077 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 1078 general_obj_types) & 1079 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 1080 attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); 1081 attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table); 1082 attr->striding_rq = MLX5_GET(cmd_hca_cap, hcattr, striding_rq); 1083 attr->ext_stride_num_range = 1084 MLX5_GET(cmd_hca_cap, hcattr, ext_stride_num_range); 1085 attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr, 1086 max_flow_counter_15_0); 1087 attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr, 1088 max_flow_counter_31_16); 1089 attr->alloc_flow_counter_pd = MLX5_GET(cmd_hca_cap, hcattr, 1090 alloc_flow_counter_pd); 1091 attr->flow_counter_access_aso = MLX5_GET(cmd_hca_cap, hcattr, 1092 flow_counter_access_aso); 1093 attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr, 1094 flow_access_aso_opc_mod); 1095 attr->wqe_based_flow_table_sup = MLX5_GET(cmd_hca_cap, hcattr, 1096 wqe_based_flow_table_update_cap); 1097 /* 1098 * Flex item support needs max_num_prog_sample_field 1099 * from the Capabilities 2 table for PARSE_GRAPH_NODE 1100 */ 1101 if (attr->parse_graph_flex_node) { 1102 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap 1103 (ctx, &attr->flex); 1104 if (rc) 1105 return -1; 1106 attr->flex.query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr, 1107 query_match_sample_info); 1108 } 1109 if (attr->crypto) { 1110 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) || 1111 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_multi_block_be_tweak) || 1112 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_single_block_le_tweak); 1113 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1114 MLX5_GET_HCA_CAP_OP_MOD_CRYPTO | 1115 MLX5_HCA_CAP_OPMOD_GET_CUR); 1116 if (!hcattr) 1117 return -1; 1118 attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps, 1119 hcattr, wrapped_import_method) 1120 & 1 << 2); 1121 attr->crypto_mmo.crypto_mmo_qp = MLX5_GET(crypto_caps, hcattr, crypto_mmo_qp); 1122 attr->crypto_mmo.gcm_256_encrypt = 1123 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_encrypt); 1124 attr->crypto_mmo.gcm_128_encrypt = 1125 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_encrypt); 1126 attr->crypto_mmo.gcm_256_decrypt = 1127 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_decrypt); 1128 attr->crypto_mmo.gcm_128_decrypt = 1129 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_decrypt); 1130 attr->crypto_mmo.gcm_auth_tag_128 = 1131 MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_128); 1132 attr->crypto_mmo.gcm_auth_tag_96 = 1133 MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_96); 1134 attr->crypto_mmo.log_crypto_mmo_max_size = 1135 MLX5_GET(crypto_caps, hcattr, log_crypto_mmo_max_size); 1136 } 1137 if (hca_cap_2_sup) { 1138 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1139 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 1140 MLX5_HCA_CAP_OPMOD_GET_CUR); 1141 if (!hcattr) { 1142 DRV_LOG(DEBUG, 1143 "Failed to query DevX HCA capabilities 2."); 1144 return rc; 1145 } 1146 attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, 1147 log_min_stride_wqe_sz); 1148 attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr, 1149 hairpin_sq_wqe_bb_size); 1150 attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr, 1151 hairpin_sq_wq_in_host_mem); 1152 attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr, 1153 hairpin_data_buffer_locked); 1154 attr->flow_counter_bulk_log_max_alloc = MLX5_GET(cmd_hca_cap_2, 1155 hcattr, flow_counter_bulk_log_max_alloc); 1156 attr->flow_counter_bulk_log_granularity = 1157 MLX5_GET(cmd_hca_cap_2, hcattr, 1158 flow_counter_bulk_log_granularity); 1159 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1160 cross_vhca_object_to_object_supported); 1161 attr->cross_vhca = 1162 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR) && 1163 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT) && 1164 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT) && 1165 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC); 1166 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1167 allowed_object_for_other_vhca_access); 1168 attr->cross_vhca = attr->cross_vhca && 1169 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR) && 1170 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_FT) && 1171 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC); 1172 } 1173 if (attr->log_min_stride_wqe_sz == 0) 1174 attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 1175 if (attr->qos.sup) { 1176 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1177 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 1178 MLX5_HCA_CAP_OPMOD_GET_CUR); 1179 if (!hcattr) { 1180 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); 1181 return rc; 1182 } 1183 attr->qos.flow_meter_old = 1184 MLX5_GET(qos_cap, hcattr, flow_meter_old); 1185 attr->qos.log_max_flow_meter = 1186 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 1187 attr->qos.flow_meter_reg_c_ids = 1188 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 1189 attr->qos.flow_meter = 1190 MLX5_GET(qos_cap, hcattr, flow_meter); 1191 attr->qos.packet_pacing = 1192 MLX5_GET(qos_cap, hcattr, packet_pacing); 1193 attr->qos.wqe_rate_pp = 1194 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 1195 if (attr->qos.flow_meter_aso_sup) { 1196 attr->qos.log_meter_aso_granularity = 1197 MLX5_GET(qos_cap, hcattr, 1198 log_meter_aso_granularity); 1199 attr->qos.log_meter_aso_max_alloc = 1200 MLX5_GET(qos_cap, hcattr, 1201 log_meter_aso_max_alloc); 1202 attr->qos.log_max_num_meter_aso = 1203 MLX5_GET(qos_cap, hcattr, 1204 log_max_num_meter_aso); 1205 } 1206 } 1207 if (attr->vdpa.valid) 1208 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 1209 if (!attr->eth_net_offloads) 1210 return 0; 1211 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 1212 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1213 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 1214 MLX5_HCA_CAP_OPMOD_GET_CUR); 1215 if (!hcattr) { 1216 attr->log_max_ft_sampler_num = 0; 1217 return rc; 1218 } 1219 attr->log_max_ft_sampler_num = MLX5_GET 1220 (flow_table_nic_cap, hcattr, 1221 flow_table_properties_nic_receive.log_max_ft_sampler_num); 1222 attr->flow.tunnel_header_0_1 = MLX5_GET 1223 (flow_table_nic_cap, hcattr, 1224 ft_field_support_2_nic_receive.tunnel_header_0_1); 1225 attr->flow.tunnel_header_2_3 = MLX5_GET 1226 (flow_table_nic_cap, hcattr, 1227 ft_field_support_2_nic_receive.tunnel_header_2_3); 1228 attr->modify_outer_ip_ecn = MLX5_GET 1229 (flow_table_nic_cap, hcattr, 1230 ft_header_modify_nic_receive.outer_ip_ecn); 1231 attr->set_reg_c = 0xff; 1232 if (attr->nic_flow_table) { 1233 #define GET_RX_REG_X_BITS \ 1234 MLX5_GET(flow_table_nic_cap, hcattr, \ 1235 ft_header_modify_nic_receive.metadata_reg_c_x) 1236 #define GET_TX_REG_X_BITS \ 1237 MLX5_GET(flow_table_nic_cap, hcattr, \ 1238 ft_header_modify_nic_transmit.metadata_reg_c_x) 1239 1240 uint32_t tx_reg, rx_reg; 1241 1242 tx_reg = GET_TX_REG_X_BITS; 1243 rx_reg = GET_RX_REG_X_BITS; 1244 attr->set_reg_c &= (rx_reg & tx_reg); 1245 1246 #undef GET_RX_REG_X_BITS 1247 #undef GET_TX_REG_X_BITS 1248 } 1249 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 1250 attr->inner_ipv4_ihl = MLX5_GET 1251 (flow_table_nic_cap, hcattr, 1252 ft_field_support_2_nic_receive.inner_ipv4_ihl); 1253 attr->outer_ipv4_ihl = MLX5_GET 1254 (flow_table_nic_cap, hcattr, 1255 ft_field_support_2_nic_receive.outer_ipv4_ihl); 1256 attr->lag_rx_port_affinity = MLX5_GET 1257 (flow_table_nic_cap, hcattr, 1258 ft_field_support_2_nic_receive.lag_rx_port_affinity); 1259 /* Query HCA offloads for Ethernet protocol. */ 1260 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1261 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 1262 MLX5_HCA_CAP_OPMOD_GET_CUR); 1263 if (!hcattr) { 1264 attr->eth_net_offloads = 0; 1265 return rc; 1266 } 1267 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 1268 hcattr, wqe_vlan_insert); 1269 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 1270 hcattr, csum_cap); 1271 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 1272 hcattr, vlan_cap); 1273 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1274 lro_cap); 1275 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1276 hcattr, max_lso_cap); 1277 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1278 hcattr, scatter_fcs); 1279 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1280 hcattr, tunnel_lro_gre); 1281 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1282 hcattr, tunnel_lro_vxlan); 1283 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1284 hcattr, swp); 1285 attr->tunnel_stateless_gre = 1286 MLX5_GET(per_protocol_networking_offload_caps, 1287 hcattr, tunnel_stateless_gre); 1288 attr->tunnel_stateless_vxlan = 1289 MLX5_GET(per_protocol_networking_offload_caps, 1290 hcattr, tunnel_stateless_vxlan); 1291 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1292 hcattr, swp_csum); 1293 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1294 hcattr, swp_lso); 1295 attr->lro_max_msg_sz_mode = MLX5_GET 1296 (per_protocol_networking_offload_caps, 1297 hcattr, lro_max_msg_sz_mode); 1298 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1299 attr->lro_timer_supported_periods[i] = 1300 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1301 lro_timer_supported_periods[i]); 1302 } 1303 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1304 hcattr, lro_min_mss_size); 1305 attr->tunnel_stateless_geneve_rx = 1306 MLX5_GET(per_protocol_networking_offload_caps, 1307 hcattr, tunnel_stateless_geneve_rx); 1308 attr->geneve_max_opt_len = 1309 MLX5_GET(per_protocol_networking_offload_caps, 1310 hcattr, max_geneve_opt_len); 1311 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1312 hcattr, wqe_inline_mode); 1313 attr->tunnel_stateless_gtp = MLX5_GET 1314 (per_protocol_networking_offload_caps, 1315 hcattr, tunnel_stateless_gtp); 1316 attr->tunnel_stateless_vxlan_gpe_nsh = MLX5_GET 1317 (per_protocol_networking_offload_caps, 1318 hcattr, tunnel_stateless_vxlan_gpe_nsh); 1319 attr->rss_ind_tbl_cap = MLX5_GET 1320 (per_protocol_networking_offload_caps, 1321 hcattr, rss_ind_tbl_cap); 1322 attr->multi_pkt_send_wqe = MLX5_GET 1323 (per_protocol_networking_offload_caps, 1324 hcattr, multi_pkt_send_wqe); 1325 attr->enhanced_multi_pkt_send_wqe = MLX5_GET 1326 (per_protocol_networking_offload_caps, 1327 hcattr, enhanced_multi_pkt_send_wqe); 1328 if (attr->wqe_based_flow_table_sup) { 1329 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1330 MLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE | 1331 MLX5_HCA_CAP_OPMOD_GET_CUR); 1332 if (!hcattr) { 1333 DRV_LOG(DEBUG, "Failed to query WQE Based Flow table capabilities"); 1334 return rc; 1335 } 1336 attr->max_header_modify_pattern_length = MLX5_GET(wqe_based_flow_table_cap, 1337 hcattr, 1338 max_header_modify_pattern_length); 1339 } 1340 /* Query HCA attribute for ROCE. */ 1341 if (attr->roce) { 1342 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1343 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1344 MLX5_HCA_CAP_OPMOD_GET_CUR); 1345 if (!hcattr) { 1346 DRV_LOG(DEBUG, 1347 "Failed to query devx HCA ROCE capabilities"); 1348 return rc; 1349 } 1350 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1351 } 1352 if (attr->eth_virt && 1353 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1354 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1355 if (rc) { 1356 attr->eth_virt = 0; 1357 goto error; 1358 } 1359 } 1360 if (attr->eswitch_manager) { 1361 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1362 MLX5_SET_HCA_CAP_OP_MOD_ESW | 1363 MLX5_HCA_CAP_OPMOD_GET_CUR); 1364 if (!hcattr) 1365 return rc; 1366 attr->esw_mgr_vport_id_valid = 1367 MLX5_GET(esw_cap, hcattr, 1368 esw_manager_vport_number_valid); 1369 attr->esw_mgr_vport_id = 1370 MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); 1371 } 1372 if (attr->eswitch_manager) { 1373 uint32_t esw_reg; 1374 1375 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1376 MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE | 1377 MLX5_HCA_CAP_OPMOD_GET_CUR); 1378 if (!hcattr) 1379 return rc; 1380 esw_reg = MLX5_GET(flow_table_esw_cap, hcattr, 1381 ft_header_modify_esw_fdb.metadata_reg_c_x); 1382 attr->set_reg_c &= esw_reg; 1383 } 1384 return 0; 1385 error: 1386 rc = (rc > 0) ? -rc : rc; 1387 return rc; 1388 } 1389 1390 /** 1391 * Query TIS transport domain from QP verbs object using DevX API. 1392 * 1393 * @param[in] qp 1394 * Pointer to verbs QP returned by ibv_create_qp . 1395 * @param[in] tis_num 1396 * TIS number of TIS to query. 1397 * @param[out] tis_td 1398 * Pointer to TIS transport domain variable, to be set by the routine. 1399 * 1400 * @return 1401 * 0 on success, a negative value otherwise. 1402 */ 1403 int 1404 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1405 uint32_t *tis_td) 1406 { 1407 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1408 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1409 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1410 int rc; 1411 void *tis_ctx; 1412 1413 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1414 MLX5_SET(query_tis_in, in, tisn, tis_num); 1415 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1416 if (rc) { 1417 DRV_LOG(ERR, "Failed to query QP using DevX"); 1418 return -rc; 1419 }; 1420 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1421 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1422 return 0; 1423 #else 1424 (void)qp; 1425 (void)tis_num; 1426 (void)tis_td; 1427 return -ENOTSUP; 1428 #endif 1429 } 1430 1431 /** 1432 * Fill WQ data for DevX API command. 1433 * Utility function for use when creating DevX objects containing a WQ. 1434 * 1435 * @param[in] wq_ctx 1436 * Pointer to WQ context to fill with data. 1437 * @param [in] wq_attr 1438 * Pointer to WQ attributes structure to fill in WQ context. 1439 */ 1440 static void 1441 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1442 { 1443 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1444 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1445 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1446 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1447 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1448 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1449 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1450 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1451 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1452 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1453 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1454 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1455 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1456 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1457 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1458 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1459 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1460 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1461 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1462 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1463 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1464 wq_attr->log_hairpin_num_packets); 1465 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1466 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1467 wq_attr->single_wqe_log_num_of_strides); 1468 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1469 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1470 wq_attr->single_stride_log_num_of_bytes); 1471 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1472 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1473 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1474 } 1475 1476 /** 1477 * Create RQ using DevX API. 1478 * 1479 * @param[in] ctx 1480 * Context returned from mlx5 open_device() glue function. 1481 * @param [in] rq_attr 1482 * Pointer to create RQ attributes structure. 1483 * @param [in] socket 1484 * CPU socket ID for allocations. 1485 * 1486 * @return 1487 * The DevX object created, NULL otherwise and rte_errno is set. 1488 */ 1489 struct mlx5_devx_obj * 1490 mlx5_devx_cmd_create_rq(void *ctx, 1491 struct mlx5_devx_create_rq_attr *rq_attr, 1492 int socket) 1493 { 1494 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1495 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1496 void *rq_ctx, *wq_ctx; 1497 struct mlx5_devx_wq_attr *wq_attr; 1498 struct mlx5_devx_obj *rq = NULL; 1499 1500 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1501 if (!rq) { 1502 DRV_LOG(ERR, "Failed to allocate RQ data"); 1503 rte_errno = ENOMEM; 1504 return NULL; 1505 } 1506 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1507 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1508 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1509 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1510 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1511 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1512 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1513 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1514 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1515 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1516 MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type); 1517 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1518 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1519 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1520 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1521 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1522 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1523 wq_attr = &rq_attr->wq_attr; 1524 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1525 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1526 out, sizeof(out)); 1527 if (!rq->obj) { 1528 DEVX_DRV_LOG(ERR, out, "create RQ", NULL, 0); 1529 mlx5_free(rq); 1530 return NULL; 1531 } 1532 rq->id = MLX5_GET(create_rq_out, out, rqn); 1533 return rq; 1534 } 1535 1536 /** 1537 * Modify RQ using DevX API. 1538 * 1539 * @param[in] rq 1540 * Pointer to RQ object structure. 1541 * @param [in] rq_attr 1542 * Pointer to modify RQ attributes structure. 1543 * 1544 * @return 1545 * 0 on success, a negative errno value otherwise and rte_errno is set. 1546 */ 1547 int 1548 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1549 struct mlx5_devx_modify_rq_attr *rq_attr) 1550 { 1551 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1552 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1553 void *rq_ctx, *wq_ctx; 1554 int ret; 1555 1556 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1557 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1558 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1559 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1560 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1561 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1562 if (rq_attr->modify_bitmask & 1563 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1564 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1565 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1566 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1567 if (rq_attr->modify_bitmask & 1568 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1569 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1570 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1571 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1572 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1573 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1574 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1575 } 1576 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1577 out, sizeof(out)); 1578 if (ret) { 1579 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1580 rte_errno = errno; 1581 return -errno; 1582 } 1583 return ret; 1584 } 1585 1586 /** 1587 * Create RMP using DevX API. 1588 * 1589 * @param[in] ctx 1590 * Context returned from mlx5 open_device() glue function. 1591 * @param [in] rmp_attr 1592 * Pointer to create RMP attributes structure. 1593 * @param [in] socket 1594 * CPU socket ID for allocations. 1595 * 1596 * @return 1597 * The DevX object created, NULL otherwise and rte_errno is set. 1598 */ 1599 struct mlx5_devx_obj * 1600 mlx5_devx_cmd_create_rmp(void *ctx, 1601 struct mlx5_devx_create_rmp_attr *rmp_attr, 1602 int socket) 1603 { 1604 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0}; 1605 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0}; 1606 void *rmp_ctx, *wq_ctx; 1607 struct mlx5_devx_wq_attr *wq_attr; 1608 struct mlx5_devx_obj *rmp = NULL; 1609 1610 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket); 1611 if (!rmp) { 1612 DRV_LOG(ERR, "Failed to allocate RMP data"); 1613 rte_errno = ENOMEM; 1614 return NULL; 1615 } 1616 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP); 1617 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx); 1618 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state); 1619 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe, 1620 rmp_attr->basic_cyclic_rcv_wqe); 1621 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq); 1622 wq_attr = &rmp_attr->wq_attr; 1623 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1624 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1625 sizeof(out)); 1626 if (!rmp->obj) { 1627 DEVX_DRV_LOG(ERR, out, "create RMP", NULL, 0); 1628 mlx5_free(rmp); 1629 return NULL; 1630 } 1631 rmp->id = MLX5_GET(create_rmp_out, out, rmpn); 1632 return rmp; 1633 } 1634 1635 /* 1636 * Create TIR using DevX API. 1637 * 1638 * @param[in] ctx 1639 * Context returned from mlx5 open_device() glue function. 1640 * @param [in] tir_attr 1641 * Pointer to TIR attributes structure. 1642 * 1643 * @return 1644 * The DevX object created, NULL otherwise and rte_errno is set. 1645 */ 1646 struct mlx5_devx_obj * 1647 mlx5_devx_cmd_create_tir(void *ctx, 1648 struct mlx5_devx_tir_attr *tir_attr) 1649 { 1650 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1651 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1652 void *tir_ctx, *outer, *inner, *rss_key; 1653 struct mlx5_devx_obj *tir = NULL; 1654 1655 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1656 if (!tir) { 1657 DRV_LOG(ERR, "Failed to allocate TIR data"); 1658 rte_errno = ENOMEM; 1659 return NULL; 1660 } 1661 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1662 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1663 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1664 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1665 tir_attr->lro_timeout_period_usecs); 1666 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1667 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1668 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1669 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1670 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1671 tir_attr->tunneled_offload_en); 1672 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1673 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1674 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1675 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1676 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1677 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1678 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1679 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1680 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1681 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1682 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1683 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1684 tir_attr->rx_hash_field_selector_outer.selected_fields); 1685 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1686 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1687 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1688 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1689 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1690 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1691 tir_attr->rx_hash_field_selector_inner.selected_fields); 1692 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1693 out, sizeof(out)); 1694 if (!tir->obj) { 1695 DEVX_DRV_LOG(ERR, out, "create TIR", NULL, 0); 1696 mlx5_free(tir); 1697 return NULL; 1698 } 1699 tir->id = MLX5_GET(create_tir_out, out, tirn); 1700 return tir; 1701 } 1702 1703 /** 1704 * Modify TIR using DevX API. 1705 * 1706 * @param[in] tir 1707 * Pointer to TIR DevX object structure. 1708 * @param [in] modify_tir_attr 1709 * Pointer to TIR modification attributes structure. 1710 * 1711 * @return 1712 * 0 on success, a negative errno value otherwise and rte_errno is set. 1713 */ 1714 int 1715 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1716 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1717 { 1718 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1719 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1720 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1721 void *tir_ctx; 1722 int ret; 1723 1724 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1725 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1726 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1727 modify_tir_attr->modify_bitmask); 1728 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1729 if (modify_tir_attr->modify_bitmask & 1730 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1731 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1732 tir_attr->lro_timeout_period_usecs); 1733 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1734 tir_attr->lro_enable_mask); 1735 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1736 tir_attr->lro_max_msg_sz); 1737 } 1738 if (modify_tir_attr->modify_bitmask & 1739 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1740 MLX5_SET(tirc, tir_ctx, indirect_table, 1741 tir_attr->indirect_table); 1742 if (modify_tir_attr->modify_bitmask & 1743 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1744 int i; 1745 void *outer, *inner; 1746 1747 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1748 tir_attr->rx_hash_symmetric); 1749 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1750 for (i = 0; i < 10; i++) { 1751 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1752 tir_attr->rx_hash_toeplitz_key[i]); 1753 } 1754 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1755 rx_hash_field_selector_outer); 1756 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1757 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1758 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1759 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1760 MLX5_SET 1761 (rx_hash_field_select, outer, selected_fields, 1762 tir_attr->rx_hash_field_selector_outer.selected_fields); 1763 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1764 rx_hash_field_selector_inner); 1765 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1766 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1767 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1768 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1769 MLX5_SET 1770 (rx_hash_field_select, inner, selected_fields, 1771 tir_attr->rx_hash_field_selector_inner.selected_fields); 1772 } 1773 if (modify_tir_attr->modify_bitmask & 1774 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1775 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1776 } 1777 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1778 out, sizeof(out)); 1779 if (ret) { 1780 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1781 rte_errno = errno; 1782 return -errno; 1783 } 1784 return ret; 1785 } 1786 1787 /** 1788 * Create RQT using DevX API. 1789 * 1790 * @param[in] ctx 1791 * Context returned from mlx5 open_device() glue function. 1792 * @param [in] rqt_attr 1793 * Pointer to RQT attributes structure. 1794 * 1795 * @return 1796 * The DevX object created, NULL otherwise and rte_errno is set. 1797 */ 1798 struct mlx5_devx_obj * 1799 mlx5_devx_cmd_create_rqt(void *ctx, 1800 struct mlx5_devx_rqt_attr *rqt_attr) 1801 { 1802 uint32_t *in = NULL; 1803 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1804 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1805 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1806 void *rqt_ctx; 1807 struct mlx5_devx_obj *rqt = NULL; 1808 int i; 1809 1810 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1811 if (!in) { 1812 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1813 rte_errno = ENOMEM; 1814 return NULL; 1815 } 1816 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1817 if (!rqt) { 1818 DRV_LOG(ERR, "Failed to allocate RQT data"); 1819 rte_errno = ENOMEM; 1820 mlx5_free(in); 1821 return NULL; 1822 } 1823 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1824 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1825 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1826 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1827 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1828 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1829 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1830 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1831 mlx5_free(in); 1832 if (!rqt->obj) { 1833 DEVX_DRV_LOG(ERR, out, "create RQT", NULL, 0); 1834 mlx5_free(rqt); 1835 return NULL; 1836 } 1837 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1838 return rqt; 1839 } 1840 1841 /** 1842 * Modify RQT using DevX API. 1843 * 1844 * @param[in] rqt 1845 * Pointer to RQT DevX object structure. 1846 * @param [in] rqt_attr 1847 * Pointer to RQT attributes structure. 1848 * 1849 * @return 1850 * 0 on success, a negative errno value otherwise and rte_errno is set. 1851 */ 1852 int 1853 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1854 struct mlx5_devx_rqt_attr *rqt_attr) 1855 { 1856 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1857 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1858 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1859 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1860 void *rqt_ctx; 1861 int i; 1862 int ret; 1863 1864 if (!in) { 1865 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1866 rte_errno = ENOMEM; 1867 return -ENOMEM; 1868 } 1869 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1870 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1871 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1872 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1873 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1874 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1875 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1876 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1877 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1878 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1879 mlx5_free(in); 1880 if (ret) { 1881 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1882 rte_errno = errno; 1883 return -rte_errno; 1884 } 1885 return ret; 1886 } 1887 1888 /** 1889 * Create SQ using DevX API. 1890 * 1891 * @param[in] ctx 1892 * Context returned from mlx5 open_device() glue function. 1893 * @param [in] sq_attr 1894 * Pointer to SQ attributes structure. 1895 * @param [in] socket 1896 * CPU socket ID for allocations. 1897 * 1898 * @return 1899 * The DevX object created, NULL otherwise and rte_errno is set. 1900 **/ 1901 struct mlx5_devx_obj * 1902 mlx5_devx_cmd_create_sq(void *ctx, 1903 struct mlx5_devx_create_sq_attr *sq_attr) 1904 { 1905 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1906 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1907 void *sq_ctx; 1908 void *wq_ctx; 1909 struct mlx5_devx_wq_attr *wq_attr; 1910 struct mlx5_devx_obj *sq = NULL; 1911 1912 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1913 if (!sq) { 1914 DRV_LOG(ERR, "Failed to allocate SQ data"); 1915 rte_errno = ENOMEM; 1916 return NULL; 1917 } 1918 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1919 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1920 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1921 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1922 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1923 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1924 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1925 sq_attr->allow_multi_pkt_send_wqe); 1926 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1927 sq_attr->min_wqe_inline_mode); 1928 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1929 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1930 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1931 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1932 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1933 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1934 MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type); 1935 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1936 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1937 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1938 sq_attr->packet_pacing_rate_limit_index); 1939 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1940 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1941 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1942 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1943 wq_attr = &sq_attr->wq_attr; 1944 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1945 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1946 out, sizeof(out)); 1947 if (!sq->obj) { 1948 DEVX_DRV_LOG(ERR, out, "create SQ", NULL, 0); 1949 mlx5_free(sq); 1950 return NULL; 1951 } 1952 sq->id = MLX5_GET(create_sq_out, out, sqn); 1953 return sq; 1954 } 1955 1956 /** 1957 * Modify SQ using DevX API. 1958 * 1959 * @param[in] sq 1960 * Pointer to SQ object structure. 1961 * @param [in] sq_attr 1962 * Pointer to SQ attributes structure. 1963 * 1964 * @return 1965 * 0 on success, a negative errno value otherwise and rte_errno is set. 1966 */ 1967 int 1968 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1969 struct mlx5_devx_modify_sq_attr *sq_attr) 1970 { 1971 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1972 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1973 void *sq_ctx; 1974 int ret; 1975 1976 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1977 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1978 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1979 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1980 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1981 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1982 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1983 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1984 out, sizeof(out)); 1985 if (ret) { 1986 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1987 rte_errno = errno; 1988 return -rte_errno; 1989 } 1990 return ret; 1991 } 1992 1993 /** 1994 * Create TIS using DevX API. 1995 * 1996 * @param[in] ctx 1997 * Context returned from mlx5 open_device() glue function. 1998 * @param [in] tis_attr 1999 * Pointer to TIS attributes structure. 2000 * 2001 * @return 2002 * The DevX object created, NULL otherwise and rte_errno is set. 2003 */ 2004 struct mlx5_devx_obj * 2005 mlx5_devx_cmd_create_tis(void *ctx, 2006 struct mlx5_devx_tis_attr *tis_attr) 2007 { 2008 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 2009 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 2010 struct mlx5_devx_obj *tis = NULL; 2011 void *tis_ctx; 2012 2013 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 2014 if (!tis) { 2015 DRV_LOG(ERR, "Failed to allocate TIS object"); 2016 rte_errno = ENOMEM; 2017 return NULL; 2018 } 2019 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 2020 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 2021 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 2022 tis_attr->strict_lag_tx_port_affinity); 2023 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 2024 tis_attr->lag_tx_port_affinity); 2025 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 2026 MLX5_SET(tisc, tis_ctx, transport_domain, 2027 tis_attr->transport_domain); 2028 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2029 out, sizeof(out)); 2030 if (!tis->obj) { 2031 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 2032 mlx5_free(tis); 2033 return NULL; 2034 } 2035 tis->id = MLX5_GET(create_tis_out, out, tisn); 2036 return tis; 2037 } 2038 2039 /** 2040 * Create transport domain using DevX API. 2041 * 2042 * @param[in] ctx 2043 * Context returned from mlx5 open_device() glue function. 2044 * @return 2045 * The DevX object created, NULL otherwise and rte_errno is set. 2046 */ 2047 struct mlx5_devx_obj * 2048 mlx5_devx_cmd_create_td(void *ctx) 2049 { 2050 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 2051 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 2052 struct mlx5_devx_obj *td = NULL; 2053 2054 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 2055 if (!td) { 2056 DRV_LOG(ERR, "Failed to allocate TD object"); 2057 rte_errno = ENOMEM; 2058 return NULL; 2059 } 2060 MLX5_SET(alloc_transport_domain_in, in, opcode, 2061 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 2062 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2063 out, sizeof(out)); 2064 if (!td->obj) { 2065 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 2066 mlx5_free(td); 2067 return NULL; 2068 } 2069 td->id = MLX5_GET(alloc_transport_domain_out, out, 2070 transport_domain); 2071 return td; 2072 } 2073 2074 /** 2075 * Dump all flows to file. 2076 * 2077 * @param[in] fdb_domain 2078 * FDB domain. 2079 * @param[in] rx_domain 2080 * RX domain. 2081 * @param[in] tx_domain 2082 * TX domain. 2083 * @param[out] file 2084 * Pointer to file stream. 2085 * 2086 * @return 2087 * 0 on success, a negative value otherwise. 2088 */ 2089 int 2090 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 2091 void *rx_domain __rte_unused, 2092 void *tx_domain __rte_unused, FILE *file __rte_unused) 2093 { 2094 int ret = 0; 2095 2096 #ifdef HAVE_MLX5_DR_FLOW_DUMP 2097 if (fdb_domain) { 2098 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 2099 if (ret) 2100 return ret; 2101 } 2102 MLX5_ASSERT(rx_domain); 2103 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 2104 if (ret) 2105 return ret; 2106 MLX5_ASSERT(tx_domain); 2107 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 2108 #else 2109 ret = ENOTSUP; 2110 #endif 2111 return -ret; 2112 } 2113 2114 int 2115 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 2116 FILE *file __rte_unused) 2117 { 2118 int ret = 0; 2119 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 2120 if (rule_info) 2121 ret = mlx5_glue->dr_dump_rule(file, rule_info); 2122 #else 2123 ret = ENOTSUP; 2124 #endif 2125 return -ret; 2126 } 2127 2128 /* 2129 * Create CQ using DevX API. 2130 * 2131 * @param[in] ctx 2132 * Context returned from mlx5 open_device() glue function. 2133 * @param [in] attr 2134 * Pointer to CQ attributes structure. 2135 * 2136 * @return 2137 * The DevX object created, NULL otherwise and rte_errno is set. 2138 */ 2139 struct mlx5_devx_obj * 2140 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 2141 { 2142 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 2143 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 2144 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2145 sizeof(*cq_obj), 2146 0, SOCKET_ID_ANY); 2147 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 2148 2149 if (!cq_obj) { 2150 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 2151 rte_errno = ENOMEM; 2152 return NULL; 2153 } 2154 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 2155 if (attr->db_umem_valid) { 2156 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 2157 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 2158 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 2159 } else { 2160 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 2161 } 2162 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 2163 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 2164 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 2165 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 2166 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 2167 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2168 MLX5_SET(cqc, cqctx, log_page_size, 2169 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2170 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 2171 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 2172 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 2173 MLX5_SET(cqc, cqctx, cqe_comp_layout, !!attr->cqe_comp_layout); 2174 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 2175 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 2176 attr->mini_cqe_res_format_ext); 2177 if (attr->q_umem_valid) { 2178 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 2179 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 2180 MLX5_SET64(create_cq_in, in, cq_umem_offset, 2181 attr->q_umem_offset); 2182 } 2183 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2184 sizeof(out)); 2185 if (!cq_obj->obj) { 2186 DEVX_DRV_LOG(ERR, out, "create CQ", NULL, 0); 2187 mlx5_free(cq_obj); 2188 return NULL; 2189 } 2190 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 2191 return cq_obj; 2192 } 2193 2194 /** 2195 * Create VIRTQ using DevX API. 2196 * 2197 * @param[in] ctx 2198 * Context returned from mlx5 open_device() glue function. 2199 * @param [in] attr 2200 * Pointer to VIRTQ attributes structure. 2201 * 2202 * @return 2203 * The DevX object created, NULL otherwise and rte_errno is set. 2204 */ 2205 struct mlx5_devx_obj * 2206 mlx5_devx_cmd_create_virtq(void *ctx, 2207 struct mlx5_devx_virtq_attr *attr) 2208 { 2209 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2210 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2211 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2212 sizeof(*virtq_obj), 2213 0, SOCKET_ID_ANY); 2214 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2215 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2216 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2217 2218 if (!virtq_obj) { 2219 DRV_LOG(ERR, "Failed to allocate virtq data."); 2220 rte_errno = ENOMEM; 2221 return NULL; 2222 } 2223 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2224 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2225 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2226 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2227 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2228 attr->hw_available_index); 2229 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 2230 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2231 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2232 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2233 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2234 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2235 attr->virtio_version_1_0); 2236 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2237 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2238 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2239 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2240 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 2241 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2242 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 2243 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2244 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 2245 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 2246 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 2247 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 2248 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 2249 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 2250 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 2251 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 2252 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 2253 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 2254 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 2255 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 2256 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 2257 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 2258 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 2259 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2260 sizeof(out)); 2261 if (!virtq_obj->obj) { 2262 DEVX_DRV_LOG(ERR, out, "create VIRTQ", NULL, 0); 2263 mlx5_free(virtq_obj); 2264 return NULL; 2265 } 2266 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2267 return virtq_obj; 2268 } 2269 2270 /** 2271 * Modify VIRTQ using DevX API. 2272 * 2273 * @param[in] virtq_obj 2274 * Pointer to virtq object structure. 2275 * @param [in] attr 2276 * Pointer to modify virtq attributes structure. 2277 * 2278 * @return 2279 * 0 on success, a negative errno value otherwise and rte_errno is set. 2280 */ 2281 int 2282 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 2283 struct mlx5_devx_virtq_attr *attr) 2284 { 2285 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2286 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2287 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2288 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2289 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2290 int ret; 2291 2292 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2293 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 2294 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2295 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2296 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2297 MLX5_SET64(virtio_net_q, virtq, modify_field_select, 2298 attr->mod_fields_bitmap); 2299 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2300 if (!attr->mod_fields_bitmap) { 2301 DRV_LOG(ERR, "Failed to modify VIRTQ for no type set."); 2302 rte_errno = EINVAL; 2303 return -rte_errno; 2304 } 2305 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE) 2306 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 2307 if (attr->mod_fields_bitmap & 2308 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) { 2309 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 2310 attr->dirty_bitmap_mkey); 2311 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 2312 attr->dirty_bitmap_addr); 2313 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 2314 attr->dirty_bitmap_size); 2315 } 2316 if (attr->mod_fields_bitmap & 2317 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE) 2318 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 2319 attr->dirty_bitmap_dump_enable); 2320 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) { 2321 MLX5_SET(virtio_q, virtctx, queue_period_mode, 2322 attr->hw_latency_mode); 2323 MLX5_SET(virtio_q, virtctx, queue_period_us, 2324 attr->hw_max_latency_us); 2325 MLX5_SET(virtio_q, virtctx, queue_max_count, 2326 attr->hw_max_pending_comp); 2327 } 2328 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) { 2329 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2330 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2331 MLX5_SET64(virtio_q, virtctx, available_addr, 2332 attr->available_addr); 2333 } 2334 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX) 2335 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2336 attr->hw_available_index); 2337 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX) 2338 MLX5_SET16(virtio_net_q, virtq, hw_used_index, 2339 attr->hw_used_index); 2340 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE) 2341 MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type); 2342 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0) 2343 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2344 attr->virtio_version_1_0); 2345 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY) 2346 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2347 if (attr->mod_fields_bitmap & 2348 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) { 2349 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2350 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2351 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2352 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2353 } 2354 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) { 2355 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2356 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2357 } 2358 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 2359 out, sizeof(out)); 2360 if (ret) { 2361 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2362 rte_errno = errno; 2363 return -rte_errno; 2364 } 2365 return ret; 2366 } 2367 2368 /** 2369 * Query VIRTQ using DevX API. 2370 * 2371 * @param[in] virtq_obj 2372 * Pointer to virtq object structure. 2373 * @param [in/out] attr 2374 * Pointer to virtq attributes structure. 2375 * 2376 * @return 2377 * 0 on success, a negative errno value otherwise and rte_errno is set. 2378 */ 2379 int 2380 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 2381 struct mlx5_devx_virtq_attr *attr) 2382 { 2383 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2384 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 2385 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 2386 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 2387 int ret; 2388 2389 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2390 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2391 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2392 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2393 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2394 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2395 out, sizeof(out)); 2396 if (ret) { 2397 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2398 rte_errno = errno; 2399 return -errno; 2400 } 2401 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2402 hw_available_index); 2403 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2404 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2405 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2406 virtio_q_context.error_type); 2407 return ret; 2408 } 2409 2410 /** 2411 * Create QP using DevX API. 2412 * 2413 * @param[in] ctx 2414 * Context returned from mlx5 open_device() glue function. 2415 * @param [in] attr 2416 * Pointer to QP attributes structure. 2417 * 2418 * @return 2419 * The DevX object created, NULL otherwise and rte_errno is set. 2420 */ 2421 struct mlx5_devx_obj * 2422 mlx5_devx_cmd_create_qp(void *ctx, 2423 struct mlx5_devx_qp_attr *attr) 2424 { 2425 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2426 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2427 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2428 sizeof(*qp_obj), 2429 0, SOCKET_ID_ANY); 2430 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2431 2432 if (!qp_obj) { 2433 DRV_LOG(ERR, "Failed to allocate QP data."); 2434 rte_errno = ENOMEM; 2435 return NULL; 2436 } 2437 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2438 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2439 MLX5_SET(qpc, qpc, pd, attr->pd); 2440 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2441 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2442 if (attr->uar_index) { 2443 if (attr->mmo) { 2444 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2445 in, qpc_extension_and_pas_list); 2446 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2447 qpc_ext_and_pas_list, qpc_data_extension); 2448 2449 MLX5_SET(create_qp_in, in, qpc_ext, 1); 2450 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2451 } 2452 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2453 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2454 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2455 MLX5_SET(qpc, qpc, log_page_size, 2456 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2457 if (attr->num_of_send_wqbbs) { 2458 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs)); 2459 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2460 MLX5_SET(qpc, qpc, log_sq_size, 2461 rte_log2_u32(attr->num_of_send_wqbbs)); 2462 } else { 2463 MLX5_SET(qpc, qpc, no_sq, 1); 2464 } 2465 if (attr->num_of_receive_wqes) { 2466 MLX5_ASSERT(RTE_IS_POWER_OF_2( 2467 attr->num_of_receive_wqes)); 2468 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2469 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2470 MLX5_LOG_RQ_STRIDE_SHIFT); 2471 MLX5_SET(qpc, qpc, log_rq_size, 2472 rte_log2_u32(attr->num_of_receive_wqes)); 2473 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2474 } else { 2475 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2476 } 2477 if (attr->dbr_umem_valid) { 2478 MLX5_SET(qpc, qpc, dbr_umem_valid, 2479 attr->dbr_umem_valid); 2480 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2481 } 2482 if (attr->cd_master) 2483 MLX5_SET(qpc, qpc, cd_master, attr->cd_master); 2484 if (attr->cd_slave_send) 2485 MLX5_SET(qpc, qpc, cd_slave_send, attr->cd_slave_send); 2486 if (attr->cd_slave_recv) 2487 MLX5_SET(qpc, qpc, cd_slave_receive, attr->cd_slave_recv); 2488 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2489 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2490 attr->wq_umem_offset); 2491 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2492 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2493 } else { 2494 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2495 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2496 MLX5_SET(qpc, qpc, no_sq, 1); 2497 } 2498 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2499 sizeof(out)); 2500 if (!qp_obj->obj) { 2501 DEVX_DRV_LOG(ERR, out, "create QP", NULL, 0); 2502 mlx5_free(qp_obj); 2503 return NULL; 2504 } 2505 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2506 return qp_obj; 2507 } 2508 2509 /** 2510 * Modify QP using DevX API. 2511 * Currently supports only force loop-back QP. 2512 * 2513 * @param[in] qp 2514 * Pointer to QP object structure. 2515 * @param [in] qp_st_mod_op 2516 * The QP state modification operation. 2517 * @param [in] remote_qp_id 2518 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2519 * 2520 * @return 2521 * 0 on success, a negative errno value otherwise and rte_errno is set. 2522 */ 2523 int 2524 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2525 uint32_t remote_qp_id) 2526 { 2527 union { 2528 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2529 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2530 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2531 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)]; 2532 } in; 2533 union { 2534 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2535 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2536 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2537 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)]; 2538 } out; 2539 void *qpc; 2540 int ret; 2541 unsigned int inlen; 2542 unsigned int outlen; 2543 2544 memset(&in, 0, sizeof(in)); 2545 memset(&out, 0, sizeof(out)); 2546 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2547 switch (qp_st_mod_op) { 2548 case MLX5_CMD_OP_RST2INIT_QP: 2549 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2550 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2551 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2552 MLX5_SET(qpc, qpc, rre, 1); 2553 MLX5_SET(qpc, qpc, rwe, 1); 2554 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2555 inlen = sizeof(in.rst2init); 2556 outlen = sizeof(out.rst2init); 2557 break; 2558 case MLX5_CMD_OP_INIT2RTR_QP: 2559 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2560 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2561 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2562 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2563 MLX5_SET(qpc, qpc, mtu, 1); 2564 MLX5_SET(qpc, qpc, log_msg_max, 30); 2565 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2566 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2567 inlen = sizeof(in.init2rtr); 2568 outlen = sizeof(out.init2rtr); 2569 break; 2570 case MLX5_CMD_OP_RTR2RTS_QP: 2571 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2572 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2573 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16); 2574 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2575 MLX5_SET(qpc, qpc, retry_count, 7); 2576 MLX5_SET(qpc, qpc, rnr_retry, 7); 2577 inlen = sizeof(in.rtr2rts); 2578 outlen = sizeof(out.rtr2rts); 2579 break; 2580 case MLX5_CMD_OP_QP_2RST: 2581 MLX5_SET(2rst_qp_in, &in, qpn, qp->id); 2582 inlen = sizeof(in.qp2rst); 2583 outlen = sizeof(out.qp2rst); 2584 break; 2585 default: 2586 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2587 qp_st_mod_op); 2588 rte_errno = EINVAL; 2589 return -rte_errno; 2590 } 2591 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2592 if (ret) { 2593 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2594 rte_errno = errno; 2595 return -rte_errno; 2596 } 2597 return ret; 2598 } 2599 2600 struct mlx5_devx_obj * 2601 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2602 { 2603 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2604 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2605 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2606 sizeof(*couners_obj), 0, 2607 SOCKET_ID_ANY); 2608 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2609 2610 if (!couners_obj) { 2611 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2612 rte_errno = ENOMEM; 2613 return NULL; 2614 } 2615 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2616 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2617 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2618 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2619 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2620 sizeof(out)); 2621 if (!couners_obj->obj) { 2622 DEVX_DRV_LOG(ERR, out, "create virtio queue counters Obj", NULL, 2623 0); 2624 mlx5_free(couners_obj); 2625 return NULL; 2626 } 2627 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2628 return couners_obj; 2629 } 2630 2631 int 2632 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2633 struct mlx5_devx_virtio_q_couners_attr *attr) 2634 { 2635 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2636 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2637 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2638 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2639 virtio_q_counters); 2640 int ret; 2641 2642 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2643 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2644 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2645 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2646 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2647 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2648 sizeof(out)); 2649 if (ret) { 2650 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2651 rte_errno = errno; 2652 return -errno; 2653 } 2654 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2655 received_desc); 2656 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2657 completed_desc); 2658 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2659 error_cqes); 2660 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2661 bad_desc_errors); 2662 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2663 exceed_max_chain); 2664 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2665 invalid_buffer); 2666 return ret; 2667 } 2668 2669 /** 2670 * Create general object of type FLOW_HIT_ASO using DevX API. 2671 * 2672 * @param[in] ctx 2673 * Context returned from mlx5 open_device() glue function. 2674 * @param [in] pd 2675 * PD value to associate the FLOW_HIT_ASO object with. 2676 * 2677 * @return 2678 * The DevX object created, NULL otherwise and rte_errno is set. 2679 */ 2680 struct mlx5_devx_obj * 2681 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2682 { 2683 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2684 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2685 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2686 void *ptr = NULL; 2687 2688 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2689 0, SOCKET_ID_ANY); 2690 if (!flow_hit_aso_obj) { 2691 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2692 rte_errno = ENOMEM; 2693 return NULL; 2694 } 2695 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2696 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2697 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2698 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2699 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2700 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2701 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2702 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2703 out, sizeof(out)); 2704 if (!flow_hit_aso_obj->obj) { 2705 DEVX_DRV_LOG(ERR, out, "create FLOW_HIT_ASO", NULL, 0); 2706 mlx5_free(flow_hit_aso_obj); 2707 return NULL; 2708 } 2709 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2710 return flow_hit_aso_obj; 2711 } 2712 2713 /* 2714 * Create PD using DevX API. 2715 * 2716 * @param[in] ctx 2717 * Context returned from mlx5 open_device() glue function. 2718 * 2719 * @return 2720 * The DevX object created, NULL otherwise and rte_errno is set. 2721 */ 2722 struct mlx5_devx_obj * 2723 mlx5_devx_cmd_alloc_pd(void *ctx) 2724 { 2725 struct mlx5_devx_obj *ppd = 2726 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2727 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2728 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2729 2730 if (!ppd) { 2731 DRV_LOG(ERR, "Failed to allocate PD data."); 2732 rte_errno = ENOMEM; 2733 return NULL; 2734 } 2735 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2736 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2737 out, sizeof(out)); 2738 if (!ppd->obj) { 2739 mlx5_free(ppd); 2740 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2741 rte_errno = errno; 2742 return NULL; 2743 } 2744 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2745 return ppd; 2746 } 2747 2748 /** 2749 * Create general object of type FLOW_METER_ASO using DevX API. 2750 * 2751 * @param[in] ctx 2752 * Context returned from mlx5 open_device() glue function. 2753 * @param [in] pd 2754 * PD value to associate the FLOW_METER_ASO object with. 2755 * @param [in] log_obj_size 2756 * log_obj_size define to allocate number of 2 * meters 2757 * in one FLOW_METER_ASO object. 2758 * 2759 * @return 2760 * The DevX object created, NULL otherwise and rte_errno is set. 2761 */ 2762 struct mlx5_devx_obj * 2763 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2764 uint32_t log_obj_size) 2765 { 2766 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2767 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2768 struct mlx5_devx_obj *flow_meter_aso_obj; 2769 void *ptr; 2770 2771 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2772 sizeof(*flow_meter_aso_obj), 2773 0, SOCKET_ID_ANY); 2774 if (!flow_meter_aso_obj) { 2775 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2776 rte_errno = ENOMEM; 2777 return NULL; 2778 } 2779 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2780 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2781 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2782 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2783 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2784 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2785 log_obj_size); 2786 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2787 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2788 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2789 ctx, in, sizeof(in), 2790 out, sizeof(out)); 2791 if (!flow_meter_aso_obj->obj) { 2792 DEVX_DRV_LOG(ERR, out, "create FLOW_METTER_ASO", NULL, 0); 2793 mlx5_free(flow_meter_aso_obj); 2794 return NULL; 2795 } 2796 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2797 out, obj_id); 2798 return flow_meter_aso_obj; 2799 } 2800 2801 /* 2802 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2803 * 2804 * @param[in] ctx 2805 * Context returned from mlx5 open_device() glue function. 2806 * @param [in] pd 2807 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2808 * @param [in] log_obj_size 2809 * log_obj_size to allocate its power of 2 * objects 2810 * in one CONN_TRACK_OFFLOAD bulk allocation. 2811 * 2812 * @return 2813 * The DevX object created, NULL otherwise and rte_errno is set. 2814 */ 2815 struct mlx5_devx_obj * 2816 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2817 uint32_t log_obj_size) 2818 { 2819 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2820 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2821 struct mlx5_devx_obj *ct_aso_obj; 2822 void *ptr; 2823 2824 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2825 0, SOCKET_ID_ANY); 2826 if (!ct_aso_obj) { 2827 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2828 rte_errno = ENOMEM; 2829 return NULL; 2830 } 2831 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2832 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2833 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2834 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2835 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2836 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2837 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2838 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2839 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2840 out, sizeof(out)); 2841 if (!ct_aso_obj->obj) { 2842 DEVX_DRV_LOG(ERR, out, "create CONN_TRACK_OFFLOAD", NULL, 0); 2843 mlx5_free(ct_aso_obj); 2844 return NULL; 2845 } 2846 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2847 return ct_aso_obj; 2848 } 2849 2850 /** 2851 * Create general object of type GENEVE TLV option using DevX API. 2852 * 2853 * @param[in] ctx 2854 * Context returned from mlx5 open_device() glue function. 2855 * @param [in] class 2856 * TLV option variable value of class 2857 * @param [in] type 2858 * TLV option variable value of type 2859 * @param [in] len 2860 * TLV option variable value of len 2861 * 2862 * @return 2863 * The DevX object created, NULL otherwise and rte_errno is set. 2864 */ 2865 struct mlx5_devx_obj * 2866 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2867 uint16_t class, uint8_t type, uint8_t len) 2868 { 2869 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2870 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2871 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2872 sizeof(*geneve_tlv_opt_obj), 2873 0, SOCKET_ID_ANY); 2874 2875 if (!geneve_tlv_opt_obj) { 2876 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2877 rte_errno = ENOMEM; 2878 return NULL; 2879 } 2880 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2881 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2882 geneve_tlv_opt); 2883 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2884 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2885 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2886 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2887 MLX5_SET(geneve_tlv_option, opt, option_class, 2888 rte_be_to_cpu_16(class)); 2889 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2890 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2891 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2892 sizeof(in), out, sizeof(out)); 2893 if (!geneve_tlv_opt_obj->obj) { 2894 DEVX_DRV_LOG(ERR, out, "create GENEVE TLV", NULL, 0); 2895 mlx5_free(geneve_tlv_opt_obj); 2896 return NULL; 2897 } 2898 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2899 return geneve_tlv_opt_obj; 2900 } 2901 2902 int 2903 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2904 { 2905 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2906 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2907 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2908 int rc; 2909 void *rq_ctx; 2910 2911 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2912 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2913 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2914 if (rc) { 2915 rte_errno = errno; 2916 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2917 "rc = %d, errno = %d.", rc, errno); 2918 return -rc; 2919 }; 2920 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2921 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2922 return 0; 2923 #else 2924 (void)wq; 2925 (void)counter_set_id; 2926 return -ENOTSUP; 2927 #endif 2928 } 2929 2930 /* 2931 * Allocate queue counters via devx interface. 2932 * 2933 * @param[in] ctx 2934 * Context returned from mlx5 open_device() glue function. 2935 * 2936 * @return 2937 * Pointer to counter object on success, a NULL value otherwise and 2938 * rte_errno is set. 2939 */ 2940 struct mlx5_devx_obj * 2941 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2942 { 2943 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2944 SOCKET_ID_ANY); 2945 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2946 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2947 2948 if (!dcs) { 2949 rte_errno = ENOMEM; 2950 return NULL; 2951 } 2952 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2953 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2954 sizeof(out)); 2955 if (!dcs->obj) { 2956 DEVX_DRV_LOG(DEBUG, out, "create q counter set", NULL, 0); 2957 mlx5_free(dcs); 2958 return NULL; 2959 } 2960 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2961 return dcs; 2962 } 2963 2964 /** 2965 * Query queue counters values. 2966 * 2967 * @param[in] dcs 2968 * devx object of the queue counter set. 2969 * @param[in] clear 2970 * Whether hardware should clear the counters after the query or not. 2971 * @param[out] out_of_buffers 2972 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2973 * 2974 * @return 2975 * 0 on success, a negative value otherwise. 2976 */ 2977 int 2978 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2979 uint32_t *out_of_buffers) 2980 { 2981 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2982 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2983 int rc; 2984 2985 MLX5_SET(query_q_counter_in, in, opcode, 2986 MLX5_CMD_OP_QUERY_Q_COUNTER); 2987 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2988 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2989 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2990 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2991 sizeof(out)); 2992 if (rc) { 2993 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2994 rte_errno = rc; 2995 return -rc; 2996 } 2997 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2998 return 0; 2999 } 3000 3001 /** 3002 * Create general object of type DEK using DevX API. 3003 * 3004 * @param[in] ctx 3005 * Context returned from mlx5 open_device() glue function. 3006 * @param [in] attr 3007 * Pointer to DEK attributes structure. 3008 * 3009 * @return 3010 * The DevX object created, NULL otherwise and rte_errno is set. 3011 */ 3012 struct mlx5_devx_obj * 3013 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 3014 { 3015 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 3016 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3017 struct mlx5_devx_obj *dek_obj = NULL; 3018 void *ptr = NULL, *key_addr = NULL; 3019 3020 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 3021 0, SOCKET_ID_ANY); 3022 if (dek_obj == NULL) { 3023 DRV_LOG(ERR, "Failed to allocate DEK object data"); 3024 rte_errno = ENOMEM; 3025 return NULL; 3026 } 3027 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 3028 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3029 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3030 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3031 MLX5_GENERAL_OBJ_TYPE_DEK); 3032 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 3033 MLX5_SET(dek, ptr, key_size, attr->key_size); 3034 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 3035 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 3036 MLX5_SET(dek, ptr, pd, attr->pd); 3037 MLX5_SET64(dek, ptr, opaque, attr->opaque); 3038 key_addr = MLX5_ADDR_OF(dek, ptr, key); 3039 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 3040 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3041 out, sizeof(out)); 3042 if (dek_obj->obj == NULL) { 3043 DEVX_DRV_LOG(ERR, out, "create DEK", NULL, 0); 3044 mlx5_free(dek_obj); 3045 return NULL; 3046 } 3047 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3048 return dek_obj; 3049 } 3050 3051 /** 3052 * Create general object of type IMPORT_KEK using DevX API. 3053 * 3054 * @param[in] ctx 3055 * Context returned from mlx5 open_device() glue function. 3056 * @param [in] attr 3057 * Pointer to IMPORT_KEK attributes structure. 3058 * 3059 * @return 3060 * The DevX object created, NULL otherwise and rte_errno is set. 3061 */ 3062 struct mlx5_devx_obj * 3063 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 3064 struct mlx5_devx_import_kek_attr *attr) 3065 { 3066 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 3067 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3068 struct mlx5_devx_obj *import_kek_obj = NULL; 3069 void *ptr = NULL, *key_addr = NULL; 3070 3071 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 3072 0, SOCKET_ID_ANY); 3073 if (import_kek_obj == NULL) { 3074 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 3075 rte_errno = ENOMEM; 3076 return NULL; 3077 } 3078 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 3079 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3080 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3081 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3082 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 3083 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 3084 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 3085 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 3086 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 3087 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3088 out, sizeof(out)); 3089 if (import_kek_obj->obj == NULL) { 3090 DEVX_DRV_LOG(ERR, out, "create IMPORT_KEK", NULL, 0); 3091 mlx5_free(import_kek_obj); 3092 return NULL; 3093 } 3094 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3095 return import_kek_obj; 3096 } 3097 3098 /** 3099 * Create general object of type CREDENTIAL using DevX API. 3100 * 3101 * @param[in] ctx 3102 * Context returned from mlx5 open_device() glue function. 3103 * @param [in] attr 3104 * Pointer to CREDENTIAL attributes structure. 3105 * 3106 * @return 3107 * The DevX object created, NULL otherwise and rte_errno is set. 3108 */ 3109 struct mlx5_devx_obj * 3110 mlx5_devx_cmd_create_credential_obj(void *ctx, 3111 struct mlx5_devx_credential_attr *attr) 3112 { 3113 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 3114 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3115 struct mlx5_devx_obj *credential_obj = NULL; 3116 void *ptr = NULL, *credential_addr = NULL; 3117 3118 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 3119 0, SOCKET_ID_ANY); 3120 if (credential_obj == NULL) { 3121 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 3122 rte_errno = ENOMEM; 3123 return NULL; 3124 } 3125 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 3126 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3127 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3128 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3129 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 3130 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 3131 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 3132 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 3133 memcpy(credential_addr, (void *)(attr->credential), 3134 MLX5_CRYPTO_CREDENTIAL_SIZE); 3135 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3136 out, sizeof(out)); 3137 if (credential_obj->obj == NULL) { 3138 DEVX_DRV_LOG(ERR, out, "create CREDENTIAL", NULL, 0); 3139 mlx5_free(credential_obj); 3140 return NULL; 3141 } 3142 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3143 return credential_obj; 3144 } 3145 3146 /** 3147 * Create general object of type CRYPTO_LOGIN using DevX API. 3148 * 3149 * @param[in] ctx 3150 * Context returned from mlx5 open_device() glue function. 3151 * @param [in] attr 3152 * Pointer to CRYPTO_LOGIN attributes structure. 3153 * 3154 * @return 3155 * The DevX object created, NULL otherwise and rte_errno is set. 3156 */ 3157 struct mlx5_devx_obj * 3158 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 3159 struct mlx5_devx_crypto_login_attr *attr) 3160 { 3161 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 3162 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3163 struct mlx5_devx_obj *crypto_login_obj = NULL; 3164 void *ptr = NULL, *credential_addr = NULL; 3165 3166 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 3167 0, SOCKET_ID_ANY); 3168 if (crypto_login_obj == NULL) { 3169 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 3170 rte_errno = ENOMEM; 3171 return NULL; 3172 } 3173 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 3174 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3175 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3176 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3177 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 3178 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 3179 MLX5_SET(crypto_login, ptr, credential_pointer, 3180 attr->credential_pointer); 3181 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 3182 attr->session_import_kek_ptr); 3183 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 3184 memcpy(credential_addr, (void *)(attr->credential), 3185 MLX5_CRYPTO_CREDENTIAL_SIZE); 3186 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3187 out, sizeof(out)); 3188 if (crypto_login_obj->obj == NULL) { 3189 DEVX_DRV_LOG(ERR, out, "create CRYPTO_LOGIN", NULL, 0); 3190 mlx5_free(crypto_login_obj); 3191 return NULL; 3192 } 3193 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3194 return crypto_login_obj; 3195 } 3196 3197 /** 3198 * Query LAG context. 3199 * 3200 * @param[in] ctx 3201 * Pointer to ibv_context, returned from mlx5dv_open_device. 3202 * @param[out] lag_ctx 3203 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 3204 * 3205 * @return 3206 * 0 on success, a negative value otherwise. 3207 */ 3208 int 3209 mlx5_devx_cmd_query_lag(void *ctx, 3210 struct mlx5_devx_lag_context *lag_ctx) 3211 { 3212 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 3213 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 3214 void *lctx; 3215 int rc; 3216 3217 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 3218 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 3219 if (rc) 3220 goto error; 3221 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 3222 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 3223 fdb_selection_mode); 3224 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 3225 port_select_mode); 3226 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 3227 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 3228 tx_remap_affinity_2); 3229 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 3230 tx_remap_affinity_1); 3231 return 0; 3232 error: 3233 rc = (rc > 0) ? -rc : rc; 3234 return rc; 3235 } 3236