1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /* FW writes status value to the OUT buffer at offset 00H */ 17 #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status) 18 /* FW writes syndrome value to the OUT buffer at offset 04H */ 19 #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome) 20 21 #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1)) 22 23 static void 24 mlx5_devx_err_log(void *out, const char *reason, 25 const char *param, uint32_t value) 26 { 27 rte_errno = errno; 28 if (!param) 29 DRV_LOG(ERR, "DevX %s failed errno=%d status=%#x syndrome=%#x", 30 reason, errno, MLX5_FW_STATUS(out), 31 MLX5_FW_SYNDROME(out)); 32 else 33 DRV_LOG(ERR, "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x", 34 reason, param, value, errno, MLX5_FW_STATUS(out), 35 MLX5_FW_SYNDROME(out)); 36 } 37 38 static void * 39 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, 40 int *err, uint32_t flags) 41 { 42 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); 43 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); 44 int rc; 45 46 memset(in, 0, size_in); 47 memset(out, 0, size_out); 48 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 49 MLX5_SET(query_hca_cap_in, in, op_mod, flags); 50 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); 51 if (rc || MLX5_FW_STATUS(out)) { 52 mlx5_devx_err_log(out, "HCA capabilities", "func", flags >> 1); 53 if (err) 54 *err = MLX5_DEVX_ERR_RC(rc); 55 return NULL; 56 } 57 if (err) 58 *err = 0; 59 return MLX5_ADDR_OF(query_hca_cap_out, out, capability); 60 } 61 62 /** 63 * Perform read access to the registers. Reads data from register 64 * and writes ones to the specified buffer. 65 * 66 * @param[in] ctx 67 * Context returned from mlx5 open_device() glue function. 68 * @param[in] reg_id 69 * Register identifier according to the PRM. 70 * @param[in] arg 71 * Register access auxiliary parameter according to the PRM. 72 * @param[out] data 73 * Pointer to the buffer to store read data. 74 * @param[in] dw_cnt 75 * Buffer size in double words. 76 * 77 * @return 78 * 0 on success, a negative value otherwise. 79 */ 80 int 81 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 82 uint32_t *data, uint32_t dw_cnt) 83 { 84 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 85 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 86 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 87 int rc; 88 89 MLX5_ASSERT(data && dw_cnt); 90 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 91 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 92 DRV_LOG(ERR, "Not enough buffer for register read data"); 93 return -1; 94 } 95 MLX5_SET(access_register_in, in, opcode, 96 MLX5_CMD_OP_ACCESS_REGISTER_USER); 97 MLX5_SET(access_register_in, in, op_mod, 98 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 99 MLX5_SET(access_register_in, in, register_id, reg_id); 100 MLX5_SET(access_register_in, in, argument, arg); 101 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 102 MLX5_ST_SZ_BYTES(access_register_out) + 103 sizeof(uint32_t) * dw_cnt); 104 if (rc || MLX5_FW_STATUS(out)) { 105 mlx5_devx_err_log(out, "read access", "NIC register", reg_id); 106 return MLX5_DEVX_ERR_RC(rc); 107 } 108 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 109 dw_cnt * sizeof(uint32_t)); 110 return 0; 111 } 112 113 /** 114 * Perform write access to the registers. 115 * 116 * @param[in] ctx 117 * Context returned from mlx5 open_device() glue function. 118 * @param[in] reg_id 119 * Register identifier according to the PRM. 120 * @param[in] arg 121 * Register access auxiliary parameter according to the PRM. 122 * @param[out] data 123 * Pointer to the buffer containing data to write. 124 * @param[in] dw_cnt 125 * Buffer size in double words (32bit units). 126 * 127 * @return 128 * 0 on success, a negative value otherwise. 129 */ 130 int 131 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 132 uint32_t *data, uint32_t dw_cnt) 133 { 134 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 135 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 136 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 137 int rc; 138 void *ptr; 139 140 MLX5_ASSERT(data && dw_cnt); 141 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 142 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 143 DRV_LOG(ERR, "Data to write exceeds max size"); 144 return -1; 145 } 146 MLX5_SET(access_register_in, in, opcode, 147 MLX5_CMD_OP_ACCESS_REGISTER_USER); 148 MLX5_SET(access_register_in, in, op_mod, 149 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 150 MLX5_SET(access_register_in, in, register_id, reg_id); 151 MLX5_SET(access_register_in, in, argument, arg); 152 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 153 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 154 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 155 if (rc || MLX5_FW_STATUS(out)) { 156 mlx5_devx_err_log(out, "write access", "NIC register", reg_id); 157 return MLX5_DEVX_ERR_RC(rc); 158 } 159 rc = mlx5_glue->devx_general_cmd(ctx, in, 160 MLX5_ST_SZ_BYTES(access_register_in) + 161 dw_cnt * sizeof(uint32_t), 162 out, sizeof(out)); 163 if (rc || MLX5_FW_STATUS(out)) { 164 mlx5_devx_err_log(out, "write access", "NIC register", reg_id); 165 return MLX5_DEVX_ERR_RC(rc); 166 } 167 return 0; 168 } 169 170 /** 171 * Allocate flow counters via devx interface. 172 * 173 * @param[in] ctx 174 * Context returned from mlx5 open_device() glue function. 175 * @param dcs 176 * Pointer to counters properties structure to be filled by the routine. 177 * @param bulk_n_128 178 * Bulk counter numbers in 128 counters units. 179 * 180 * @return 181 * Pointer to counter object on success, a negative value otherwise and 182 * rte_errno is set. 183 */ 184 struct mlx5_devx_obj * 185 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 186 { 187 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 188 0, SOCKET_ID_ANY); 189 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 190 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 191 192 if (!dcs) { 193 rte_errno = ENOMEM; 194 return NULL; 195 } 196 MLX5_SET(alloc_flow_counter_in, in, opcode, 197 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 198 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 199 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 200 sizeof(in), out, sizeof(out)); 201 if (!dcs->obj) { 202 mlx5_devx_err_log(out, "allocate counters", NULL, 0); 203 mlx5_free(dcs); 204 return NULL; 205 } 206 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 207 return dcs; 208 } 209 210 /** 211 * Query flow counters values. 212 * 213 * @param[in] dcs 214 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 215 * @param[in] clear 216 * Whether hardware should clear the counters after the query or not. 217 * @param[in] n_counters 218 * 0 in case of 1 counter to read, otherwise the counter number to read. 219 * @param pkts 220 * The number of packets that matched the flow. 221 * @param bytes 222 * The number of bytes that matched the flow. 223 * @param mkey 224 * The mkey key for batch query. 225 * @param addr 226 * The address in the mkey range for batch query. 227 * @param cmd_comp 228 * The completion object for asynchronous batch query. 229 * @param async_id 230 * The ID to be returned in the asynchronous batch query response. 231 * 232 * @return 233 * 0 on success, a negative value otherwise. 234 */ 235 int 236 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 237 int clear, uint32_t n_counters, 238 uint64_t *pkts, uint64_t *bytes, 239 uint32_t mkey, void *addr, 240 void *cmd_comp, 241 uint64_t async_id) 242 { 243 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 244 MLX5_ST_SZ_BYTES(traffic_counter); 245 uint32_t out[out_len]; 246 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 247 void *stats; 248 int rc; 249 250 MLX5_SET(query_flow_counter_in, in, opcode, 251 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 252 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 253 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 254 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 255 256 if (n_counters) { 257 MLX5_SET(query_flow_counter_in, in, num_of_counters, 258 n_counters); 259 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 260 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 261 MLX5_SET64(query_flow_counter_in, in, address, 262 (uint64_t)(uintptr_t)addr); 263 } 264 if (!cmd_comp) 265 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 266 out_len); 267 else 268 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 269 out_len, async_id, 270 cmd_comp); 271 if (rc) { 272 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 273 rte_errno = rc; 274 return -rc; 275 } 276 if (!n_counters) { 277 stats = MLX5_ADDR_OF(query_flow_counter_out, 278 out, flow_statistics); 279 *pkts = MLX5_GET64(traffic_counter, stats, packets); 280 *bytes = MLX5_GET64(traffic_counter, stats, octets); 281 } 282 return 0; 283 } 284 285 /** 286 * Create a new mkey. 287 * 288 * @param[in] ctx 289 * Context returned from mlx5 open_device() glue function. 290 * @param[in] attr 291 * Attributes of the requested mkey. 292 * 293 * @return 294 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 295 * is set. 296 */ 297 struct mlx5_devx_obj * 298 mlx5_devx_cmd_mkey_create(void *ctx, 299 struct mlx5_devx_mkey_attr *attr) 300 { 301 struct mlx5_klm *klm_array = attr->klm_array; 302 int klm_num = attr->klm_num; 303 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 304 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 305 uint32_t in[in_size_dw]; 306 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 307 void *mkc; 308 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 309 0, SOCKET_ID_ANY); 310 size_t pgsize; 311 uint32_t translation_size; 312 313 if (!mkey) { 314 rte_errno = ENOMEM; 315 return NULL; 316 } 317 memset(in, 0, in_size_dw * 4); 318 pgsize = rte_mem_page_size(); 319 if (pgsize == (size_t)-1) { 320 mlx5_free(mkey); 321 DRV_LOG(ERR, "Failed to get page size"); 322 rte_errno = ENOMEM; 323 return NULL; 324 } 325 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 326 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 327 if (klm_num > 0) { 328 int i; 329 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 330 klm_pas_mtt); 331 translation_size = RTE_ALIGN(klm_num, 4); 332 for (i = 0; i < klm_num; i++) { 333 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 334 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 335 MLX5_SET64(klm, klm, address, klm_array[i].address); 336 klm += MLX5_ST_SZ_BYTES(klm); 337 } 338 for (; i < (int)translation_size; i++) { 339 MLX5_SET(klm, klm, mkey, 0x0); 340 MLX5_SET64(klm, klm, address, 0x0); 341 klm += MLX5_ST_SZ_BYTES(klm); 342 } 343 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 344 MLX5_MKC_ACCESS_MODE_KLM_FBS : 345 MLX5_MKC_ACCESS_MODE_KLM); 346 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 347 } else { 348 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 349 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 350 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 351 } 352 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 353 translation_size); 354 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 355 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 356 MLX5_SET(mkc, mkc, lw, 0x1); 357 MLX5_SET(mkc, mkc, lr, 0x1); 358 if (attr->set_remote_rw) { 359 MLX5_SET(mkc, mkc, rw, 0x1); 360 MLX5_SET(mkc, mkc, rr, 0x1); 361 } 362 MLX5_SET(mkc, mkc, qpn, 0xffffff); 363 MLX5_SET(mkc, mkc, pd, attr->pd); 364 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 365 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 366 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 367 MLX5_SET(mkc, mkc, relaxed_ordering_write, 368 attr->relaxed_ordering_write); 369 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 370 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 371 MLX5_SET64(mkc, mkc, len, attr->size); 372 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 373 if (attr->crypto_en) { 374 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 375 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 376 } 377 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 378 sizeof(out)); 379 if (!mkey->obj) { 380 mlx5_devx_err_log(out, 381 klm_num ? "create indirect mkey" : "create direct key", 382 NULL, 0); 383 mlx5_free(mkey); 384 return NULL; 385 } 386 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 387 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 388 return mkey; 389 } 390 391 /** 392 * Get status of devx command response. 393 * Mainly used for asynchronous commands. 394 * 395 * @param[in] out 396 * The out response buffer. 397 * 398 * @return 399 * 0 on success, non-zero value otherwise. 400 */ 401 int 402 mlx5_devx_get_out_command_status(void *out) 403 { 404 int status; 405 406 if (!out) 407 return -EINVAL; 408 status = MLX5_GET(query_flow_counter_out, out, status); 409 if (status) { 410 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 411 412 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 413 syndrome); 414 } 415 return status; 416 } 417 418 /** 419 * Destroy any object allocated by a Devx API. 420 * 421 * @param[in] obj 422 * Pointer to a general object. 423 * 424 * @return 425 * 0 on success, a negative value otherwise. 426 */ 427 int 428 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 429 { 430 int ret; 431 432 if (!obj) 433 return 0; 434 ret = mlx5_glue->devx_obj_destroy(obj->obj); 435 mlx5_free(obj); 436 return ret; 437 } 438 439 /** 440 * Query NIC vport context. 441 * Fills minimal inline attribute. 442 * 443 * @param[in] ctx 444 * ibv contexts returned from mlx5dv_open_device. 445 * @param[in] vport 446 * vport index 447 * @param[out] attr 448 * Attributes device values. 449 * 450 * @return 451 * 0 on success, a negative value otherwise. 452 */ 453 static int 454 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 455 unsigned int vport, 456 struct mlx5_hca_attr *attr) 457 { 458 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 459 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 460 void *vctx; 461 int rc; 462 463 /* Query NIC vport context to determine inline mode. */ 464 MLX5_SET(query_nic_vport_context_in, in, opcode, 465 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 466 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 467 if (vport) 468 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 469 rc = mlx5_glue->devx_general_cmd(ctx, 470 in, sizeof(in), 471 out, sizeof(out)); 472 if (rc || MLX5_FW_STATUS(out)) { 473 mlx5_devx_err_log(out, "query NIC vport context", NULL, 0); 474 return MLX5_DEVX_ERR_RC(rc); 475 } 476 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 477 nic_vport_context); 478 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 479 min_wqe_inline_mode); 480 return 0; 481 } 482 483 /** 484 * Query NIC vDPA attributes. 485 * 486 * @param[in] ctx 487 * Context returned from mlx5 open_device() glue function. 488 * @param[out] vdpa_attr 489 * vDPA Attributes structure to fill. 490 */ 491 static void 492 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 493 struct mlx5_hca_vdpa_attr *vdpa_attr) 494 { 495 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 496 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 497 void *hcattr; 498 499 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, 500 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 501 MLX5_HCA_CAP_OPMOD_GET_CUR); 502 if (!hcattr) { 503 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities"); 504 vdpa_attr->valid = 0; 505 } else { 506 vdpa_attr->valid = 1; 507 vdpa_attr->desc_tunnel_offload_type = 508 MLX5_GET(virtio_emulation_cap, hcattr, 509 desc_tunnel_offload_type); 510 vdpa_attr->eth_frame_offload_type = 511 MLX5_GET(virtio_emulation_cap, hcattr, 512 eth_frame_offload_type); 513 vdpa_attr->virtio_version_1_0 = 514 MLX5_GET(virtio_emulation_cap, hcattr, 515 virtio_version_1_0); 516 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 517 tso_ipv4); 518 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 519 tso_ipv6); 520 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 521 tx_csum); 522 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 523 rx_csum); 524 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 525 event_mode); 526 vdpa_attr->virtio_queue_type = 527 MLX5_GET(virtio_emulation_cap, hcattr, 528 virtio_queue_type); 529 vdpa_attr->log_doorbell_stride = 530 MLX5_GET(virtio_emulation_cap, hcattr, 531 log_doorbell_stride); 532 vdpa_attr->vnet_modify_ext = 533 MLX5_GET(virtio_emulation_cap, hcattr, 534 vnet_modify_ext); 535 vdpa_attr->virtio_net_q_addr_modify = 536 MLX5_GET(virtio_emulation_cap, hcattr, 537 virtio_net_q_addr_modify); 538 vdpa_attr->virtio_q_index_modify = 539 MLX5_GET(virtio_emulation_cap, hcattr, 540 virtio_q_index_modify); 541 vdpa_attr->log_doorbell_bar_size = 542 MLX5_GET(virtio_emulation_cap, hcattr, 543 log_doorbell_bar_size); 544 vdpa_attr->doorbell_bar_offset = 545 MLX5_GET64(virtio_emulation_cap, hcattr, 546 doorbell_bar_offset); 547 vdpa_attr->max_num_virtio_queues = 548 MLX5_GET(virtio_emulation_cap, hcattr, 549 max_num_virtio_queues); 550 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 551 umem_1_buffer_param_a); 552 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 553 umem_1_buffer_param_b); 554 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 555 umem_2_buffer_param_a); 556 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 557 umem_2_buffer_param_b); 558 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 559 umem_3_buffer_param_a); 560 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 561 umem_3_buffer_param_b); 562 } 563 } 564 565 int 566 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 567 uint32_t ids[], uint32_t num) 568 { 569 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 570 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 571 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 572 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 573 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 574 int ret; 575 uint32_t idx = 0; 576 uint32_t i; 577 578 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 579 rte_errno = EINVAL; 580 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 581 return -rte_errno; 582 } 583 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 584 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 585 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 586 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 587 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 588 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 589 out, sizeof(out)); 590 if (ret) { 591 rte_errno = ret; 592 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 593 (void *)flex_obj); 594 return -rte_errno; 595 } 596 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 597 void *s_off = (void *)((char *)sample + i * 598 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 599 uint32_t en; 600 601 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 602 flow_match_sample_en); 603 if (!en) 604 continue; 605 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 606 flow_match_sample_field_id); 607 } 608 if (num != idx) { 609 rte_errno = EINVAL; 610 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 611 return -rte_errno; 612 } 613 return ret; 614 } 615 616 struct mlx5_devx_obj * 617 mlx5_devx_cmd_create_flex_parser(void *ctx, 618 struct mlx5_devx_graph_node_attr *data) 619 { 620 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 621 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 622 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 623 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 624 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 625 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 626 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 627 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 628 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 629 uint32_t i; 630 631 if (!parse_flex_obj) { 632 DRV_LOG(ERR, "Failed to allocate flex parser data."); 633 rte_errno = ENOMEM; 634 return NULL; 635 } 636 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 637 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 638 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 639 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 640 MLX5_SET(parse_graph_flex, flex, header_length_mode, 641 data->header_length_mode); 642 MLX5_SET64(parse_graph_flex, flex, modify_field_select, 643 data->modify_field_select); 644 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 645 data->header_length_base_value); 646 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 647 data->header_length_field_offset); 648 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 649 data->header_length_field_shift); 650 MLX5_SET(parse_graph_flex, flex, next_header_field_offset, 651 data->next_header_field_offset); 652 MLX5_SET(parse_graph_flex, flex, next_header_field_size, 653 data->next_header_field_size); 654 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 655 data->header_length_field_mask); 656 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 657 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 658 void *s_off = (void *)((char *)sample + i * 659 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 660 661 if (!s->flow_match_sample_en) 662 continue; 663 MLX5_SET(parse_graph_flow_match_sample, s_off, 664 flow_match_sample_en, !!s->flow_match_sample_en); 665 MLX5_SET(parse_graph_flow_match_sample, s_off, 666 flow_match_sample_field_offset, 667 s->flow_match_sample_field_offset); 668 MLX5_SET(parse_graph_flow_match_sample, s_off, 669 flow_match_sample_offset_mode, 670 s->flow_match_sample_offset_mode); 671 MLX5_SET(parse_graph_flow_match_sample, s_off, 672 flow_match_sample_field_offset_mask, 673 s->flow_match_sample_field_offset_mask); 674 MLX5_SET(parse_graph_flow_match_sample, s_off, 675 flow_match_sample_field_offset_shift, 676 s->flow_match_sample_field_offset_shift); 677 MLX5_SET(parse_graph_flow_match_sample, s_off, 678 flow_match_sample_field_base_offset, 679 s->flow_match_sample_field_base_offset); 680 MLX5_SET(parse_graph_flow_match_sample, s_off, 681 flow_match_sample_tunnel_mode, 682 s->flow_match_sample_tunnel_mode); 683 } 684 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 685 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 686 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 687 void *in_off = (void *)((char *)in_arc + i * 688 MLX5_ST_SZ_BYTES(parse_graph_arc)); 689 void *out_off = (void *)((char *)out_arc + i * 690 MLX5_ST_SZ_BYTES(parse_graph_arc)); 691 692 if (ia->arc_parse_graph_node != 0) { 693 MLX5_SET(parse_graph_arc, in_off, 694 compare_condition_value, 695 ia->compare_condition_value); 696 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 697 ia->start_inner_tunnel); 698 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 699 ia->arc_parse_graph_node); 700 MLX5_SET(parse_graph_arc, in_off, 701 parse_graph_node_handle, 702 ia->parse_graph_node_handle); 703 } 704 if (oa->arc_parse_graph_node != 0) { 705 MLX5_SET(parse_graph_arc, out_off, 706 compare_condition_value, 707 oa->compare_condition_value); 708 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 709 oa->start_inner_tunnel); 710 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 711 oa->arc_parse_graph_node); 712 MLX5_SET(parse_graph_arc, out_off, 713 parse_graph_node_handle, 714 oa->parse_graph_node_handle); 715 } 716 } 717 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 718 out, sizeof(out)); 719 if (!parse_flex_obj->obj) { 720 mlx5_devx_err_log(out, "create FLEX PARSE GRAPH", NULL, 0); 721 mlx5_free(parse_flex_obj); 722 return NULL; 723 } 724 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 725 return parse_flex_obj; 726 } 727 728 static int 729 mlx5_devx_cmd_query_hca_parse_graph_node_cap 730 (void *ctx, struct mlx5_hca_flex_attr *attr) 731 { 732 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 733 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 734 void *hcattr; 735 int rc; 736 737 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 738 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | 739 MLX5_HCA_CAP_OPMOD_GET_CUR); 740 if (!hcattr) 741 return rc; 742 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); 743 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); 744 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, 745 header_length_mode); 746 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, 747 sample_offset_mode); 748 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, 749 max_num_arc_in); 750 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, 751 max_num_arc_out); 752 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, 753 max_num_sample); 754 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, 755 sample_id_in_out); 756 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, 757 max_base_header_length); 758 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, 759 max_sample_base_offset); 760 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, 761 max_next_header_offset); 762 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, 763 header_length_mask_width); 764 /* Get the max supported samples from HCA CAP 2 */ 765 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 766 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 767 MLX5_HCA_CAP_OPMOD_GET_CUR); 768 if (!hcattr) 769 return rc; 770 attr->max_num_prog_sample = 771 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); 772 return 0; 773 } 774 775 static int 776 mlx5_devx_query_pkt_integrity_match(void *hcattr) 777 { 778 return MLX5_GET(flow_table_nic_cap, hcattr, 779 ft_field_support_2_nic_receive.inner_l3_ok) && 780 MLX5_GET(flow_table_nic_cap, hcattr, 781 ft_field_support_2_nic_receive.inner_l4_ok) && 782 MLX5_GET(flow_table_nic_cap, hcattr, 783 ft_field_support_2_nic_receive.outer_l3_ok) && 784 MLX5_GET(flow_table_nic_cap, hcattr, 785 ft_field_support_2_nic_receive.outer_l4_ok) && 786 MLX5_GET(flow_table_nic_cap, hcattr, 787 ft_field_support_2_nic_receive 788 .inner_ipv4_checksum_ok) && 789 MLX5_GET(flow_table_nic_cap, hcattr, 790 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 791 MLX5_GET(flow_table_nic_cap, hcattr, 792 ft_field_support_2_nic_receive 793 .outer_ipv4_checksum_ok) && 794 MLX5_GET(flow_table_nic_cap, hcattr, 795 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 796 } 797 798 /** 799 * Query HCA attributes. 800 * Using those attributes we can check on run time if the device 801 * is having the required capabilities. 802 * 803 * @param[in] ctx 804 * Context returned from mlx5 open_device() glue function. 805 * @param[out] attr 806 * Attributes device values. 807 * 808 * @return 809 * 0 on success, a negative value otherwise. 810 */ 811 int 812 mlx5_devx_cmd_query_hca_attr(void *ctx, 813 struct mlx5_hca_attr *attr) 814 { 815 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 816 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 817 bool hca_cap_2_sup; 818 uint64_t general_obj_types_supported = 0; 819 void *hcattr; 820 int rc, i; 821 822 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 823 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 824 MLX5_HCA_CAP_OPMOD_GET_CUR); 825 if (!hcattr) 826 return rc; 827 hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2); 828 attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq); 829 attr->flow_counter_bulk_alloc_bitmap = 830 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 831 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 832 flow_counters_dump); 833 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp); 834 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp); 835 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 836 log_max_rqt_size); 837 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 838 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 839 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 840 log_max_hairpin_queues); 841 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 842 log_max_hairpin_wq_data_sz); 843 attr->log_max_hairpin_num_packets = MLX5_GET 844 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 845 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 846 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 847 relaxed_ordering_write); 848 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 849 relaxed_ordering_read); 850 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 851 access_register_user); 852 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 853 eth_net_offloads); 854 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 855 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 856 flex_parser_protocols); 857 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 858 max_geneve_tlv_options); 859 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 860 max_geneve_tlv_option_data_len); 861 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 862 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 863 general_obj_types) & 864 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 865 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 866 general_obj_types) & 867 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 868 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 869 general_obj_types) & 870 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 871 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 872 general_obj_types) & 873 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 874 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 875 wqe_index_ignore_cap); 876 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 877 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 878 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 879 log_max_static_sq_wq); 880 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 881 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 882 device_frequency_khz); 883 attr->scatter_fcs_w_decap_disable = 884 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 885 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 886 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 887 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 888 attr->steering_format_version = 889 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 890 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 891 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 892 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 893 regexp_num_of_engines); 894 /* Read the general_obj_types bitmap and extract the relevant bits. */ 895 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 896 general_obj_types); 897 attr->vdpa.valid = !!(general_obj_types_supported & 898 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 899 attr->vdpa.queue_counters_valid = 900 !!(general_obj_types_supported & 901 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 902 attr->parse_graph_flex_node = 903 !!(general_obj_types_supported & 904 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 905 attr->flow_hit_aso = !!(general_obj_types_supported & 906 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 907 attr->geneve_tlv_opt = !!(general_obj_types_supported & 908 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 909 attr->dek = !!(general_obj_types_supported & 910 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 911 attr->import_kek = !!(general_obj_types_supported & 912 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 913 attr->credential = !!(general_obj_types_supported & 914 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 915 attr->crypto_login = !!(general_obj_types_supported & 916 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 917 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 918 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 919 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 920 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 921 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 922 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 923 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 924 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 925 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 926 attr->reg_c_preserve = 927 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 928 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 929 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 930 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 931 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 932 compress_mmo_sq); 933 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 934 decompress_mmo_sq); 935 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 936 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 937 compress_mmo_qp); 938 attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 939 decompress_mmo_qp); 940 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 941 compress_min_block_size); 942 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 943 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 944 log_compress_mmo_size); 945 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 946 log_decompress_mmo_size); 947 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 948 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 949 mini_cqe_resp_flow_tag); 950 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 951 mini_cqe_resp_l3_l4_tag); 952 attr->umr_indirect_mkey_disabled = 953 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 954 attr->umr_modify_entity_size_disabled = 955 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 956 attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time); 957 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 958 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 959 general_obj_types) & 960 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 961 attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); 962 if (attr->crypto) { 963 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts); 964 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 965 MLX5_GET_HCA_CAP_OP_MOD_CRYPTO | 966 MLX5_HCA_CAP_OPMOD_GET_CUR); 967 if (!hcattr) 968 return -1; 969 attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps, 970 hcattr, wrapped_import_method) 971 & 1 << 2); 972 } 973 if (hca_cap_2_sup) { 974 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 975 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 976 MLX5_HCA_CAP_OPMOD_GET_CUR); 977 if (!hcattr) { 978 DRV_LOG(DEBUG, 979 "Failed to query DevX HCA capabilities 2."); 980 return rc; 981 } 982 attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, 983 log_min_stride_wqe_sz); 984 } 985 if (attr->log_min_stride_wqe_sz == 0) 986 attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 987 if (attr->qos.sup) { 988 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 989 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 990 MLX5_HCA_CAP_OPMOD_GET_CUR); 991 if (!hcattr) { 992 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); 993 return rc; 994 } 995 attr->qos.flow_meter_old = 996 MLX5_GET(qos_cap, hcattr, flow_meter_old); 997 attr->qos.log_max_flow_meter = 998 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 999 attr->qos.flow_meter_reg_c_ids = 1000 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 1001 attr->qos.flow_meter = 1002 MLX5_GET(qos_cap, hcattr, flow_meter); 1003 attr->qos.packet_pacing = 1004 MLX5_GET(qos_cap, hcattr, packet_pacing); 1005 attr->qos.wqe_rate_pp = 1006 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 1007 if (attr->qos.flow_meter_aso_sup) { 1008 attr->qos.log_meter_aso_granularity = 1009 MLX5_GET(qos_cap, hcattr, 1010 log_meter_aso_granularity); 1011 attr->qos.log_meter_aso_max_alloc = 1012 MLX5_GET(qos_cap, hcattr, 1013 log_meter_aso_max_alloc); 1014 attr->qos.log_max_num_meter_aso = 1015 MLX5_GET(qos_cap, hcattr, 1016 log_max_num_meter_aso); 1017 } 1018 } 1019 /* 1020 * Flex item support needs max_num_prog_sample_field 1021 * from the Capabilities 2 table for PARSE_GRAPH_NODE 1022 */ 1023 if (attr->parse_graph_flex_node) { 1024 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap 1025 (ctx, &attr->flex); 1026 if (rc) 1027 return -1; 1028 } 1029 if (attr->vdpa.valid) 1030 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 1031 if (!attr->eth_net_offloads) 1032 return 0; 1033 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 1034 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1035 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 1036 MLX5_HCA_CAP_OPMOD_GET_CUR); 1037 if (!hcattr) { 1038 attr->log_max_ft_sampler_num = 0; 1039 return rc; 1040 } 1041 attr->log_max_ft_sampler_num = MLX5_GET 1042 (flow_table_nic_cap, hcattr, 1043 flow_table_properties_nic_receive.log_max_ft_sampler_num); 1044 attr->flow.tunnel_header_0_1 = MLX5_GET 1045 (flow_table_nic_cap, hcattr, 1046 ft_field_support_2_nic_receive.tunnel_header_0_1); 1047 attr->flow.tunnel_header_2_3 = MLX5_GET 1048 (flow_table_nic_cap, hcattr, 1049 ft_field_support_2_nic_receive.tunnel_header_2_3); 1050 attr->modify_outer_ip_ecn = MLX5_GET 1051 (flow_table_nic_cap, hcattr, 1052 ft_header_modify_nic_receive.outer_ip_ecn); 1053 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 1054 attr->inner_ipv4_ihl = MLX5_GET 1055 (flow_table_nic_cap, hcattr, 1056 ft_field_support_2_nic_receive.inner_ipv4_ihl); 1057 attr->outer_ipv4_ihl = MLX5_GET 1058 (flow_table_nic_cap, hcattr, 1059 ft_field_support_2_nic_receive.outer_ipv4_ihl); 1060 /* Query HCA offloads for Ethernet protocol. */ 1061 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1062 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 1063 MLX5_HCA_CAP_OPMOD_GET_CUR); 1064 if (!hcattr) { 1065 attr->eth_net_offloads = 0; 1066 return rc; 1067 } 1068 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 1069 hcattr, wqe_vlan_insert); 1070 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 1071 hcattr, csum_cap); 1072 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 1073 hcattr, vlan_cap); 1074 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1075 lro_cap); 1076 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1077 hcattr, max_lso_cap); 1078 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1079 hcattr, scatter_fcs); 1080 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1081 hcattr, tunnel_lro_gre); 1082 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1083 hcattr, tunnel_lro_vxlan); 1084 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1085 hcattr, swp); 1086 attr->tunnel_stateless_gre = 1087 MLX5_GET(per_protocol_networking_offload_caps, 1088 hcattr, tunnel_stateless_gre); 1089 attr->tunnel_stateless_vxlan = 1090 MLX5_GET(per_protocol_networking_offload_caps, 1091 hcattr, tunnel_stateless_vxlan); 1092 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1093 hcattr, swp_csum); 1094 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1095 hcattr, swp_lso); 1096 attr->lro_max_msg_sz_mode = MLX5_GET 1097 (per_protocol_networking_offload_caps, 1098 hcattr, lro_max_msg_sz_mode); 1099 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1100 attr->lro_timer_supported_periods[i] = 1101 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1102 lro_timer_supported_periods[i]); 1103 } 1104 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1105 hcattr, lro_min_mss_size); 1106 attr->tunnel_stateless_geneve_rx = 1107 MLX5_GET(per_protocol_networking_offload_caps, 1108 hcattr, tunnel_stateless_geneve_rx); 1109 attr->geneve_max_opt_len = 1110 MLX5_GET(per_protocol_networking_offload_caps, 1111 hcattr, max_geneve_opt_len); 1112 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1113 hcattr, wqe_inline_mode); 1114 attr->tunnel_stateless_gtp = MLX5_GET 1115 (per_protocol_networking_offload_caps, 1116 hcattr, tunnel_stateless_gtp); 1117 attr->rss_ind_tbl_cap = MLX5_GET 1118 (per_protocol_networking_offload_caps, 1119 hcattr, rss_ind_tbl_cap); 1120 /* Query HCA attribute for ROCE. */ 1121 if (attr->roce) { 1122 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1123 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1124 MLX5_HCA_CAP_OPMOD_GET_CUR); 1125 if (!hcattr) { 1126 DRV_LOG(DEBUG, 1127 "Failed to query devx HCA ROCE capabilities"); 1128 return rc; 1129 } 1130 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1131 } 1132 if (attr->eth_virt && 1133 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1134 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1135 if (rc) { 1136 attr->eth_virt = 0; 1137 goto error; 1138 } 1139 } 1140 if (attr->eswitch_manager) { 1141 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1142 MLX5_SET_HCA_CAP_OP_MOD_ESW | 1143 MLX5_HCA_CAP_OPMOD_GET_CUR); 1144 if (!hcattr) 1145 return rc; 1146 attr->esw_mgr_vport_id_valid = 1147 MLX5_GET(esw_cap, hcattr, 1148 esw_manager_vport_number_valid); 1149 attr->esw_mgr_vport_id = 1150 MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); 1151 } 1152 return 0; 1153 error: 1154 rc = (rc > 0) ? -rc : rc; 1155 return rc; 1156 } 1157 1158 /** 1159 * Query TIS transport domain from QP verbs object using DevX API. 1160 * 1161 * @param[in] qp 1162 * Pointer to verbs QP returned by ibv_create_qp . 1163 * @param[in] tis_num 1164 * TIS number of TIS to query. 1165 * @param[out] tis_td 1166 * Pointer to TIS transport domain variable, to be set by the routine. 1167 * 1168 * @return 1169 * 0 on success, a negative value otherwise. 1170 */ 1171 int 1172 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1173 uint32_t *tis_td) 1174 { 1175 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1176 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1177 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1178 int rc; 1179 void *tis_ctx; 1180 1181 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1182 MLX5_SET(query_tis_in, in, tisn, tis_num); 1183 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1184 if (rc) { 1185 DRV_LOG(ERR, "Failed to query QP using DevX"); 1186 return -rc; 1187 }; 1188 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1189 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1190 return 0; 1191 #else 1192 (void)qp; 1193 (void)tis_num; 1194 (void)tis_td; 1195 return -ENOTSUP; 1196 #endif 1197 } 1198 1199 /** 1200 * Fill WQ data for DevX API command. 1201 * Utility function for use when creating DevX objects containing a WQ. 1202 * 1203 * @param[in] wq_ctx 1204 * Pointer to WQ context to fill with data. 1205 * @param [in] wq_attr 1206 * Pointer to WQ attributes structure to fill in WQ context. 1207 */ 1208 static void 1209 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1210 { 1211 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1212 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1213 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1214 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1215 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1216 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1217 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1218 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1219 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1220 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1221 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1222 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1223 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1224 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1225 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1226 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1227 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1228 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1229 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1230 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1231 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1232 wq_attr->log_hairpin_num_packets); 1233 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1234 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1235 wq_attr->single_wqe_log_num_of_strides); 1236 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1237 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1238 wq_attr->single_stride_log_num_of_bytes); 1239 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1240 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1241 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1242 } 1243 1244 /** 1245 * Create RQ using DevX API. 1246 * 1247 * @param[in] ctx 1248 * Context returned from mlx5 open_device() glue function. 1249 * @param [in] rq_attr 1250 * Pointer to create RQ attributes structure. 1251 * @param [in] socket 1252 * CPU socket ID for allocations. 1253 * 1254 * @return 1255 * The DevX object created, NULL otherwise and rte_errno is set. 1256 */ 1257 struct mlx5_devx_obj * 1258 mlx5_devx_cmd_create_rq(void *ctx, 1259 struct mlx5_devx_create_rq_attr *rq_attr, 1260 int socket) 1261 { 1262 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1263 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1264 void *rq_ctx, *wq_ctx; 1265 struct mlx5_devx_wq_attr *wq_attr; 1266 struct mlx5_devx_obj *rq = NULL; 1267 1268 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1269 if (!rq) { 1270 DRV_LOG(ERR, "Failed to allocate RQ data"); 1271 rte_errno = ENOMEM; 1272 return NULL; 1273 } 1274 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1275 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1276 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1277 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1278 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1279 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1280 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1281 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1282 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1283 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1284 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1285 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1286 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1287 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1288 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1289 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1290 wq_attr = &rq_attr->wq_attr; 1291 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1292 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1293 out, sizeof(out)); 1294 if (!rq->obj) { 1295 mlx5_devx_err_log(out, "create RQ", NULL, 0); 1296 mlx5_free(rq); 1297 return NULL; 1298 } 1299 rq->id = MLX5_GET(create_rq_out, out, rqn); 1300 return rq; 1301 } 1302 1303 /** 1304 * Modify RQ using DevX API. 1305 * 1306 * @param[in] rq 1307 * Pointer to RQ object structure. 1308 * @param [in] rq_attr 1309 * Pointer to modify RQ attributes structure. 1310 * 1311 * @return 1312 * 0 on success, a negative errno value otherwise and rte_errno is set. 1313 */ 1314 int 1315 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1316 struct mlx5_devx_modify_rq_attr *rq_attr) 1317 { 1318 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1319 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1320 void *rq_ctx, *wq_ctx; 1321 int ret; 1322 1323 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1324 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1325 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1326 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1327 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1328 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1329 if (rq_attr->modify_bitmask & 1330 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1331 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1332 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1333 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1334 if (rq_attr->modify_bitmask & 1335 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1336 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1337 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1338 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1339 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1340 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1341 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1342 } 1343 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1344 out, sizeof(out)); 1345 if (ret) { 1346 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1347 rte_errno = errno; 1348 return -errno; 1349 } 1350 return ret; 1351 } 1352 1353 /** 1354 * Create RMP using DevX API. 1355 * 1356 * @param[in] ctx 1357 * Context returned from mlx5 open_device() glue function. 1358 * @param [in] rmp_attr 1359 * Pointer to create RMP attributes structure. 1360 * @param [in] socket 1361 * CPU socket ID for allocations. 1362 * 1363 * @return 1364 * The DevX object created, NULL otherwise and rte_errno is set. 1365 */ 1366 struct mlx5_devx_obj * 1367 mlx5_devx_cmd_create_rmp(void *ctx, 1368 struct mlx5_devx_create_rmp_attr *rmp_attr, 1369 int socket) 1370 { 1371 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0}; 1372 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0}; 1373 void *rmp_ctx, *wq_ctx; 1374 struct mlx5_devx_wq_attr *wq_attr; 1375 struct mlx5_devx_obj *rmp = NULL; 1376 1377 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket); 1378 if (!rmp) { 1379 DRV_LOG(ERR, "Failed to allocate RMP data"); 1380 rte_errno = ENOMEM; 1381 return NULL; 1382 } 1383 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP); 1384 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx); 1385 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state); 1386 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe, 1387 rmp_attr->basic_cyclic_rcv_wqe); 1388 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq); 1389 wq_attr = &rmp_attr->wq_attr; 1390 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1391 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1392 sizeof(out)); 1393 if (!rmp->obj) { 1394 mlx5_devx_err_log(out, "create RMP", NULL, 0); 1395 mlx5_free(rmp); 1396 return NULL; 1397 } 1398 rmp->id = MLX5_GET(create_rmp_out, out, rmpn); 1399 return rmp; 1400 } 1401 1402 /* 1403 * Create TIR using DevX API. 1404 * 1405 * @param[in] ctx 1406 * Context returned from mlx5 open_device() glue function. 1407 * @param [in] tir_attr 1408 * Pointer to TIR attributes structure. 1409 * 1410 * @return 1411 * The DevX object created, NULL otherwise and rte_errno is set. 1412 */ 1413 struct mlx5_devx_obj * 1414 mlx5_devx_cmd_create_tir(void *ctx, 1415 struct mlx5_devx_tir_attr *tir_attr) 1416 { 1417 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1418 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1419 void *tir_ctx, *outer, *inner, *rss_key; 1420 struct mlx5_devx_obj *tir = NULL; 1421 1422 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1423 if (!tir) { 1424 DRV_LOG(ERR, "Failed to allocate TIR data"); 1425 rte_errno = ENOMEM; 1426 return NULL; 1427 } 1428 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1429 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1430 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1431 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1432 tir_attr->lro_timeout_period_usecs); 1433 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1434 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1435 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1436 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1437 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1438 tir_attr->tunneled_offload_en); 1439 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1440 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1441 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1442 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1443 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1444 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1445 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1446 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1447 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1448 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1449 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1450 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1451 tir_attr->rx_hash_field_selector_outer.selected_fields); 1452 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1453 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1454 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1455 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1456 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1457 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1458 tir_attr->rx_hash_field_selector_inner.selected_fields); 1459 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1460 out, sizeof(out)); 1461 if (!tir->obj) { 1462 mlx5_devx_err_log(out, "create TIR", NULL, 0); 1463 mlx5_free(tir); 1464 return NULL; 1465 } 1466 tir->id = MLX5_GET(create_tir_out, out, tirn); 1467 return tir; 1468 } 1469 1470 /** 1471 * Modify TIR using DevX API. 1472 * 1473 * @param[in] tir 1474 * Pointer to TIR DevX object structure. 1475 * @param [in] modify_tir_attr 1476 * Pointer to TIR modification attributes structure. 1477 * 1478 * @return 1479 * 0 on success, a negative errno value otherwise and rte_errno is set. 1480 */ 1481 int 1482 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1483 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1484 { 1485 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1486 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1487 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1488 void *tir_ctx; 1489 int ret; 1490 1491 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1492 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1493 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1494 modify_tir_attr->modify_bitmask); 1495 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1496 if (modify_tir_attr->modify_bitmask & 1497 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1498 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1499 tir_attr->lro_timeout_period_usecs); 1500 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1501 tir_attr->lro_enable_mask); 1502 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1503 tir_attr->lro_max_msg_sz); 1504 } 1505 if (modify_tir_attr->modify_bitmask & 1506 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1507 MLX5_SET(tirc, tir_ctx, indirect_table, 1508 tir_attr->indirect_table); 1509 if (modify_tir_attr->modify_bitmask & 1510 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1511 int i; 1512 void *outer, *inner; 1513 1514 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1515 tir_attr->rx_hash_symmetric); 1516 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1517 for (i = 0; i < 10; i++) { 1518 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1519 tir_attr->rx_hash_toeplitz_key[i]); 1520 } 1521 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1522 rx_hash_field_selector_outer); 1523 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1524 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1525 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1526 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1527 MLX5_SET 1528 (rx_hash_field_select, outer, selected_fields, 1529 tir_attr->rx_hash_field_selector_outer.selected_fields); 1530 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1531 rx_hash_field_selector_inner); 1532 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1533 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1534 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1535 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1536 MLX5_SET 1537 (rx_hash_field_select, inner, selected_fields, 1538 tir_attr->rx_hash_field_selector_inner.selected_fields); 1539 } 1540 if (modify_tir_attr->modify_bitmask & 1541 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1542 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1543 } 1544 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1545 out, sizeof(out)); 1546 if (ret) { 1547 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1548 rte_errno = errno; 1549 return -errno; 1550 } 1551 return ret; 1552 } 1553 1554 /** 1555 * Create RQT using DevX API. 1556 * 1557 * @param[in] ctx 1558 * Context returned from mlx5 open_device() glue function. 1559 * @param [in] rqt_attr 1560 * Pointer to RQT attributes structure. 1561 * 1562 * @return 1563 * The DevX object created, NULL otherwise and rte_errno is set. 1564 */ 1565 struct mlx5_devx_obj * 1566 mlx5_devx_cmd_create_rqt(void *ctx, 1567 struct mlx5_devx_rqt_attr *rqt_attr) 1568 { 1569 uint32_t *in = NULL; 1570 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1571 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1572 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1573 void *rqt_ctx; 1574 struct mlx5_devx_obj *rqt = NULL; 1575 int i; 1576 1577 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1578 if (!in) { 1579 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1580 rte_errno = ENOMEM; 1581 return NULL; 1582 } 1583 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1584 if (!rqt) { 1585 DRV_LOG(ERR, "Failed to allocate RQT data"); 1586 rte_errno = ENOMEM; 1587 mlx5_free(in); 1588 return NULL; 1589 } 1590 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1591 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1592 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1593 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1594 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1595 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1596 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1597 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1598 mlx5_free(in); 1599 if (!rqt->obj) { 1600 mlx5_devx_err_log(out, "create RQT", NULL, 0); 1601 mlx5_free(rqt); 1602 return NULL; 1603 } 1604 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1605 return rqt; 1606 } 1607 1608 /** 1609 * Modify RQT using DevX API. 1610 * 1611 * @param[in] rqt 1612 * Pointer to RQT DevX object structure. 1613 * @param [in] rqt_attr 1614 * Pointer to RQT attributes structure. 1615 * 1616 * @return 1617 * 0 on success, a negative errno value otherwise and rte_errno is set. 1618 */ 1619 int 1620 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1621 struct mlx5_devx_rqt_attr *rqt_attr) 1622 { 1623 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1624 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1625 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1626 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1627 void *rqt_ctx; 1628 int i; 1629 int ret; 1630 1631 if (!in) { 1632 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1633 rte_errno = ENOMEM; 1634 return -ENOMEM; 1635 } 1636 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1637 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1638 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1639 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1640 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1641 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1642 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1643 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1644 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1645 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1646 mlx5_free(in); 1647 if (ret) { 1648 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1649 rte_errno = errno; 1650 return -rte_errno; 1651 } 1652 return ret; 1653 } 1654 1655 /** 1656 * Create SQ using DevX API. 1657 * 1658 * @param[in] ctx 1659 * Context returned from mlx5 open_device() glue function. 1660 * @param [in] sq_attr 1661 * Pointer to SQ attributes structure. 1662 * @param [in] socket 1663 * CPU socket ID for allocations. 1664 * 1665 * @return 1666 * The DevX object created, NULL otherwise and rte_errno is set. 1667 **/ 1668 struct mlx5_devx_obj * 1669 mlx5_devx_cmd_create_sq(void *ctx, 1670 struct mlx5_devx_create_sq_attr *sq_attr) 1671 { 1672 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1673 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1674 void *sq_ctx; 1675 void *wq_ctx; 1676 struct mlx5_devx_wq_attr *wq_attr; 1677 struct mlx5_devx_obj *sq = NULL; 1678 1679 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1680 if (!sq) { 1681 DRV_LOG(ERR, "Failed to allocate SQ data"); 1682 rte_errno = ENOMEM; 1683 return NULL; 1684 } 1685 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1686 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1687 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1688 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1689 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1690 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1691 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1692 sq_attr->allow_multi_pkt_send_wqe); 1693 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1694 sq_attr->min_wqe_inline_mode); 1695 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1696 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1697 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1698 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1699 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1700 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1701 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1702 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1703 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1704 sq_attr->packet_pacing_rate_limit_index); 1705 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1706 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1707 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1708 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1709 wq_attr = &sq_attr->wq_attr; 1710 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1711 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1712 out, sizeof(out)); 1713 if (!sq->obj) { 1714 mlx5_devx_err_log(out, "create SQ", NULL, 0); 1715 mlx5_free(sq); 1716 return NULL; 1717 } 1718 sq->id = MLX5_GET(create_sq_out, out, sqn); 1719 return sq; 1720 } 1721 1722 /** 1723 * Modify SQ using DevX API. 1724 * 1725 * @param[in] sq 1726 * Pointer to SQ object structure. 1727 * @param [in] sq_attr 1728 * Pointer to SQ attributes structure. 1729 * 1730 * @return 1731 * 0 on success, a negative errno value otherwise and rte_errno is set. 1732 */ 1733 int 1734 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1735 struct mlx5_devx_modify_sq_attr *sq_attr) 1736 { 1737 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1738 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1739 void *sq_ctx; 1740 int ret; 1741 1742 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1743 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1744 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1745 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1746 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1747 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1748 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1749 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1750 out, sizeof(out)); 1751 if (ret) { 1752 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1753 rte_errno = errno; 1754 return -rte_errno; 1755 } 1756 return ret; 1757 } 1758 1759 /** 1760 * Create TIS using DevX API. 1761 * 1762 * @param[in] ctx 1763 * Context returned from mlx5 open_device() glue function. 1764 * @param [in] tis_attr 1765 * Pointer to TIS attributes structure. 1766 * 1767 * @return 1768 * The DevX object created, NULL otherwise and rte_errno is set. 1769 */ 1770 struct mlx5_devx_obj * 1771 mlx5_devx_cmd_create_tis(void *ctx, 1772 struct mlx5_devx_tis_attr *tis_attr) 1773 { 1774 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1775 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1776 struct mlx5_devx_obj *tis = NULL; 1777 void *tis_ctx; 1778 1779 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1780 if (!tis) { 1781 DRV_LOG(ERR, "Failed to allocate TIS object"); 1782 rte_errno = ENOMEM; 1783 return NULL; 1784 } 1785 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1786 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1787 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1788 tis_attr->strict_lag_tx_port_affinity); 1789 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1790 tis_attr->lag_tx_port_affinity); 1791 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1792 MLX5_SET(tisc, tis_ctx, transport_domain, 1793 tis_attr->transport_domain); 1794 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1795 out, sizeof(out)); 1796 if (!tis->obj) { 1797 mlx5_devx_err_log(out, "create TIS", NULL, 0); 1798 mlx5_free(tis); 1799 return NULL; 1800 } 1801 tis->id = MLX5_GET(create_tis_out, out, tisn); 1802 return tis; 1803 } 1804 1805 /** 1806 * Create transport domain using DevX API. 1807 * 1808 * @param[in] ctx 1809 * Context returned from mlx5 open_device() glue function. 1810 * @return 1811 * The DevX object created, NULL otherwise and rte_errno is set. 1812 */ 1813 struct mlx5_devx_obj * 1814 mlx5_devx_cmd_create_td(void *ctx) 1815 { 1816 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1817 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1818 struct mlx5_devx_obj *td = NULL; 1819 1820 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1821 if (!td) { 1822 DRV_LOG(ERR, "Failed to allocate TD object"); 1823 rte_errno = ENOMEM; 1824 return NULL; 1825 } 1826 MLX5_SET(alloc_transport_domain_in, in, opcode, 1827 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1828 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1829 out, sizeof(out)); 1830 if (!td->obj) { 1831 mlx5_devx_err_log(out, "create TIS", NULL, 0); 1832 mlx5_free(td); 1833 return NULL; 1834 } 1835 td->id = MLX5_GET(alloc_transport_domain_out, out, 1836 transport_domain); 1837 return td; 1838 } 1839 1840 /** 1841 * Dump all flows to file. 1842 * 1843 * @param[in] fdb_domain 1844 * FDB domain. 1845 * @param[in] rx_domain 1846 * RX domain. 1847 * @param[in] tx_domain 1848 * TX domain. 1849 * @param[out] file 1850 * Pointer to file stream. 1851 * 1852 * @return 1853 * 0 on success, a negative value otherwise. 1854 */ 1855 int 1856 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1857 void *rx_domain __rte_unused, 1858 void *tx_domain __rte_unused, FILE *file __rte_unused) 1859 { 1860 int ret = 0; 1861 1862 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1863 if (fdb_domain) { 1864 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1865 if (ret) 1866 return ret; 1867 } 1868 MLX5_ASSERT(rx_domain); 1869 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1870 if (ret) 1871 return ret; 1872 MLX5_ASSERT(tx_domain); 1873 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1874 #else 1875 ret = ENOTSUP; 1876 #endif 1877 return -ret; 1878 } 1879 1880 int 1881 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 1882 FILE *file __rte_unused) 1883 { 1884 int ret = 0; 1885 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 1886 if (rule_info) 1887 ret = mlx5_glue->dr_dump_rule(file, rule_info); 1888 #else 1889 ret = ENOTSUP; 1890 #endif 1891 return -ret; 1892 } 1893 1894 /* 1895 * Create CQ using DevX API. 1896 * 1897 * @param[in] ctx 1898 * Context returned from mlx5 open_device() glue function. 1899 * @param [in] attr 1900 * Pointer to CQ attributes structure. 1901 * 1902 * @return 1903 * The DevX object created, NULL otherwise and rte_errno is set. 1904 */ 1905 struct mlx5_devx_obj * 1906 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1907 { 1908 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1909 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1910 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1911 sizeof(*cq_obj), 1912 0, SOCKET_ID_ANY); 1913 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1914 1915 if (!cq_obj) { 1916 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1917 rte_errno = ENOMEM; 1918 return NULL; 1919 } 1920 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1921 if (attr->db_umem_valid) { 1922 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1923 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1924 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1925 } else { 1926 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1927 } 1928 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1929 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1930 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1931 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1932 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1933 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1934 MLX5_SET(cqc, cqctx, log_page_size, 1935 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1936 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1937 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1938 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1939 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1940 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1941 attr->mini_cqe_res_format_ext); 1942 if (attr->q_umem_valid) { 1943 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1944 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1945 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1946 attr->q_umem_offset); 1947 } 1948 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1949 sizeof(out)); 1950 if (!cq_obj->obj) { 1951 mlx5_devx_err_log(out, "create CQ", NULL, 0); 1952 mlx5_free(cq_obj); 1953 return NULL; 1954 } 1955 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1956 return cq_obj; 1957 } 1958 1959 /** 1960 * Create VIRTQ using DevX API. 1961 * 1962 * @param[in] ctx 1963 * Context returned from mlx5 open_device() glue function. 1964 * @param [in] attr 1965 * Pointer to VIRTQ attributes structure. 1966 * 1967 * @return 1968 * The DevX object created, NULL otherwise and rte_errno is set. 1969 */ 1970 struct mlx5_devx_obj * 1971 mlx5_devx_cmd_create_virtq(void *ctx, 1972 struct mlx5_devx_virtq_attr *attr) 1973 { 1974 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1975 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1976 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1977 sizeof(*virtq_obj), 1978 0, SOCKET_ID_ANY); 1979 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1980 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1981 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1982 1983 if (!virtq_obj) { 1984 DRV_LOG(ERR, "Failed to allocate virtq data."); 1985 rte_errno = ENOMEM; 1986 return NULL; 1987 } 1988 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1989 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1990 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1991 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1992 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1993 attr->hw_available_index); 1994 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1995 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1996 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1997 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1998 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1999 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2000 attr->virtio_version_1_0); 2001 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2002 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2003 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2004 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2005 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 2006 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2007 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 2008 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2009 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 2010 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 2011 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 2012 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 2013 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 2014 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 2015 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 2016 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 2017 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 2018 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 2019 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 2020 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 2021 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 2022 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 2023 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 2024 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2025 sizeof(out)); 2026 if (!virtq_obj->obj) { 2027 mlx5_devx_err_log(out, "create VIRTQ", NULL, 0); 2028 mlx5_free(virtq_obj); 2029 return NULL; 2030 } 2031 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2032 return virtq_obj; 2033 } 2034 2035 /** 2036 * Modify VIRTQ using DevX API. 2037 * 2038 * @param[in] virtq_obj 2039 * Pointer to virtq object structure. 2040 * @param [in] attr 2041 * Pointer to modify virtq attributes structure. 2042 * 2043 * @return 2044 * 0 on success, a negative errno value otherwise and rte_errno is set. 2045 */ 2046 int 2047 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 2048 struct mlx5_devx_virtq_attr *attr) 2049 { 2050 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2051 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2052 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2053 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2054 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2055 int ret; 2056 2057 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2058 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 2059 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2060 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2061 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2062 MLX5_SET64(virtio_net_q, virtq, modify_field_select, 2063 attr->mod_fields_bitmap); 2064 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2065 if (!attr->mod_fields_bitmap) { 2066 DRV_LOG(ERR, "Failed to modify VIRTQ for no type set."); 2067 rte_errno = EINVAL; 2068 return -rte_errno; 2069 } 2070 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE) 2071 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 2072 if (attr->mod_fields_bitmap & 2073 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) { 2074 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 2075 attr->dirty_bitmap_mkey); 2076 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 2077 attr->dirty_bitmap_addr); 2078 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 2079 attr->dirty_bitmap_size); 2080 } 2081 if (attr->mod_fields_bitmap & 2082 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE) 2083 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 2084 attr->dirty_bitmap_dump_enable); 2085 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) { 2086 MLX5_SET(virtio_q, virtctx, queue_period_mode, 2087 attr->hw_latency_mode); 2088 MLX5_SET(virtio_q, virtctx, queue_period_us, 2089 attr->hw_max_latency_us); 2090 MLX5_SET(virtio_q, virtctx, queue_max_count, 2091 attr->hw_max_pending_comp); 2092 } 2093 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) { 2094 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2095 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2096 MLX5_SET64(virtio_q, virtctx, available_addr, 2097 attr->available_addr); 2098 } 2099 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX) 2100 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2101 attr->hw_available_index); 2102 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX) 2103 MLX5_SET16(virtio_net_q, virtq, hw_used_index, 2104 attr->hw_used_index); 2105 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE) 2106 MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type); 2107 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0) 2108 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2109 attr->virtio_version_1_0); 2110 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY) 2111 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2112 if (attr->mod_fields_bitmap & 2113 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) { 2114 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2115 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2116 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2117 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2118 } 2119 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) { 2120 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2121 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2122 } 2123 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 2124 out, sizeof(out)); 2125 if (ret) { 2126 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2127 rte_errno = errno; 2128 return -rte_errno; 2129 } 2130 return ret; 2131 } 2132 2133 /** 2134 * Query VIRTQ using DevX API. 2135 * 2136 * @param[in] virtq_obj 2137 * Pointer to virtq object structure. 2138 * @param [in/out] attr 2139 * Pointer to virtq attributes structure. 2140 * 2141 * @return 2142 * 0 on success, a negative errno value otherwise and rte_errno is set. 2143 */ 2144 int 2145 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 2146 struct mlx5_devx_virtq_attr *attr) 2147 { 2148 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2149 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 2150 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 2151 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 2152 int ret; 2153 2154 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2155 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2156 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2157 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2158 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2159 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2160 out, sizeof(out)); 2161 if (ret) { 2162 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2163 rte_errno = errno; 2164 return -errno; 2165 } 2166 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2167 hw_available_index); 2168 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2169 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2170 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2171 virtio_q_context.error_type); 2172 return ret; 2173 } 2174 2175 /** 2176 * Create QP using DevX API. 2177 * 2178 * @param[in] ctx 2179 * Context returned from mlx5 open_device() glue function. 2180 * @param [in] attr 2181 * Pointer to QP attributes structure. 2182 * 2183 * @return 2184 * The DevX object created, NULL otherwise and rte_errno is set. 2185 */ 2186 struct mlx5_devx_obj * 2187 mlx5_devx_cmd_create_qp(void *ctx, 2188 struct mlx5_devx_qp_attr *attr) 2189 { 2190 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2191 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2192 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2193 sizeof(*qp_obj), 2194 0, SOCKET_ID_ANY); 2195 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2196 2197 if (!qp_obj) { 2198 DRV_LOG(ERR, "Failed to allocate QP data."); 2199 rte_errno = ENOMEM; 2200 return NULL; 2201 } 2202 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2203 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2204 MLX5_SET(qpc, qpc, pd, attr->pd); 2205 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2206 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2207 if (attr->uar_index) { 2208 if (attr->mmo) { 2209 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2210 in, qpc_extension_and_pas_list); 2211 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2212 qpc_ext_and_pas_list, qpc_data_extension); 2213 2214 MLX5_SET(create_qp_in, in, qpc_ext, 1); 2215 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2216 } 2217 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2218 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2219 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2220 MLX5_SET(qpc, qpc, log_page_size, 2221 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2222 if (attr->num_of_send_wqbbs) { 2223 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs)); 2224 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2225 MLX5_SET(qpc, qpc, log_sq_size, 2226 rte_log2_u32(attr->num_of_send_wqbbs)); 2227 } else { 2228 MLX5_SET(qpc, qpc, no_sq, 1); 2229 } 2230 if (attr->num_of_receive_wqes) { 2231 MLX5_ASSERT(RTE_IS_POWER_OF_2( 2232 attr->num_of_receive_wqes)); 2233 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2234 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2235 MLX5_LOG_RQ_STRIDE_SHIFT); 2236 MLX5_SET(qpc, qpc, log_rq_size, 2237 rte_log2_u32(attr->num_of_receive_wqes)); 2238 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2239 } else { 2240 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2241 } 2242 if (attr->dbr_umem_valid) { 2243 MLX5_SET(qpc, qpc, dbr_umem_valid, 2244 attr->dbr_umem_valid); 2245 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2246 } 2247 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2248 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2249 attr->wq_umem_offset); 2250 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2251 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2252 } else { 2253 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2254 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2255 MLX5_SET(qpc, qpc, no_sq, 1); 2256 } 2257 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2258 sizeof(out)); 2259 if (!qp_obj->obj) { 2260 mlx5_devx_err_log(out, "create QP", NULL, 0); 2261 mlx5_free(qp_obj); 2262 return NULL; 2263 } 2264 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2265 return qp_obj; 2266 } 2267 2268 /** 2269 * Modify QP using DevX API. 2270 * Currently supports only force loop-back QP. 2271 * 2272 * @param[in] qp 2273 * Pointer to QP object structure. 2274 * @param [in] qp_st_mod_op 2275 * The QP state modification operation. 2276 * @param [in] remote_qp_id 2277 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2278 * 2279 * @return 2280 * 0 on success, a negative errno value otherwise and rte_errno is set. 2281 */ 2282 int 2283 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2284 uint32_t remote_qp_id) 2285 { 2286 union { 2287 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2288 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2289 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2290 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)]; 2291 } in; 2292 union { 2293 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2294 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2295 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2296 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)]; 2297 } out; 2298 void *qpc; 2299 int ret; 2300 unsigned int inlen; 2301 unsigned int outlen; 2302 2303 memset(&in, 0, sizeof(in)); 2304 memset(&out, 0, sizeof(out)); 2305 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2306 switch (qp_st_mod_op) { 2307 case MLX5_CMD_OP_RST2INIT_QP: 2308 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2309 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2310 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2311 MLX5_SET(qpc, qpc, rre, 1); 2312 MLX5_SET(qpc, qpc, rwe, 1); 2313 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2314 inlen = sizeof(in.rst2init); 2315 outlen = sizeof(out.rst2init); 2316 break; 2317 case MLX5_CMD_OP_INIT2RTR_QP: 2318 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2319 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2320 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2321 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2322 MLX5_SET(qpc, qpc, mtu, 1); 2323 MLX5_SET(qpc, qpc, log_msg_max, 30); 2324 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2325 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2326 inlen = sizeof(in.init2rtr); 2327 outlen = sizeof(out.init2rtr); 2328 break; 2329 case MLX5_CMD_OP_RTR2RTS_QP: 2330 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2331 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2332 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16); 2333 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2334 MLX5_SET(qpc, qpc, retry_count, 7); 2335 MLX5_SET(qpc, qpc, rnr_retry, 7); 2336 inlen = sizeof(in.rtr2rts); 2337 outlen = sizeof(out.rtr2rts); 2338 break; 2339 case MLX5_CMD_OP_QP_2RST: 2340 MLX5_SET(2rst_qp_in, &in, qpn, qp->id); 2341 inlen = sizeof(in.qp2rst); 2342 outlen = sizeof(out.qp2rst); 2343 break; 2344 default: 2345 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2346 qp_st_mod_op); 2347 rte_errno = EINVAL; 2348 return -rte_errno; 2349 } 2350 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2351 if (ret) { 2352 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2353 rte_errno = errno; 2354 return -rte_errno; 2355 } 2356 return ret; 2357 } 2358 2359 struct mlx5_devx_obj * 2360 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2361 { 2362 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2363 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2364 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2365 sizeof(*couners_obj), 0, 2366 SOCKET_ID_ANY); 2367 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2368 2369 if (!couners_obj) { 2370 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2371 rte_errno = ENOMEM; 2372 return NULL; 2373 } 2374 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2375 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2376 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2377 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2378 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2379 sizeof(out)); 2380 if (!couners_obj->obj) { 2381 mlx5_devx_err_log(out, "create virtio queue counters Obj", 2382 NULL, 0); 2383 mlx5_free(couners_obj); 2384 return NULL; 2385 } 2386 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2387 return couners_obj; 2388 } 2389 2390 int 2391 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2392 struct mlx5_devx_virtio_q_couners_attr *attr) 2393 { 2394 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2395 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2396 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2397 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2398 virtio_q_counters); 2399 int ret; 2400 2401 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2402 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2403 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2404 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2405 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2406 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2407 sizeof(out)); 2408 if (ret) { 2409 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2410 rte_errno = errno; 2411 return -errno; 2412 } 2413 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2414 received_desc); 2415 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2416 completed_desc); 2417 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2418 error_cqes); 2419 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2420 bad_desc_errors); 2421 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2422 exceed_max_chain); 2423 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2424 invalid_buffer); 2425 return ret; 2426 } 2427 2428 /** 2429 * Create general object of type FLOW_HIT_ASO using DevX API. 2430 * 2431 * @param[in] ctx 2432 * Context returned from mlx5 open_device() glue function. 2433 * @param [in] pd 2434 * PD value to associate the FLOW_HIT_ASO object with. 2435 * 2436 * @return 2437 * The DevX object created, NULL otherwise and rte_errno is set. 2438 */ 2439 struct mlx5_devx_obj * 2440 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2441 { 2442 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2443 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2444 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2445 void *ptr = NULL; 2446 2447 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2448 0, SOCKET_ID_ANY); 2449 if (!flow_hit_aso_obj) { 2450 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2451 rte_errno = ENOMEM; 2452 return NULL; 2453 } 2454 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2455 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2456 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2457 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2458 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2459 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2460 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2461 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2462 out, sizeof(out)); 2463 if (!flow_hit_aso_obj->obj) { 2464 mlx5_devx_err_log(out, "create FLOW_HIT_ASO", NULL, 0); 2465 mlx5_free(flow_hit_aso_obj); 2466 return NULL; 2467 } 2468 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2469 return flow_hit_aso_obj; 2470 } 2471 2472 /* 2473 * Create PD using DevX API. 2474 * 2475 * @param[in] ctx 2476 * Context returned from mlx5 open_device() glue function. 2477 * 2478 * @return 2479 * The DevX object created, NULL otherwise and rte_errno is set. 2480 */ 2481 struct mlx5_devx_obj * 2482 mlx5_devx_cmd_alloc_pd(void *ctx) 2483 { 2484 struct mlx5_devx_obj *ppd = 2485 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2486 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2487 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2488 2489 if (!ppd) { 2490 DRV_LOG(ERR, "Failed to allocate PD data."); 2491 rte_errno = ENOMEM; 2492 return NULL; 2493 } 2494 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2495 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2496 out, sizeof(out)); 2497 if (!ppd->obj) { 2498 mlx5_free(ppd); 2499 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2500 rte_errno = errno; 2501 return NULL; 2502 } 2503 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2504 return ppd; 2505 } 2506 2507 /** 2508 * Create general object of type FLOW_METER_ASO using DevX API. 2509 * 2510 * @param[in] ctx 2511 * Context returned from mlx5 open_device() glue function. 2512 * @param [in] pd 2513 * PD value to associate the FLOW_METER_ASO object with. 2514 * @param [in] log_obj_size 2515 * log_obj_size define to allocate number of 2 * meters 2516 * in one FLOW_METER_ASO object. 2517 * 2518 * @return 2519 * The DevX object created, NULL otherwise and rte_errno is set. 2520 */ 2521 struct mlx5_devx_obj * 2522 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2523 uint32_t log_obj_size) 2524 { 2525 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2526 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2527 struct mlx5_devx_obj *flow_meter_aso_obj; 2528 void *ptr; 2529 2530 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2531 sizeof(*flow_meter_aso_obj), 2532 0, SOCKET_ID_ANY); 2533 if (!flow_meter_aso_obj) { 2534 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2535 rte_errno = ENOMEM; 2536 return NULL; 2537 } 2538 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2539 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2540 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2541 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2542 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2543 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2544 log_obj_size); 2545 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2546 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2547 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2548 ctx, in, sizeof(in), 2549 out, sizeof(out)); 2550 if (!flow_meter_aso_obj->obj) { 2551 mlx5_devx_err_log(out, "create FLOW_METTER_ASO", NULL, 0); 2552 mlx5_free(flow_meter_aso_obj); 2553 return NULL; 2554 } 2555 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2556 out, obj_id); 2557 return flow_meter_aso_obj; 2558 } 2559 2560 /* 2561 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2562 * 2563 * @param[in] ctx 2564 * Context returned from mlx5 open_device() glue function. 2565 * @param [in] pd 2566 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2567 * @param [in] log_obj_size 2568 * log_obj_size to allocate its power of 2 * objects 2569 * in one CONN_TRACK_OFFLOAD bulk allocation. 2570 * 2571 * @return 2572 * The DevX object created, NULL otherwise and rte_errno is set. 2573 */ 2574 struct mlx5_devx_obj * 2575 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2576 uint32_t log_obj_size) 2577 { 2578 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2579 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2580 struct mlx5_devx_obj *ct_aso_obj; 2581 void *ptr; 2582 2583 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2584 0, SOCKET_ID_ANY); 2585 if (!ct_aso_obj) { 2586 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2587 rte_errno = ENOMEM; 2588 return NULL; 2589 } 2590 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2591 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2592 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2593 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2594 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2595 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2596 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2597 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2598 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2599 out, sizeof(out)); 2600 if (!ct_aso_obj->obj) { 2601 mlx5_devx_err_log(out, "create CONN_TRACK_OFFLOAD", NULL, 0); 2602 mlx5_free(ct_aso_obj); 2603 return NULL; 2604 } 2605 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2606 return ct_aso_obj; 2607 } 2608 2609 /** 2610 * Create general object of type GENEVE TLV option using DevX API. 2611 * 2612 * @param[in] ctx 2613 * Context returned from mlx5 open_device() glue function. 2614 * @param [in] class 2615 * TLV option variable value of class 2616 * @param [in] type 2617 * TLV option variable value of type 2618 * @param [in] len 2619 * TLV option variable value of len 2620 * 2621 * @return 2622 * The DevX object created, NULL otherwise and rte_errno is set. 2623 */ 2624 struct mlx5_devx_obj * 2625 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2626 uint16_t class, uint8_t type, uint8_t len) 2627 { 2628 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2629 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2630 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2631 sizeof(*geneve_tlv_opt_obj), 2632 0, SOCKET_ID_ANY); 2633 2634 if (!geneve_tlv_opt_obj) { 2635 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2636 rte_errno = ENOMEM; 2637 return NULL; 2638 } 2639 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2640 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2641 geneve_tlv_opt); 2642 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2643 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2644 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2645 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2646 MLX5_SET(geneve_tlv_option, opt, option_class, 2647 rte_be_to_cpu_16(class)); 2648 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2649 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2650 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2651 sizeof(in), out, sizeof(out)); 2652 if (!geneve_tlv_opt_obj->obj) { 2653 mlx5_devx_err_log(out, "create GENEVE TLV", NULL, 0); 2654 mlx5_free(geneve_tlv_opt_obj); 2655 return NULL; 2656 } 2657 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2658 return geneve_tlv_opt_obj; 2659 } 2660 2661 int 2662 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2663 { 2664 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2665 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2666 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2667 int rc; 2668 void *rq_ctx; 2669 2670 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2671 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2672 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2673 if (rc) { 2674 rte_errno = errno; 2675 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2676 "rc = %d, errno = %d.", rc, errno); 2677 return -rc; 2678 }; 2679 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2680 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2681 return 0; 2682 #else 2683 (void)wq; 2684 (void)counter_set_id; 2685 return -ENOTSUP; 2686 #endif 2687 } 2688 2689 /* 2690 * Allocate queue counters via devx interface. 2691 * 2692 * @param[in] ctx 2693 * Context returned from mlx5 open_device() glue function. 2694 * 2695 * @return 2696 * Pointer to counter object on success, a NULL value otherwise and 2697 * rte_errno is set. 2698 */ 2699 struct mlx5_devx_obj * 2700 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2701 { 2702 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2703 SOCKET_ID_ANY); 2704 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2705 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2706 2707 if (!dcs) { 2708 rte_errno = ENOMEM; 2709 return NULL; 2710 } 2711 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2712 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2713 sizeof(out)); 2714 if (!dcs->obj) { 2715 mlx5_devx_err_log(out, "create q counter set", NULL, 0); 2716 mlx5_free(dcs); 2717 return NULL; 2718 } 2719 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2720 return dcs; 2721 } 2722 2723 /** 2724 * Query queue counters values. 2725 * 2726 * @param[in] dcs 2727 * devx object of the queue counter set. 2728 * @param[in] clear 2729 * Whether hardware should clear the counters after the query or not. 2730 * @param[out] out_of_buffers 2731 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2732 * 2733 * @return 2734 * 0 on success, a negative value otherwise. 2735 */ 2736 int 2737 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2738 uint32_t *out_of_buffers) 2739 { 2740 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2741 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2742 int rc; 2743 2744 MLX5_SET(query_q_counter_in, in, opcode, 2745 MLX5_CMD_OP_QUERY_Q_COUNTER); 2746 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2747 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2748 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2749 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2750 sizeof(out)); 2751 if (rc) { 2752 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2753 rte_errno = rc; 2754 return -rc; 2755 } 2756 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2757 return 0; 2758 } 2759 2760 /** 2761 * Create general object of type DEK using DevX API. 2762 * 2763 * @param[in] ctx 2764 * Context returned from mlx5 open_device() glue function. 2765 * @param [in] attr 2766 * Pointer to DEK attributes structure. 2767 * 2768 * @return 2769 * The DevX object created, NULL otherwise and rte_errno is set. 2770 */ 2771 struct mlx5_devx_obj * 2772 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2773 { 2774 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2775 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2776 struct mlx5_devx_obj *dek_obj = NULL; 2777 void *ptr = NULL, *key_addr = NULL; 2778 2779 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2780 0, SOCKET_ID_ANY); 2781 if (dek_obj == NULL) { 2782 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2783 rte_errno = ENOMEM; 2784 return NULL; 2785 } 2786 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2787 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2788 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2789 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2790 MLX5_GENERAL_OBJ_TYPE_DEK); 2791 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2792 MLX5_SET(dek, ptr, key_size, attr->key_size); 2793 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2794 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2795 MLX5_SET(dek, ptr, pd, attr->pd); 2796 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2797 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2798 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2799 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2800 out, sizeof(out)); 2801 if (dek_obj->obj == NULL) { 2802 mlx5_devx_err_log(out, "create DEK", NULL, 0); 2803 mlx5_free(dek_obj); 2804 return NULL; 2805 } 2806 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2807 return dek_obj; 2808 } 2809 2810 /** 2811 * Create general object of type IMPORT_KEK using DevX API. 2812 * 2813 * @param[in] ctx 2814 * Context returned from mlx5 open_device() glue function. 2815 * @param [in] attr 2816 * Pointer to IMPORT_KEK attributes structure. 2817 * 2818 * @return 2819 * The DevX object created, NULL otherwise and rte_errno is set. 2820 */ 2821 struct mlx5_devx_obj * 2822 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 2823 struct mlx5_devx_import_kek_attr *attr) 2824 { 2825 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 2826 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2827 struct mlx5_devx_obj *import_kek_obj = NULL; 2828 void *ptr = NULL, *key_addr = NULL; 2829 2830 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 2831 0, SOCKET_ID_ANY); 2832 if (import_kek_obj == NULL) { 2833 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 2834 rte_errno = ENOMEM; 2835 return NULL; 2836 } 2837 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 2838 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2839 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2840 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2841 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 2842 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 2843 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 2844 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 2845 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2846 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2847 out, sizeof(out)); 2848 if (import_kek_obj->obj == NULL) { 2849 mlx5_devx_err_log(out, "create IMPORT_KEK", NULL, 0); 2850 mlx5_free(import_kek_obj); 2851 return NULL; 2852 } 2853 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2854 return import_kek_obj; 2855 } 2856 2857 /** 2858 * Create general object of type CREDENTIAL using DevX API. 2859 * 2860 * @param[in] ctx 2861 * Context returned from mlx5 open_device() glue function. 2862 * @param [in] attr 2863 * Pointer to CREDENTIAL attributes structure. 2864 * 2865 * @return 2866 * The DevX object created, NULL otherwise and rte_errno is set. 2867 */ 2868 struct mlx5_devx_obj * 2869 mlx5_devx_cmd_create_credential_obj(void *ctx, 2870 struct mlx5_devx_credential_attr *attr) 2871 { 2872 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 2873 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2874 struct mlx5_devx_obj *credential_obj = NULL; 2875 void *ptr = NULL, *credential_addr = NULL; 2876 2877 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 2878 0, SOCKET_ID_ANY); 2879 if (credential_obj == NULL) { 2880 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 2881 rte_errno = ENOMEM; 2882 return NULL; 2883 } 2884 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 2885 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2886 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2887 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2888 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 2889 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 2890 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 2891 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 2892 memcpy(credential_addr, (void *)(attr->credential), 2893 MLX5_CRYPTO_CREDENTIAL_SIZE); 2894 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2895 out, sizeof(out)); 2896 if (credential_obj->obj == NULL) { 2897 mlx5_devx_err_log(out, "create CREDENTIAL", NULL, 0); 2898 mlx5_free(credential_obj); 2899 return NULL; 2900 } 2901 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2902 return credential_obj; 2903 } 2904 2905 /** 2906 * Create general object of type CRYPTO_LOGIN using DevX API. 2907 * 2908 * @param[in] ctx 2909 * Context returned from mlx5 open_device() glue function. 2910 * @param [in] attr 2911 * Pointer to CRYPTO_LOGIN attributes structure. 2912 * 2913 * @return 2914 * The DevX object created, NULL otherwise and rte_errno is set. 2915 */ 2916 struct mlx5_devx_obj * 2917 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 2918 struct mlx5_devx_crypto_login_attr *attr) 2919 { 2920 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 2921 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2922 struct mlx5_devx_obj *crypto_login_obj = NULL; 2923 void *ptr = NULL, *credential_addr = NULL; 2924 2925 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 2926 0, SOCKET_ID_ANY); 2927 if (crypto_login_obj == NULL) { 2928 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 2929 rte_errno = ENOMEM; 2930 return NULL; 2931 } 2932 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 2933 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2934 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2935 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2936 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 2937 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 2938 MLX5_SET(crypto_login, ptr, credential_pointer, 2939 attr->credential_pointer); 2940 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 2941 attr->session_import_kek_ptr); 2942 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 2943 memcpy(credential_addr, (void *)(attr->credential), 2944 MLX5_CRYPTO_CREDENTIAL_SIZE); 2945 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2946 out, sizeof(out)); 2947 if (crypto_login_obj->obj == NULL) { 2948 mlx5_devx_err_log(out, "create CRYPTO_LOGIN", NULL, 0); 2949 mlx5_free(crypto_login_obj); 2950 return NULL; 2951 } 2952 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2953 return crypto_login_obj; 2954 } 2955 2956 /** 2957 * Query LAG context. 2958 * 2959 * @param[in] ctx 2960 * Pointer to ibv_context, returned from mlx5dv_open_device. 2961 * @param[out] lag_ctx 2962 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 2963 * 2964 * @return 2965 * 0 on success, a negative value otherwise. 2966 */ 2967 int 2968 mlx5_devx_cmd_query_lag(void *ctx, 2969 struct mlx5_devx_lag_context *lag_ctx) 2970 { 2971 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 2972 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 2973 void *lctx; 2974 int rc; 2975 2976 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 2977 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 2978 if (rc) 2979 goto error; 2980 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 2981 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 2982 fdb_selection_mode); 2983 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 2984 port_select_mode); 2985 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 2986 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 2987 tx_remap_affinity_2); 2988 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 2989 tx_remap_affinity_1); 2990 return 0; 2991 error: 2992 rc = (rc > 0) ? -rc : rc; 2993 return rc; 2994 } 2995