1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 static void * 17 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, 18 int *err, uint32_t flags) 19 { 20 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); 21 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); 22 int status, syndrome, rc; 23 24 if (err) 25 *err = 0; 26 memset(in, 0, size_in); 27 memset(out, 0, size_out); 28 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 29 MLX5_SET(query_hca_cap_in, in, op_mod, flags); 30 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); 31 if (rc) { 32 DRV_LOG(ERR, 33 "Failed to query devx HCA capabilities func %#02x", 34 flags >> 1); 35 if (err) 36 *err = rc > 0 ? -rc : rc; 37 return NULL; 38 } 39 status = MLX5_GET(query_hca_cap_out, out, status); 40 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 41 if (status) { 42 DRV_LOG(ERR, 43 "Failed to query devx HCA capabilities func %#02x status %x, syndrome = %x", 44 flags >> 1, status, syndrome); 45 if (err) 46 *err = -1; 47 return NULL; 48 } 49 return MLX5_ADDR_OF(query_hca_cap_out, out, capability); 50 } 51 52 /** 53 * Perform read access to the registers. Reads data from register 54 * and writes ones to the specified buffer. 55 * 56 * @param[in] ctx 57 * Context returned from mlx5 open_device() glue function. 58 * @param[in] reg_id 59 * Register identifier according to the PRM. 60 * @param[in] arg 61 * Register access auxiliary parameter according to the PRM. 62 * @param[out] data 63 * Pointer to the buffer to store read data. 64 * @param[in] dw_cnt 65 * Buffer size in double words. 66 * 67 * @return 68 * 0 on success, a negative value otherwise. 69 */ 70 int 71 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 72 uint32_t *data, uint32_t dw_cnt) 73 { 74 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 75 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 76 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 77 int status, rc; 78 79 MLX5_ASSERT(data && dw_cnt); 80 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 81 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 82 DRV_LOG(ERR, "Not enough buffer for register read data"); 83 return -1; 84 } 85 MLX5_SET(access_register_in, in, opcode, 86 MLX5_CMD_OP_ACCESS_REGISTER_USER); 87 MLX5_SET(access_register_in, in, op_mod, 88 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 89 MLX5_SET(access_register_in, in, register_id, reg_id); 90 MLX5_SET(access_register_in, in, argument, arg); 91 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 92 MLX5_ST_SZ_BYTES(access_register_out) + 93 sizeof(uint32_t) * dw_cnt); 94 if (rc) 95 goto error; 96 status = MLX5_GET(access_register_out, out, status); 97 if (status) { 98 int syndrome = MLX5_GET(access_register_out, out, syndrome); 99 100 DRV_LOG(DEBUG, "Failed to read access NIC register 0x%X, " 101 "status %x, syndrome = %x", 102 reg_id, status, syndrome); 103 return -1; 104 } 105 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 106 dw_cnt * sizeof(uint32_t)); 107 return 0; 108 error: 109 rc = (rc > 0) ? -rc : rc; 110 return rc; 111 } 112 113 /** 114 * Perform write access to the registers. 115 * 116 * @param[in] ctx 117 * Context returned from mlx5 open_device() glue function. 118 * @param[in] reg_id 119 * Register identifier according to the PRM. 120 * @param[in] arg 121 * Register access auxiliary parameter according to the PRM. 122 * @param[out] data 123 * Pointer to the buffer containing data to write. 124 * @param[in] dw_cnt 125 * Buffer size in double words (32bit units). 126 * 127 * @return 128 * 0 on success, a negative value otherwise. 129 */ 130 int 131 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 132 uint32_t *data, uint32_t dw_cnt) 133 { 134 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 135 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 136 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 137 int status, rc; 138 void *ptr; 139 140 MLX5_ASSERT(data && dw_cnt); 141 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 142 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 143 DRV_LOG(ERR, "Data to write exceeds max size"); 144 return -1; 145 } 146 MLX5_SET(access_register_in, in, opcode, 147 MLX5_CMD_OP_ACCESS_REGISTER_USER); 148 MLX5_SET(access_register_in, in, op_mod, 149 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 150 MLX5_SET(access_register_in, in, register_id, reg_id); 151 MLX5_SET(access_register_in, in, argument, arg); 152 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 153 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 154 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 155 156 rc = mlx5_glue->devx_general_cmd(ctx, in, 157 MLX5_ST_SZ_BYTES(access_register_in) + 158 dw_cnt * sizeof(uint32_t), 159 out, sizeof(out)); 160 if (rc) 161 goto error; 162 status = MLX5_GET(access_register_out, out, status); 163 if (status) { 164 int syndrome = MLX5_GET(access_register_out, out, syndrome); 165 166 DRV_LOG(DEBUG, "Failed to write access NIC register 0x%X, " 167 "status %x, syndrome = %x", 168 reg_id, status, syndrome); 169 return -1; 170 } 171 return 0; 172 error: 173 rc = (rc > 0) ? -rc : rc; 174 return rc; 175 } 176 177 /** 178 * Allocate flow counters via devx interface. 179 * 180 * @param[in] ctx 181 * Context returned from mlx5 open_device() glue function. 182 * @param dcs 183 * Pointer to counters properties structure to be filled by the routine. 184 * @param bulk_n_128 185 * Bulk counter numbers in 128 counters units. 186 * 187 * @return 188 * Pointer to counter object on success, a negative value otherwise and 189 * rte_errno is set. 190 */ 191 struct mlx5_devx_obj * 192 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 193 { 194 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 195 0, SOCKET_ID_ANY); 196 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 197 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 198 199 if (!dcs) { 200 rte_errno = ENOMEM; 201 return NULL; 202 } 203 MLX5_SET(alloc_flow_counter_in, in, opcode, 204 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 205 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 206 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 207 sizeof(in), out, sizeof(out)); 208 if (!dcs->obj) { 209 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 210 rte_errno = errno; 211 mlx5_free(dcs); 212 return NULL; 213 } 214 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 215 return dcs; 216 } 217 218 /** 219 * Query flow counters values. 220 * 221 * @param[in] dcs 222 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 223 * @param[in] clear 224 * Whether hardware should clear the counters after the query or not. 225 * @param[in] n_counters 226 * 0 in case of 1 counter to read, otherwise the counter number to read. 227 * @param pkts 228 * The number of packets that matched the flow. 229 * @param bytes 230 * The number of bytes that matched the flow. 231 * @param mkey 232 * The mkey key for batch query. 233 * @param addr 234 * The address in the mkey range for batch query. 235 * @param cmd_comp 236 * The completion object for asynchronous batch query. 237 * @param async_id 238 * The ID to be returned in the asynchronous batch query response. 239 * 240 * @return 241 * 0 on success, a negative value otherwise. 242 */ 243 int 244 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 245 int clear, uint32_t n_counters, 246 uint64_t *pkts, uint64_t *bytes, 247 uint32_t mkey, void *addr, 248 void *cmd_comp, 249 uint64_t async_id) 250 { 251 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 252 MLX5_ST_SZ_BYTES(traffic_counter); 253 uint32_t out[out_len]; 254 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 255 void *stats; 256 int rc; 257 258 MLX5_SET(query_flow_counter_in, in, opcode, 259 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 260 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 261 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 262 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 263 264 if (n_counters) { 265 MLX5_SET(query_flow_counter_in, in, num_of_counters, 266 n_counters); 267 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 268 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 269 MLX5_SET64(query_flow_counter_in, in, address, 270 (uint64_t)(uintptr_t)addr); 271 } 272 if (!cmd_comp) 273 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 274 out_len); 275 else 276 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 277 out_len, async_id, 278 cmd_comp); 279 if (rc) { 280 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 281 rte_errno = rc; 282 return -rc; 283 } 284 if (!n_counters) { 285 stats = MLX5_ADDR_OF(query_flow_counter_out, 286 out, flow_statistics); 287 *pkts = MLX5_GET64(traffic_counter, stats, packets); 288 *bytes = MLX5_GET64(traffic_counter, stats, octets); 289 } 290 return 0; 291 } 292 293 /** 294 * Create a new mkey. 295 * 296 * @param[in] ctx 297 * Context returned from mlx5 open_device() glue function. 298 * @param[in] attr 299 * Attributes of the requested mkey. 300 * 301 * @return 302 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 303 * is set. 304 */ 305 struct mlx5_devx_obj * 306 mlx5_devx_cmd_mkey_create(void *ctx, 307 struct mlx5_devx_mkey_attr *attr) 308 { 309 struct mlx5_klm *klm_array = attr->klm_array; 310 int klm_num = attr->klm_num; 311 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 312 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 313 uint32_t in[in_size_dw]; 314 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 315 void *mkc; 316 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 317 0, SOCKET_ID_ANY); 318 size_t pgsize; 319 uint32_t translation_size; 320 321 if (!mkey) { 322 rte_errno = ENOMEM; 323 return NULL; 324 } 325 memset(in, 0, in_size_dw * 4); 326 pgsize = rte_mem_page_size(); 327 if (pgsize == (size_t)-1) { 328 mlx5_free(mkey); 329 DRV_LOG(ERR, "Failed to get page size"); 330 rte_errno = ENOMEM; 331 return NULL; 332 } 333 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 334 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 335 if (klm_num > 0) { 336 int i; 337 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 338 klm_pas_mtt); 339 translation_size = RTE_ALIGN(klm_num, 4); 340 for (i = 0; i < klm_num; i++) { 341 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 342 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 343 MLX5_SET64(klm, klm, address, klm_array[i].address); 344 klm += MLX5_ST_SZ_BYTES(klm); 345 } 346 for (; i < (int)translation_size; i++) { 347 MLX5_SET(klm, klm, mkey, 0x0); 348 MLX5_SET64(klm, klm, address, 0x0); 349 klm += MLX5_ST_SZ_BYTES(klm); 350 } 351 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 352 MLX5_MKC_ACCESS_MODE_KLM_FBS : 353 MLX5_MKC_ACCESS_MODE_KLM); 354 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 355 } else { 356 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 357 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 358 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 359 } 360 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 361 translation_size); 362 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 363 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 364 MLX5_SET(mkc, mkc, lw, 0x1); 365 MLX5_SET(mkc, mkc, lr, 0x1); 366 if (attr->set_remote_rw) { 367 MLX5_SET(mkc, mkc, rw, 0x1); 368 MLX5_SET(mkc, mkc, rr, 0x1); 369 } 370 MLX5_SET(mkc, mkc, qpn, 0xffffff); 371 MLX5_SET(mkc, mkc, pd, attr->pd); 372 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 373 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 374 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 375 MLX5_SET(mkc, mkc, relaxed_ordering_write, 376 attr->relaxed_ordering_write); 377 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 378 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 379 MLX5_SET64(mkc, mkc, len, attr->size); 380 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 381 if (attr->crypto_en) { 382 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 383 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 384 } 385 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 386 sizeof(out)); 387 if (!mkey->obj) { 388 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d", 389 klm_num ? "an in" : "a ", errno); 390 rte_errno = errno; 391 mlx5_free(mkey); 392 return NULL; 393 } 394 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 395 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 396 return mkey; 397 } 398 399 /** 400 * Get status of devx command response. 401 * Mainly used for asynchronous commands. 402 * 403 * @param[in] out 404 * The out response buffer. 405 * 406 * @return 407 * 0 on success, non-zero value otherwise. 408 */ 409 int 410 mlx5_devx_get_out_command_status(void *out) 411 { 412 int status; 413 414 if (!out) 415 return -EINVAL; 416 status = MLX5_GET(query_flow_counter_out, out, status); 417 if (status) { 418 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 419 420 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 421 syndrome); 422 } 423 return status; 424 } 425 426 /** 427 * Destroy any object allocated by a Devx API. 428 * 429 * @param[in] obj 430 * Pointer to a general object. 431 * 432 * @return 433 * 0 on success, a negative value otherwise. 434 */ 435 int 436 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 437 { 438 int ret; 439 440 if (!obj) 441 return 0; 442 ret = mlx5_glue->devx_obj_destroy(obj->obj); 443 mlx5_free(obj); 444 return ret; 445 } 446 447 /** 448 * Query NIC vport context. 449 * Fills minimal inline attribute. 450 * 451 * @param[in] ctx 452 * ibv contexts returned from mlx5dv_open_device. 453 * @param[in] vport 454 * vport index 455 * @param[out] attr 456 * Attributes device values. 457 * 458 * @return 459 * 0 on success, a negative value otherwise. 460 */ 461 static int 462 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 463 unsigned int vport, 464 struct mlx5_hca_attr *attr) 465 { 466 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 467 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 468 void *vctx; 469 int status, syndrome, rc; 470 471 /* Query NIC vport context to determine inline mode. */ 472 MLX5_SET(query_nic_vport_context_in, in, opcode, 473 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 474 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 475 if (vport) 476 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 477 rc = mlx5_glue->devx_general_cmd(ctx, 478 in, sizeof(in), 479 out, sizeof(out)); 480 if (rc) 481 goto error; 482 status = MLX5_GET(query_nic_vport_context_out, out, status); 483 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 484 if (status) { 485 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 486 "status %x, syndrome = %x", status, syndrome); 487 return -1; 488 } 489 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 490 nic_vport_context); 491 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 492 min_wqe_inline_mode); 493 return 0; 494 error: 495 rc = (rc > 0) ? -rc : rc; 496 return rc; 497 } 498 499 /** 500 * Query NIC vDPA attributes. 501 * 502 * @param[in] ctx 503 * Context returned from mlx5 open_device() glue function. 504 * @param[out] vdpa_attr 505 * vDPA Attributes structure to fill. 506 */ 507 static void 508 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 509 struct mlx5_hca_vdpa_attr *vdpa_attr) 510 { 511 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 512 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 513 void *hcattr; 514 515 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, 516 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 517 MLX5_HCA_CAP_OPMOD_GET_CUR); 518 if (!hcattr) { 519 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities"); 520 vdpa_attr->valid = 0; 521 } else { 522 vdpa_attr->valid = 1; 523 vdpa_attr->desc_tunnel_offload_type = 524 MLX5_GET(virtio_emulation_cap, hcattr, 525 desc_tunnel_offload_type); 526 vdpa_attr->eth_frame_offload_type = 527 MLX5_GET(virtio_emulation_cap, hcattr, 528 eth_frame_offload_type); 529 vdpa_attr->virtio_version_1_0 = 530 MLX5_GET(virtio_emulation_cap, hcattr, 531 virtio_version_1_0); 532 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 533 tso_ipv4); 534 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 535 tso_ipv6); 536 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 537 tx_csum); 538 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 539 rx_csum); 540 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 541 event_mode); 542 vdpa_attr->virtio_queue_type = 543 MLX5_GET(virtio_emulation_cap, hcattr, 544 virtio_queue_type); 545 vdpa_attr->log_doorbell_stride = 546 MLX5_GET(virtio_emulation_cap, hcattr, 547 log_doorbell_stride); 548 vdpa_attr->log_doorbell_bar_size = 549 MLX5_GET(virtio_emulation_cap, hcattr, 550 log_doorbell_bar_size); 551 vdpa_attr->doorbell_bar_offset = 552 MLX5_GET64(virtio_emulation_cap, hcattr, 553 doorbell_bar_offset); 554 vdpa_attr->max_num_virtio_queues = 555 MLX5_GET(virtio_emulation_cap, hcattr, 556 max_num_virtio_queues); 557 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 558 umem_1_buffer_param_a); 559 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 560 umem_1_buffer_param_b); 561 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 562 umem_2_buffer_param_a); 563 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 564 umem_2_buffer_param_b); 565 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 566 umem_3_buffer_param_a); 567 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 568 umem_3_buffer_param_b); 569 } 570 } 571 572 int 573 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 574 uint32_t ids[], uint32_t num) 575 { 576 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 577 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 578 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 579 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 580 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 581 int ret; 582 uint32_t idx = 0; 583 uint32_t i; 584 585 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 586 rte_errno = EINVAL; 587 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 588 return -rte_errno; 589 } 590 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 591 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 592 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 593 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 594 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 595 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 596 out, sizeof(out)); 597 if (ret) { 598 rte_errno = ret; 599 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 600 (void *)flex_obj); 601 return -rte_errno; 602 } 603 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 604 void *s_off = (void *)((char *)sample + i * 605 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 606 uint32_t en; 607 608 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 609 flow_match_sample_en); 610 if (!en) 611 continue; 612 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 613 flow_match_sample_field_id); 614 } 615 if (num != idx) { 616 rte_errno = EINVAL; 617 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 618 return -rte_errno; 619 } 620 return ret; 621 } 622 623 struct mlx5_devx_obj * 624 mlx5_devx_cmd_create_flex_parser(void *ctx, 625 struct mlx5_devx_graph_node_attr *data) 626 { 627 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 628 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 629 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 630 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 631 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 632 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 633 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 634 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 635 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 636 uint32_t i; 637 638 if (!parse_flex_obj) { 639 DRV_LOG(ERR, "Failed to allocate flex parser data."); 640 rte_errno = ENOMEM; 641 return NULL; 642 } 643 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 644 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 645 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 646 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 647 MLX5_SET(parse_graph_flex, flex, header_length_mode, 648 data->header_length_mode); 649 MLX5_SET64(parse_graph_flex, flex, modify_field_select, 650 data->modify_field_select); 651 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 652 data->header_length_base_value); 653 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 654 data->header_length_field_offset); 655 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 656 data->header_length_field_shift); 657 MLX5_SET(parse_graph_flex, flex, next_header_field_offset, 658 data->next_header_field_offset); 659 MLX5_SET(parse_graph_flex, flex, next_header_field_size, 660 data->next_header_field_size); 661 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 662 data->header_length_field_mask); 663 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 664 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 665 void *s_off = (void *)((char *)sample + i * 666 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 667 668 if (!s->flow_match_sample_en) 669 continue; 670 MLX5_SET(parse_graph_flow_match_sample, s_off, 671 flow_match_sample_en, !!s->flow_match_sample_en); 672 MLX5_SET(parse_graph_flow_match_sample, s_off, 673 flow_match_sample_field_offset, 674 s->flow_match_sample_field_offset); 675 MLX5_SET(parse_graph_flow_match_sample, s_off, 676 flow_match_sample_offset_mode, 677 s->flow_match_sample_offset_mode); 678 MLX5_SET(parse_graph_flow_match_sample, s_off, 679 flow_match_sample_field_offset_mask, 680 s->flow_match_sample_field_offset_mask); 681 MLX5_SET(parse_graph_flow_match_sample, s_off, 682 flow_match_sample_field_offset_shift, 683 s->flow_match_sample_field_offset_shift); 684 MLX5_SET(parse_graph_flow_match_sample, s_off, 685 flow_match_sample_field_base_offset, 686 s->flow_match_sample_field_base_offset); 687 MLX5_SET(parse_graph_flow_match_sample, s_off, 688 flow_match_sample_tunnel_mode, 689 s->flow_match_sample_tunnel_mode); 690 } 691 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 692 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 693 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 694 void *in_off = (void *)((char *)in_arc + i * 695 MLX5_ST_SZ_BYTES(parse_graph_arc)); 696 void *out_off = (void *)((char *)out_arc + i * 697 MLX5_ST_SZ_BYTES(parse_graph_arc)); 698 699 if (ia->arc_parse_graph_node != 0) { 700 MLX5_SET(parse_graph_arc, in_off, 701 compare_condition_value, 702 ia->compare_condition_value); 703 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 704 ia->start_inner_tunnel); 705 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 706 ia->arc_parse_graph_node); 707 MLX5_SET(parse_graph_arc, in_off, 708 parse_graph_node_handle, 709 ia->parse_graph_node_handle); 710 } 711 if (oa->arc_parse_graph_node != 0) { 712 MLX5_SET(parse_graph_arc, out_off, 713 compare_condition_value, 714 oa->compare_condition_value); 715 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 716 oa->start_inner_tunnel); 717 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 718 oa->arc_parse_graph_node); 719 MLX5_SET(parse_graph_arc, out_off, 720 parse_graph_node_handle, 721 oa->parse_graph_node_handle); 722 } 723 } 724 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 725 out, sizeof(out)); 726 if (!parse_flex_obj->obj) { 727 rte_errno = errno; 728 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 729 "by using DevX."); 730 mlx5_free(parse_flex_obj); 731 return NULL; 732 } 733 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 734 return parse_flex_obj; 735 } 736 737 static int 738 mlx5_devx_cmd_query_hca_parse_graph_node_cap 739 (void *ctx, struct mlx5_hca_flex_attr *attr) 740 { 741 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 742 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 743 void *hcattr; 744 int rc; 745 746 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 747 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | 748 MLX5_HCA_CAP_OPMOD_GET_CUR); 749 if (!hcattr) 750 return rc; 751 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); 752 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); 753 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, 754 header_length_mode); 755 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, 756 sample_offset_mode); 757 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, 758 max_num_arc_in); 759 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, 760 max_num_arc_out); 761 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, 762 max_num_sample); 763 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, 764 sample_id_in_out); 765 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, 766 max_base_header_length); 767 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, 768 max_sample_base_offset); 769 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, 770 max_next_header_offset); 771 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, 772 header_length_mask_width); 773 /* Get the max supported samples from HCA CAP 2 */ 774 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 775 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 776 MLX5_HCA_CAP_OPMOD_GET_CUR); 777 if (!hcattr) 778 return rc; 779 attr->max_num_prog_sample = 780 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); 781 return 0; 782 } 783 784 static int 785 mlx5_devx_query_pkt_integrity_match(void *hcattr) 786 { 787 return MLX5_GET(flow_table_nic_cap, hcattr, 788 ft_field_support_2_nic_receive.inner_l3_ok) && 789 MLX5_GET(flow_table_nic_cap, hcattr, 790 ft_field_support_2_nic_receive.inner_l4_ok) && 791 MLX5_GET(flow_table_nic_cap, hcattr, 792 ft_field_support_2_nic_receive.outer_l3_ok) && 793 MLX5_GET(flow_table_nic_cap, hcattr, 794 ft_field_support_2_nic_receive.outer_l4_ok) && 795 MLX5_GET(flow_table_nic_cap, hcattr, 796 ft_field_support_2_nic_receive 797 .inner_ipv4_checksum_ok) && 798 MLX5_GET(flow_table_nic_cap, hcattr, 799 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 800 MLX5_GET(flow_table_nic_cap, hcattr, 801 ft_field_support_2_nic_receive 802 .outer_ipv4_checksum_ok) && 803 MLX5_GET(flow_table_nic_cap, hcattr, 804 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 805 } 806 807 /** 808 * Query HCA attributes. 809 * Using those attributes we can check on run time if the device 810 * is having the required capabilities. 811 * 812 * @param[in] ctx 813 * Context returned from mlx5 open_device() glue function. 814 * @param[out] attr 815 * Attributes device values. 816 * 817 * @return 818 * 0 on success, a negative value otherwise. 819 */ 820 int 821 mlx5_devx_cmd_query_hca_attr(void *ctx, 822 struct mlx5_hca_attr *attr) 823 { 824 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 825 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 826 uint64_t general_obj_types_supported = 0; 827 void *hcattr; 828 int rc, i; 829 830 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 831 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 832 MLX5_HCA_CAP_OPMOD_GET_CUR); 833 if (!hcattr) 834 return rc; 835 attr->flow_counter_bulk_alloc_bitmap = 836 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 837 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 838 flow_counters_dump); 839 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp); 840 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp); 841 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 842 log_max_rqt_size); 843 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 844 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 845 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 846 log_max_hairpin_queues); 847 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 848 log_max_hairpin_wq_data_sz); 849 attr->log_max_hairpin_num_packets = MLX5_GET 850 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 851 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 852 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 853 relaxed_ordering_write); 854 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 855 relaxed_ordering_read); 856 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 857 access_register_user); 858 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 859 eth_net_offloads); 860 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 861 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 862 flex_parser_protocols); 863 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 864 max_geneve_tlv_options); 865 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 866 max_geneve_tlv_option_data_len); 867 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 868 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 869 general_obj_types) & 870 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 871 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 872 general_obj_types) & 873 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 874 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 875 general_obj_types) & 876 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 877 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 878 general_obj_types) & 879 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 880 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 881 wqe_index_ignore_cap); 882 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 883 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 884 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 885 log_max_static_sq_wq); 886 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 887 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 888 device_frequency_khz); 889 attr->scatter_fcs_w_decap_disable = 890 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 891 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 892 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 893 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 894 attr->steering_format_version = 895 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 896 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 897 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 898 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 899 regexp_num_of_engines); 900 /* Read the general_obj_types bitmap and extract the relevant bits. */ 901 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 902 general_obj_types); 903 attr->vdpa.valid = !!(general_obj_types_supported & 904 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 905 attr->vdpa.queue_counters_valid = 906 !!(general_obj_types_supported & 907 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 908 attr->parse_graph_flex_node = 909 !!(general_obj_types_supported & 910 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 911 attr->flow_hit_aso = !!(general_obj_types_supported & 912 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 913 attr->geneve_tlv_opt = !!(general_obj_types_supported & 914 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 915 attr->dek = !!(general_obj_types_supported & 916 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 917 attr->import_kek = !!(general_obj_types_supported & 918 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 919 attr->credential = !!(general_obj_types_supported & 920 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 921 attr->crypto_login = !!(general_obj_types_supported & 922 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 923 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 924 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 925 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 926 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 927 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 928 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 929 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 930 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 931 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 932 attr->reg_c_preserve = 933 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 934 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 935 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 936 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 937 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 938 compress_mmo_sq); 939 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 940 decompress_mmo_sq); 941 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 942 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 943 compress_mmo_qp); 944 attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 945 decompress_mmo_qp); 946 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 947 compress_min_block_size); 948 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 949 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 950 log_compress_mmo_size); 951 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 952 log_decompress_mmo_size); 953 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 954 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 955 mini_cqe_resp_flow_tag); 956 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 957 mini_cqe_resp_l3_l4_tag); 958 attr->umr_indirect_mkey_disabled = 959 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 960 attr->umr_modify_entity_size_disabled = 961 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 962 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 963 if (attr->crypto) 964 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts); 965 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 966 general_obj_types) & 967 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 968 attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); 969 if (attr->qos.sup) { 970 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 971 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 972 MLX5_HCA_CAP_OPMOD_GET_CUR); 973 if (!hcattr) { 974 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); 975 return rc; 976 } 977 attr->qos.flow_meter_old = 978 MLX5_GET(qos_cap, hcattr, flow_meter_old); 979 attr->qos.log_max_flow_meter = 980 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 981 attr->qos.flow_meter_reg_c_ids = 982 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 983 attr->qos.flow_meter = 984 MLX5_GET(qos_cap, hcattr, flow_meter); 985 attr->qos.packet_pacing = 986 MLX5_GET(qos_cap, hcattr, packet_pacing); 987 attr->qos.wqe_rate_pp = 988 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 989 if (attr->qos.flow_meter_aso_sup) { 990 attr->qos.log_meter_aso_granularity = 991 MLX5_GET(qos_cap, hcattr, 992 log_meter_aso_granularity); 993 attr->qos.log_meter_aso_max_alloc = 994 MLX5_GET(qos_cap, hcattr, 995 log_meter_aso_max_alloc); 996 attr->qos.log_max_num_meter_aso = 997 MLX5_GET(qos_cap, hcattr, 998 log_max_num_meter_aso); 999 } 1000 } 1001 /* 1002 * Flex item support needs max_num_prog_sample_field 1003 * from the Capabilities 2 table for PARSE_GRAPH_NODE 1004 */ 1005 if (attr->parse_graph_flex_node) { 1006 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap 1007 (ctx, &attr->flex); 1008 if (rc) 1009 return -1; 1010 } 1011 if (attr->vdpa.valid) 1012 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 1013 if (!attr->eth_net_offloads) 1014 return 0; 1015 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 1016 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1017 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 1018 MLX5_HCA_CAP_OPMOD_GET_CUR); 1019 if (!hcattr) { 1020 attr->log_max_ft_sampler_num = 0; 1021 return rc; 1022 } 1023 attr->log_max_ft_sampler_num = MLX5_GET 1024 (flow_table_nic_cap, hcattr, 1025 flow_table_properties_nic_receive.log_max_ft_sampler_num); 1026 attr->flow.tunnel_header_0_1 = MLX5_GET 1027 (flow_table_nic_cap, hcattr, 1028 ft_field_support_2_nic_receive.tunnel_header_0_1); 1029 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 1030 attr->inner_ipv4_ihl = MLX5_GET 1031 (flow_table_nic_cap, hcattr, 1032 ft_field_support_2_nic_receive.inner_ipv4_ihl); 1033 attr->outer_ipv4_ihl = MLX5_GET 1034 (flow_table_nic_cap, hcattr, 1035 ft_field_support_2_nic_receive.outer_ipv4_ihl); 1036 /* Query HCA offloads for Ethernet protocol. */ 1037 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1038 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 1039 MLX5_HCA_CAP_OPMOD_GET_CUR); 1040 if (!hcattr) { 1041 attr->eth_net_offloads = 0; 1042 return rc; 1043 } 1044 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 1045 hcattr, wqe_vlan_insert); 1046 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 1047 hcattr, csum_cap); 1048 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 1049 hcattr, vlan_cap); 1050 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1051 lro_cap); 1052 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1053 hcattr, max_lso_cap); 1054 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1055 hcattr, scatter_fcs); 1056 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1057 hcattr, tunnel_lro_gre); 1058 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1059 hcattr, tunnel_lro_vxlan); 1060 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1061 hcattr, swp); 1062 attr->tunnel_stateless_gre = 1063 MLX5_GET(per_protocol_networking_offload_caps, 1064 hcattr, tunnel_stateless_gre); 1065 attr->tunnel_stateless_vxlan = 1066 MLX5_GET(per_protocol_networking_offload_caps, 1067 hcattr, tunnel_stateless_vxlan); 1068 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1069 hcattr, swp_csum); 1070 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1071 hcattr, swp_lso); 1072 attr->lro_max_msg_sz_mode = MLX5_GET 1073 (per_protocol_networking_offload_caps, 1074 hcattr, lro_max_msg_sz_mode); 1075 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1076 attr->lro_timer_supported_periods[i] = 1077 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1078 lro_timer_supported_periods[i]); 1079 } 1080 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1081 hcattr, lro_min_mss_size); 1082 attr->tunnel_stateless_geneve_rx = 1083 MLX5_GET(per_protocol_networking_offload_caps, 1084 hcattr, tunnel_stateless_geneve_rx); 1085 attr->geneve_max_opt_len = 1086 MLX5_GET(per_protocol_networking_offload_caps, 1087 hcattr, max_geneve_opt_len); 1088 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1089 hcattr, wqe_inline_mode); 1090 attr->tunnel_stateless_gtp = MLX5_GET 1091 (per_protocol_networking_offload_caps, 1092 hcattr, tunnel_stateless_gtp); 1093 attr->rss_ind_tbl_cap = MLX5_GET 1094 (per_protocol_networking_offload_caps, 1095 hcattr, rss_ind_tbl_cap); 1096 /* Query HCA attribute for ROCE. */ 1097 if (attr->roce) { 1098 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1099 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1100 MLX5_HCA_CAP_OPMOD_GET_CUR); 1101 if (!hcattr) { 1102 DRV_LOG(DEBUG, 1103 "Failed to query devx HCA ROCE capabilities"); 1104 return rc; 1105 } 1106 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1107 } 1108 if (attr->eth_virt && 1109 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1110 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1111 if (rc) { 1112 attr->eth_virt = 0; 1113 goto error; 1114 } 1115 } 1116 return 0; 1117 error: 1118 rc = (rc > 0) ? -rc : rc; 1119 return rc; 1120 } 1121 1122 /** 1123 * Query TIS transport domain from QP verbs object using DevX API. 1124 * 1125 * @param[in] qp 1126 * Pointer to verbs QP returned by ibv_create_qp . 1127 * @param[in] tis_num 1128 * TIS number of TIS to query. 1129 * @param[out] tis_td 1130 * Pointer to TIS transport domain variable, to be set by the routine. 1131 * 1132 * @return 1133 * 0 on success, a negative value otherwise. 1134 */ 1135 int 1136 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1137 uint32_t *tis_td) 1138 { 1139 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1140 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1141 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1142 int rc; 1143 void *tis_ctx; 1144 1145 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1146 MLX5_SET(query_tis_in, in, tisn, tis_num); 1147 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1148 if (rc) { 1149 DRV_LOG(ERR, "Failed to query QP using DevX"); 1150 return -rc; 1151 }; 1152 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1153 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1154 return 0; 1155 #else 1156 (void)qp; 1157 (void)tis_num; 1158 (void)tis_td; 1159 return -ENOTSUP; 1160 #endif 1161 } 1162 1163 /** 1164 * Fill WQ data for DevX API command. 1165 * Utility function for use when creating DevX objects containing a WQ. 1166 * 1167 * @param[in] wq_ctx 1168 * Pointer to WQ context to fill with data. 1169 * @param [in] wq_attr 1170 * Pointer to WQ attributes structure to fill in WQ context. 1171 */ 1172 static void 1173 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1174 { 1175 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1176 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1177 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1178 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1179 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1180 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1181 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1182 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1183 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1184 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1185 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1186 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1187 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1188 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1189 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1190 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1191 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1192 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1193 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1194 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1195 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1196 wq_attr->log_hairpin_num_packets); 1197 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1198 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1199 wq_attr->single_wqe_log_num_of_strides); 1200 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1201 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1202 wq_attr->single_stride_log_num_of_bytes); 1203 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1204 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1205 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1206 } 1207 1208 /** 1209 * Create RQ using DevX API. 1210 * 1211 * @param[in] ctx 1212 * Context returned from mlx5 open_device() glue function. 1213 * @param [in] rq_attr 1214 * Pointer to create RQ attributes structure. 1215 * @param [in] socket 1216 * CPU socket ID for allocations. 1217 * 1218 * @return 1219 * The DevX object created, NULL otherwise and rte_errno is set. 1220 */ 1221 struct mlx5_devx_obj * 1222 mlx5_devx_cmd_create_rq(void *ctx, 1223 struct mlx5_devx_create_rq_attr *rq_attr, 1224 int socket) 1225 { 1226 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1227 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1228 void *rq_ctx, *wq_ctx; 1229 struct mlx5_devx_wq_attr *wq_attr; 1230 struct mlx5_devx_obj *rq = NULL; 1231 1232 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1233 if (!rq) { 1234 DRV_LOG(ERR, "Failed to allocate RQ data"); 1235 rte_errno = ENOMEM; 1236 return NULL; 1237 } 1238 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1239 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1240 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1241 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1242 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1243 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1244 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1245 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1246 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1247 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1248 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1249 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1250 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1251 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1252 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1253 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1254 wq_attr = &rq_attr->wq_attr; 1255 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1256 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1257 out, sizeof(out)); 1258 if (!rq->obj) { 1259 DRV_LOG(ERR, "Failed to create RQ using DevX"); 1260 rte_errno = errno; 1261 mlx5_free(rq); 1262 return NULL; 1263 } 1264 rq->id = MLX5_GET(create_rq_out, out, rqn); 1265 return rq; 1266 } 1267 1268 /** 1269 * Modify RQ using DevX API. 1270 * 1271 * @param[in] rq 1272 * Pointer to RQ object structure. 1273 * @param [in] rq_attr 1274 * Pointer to modify RQ attributes structure. 1275 * 1276 * @return 1277 * 0 on success, a negative errno value otherwise and rte_errno is set. 1278 */ 1279 int 1280 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1281 struct mlx5_devx_modify_rq_attr *rq_attr) 1282 { 1283 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1284 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1285 void *rq_ctx, *wq_ctx; 1286 int ret; 1287 1288 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1289 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1290 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1291 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1292 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1293 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1294 if (rq_attr->modify_bitmask & 1295 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1296 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1297 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1298 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1299 if (rq_attr->modify_bitmask & 1300 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1301 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1302 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1303 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1304 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1305 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1306 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1307 } 1308 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1309 out, sizeof(out)); 1310 if (ret) { 1311 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1312 rte_errno = errno; 1313 return -errno; 1314 } 1315 return ret; 1316 } 1317 1318 /** 1319 * Create RMP using DevX API. 1320 * 1321 * @param[in] ctx 1322 * Context returned from mlx5 open_device() glue function. 1323 * @param [in] rmp_attr 1324 * Pointer to create RMP attributes structure. 1325 * @param [in] socket 1326 * CPU socket ID for allocations. 1327 * 1328 * @return 1329 * The DevX object created, NULL otherwise and rte_errno is set. 1330 */ 1331 struct mlx5_devx_obj * 1332 mlx5_devx_cmd_create_rmp(void *ctx, 1333 struct mlx5_devx_create_rmp_attr *rmp_attr, 1334 int socket) 1335 { 1336 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0}; 1337 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0}; 1338 void *rmp_ctx, *wq_ctx; 1339 struct mlx5_devx_wq_attr *wq_attr; 1340 struct mlx5_devx_obj *rmp = NULL; 1341 1342 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket); 1343 if (!rmp) { 1344 DRV_LOG(ERR, "Failed to allocate RMP data"); 1345 rte_errno = ENOMEM; 1346 return NULL; 1347 } 1348 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP); 1349 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx); 1350 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state); 1351 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe, 1352 rmp_attr->basic_cyclic_rcv_wqe); 1353 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq); 1354 wq_attr = &rmp_attr->wq_attr; 1355 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1356 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1357 sizeof(out)); 1358 if (!rmp->obj) { 1359 DRV_LOG(ERR, "Failed to create RMP using DevX"); 1360 rte_errno = errno; 1361 mlx5_free(rmp); 1362 return NULL; 1363 } 1364 rmp->id = MLX5_GET(create_rmp_out, out, rmpn); 1365 return rmp; 1366 } 1367 1368 /* 1369 * Create TIR using DevX API. 1370 * 1371 * @param[in] ctx 1372 * Context returned from mlx5 open_device() glue function. 1373 * @param [in] tir_attr 1374 * Pointer to TIR attributes structure. 1375 * 1376 * @return 1377 * The DevX object created, NULL otherwise and rte_errno is set. 1378 */ 1379 struct mlx5_devx_obj * 1380 mlx5_devx_cmd_create_tir(void *ctx, 1381 struct mlx5_devx_tir_attr *tir_attr) 1382 { 1383 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1384 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1385 void *tir_ctx, *outer, *inner, *rss_key; 1386 struct mlx5_devx_obj *tir = NULL; 1387 1388 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1389 if (!tir) { 1390 DRV_LOG(ERR, "Failed to allocate TIR data"); 1391 rte_errno = ENOMEM; 1392 return NULL; 1393 } 1394 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1395 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1396 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1397 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1398 tir_attr->lro_timeout_period_usecs); 1399 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1400 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1401 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1402 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1403 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1404 tir_attr->tunneled_offload_en); 1405 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1406 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1407 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1408 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1409 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1410 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1411 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1412 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1413 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1414 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1415 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1416 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1417 tir_attr->rx_hash_field_selector_outer.selected_fields); 1418 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1419 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1420 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1421 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1422 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1423 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1424 tir_attr->rx_hash_field_selector_inner.selected_fields); 1425 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1426 out, sizeof(out)); 1427 if (!tir->obj) { 1428 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1429 rte_errno = errno; 1430 mlx5_free(tir); 1431 return NULL; 1432 } 1433 tir->id = MLX5_GET(create_tir_out, out, tirn); 1434 return tir; 1435 } 1436 1437 /** 1438 * Modify TIR using DevX API. 1439 * 1440 * @param[in] tir 1441 * Pointer to TIR DevX object structure. 1442 * @param [in] modify_tir_attr 1443 * Pointer to TIR modification attributes structure. 1444 * 1445 * @return 1446 * 0 on success, a negative errno value otherwise and rte_errno is set. 1447 */ 1448 int 1449 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1450 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1451 { 1452 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1453 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1454 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1455 void *tir_ctx; 1456 int ret; 1457 1458 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1459 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1460 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1461 modify_tir_attr->modify_bitmask); 1462 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1463 if (modify_tir_attr->modify_bitmask & 1464 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1465 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1466 tir_attr->lro_timeout_period_usecs); 1467 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1468 tir_attr->lro_enable_mask); 1469 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1470 tir_attr->lro_max_msg_sz); 1471 } 1472 if (modify_tir_attr->modify_bitmask & 1473 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1474 MLX5_SET(tirc, tir_ctx, indirect_table, 1475 tir_attr->indirect_table); 1476 if (modify_tir_attr->modify_bitmask & 1477 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1478 int i; 1479 void *outer, *inner; 1480 1481 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1482 tir_attr->rx_hash_symmetric); 1483 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1484 for (i = 0; i < 10; i++) { 1485 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1486 tir_attr->rx_hash_toeplitz_key[i]); 1487 } 1488 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1489 rx_hash_field_selector_outer); 1490 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1491 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1492 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1493 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1494 MLX5_SET 1495 (rx_hash_field_select, outer, selected_fields, 1496 tir_attr->rx_hash_field_selector_outer.selected_fields); 1497 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1498 rx_hash_field_selector_inner); 1499 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1500 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1501 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1502 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1503 MLX5_SET 1504 (rx_hash_field_select, inner, selected_fields, 1505 tir_attr->rx_hash_field_selector_inner.selected_fields); 1506 } 1507 if (modify_tir_attr->modify_bitmask & 1508 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1509 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1510 } 1511 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1512 out, sizeof(out)); 1513 if (ret) { 1514 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1515 rte_errno = errno; 1516 return -errno; 1517 } 1518 return ret; 1519 } 1520 1521 /** 1522 * Create RQT using DevX API. 1523 * 1524 * @param[in] ctx 1525 * Context returned from mlx5 open_device() glue function. 1526 * @param [in] rqt_attr 1527 * Pointer to RQT attributes structure. 1528 * 1529 * @return 1530 * The DevX object created, NULL otherwise and rte_errno is set. 1531 */ 1532 struct mlx5_devx_obj * 1533 mlx5_devx_cmd_create_rqt(void *ctx, 1534 struct mlx5_devx_rqt_attr *rqt_attr) 1535 { 1536 uint32_t *in = NULL; 1537 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1538 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1539 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1540 void *rqt_ctx; 1541 struct mlx5_devx_obj *rqt = NULL; 1542 int i; 1543 1544 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1545 if (!in) { 1546 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1547 rte_errno = ENOMEM; 1548 return NULL; 1549 } 1550 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1551 if (!rqt) { 1552 DRV_LOG(ERR, "Failed to allocate RQT data"); 1553 rte_errno = ENOMEM; 1554 mlx5_free(in); 1555 return NULL; 1556 } 1557 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1558 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1559 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1560 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1561 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1562 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1563 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1564 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1565 mlx5_free(in); 1566 if (!rqt->obj) { 1567 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1568 rte_errno = errno; 1569 mlx5_free(rqt); 1570 return NULL; 1571 } 1572 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1573 return rqt; 1574 } 1575 1576 /** 1577 * Modify RQT using DevX API. 1578 * 1579 * @param[in] rqt 1580 * Pointer to RQT DevX object structure. 1581 * @param [in] rqt_attr 1582 * Pointer to RQT attributes structure. 1583 * 1584 * @return 1585 * 0 on success, a negative errno value otherwise and rte_errno is set. 1586 */ 1587 int 1588 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1589 struct mlx5_devx_rqt_attr *rqt_attr) 1590 { 1591 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1592 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1593 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1594 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1595 void *rqt_ctx; 1596 int i; 1597 int ret; 1598 1599 if (!in) { 1600 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1601 rte_errno = ENOMEM; 1602 return -ENOMEM; 1603 } 1604 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1605 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1606 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1607 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1608 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1609 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1610 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1611 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1612 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1613 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1614 mlx5_free(in); 1615 if (ret) { 1616 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1617 rte_errno = errno; 1618 return -rte_errno; 1619 } 1620 return ret; 1621 } 1622 1623 /** 1624 * Create SQ using DevX API. 1625 * 1626 * @param[in] ctx 1627 * Context returned from mlx5 open_device() glue function. 1628 * @param [in] sq_attr 1629 * Pointer to SQ attributes structure. 1630 * @param [in] socket 1631 * CPU socket ID for allocations. 1632 * 1633 * @return 1634 * The DevX object created, NULL otherwise and rte_errno is set. 1635 **/ 1636 struct mlx5_devx_obj * 1637 mlx5_devx_cmd_create_sq(void *ctx, 1638 struct mlx5_devx_create_sq_attr *sq_attr) 1639 { 1640 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1641 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1642 void *sq_ctx; 1643 void *wq_ctx; 1644 struct mlx5_devx_wq_attr *wq_attr; 1645 struct mlx5_devx_obj *sq = NULL; 1646 1647 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1648 if (!sq) { 1649 DRV_LOG(ERR, "Failed to allocate SQ data"); 1650 rte_errno = ENOMEM; 1651 return NULL; 1652 } 1653 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1654 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1655 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1656 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1657 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1658 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1659 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1660 sq_attr->allow_multi_pkt_send_wqe); 1661 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1662 sq_attr->min_wqe_inline_mode); 1663 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1664 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1665 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1666 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1667 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1668 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1669 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1670 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1671 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1672 sq_attr->packet_pacing_rate_limit_index); 1673 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1674 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1675 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1676 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1677 wq_attr = &sq_attr->wq_attr; 1678 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1679 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1680 out, sizeof(out)); 1681 if (!sq->obj) { 1682 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1683 rte_errno = errno; 1684 mlx5_free(sq); 1685 return NULL; 1686 } 1687 sq->id = MLX5_GET(create_sq_out, out, sqn); 1688 return sq; 1689 } 1690 1691 /** 1692 * Modify SQ using DevX API. 1693 * 1694 * @param[in] sq 1695 * Pointer to SQ object structure. 1696 * @param [in] sq_attr 1697 * Pointer to SQ attributes structure. 1698 * 1699 * @return 1700 * 0 on success, a negative errno value otherwise and rte_errno is set. 1701 */ 1702 int 1703 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1704 struct mlx5_devx_modify_sq_attr *sq_attr) 1705 { 1706 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1707 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1708 void *sq_ctx; 1709 int ret; 1710 1711 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1712 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1713 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1714 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1715 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1716 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1717 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1718 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1719 out, sizeof(out)); 1720 if (ret) { 1721 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1722 rte_errno = errno; 1723 return -rte_errno; 1724 } 1725 return ret; 1726 } 1727 1728 /** 1729 * Create TIS using DevX API. 1730 * 1731 * @param[in] ctx 1732 * Context returned from mlx5 open_device() glue function. 1733 * @param [in] tis_attr 1734 * Pointer to TIS attributes structure. 1735 * 1736 * @return 1737 * The DevX object created, NULL otherwise and rte_errno is set. 1738 */ 1739 struct mlx5_devx_obj * 1740 mlx5_devx_cmd_create_tis(void *ctx, 1741 struct mlx5_devx_tis_attr *tis_attr) 1742 { 1743 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1744 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1745 struct mlx5_devx_obj *tis = NULL; 1746 void *tis_ctx; 1747 1748 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1749 if (!tis) { 1750 DRV_LOG(ERR, "Failed to allocate TIS object"); 1751 rte_errno = ENOMEM; 1752 return NULL; 1753 } 1754 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1755 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1756 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1757 tis_attr->strict_lag_tx_port_affinity); 1758 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1759 tis_attr->lag_tx_port_affinity); 1760 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1761 MLX5_SET(tisc, tis_ctx, transport_domain, 1762 tis_attr->transport_domain); 1763 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1764 out, sizeof(out)); 1765 if (!tis->obj) { 1766 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1767 rte_errno = errno; 1768 mlx5_free(tis); 1769 return NULL; 1770 } 1771 tis->id = MLX5_GET(create_tis_out, out, tisn); 1772 return tis; 1773 } 1774 1775 /** 1776 * Create transport domain using DevX API. 1777 * 1778 * @param[in] ctx 1779 * Context returned from mlx5 open_device() glue function. 1780 * @return 1781 * The DevX object created, NULL otherwise and rte_errno is set. 1782 */ 1783 struct mlx5_devx_obj * 1784 mlx5_devx_cmd_create_td(void *ctx) 1785 { 1786 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1787 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1788 struct mlx5_devx_obj *td = NULL; 1789 1790 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1791 if (!td) { 1792 DRV_LOG(ERR, "Failed to allocate TD object"); 1793 rte_errno = ENOMEM; 1794 return NULL; 1795 } 1796 MLX5_SET(alloc_transport_domain_in, in, opcode, 1797 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1798 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1799 out, sizeof(out)); 1800 if (!td->obj) { 1801 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1802 rte_errno = errno; 1803 mlx5_free(td); 1804 return NULL; 1805 } 1806 td->id = MLX5_GET(alloc_transport_domain_out, out, 1807 transport_domain); 1808 return td; 1809 } 1810 1811 /** 1812 * Dump all flows to file. 1813 * 1814 * @param[in] fdb_domain 1815 * FDB domain. 1816 * @param[in] rx_domain 1817 * RX domain. 1818 * @param[in] tx_domain 1819 * TX domain. 1820 * @param[out] file 1821 * Pointer to file stream. 1822 * 1823 * @return 1824 * 0 on success, a nagative value otherwise. 1825 */ 1826 int 1827 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1828 void *rx_domain __rte_unused, 1829 void *tx_domain __rte_unused, FILE *file __rte_unused) 1830 { 1831 int ret = 0; 1832 1833 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1834 if (fdb_domain) { 1835 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1836 if (ret) 1837 return ret; 1838 } 1839 MLX5_ASSERT(rx_domain); 1840 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1841 if (ret) 1842 return ret; 1843 MLX5_ASSERT(tx_domain); 1844 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1845 #else 1846 ret = ENOTSUP; 1847 #endif 1848 return -ret; 1849 } 1850 1851 int 1852 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 1853 FILE *file __rte_unused) 1854 { 1855 int ret = 0; 1856 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 1857 if (rule_info) 1858 ret = mlx5_glue->dr_dump_rule(file, rule_info); 1859 #else 1860 ret = ENOTSUP; 1861 #endif 1862 return -ret; 1863 } 1864 1865 /* 1866 * Create CQ using DevX API. 1867 * 1868 * @param[in] ctx 1869 * Context returned from mlx5 open_device() glue function. 1870 * @param [in] attr 1871 * Pointer to CQ attributes structure. 1872 * 1873 * @return 1874 * The DevX object created, NULL otherwise and rte_errno is set. 1875 */ 1876 struct mlx5_devx_obj * 1877 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1878 { 1879 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1880 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1881 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1882 sizeof(*cq_obj), 1883 0, SOCKET_ID_ANY); 1884 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1885 1886 if (!cq_obj) { 1887 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1888 rte_errno = ENOMEM; 1889 return NULL; 1890 } 1891 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1892 if (attr->db_umem_valid) { 1893 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1894 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1895 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1896 } else { 1897 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1898 } 1899 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1900 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1901 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1902 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1903 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1904 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1905 MLX5_SET(cqc, cqctx, log_page_size, 1906 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1907 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1908 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1909 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1910 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1911 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1912 attr->mini_cqe_res_format_ext); 1913 if (attr->q_umem_valid) { 1914 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1915 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1916 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1917 attr->q_umem_offset); 1918 } 1919 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1920 sizeof(out)); 1921 if (!cq_obj->obj) { 1922 rte_errno = errno; 1923 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1924 mlx5_free(cq_obj); 1925 return NULL; 1926 } 1927 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1928 return cq_obj; 1929 } 1930 1931 /** 1932 * Create VIRTQ using DevX API. 1933 * 1934 * @param[in] ctx 1935 * Context returned from mlx5 open_device() glue function. 1936 * @param [in] attr 1937 * Pointer to VIRTQ attributes structure. 1938 * 1939 * @return 1940 * The DevX object created, NULL otherwise and rte_errno is set. 1941 */ 1942 struct mlx5_devx_obj * 1943 mlx5_devx_cmd_create_virtq(void *ctx, 1944 struct mlx5_devx_virtq_attr *attr) 1945 { 1946 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1947 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1948 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1949 sizeof(*virtq_obj), 1950 0, SOCKET_ID_ANY); 1951 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1952 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1953 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1954 1955 if (!virtq_obj) { 1956 DRV_LOG(ERR, "Failed to allocate virtq data."); 1957 rte_errno = ENOMEM; 1958 return NULL; 1959 } 1960 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1961 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1962 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1963 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1964 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1965 attr->hw_available_index); 1966 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1967 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1968 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1969 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1970 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1971 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1972 attr->virtio_version_1_0); 1973 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1974 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1975 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1976 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1977 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1978 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1979 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1980 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1981 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1982 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 1983 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 1984 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 1985 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 1986 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 1987 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 1988 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 1989 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 1990 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 1991 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 1992 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 1993 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 1994 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 1995 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 1996 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1997 sizeof(out)); 1998 if (!virtq_obj->obj) { 1999 rte_errno = errno; 2000 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 2001 mlx5_free(virtq_obj); 2002 return NULL; 2003 } 2004 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2005 return virtq_obj; 2006 } 2007 2008 /** 2009 * Modify VIRTQ using DevX API. 2010 * 2011 * @param[in] virtq_obj 2012 * Pointer to virtq object structure. 2013 * @param [in] attr 2014 * Pointer to modify virtq attributes structure. 2015 * 2016 * @return 2017 * 0 on success, a negative errno value otherwise and rte_errno is set. 2018 */ 2019 int 2020 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 2021 struct mlx5_devx_virtq_attr *attr) 2022 { 2023 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2024 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2025 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2026 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2027 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2028 int ret; 2029 2030 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2031 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 2032 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2033 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2034 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2035 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 2036 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2037 switch (attr->type) { 2038 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 2039 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 2040 break; 2041 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 2042 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 2043 attr->dirty_bitmap_mkey); 2044 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 2045 attr->dirty_bitmap_addr); 2046 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 2047 attr->dirty_bitmap_size); 2048 break; 2049 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 2050 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 2051 attr->dirty_bitmap_dump_enable); 2052 break; 2053 default: 2054 rte_errno = EINVAL; 2055 return -rte_errno; 2056 } 2057 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 2058 out, sizeof(out)); 2059 if (ret) { 2060 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2061 rte_errno = errno; 2062 return -rte_errno; 2063 } 2064 return ret; 2065 } 2066 2067 /** 2068 * Query VIRTQ using DevX API. 2069 * 2070 * @param[in] virtq_obj 2071 * Pointer to virtq object structure. 2072 * @param [in/out] attr 2073 * Pointer to virtq attributes structure. 2074 * 2075 * @return 2076 * 0 on success, a negative errno value otherwise and rte_errno is set. 2077 */ 2078 int 2079 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 2080 struct mlx5_devx_virtq_attr *attr) 2081 { 2082 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2083 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 2084 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 2085 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 2086 int ret; 2087 2088 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2089 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2090 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2091 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2092 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2093 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2094 out, sizeof(out)); 2095 if (ret) { 2096 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2097 rte_errno = errno; 2098 return -errno; 2099 } 2100 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2101 hw_available_index); 2102 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2103 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2104 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2105 virtio_q_context.error_type); 2106 return ret; 2107 } 2108 2109 /** 2110 * Create QP using DevX API. 2111 * 2112 * @param[in] ctx 2113 * Context returned from mlx5 open_device() glue function. 2114 * @param [in] attr 2115 * Pointer to QP attributes structure. 2116 * 2117 * @return 2118 * The DevX object created, NULL otherwise and rte_errno is set. 2119 */ 2120 struct mlx5_devx_obj * 2121 mlx5_devx_cmd_create_qp(void *ctx, 2122 struct mlx5_devx_qp_attr *attr) 2123 { 2124 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2125 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2126 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2127 sizeof(*qp_obj), 2128 0, SOCKET_ID_ANY); 2129 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2130 2131 if (!qp_obj) { 2132 DRV_LOG(ERR, "Failed to allocate QP data."); 2133 rte_errno = ENOMEM; 2134 return NULL; 2135 } 2136 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2137 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2138 MLX5_SET(qpc, qpc, pd, attr->pd); 2139 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2140 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2141 if (attr->uar_index) { 2142 if (attr->mmo) { 2143 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2144 in, qpc_extension_and_pas_list); 2145 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2146 qpc_ext_and_pas_list, qpc_data_extension); 2147 2148 MLX5_SET(create_qp_in, in, qpc_ext, 1); 2149 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2150 } 2151 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2152 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2153 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2154 MLX5_SET(qpc, qpc, log_page_size, 2155 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2156 if (attr->sq_size) { 2157 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); 2158 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2159 MLX5_SET(qpc, qpc, log_sq_size, 2160 rte_log2_u32(attr->sq_size)); 2161 } else { 2162 MLX5_SET(qpc, qpc, no_sq, 1); 2163 } 2164 if (attr->rq_size) { 2165 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); 2166 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2167 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2168 MLX5_LOG_RQ_STRIDE_SHIFT); 2169 MLX5_SET(qpc, qpc, log_rq_size, 2170 rte_log2_u32(attr->rq_size)); 2171 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2172 } else { 2173 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2174 } 2175 if (attr->dbr_umem_valid) { 2176 MLX5_SET(qpc, qpc, dbr_umem_valid, 2177 attr->dbr_umem_valid); 2178 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2179 } 2180 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2181 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2182 attr->wq_umem_offset); 2183 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2184 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2185 } else { 2186 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2187 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2188 MLX5_SET(qpc, qpc, no_sq, 1); 2189 } 2190 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2191 sizeof(out)); 2192 if (!qp_obj->obj) { 2193 rte_errno = errno; 2194 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 2195 mlx5_free(qp_obj); 2196 return NULL; 2197 } 2198 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2199 return qp_obj; 2200 } 2201 2202 /** 2203 * Modify QP using DevX API. 2204 * Currently supports only force loop-back QP. 2205 * 2206 * @param[in] qp 2207 * Pointer to QP object structure. 2208 * @param [in] qp_st_mod_op 2209 * The QP state modification operation. 2210 * @param [in] remote_qp_id 2211 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2212 * 2213 * @return 2214 * 0 on success, a negative errno value otherwise and rte_errno is set. 2215 */ 2216 int 2217 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2218 uint32_t remote_qp_id) 2219 { 2220 union { 2221 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2222 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2223 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2224 } in; 2225 union { 2226 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2227 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2228 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2229 } out; 2230 void *qpc; 2231 int ret; 2232 unsigned int inlen; 2233 unsigned int outlen; 2234 2235 memset(&in, 0, sizeof(in)); 2236 memset(&out, 0, sizeof(out)); 2237 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2238 switch (qp_st_mod_op) { 2239 case MLX5_CMD_OP_RST2INIT_QP: 2240 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2241 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2242 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2243 MLX5_SET(qpc, qpc, rre, 1); 2244 MLX5_SET(qpc, qpc, rwe, 1); 2245 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2246 inlen = sizeof(in.rst2init); 2247 outlen = sizeof(out.rst2init); 2248 break; 2249 case MLX5_CMD_OP_INIT2RTR_QP: 2250 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2251 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2252 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2253 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2254 MLX5_SET(qpc, qpc, mtu, 1); 2255 MLX5_SET(qpc, qpc, log_msg_max, 30); 2256 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2257 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2258 inlen = sizeof(in.init2rtr); 2259 outlen = sizeof(out.init2rtr); 2260 break; 2261 case MLX5_CMD_OP_RTR2RTS_QP: 2262 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2263 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2264 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 2265 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2266 MLX5_SET(qpc, qpc, retry_count, 7); 2267 MLX5_SET(qpc, qpc, rnr_retry, 7); 2268 inlen = sizeof(in.rtr2rts); 2269 outlen = sizeof(out.rtr2rts); 2270 break; 2271 default: 2272 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2273 qp_st_mod_op); 2274 rte_errno = EINVAL; 2275 return -rte_errno; 2276 } 2277 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2278 if (ret) { 2279 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2280 rte_errno = errno; 2281 return -rte_errno; 2282 } 2283 return ret; 2284 } 2285 2286 struct mlx5_devx_obj * 2287 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2288 { 2289 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2290 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2291 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2292 sizeof(*couners_obj), 0, 2293 SOCKET_ID_ANY); 2294 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2295 2296 if (!couners_obj) { 2297 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2298 rte_errno = ENOMEM; 2299 return NULL; 2300 } 2301 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2302 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2303 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2304 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2305 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2306 sizeof(out)); 2307 if (!couners_obj->obj) { 2308 rte_errno = errno; 2309 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 2310 " DevX."); 2311 mlx5_free(couners_obj); 2312 return NULL; 2313 } 2314 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2315 return couners_obj; 2316 } 2317 2318 int 2319 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2320 struct mlx5_devx_virtio_q_couners_attr *attr) 2321 { 2322 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2323 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2324 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2325 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2326 virtio_q_counters); 2327 int ret; 2328 2329 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2330 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2331 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2332 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2333 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2334 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2335 sizeof(out)); 2336 if (ret) { 2337 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2338 rte_errno = errno; 2339 return -errno; 2340 } 2341 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2342 received_desc); 2343 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2344 completed_desc); 2345 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2346 error_cqes); 2347 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2348 bad_desc_errors); 2349 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2350 exceed_max_chain); 2351 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2352 invalid_buffer); 2353 return ret; 2354 } 2355 2356 /** 2357 * Create general object of type FLOW_HIT_ASO using DevX API. 2358 * 2359 * @param[in] ctx 2360 * Context returned from mlx5 open_device() glue function. 2361 * @param [in] pd 2362 * PD value to associate the FLOW_HIT_ASO object with. 2363 * 2364 * @return 2365 * The DevX object created, NULL otherwise and rte_errno is set. 2366 */ 2367 struct mlx5_devx_obj * 2368 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2369 { 2370 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2371 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2372 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2373 void *ptr = NULL; 2374 2375 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2376 0, SOCKET_ID_ANY); 2377 if (!flow_hit_aso_obj) { 2378 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2379 rte_errno = ENOMEM; 2380 return NULL; 2381 } 2382 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2383 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2384 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2385 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2386 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2387 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2388 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2389 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2390 out, sizeof(out)); 2391 if (!flow_hit_aso_obj->obj) { 2392 rte_errno = errno; 2393 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX."); 2394 mlx5_free(flow_hit_aso_obj); 2395 return NULL; 2396 } 2397 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2398 return flow_hit_aso_obj; 2399 } 2400 2401 /* 2402 * Create PD using DevX API. 2403 * 2404 * @param[in] ctx 2405 * Context returned from mlx5 open_device() glue function. 2406 * 2407 * @return 2408 * The DevX object created, NULL otherwise and rte_errno is set. 2409 */ 2410 struct mlx5_devx_obj * 2411 mlx5_devx_cmd_alloc_pd(void *ctx) 2412 { 2413 struct mlx5_devx_obj *ppd = 2414 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2415 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2416 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2417 2418 if (!ppd) { 2419 DRV_LOG(ERR, "Failed to allocate PD data."); 2420 rte_errno = ENOMEM; 2421 return NULL; 2422 } 2423 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2424 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2425 out, sizeof(out)); 2426 if (!ppd->obj) { 2427 mlx5_free(ppd); 2428 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2429 rte_errno = errno; 2430 return NULL; 2431 } 2432 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2433 return ppd; 2434 } 2435 2436 /** 2437 * Create general object of type FLOW_METER_ASO using DevX API. 2438 * 2439 * @param[in] ctx 2440 * Context returned from mlx5 open_device() glue function. 2441 * @param [in] pd 2442 * PD value to associate the FLOW_METER_ASO object with. 2443 * @param [in] log_obj_size 2444 * log_obj_size define to allocate number of 2 * meters 2445 * in one FLOW_METER_ASO object. 2446 * 2447 * @return 2448 * The DevX object created, NULL otherwise and rte_errno is set. 2449 */ 2450 struct mlx5_devx_obj * 2451 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2452 uint32_t log_obj_size) 2453 { 2454 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2455 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2456 struct mlx5_devx_obj *flow_meter_aso_obj; 2457 void *ptr; 2458 2459 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2460 sizeof(*flow_meter_aso_obj), 2461 0, SOCKET_ID_ANY); 2462 if (!flow_meter_aso_obj) { 2463 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2464 rte_errno = ENOMEM; 2465 return NULL; 2466 } 2467 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2468 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2469 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2470 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2471 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2472 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2473 log_obj_size); 2474 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2475 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2476 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2477 ctx, in, sizeof(in), 2478 out, sizeof(out)); 2479 if (!flow_meter_aso_obj->obj) { 2480 rte_errno = errno; 2481 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX."); 2482 mlx5_free(flow_meter_aso_obj); 2483 return NULL; 2484 } 2485 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2486 out, obj_id); 2487 return flow_meter_aso_obj; 2488 } 2489 2490 /* 2491 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2492 * 2493 * @param[in] ctx 2494 * Context returned from mlx5 open_device() glue function. 2495 * @param [in] pd 2496 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2497 * @param [in] log_obj_size 2498 * log_obj_size to allocate its power of 2 * objects 2499 * in one CONN_TRACK_OFFLOAD bulk allocation. 2500 * 2501 * @return 2502 * The DevX object created, NULL otherwise and rte_errno is set. 2503 */ 2504 struct mlx5_devx_obj * 2505 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2506 uint32_t log_obj_size) 2507 { 2508 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2509 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2510 struct mlx5_devx_obj *ct_aso_obj; 2511 void *ptr; 2512 2513 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2514 0, SOCKET_ID_ANY); 2515 if (!ct_aso_obj) { 2516 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2517 rte_errno = ENOMEM; 2518 return NULL; 2519 } 2520 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2521 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2522 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2523 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2524 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2525 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2526 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2527 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2528 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2529 out, sizeof(out)); 2530 if (!ct_aso_obj->obj) { 2531 rte_errno = errno; 2532 DRV_LOG(ERR, "Failed to create CONN_TRACK_OFFLOAD obj by using DevX."); 2533 mlx5_free(ct_aso_obj); 2534 return NULL; 2535 } 2536 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2537 return ct_aso_obj; 2538 } 2539 2540 /** 2541 * Create general object of type GENEVE TLV option using DevX API. 2542 * 2543 * @param[in] ctx 2544 * Context returned from mlx5 open_device() glue function. 2545 * @param [in] class 2546 * TLV option variable value of class 2547 * @param [in] type 2548 * TLV option variable value of type 2549 * @param [in] len 2550 * TLV option variable value of len 2551 * 2552 * @return 2553 * The DevX object created, NULL otherwise and rte_errno is set. 2554 */ 2555 struct mlx5_devx_obj * 2556 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2557 uint16_t class, uint8_t type, uint8_t len) 2558 { 2559 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2560 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2561 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2562 sizeof(*geneve_tlv_opt_obj), 2563 0, SOCKET_ID_ANY); 2564 2565 if (!geneve_tlv_opt_obj) { 2566 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2567 rte_errno = ENOMEM; 2568 return NULL; 2569 } 2570 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2571 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2572 geneve_tlv_opt); 2573 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2574 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2575 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2576 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2577 MLX5_SET(geneve_tlv_option, opt, option_class, 2578 rte_be_to_cpu_16(class)); 2579 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2580 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2581 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2582 sizeof(in), out, sizeof(out)); 2583 if (!geneve_tlv_opt_obj->obj) { 2584 rte_errno = errno; 2585 DRV_LOG(ERR, "Failed to create Geneve tlv option " 2586 "Obj using DevX."); 2587 mlx5_free(geneve_tlv_opt_obj); 2588 return NULL; 2589 } 2590 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2591 return geneve_tlv_opt_obj; 2592 } 2593 2594 int 2595 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2596 { 2597 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2598 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2599 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2600 int rc; 2601 void *rq_ctx; 2602 2603 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2604 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2605 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2606 if (rc) { 2607 rte_errno = errno; 2608 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2609 "rc = %d, errno = %d.", rc, errno); 2610 return -rc; 2611 }; 2612 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2613 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2614 return 0; 2615 #else 2616 (void)wq; 2617 (void)counter_set_id; 2618 return -ENOTSUP; 2619 #endif 2620 } 2621 2622 /* 2623 * Allocate queue counters via devx interface. 2624 * 2625 * @param[in] ctx 2626 * Context returned from mlx5 open_device() glue function. 2627 * 2628 * @return 2629 * Pointer to counter object on success, a NULL value otherwise and 2630 * rte_errno is set. 2631 */ 2632 struct mlx5_devx_obj * 2633 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2634 { 2635 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2636 SOCKET_ID_ANY); 2637 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2638 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2639 2640 if (!dcs) { 2641 rte_errno = ENOMEM; 2642 return NULL; 2643 } 2644 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2645 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2646 sizeof(out)); 2647 if (!dcs->obj) { 2648 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error " 2649 "%d.", errno); 2650 rte_errno = errno; 2651 mlx5_free(dcs); 2652 return NULL; 2653 } 2654 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2655 return dcs; 2656 } 2657 2658 /** 2659 * Query queue counters values. 2660 * 2661 * @param[in] dcs 2662 * devx object of the queue counter set. 2663 * @param[in] clear 2664 * Whether hardware should clear the counters after the query or not. 2665 * @param[out] out_of_buffers 2666 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2667 * 2668 * @return 2669 * 0 on success, a negative value otherwise. 2670 */ 2671 int 2672 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2673 uint32_t *out_of_buffers) 2674 { 2675 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2676 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2677 int rc; 2678 2679 MLX5_SET(query_q_counter_in, in, opcode, 2680 MLX5_CMD_OP_QUERY_Q_COUNTER); 2681 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2682 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2683 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2684 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2685 sizeof(out)); 2686 if (rc) { 2687 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2688 rte_errno = rc; 2689 return -rc; 2690 } 2691 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2692 return 0; 2693 } 2694 2695 /** 2696 * Create general object of type DEK using DevX API. 2697 * 2698 * @param[in] ctx 2699 * Context returned from mlx5 open_device() glue function. 2700 * @param [in] attr 2701 * Pointer to DEK attributes structure. 2702 * 2703 * @return 2704 * The DevX object created, NULL otherwise and rte_errno is set. 2705 */ 2706 struct mlx5_devx_obj * 2707 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2708 { 2709 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2710 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2711 struct mlx5_devx_obj *dek_obj = NULL; 2712 void *ptr = NULL, *key_addr = NULL; 2713 2714 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2715 0, SOCKET_ID_ANY); 2716 if (dek_obj == NULL) { 2717 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2718 rte_errno = ENOMEM; 2719 return NULL; 2720 } 2721 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2722 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2723 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2724 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2725 MLX5_GENERAL_OBJ_TYPE_DEK); 2726 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2727 MLX5_SET(dek, ptr, key_size, attr->key_size); 2728 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2729 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2730 MLX5_SET(dek, ptr, pd, attr->pd); 2731 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2732 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2733 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2734 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2735 out, sizeof(out)); 2736 if (dek_obj->obj == NULL) { 2737 rte_errno = errno; 2738 DRV_LOG(ERR, "Failed to create DEK obj using DevX."); 2739 mlx5_free(dek_obj); 2740 return NULL; 2741 } 2742 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2743 return dek_obj; 2744 } 2745 2746 /** 2747 * Create general object of type IMPORT_KEK using DevX API. 2748 * 2749 * @param[in] ctx 2750 * Context returned from mlx5 open_device() glue function. 2751 * @param [in] attr 2752 * Pointer to IMPORT_KEK attributes structure. 2753 * 2754 * @return 2755 * The DevX object created, NULL otherwise and rte_errno is set. 2756 */ 2757 struct mlx5_devx_obj * 2758 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 2759 struct mlx5_devx_import_kek_attr *attr) 2760 { 2761 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 2762 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2763 struct mlx5_devx_obj *import_kek_obj = NULL; 2764 void *ptr = NULL, *key_addr = NULL; 2765 2766 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 2767 0, SOCKET_ID_ANY); 2768 if (import_kek_obj == NULL) { 2769 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 2770 rte_errno = ENOMEM; 2771 return NULL; 2772 } 2773 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 2774 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2775 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2776 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2777 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 2778 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 2779 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 2780 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 2781 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2782 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2783 out, sizeof(out)); 2784 if (import_kek_obj->obj == NULL) { 2785 rte_errno = errno; 2786 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX."); 2787 mlx5_free(import_kek_obj); 2788 return NULL; 2789 } 2790 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2791 return import_kek_obj; 2792 } 2793 2794 /** 2795 * Create general object of type CREDENTIAL using DevX API. 2796 * 2797 * @param[in] ctx 2798 * Context returned from mlx5 open_device() glue function. 2799 * @param [in] attr 2800 * Pointer to CREDENTIAL attributes structure. 2801 * 2802 * @return 2803 * The DevX object created, NULL otherwise and rte_errno is set. 2804 */ 2805 struct mlx5_devx_obj * 2806 mlx5_devx_cmd_create_credential_obj(void *ctx, 2807 struct mlx5_devx_credential_attr *attr) 2808 { 2809 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 2810 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2811 struct mlx5_devx_obj *credential_obj = NULL; 2812 void *ptr = NULL, *credential_addr = NULL; 2813 2814 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 2815 0, SOCKET_ID_ANY); 2816 if (credential_obj == NULL) { 2817 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 2818 rte_errno = ENOMEM; 2819 return NULL; 2820 } 2821 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 2822 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2823 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2824 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2825 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 2826 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 2827 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 2828 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 2829 memcpy(credential_addr, (void *)(attr->credential), 2830 MLX5_CRYPTO_CREDENTIAL_SIZE); 2831 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2832 out, sizeof(out)); 2833 if (credential_obj->obj == NULL) { 2834 rte_errno = errno; 2835 DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX."); 2836 mlx5_free(credential_obj); 2837 return NULL; 2838 } 2839 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2840 return credential_obj; 2841 } 2842 2843 /** 2844 * Create general object of type CRYPTO_LOGIN using DevX API. 2845 * 2846 * @param[in] ctx 2847 * Context returned from mlx5 open_device() glue function. 2848 * @param [in] attr 2849 * Pointer to CRYPTO_LOGIN attributes structure. 2850 * 2851 * @return 2852 * The DevX object created, NULL otherwise and rte_errno is set. 2853 */ 2854 struct mlx5_devx_obj * 2855 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 2856 struct mlx5_devx_crypto_login_attr *attr) 2857 { 2858 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 2859 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2860 struct mlx5_devx_obj *crypto_login_obj = NULL; 2861 void *ptr = NULL, *credential_addr = NULL; 2862 2863 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 2864 0, SOCKET_ID_ANY); 2865 if (crypto_login_obj == NULL) { 2866 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 2867 rte_errno = ENOMEM; 2868 return NULL; 2869 } 2870 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 2871 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2872 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2873 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2874 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 2875 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 2876 MLX5_SET(crypto_login, ptr, credential_pointer, 2877 attr->credential_pointer); 2878 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 2879 attr->session_import_kek_ptr); 2880 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 2881 memcpy(credential_addr, (void *)(attr->credential), 2882 MLX5_CRYPTO_CREDENTIAL_SIZE); 2883 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2884 out, sizeof(out)); 2885 if (crypto_login_obj->obj == NULL) { 2886 rte_errno = errno; 2887 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX."); 2888 mlx5_free(crypto_login_obj); 2889 return NULL; 2890 } 2891 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2892 return crypto_login_obj; 2893 } 2894 2895 /** 2896 * Query LAG context. 2897 * 2898 * @param[in] ctx 2899 * Pointer to ibv_context, returned from mlx5dv_open_device. 2900 * @param[out] lag_ctx 2901 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 2902 * 2903 * @return 2904 * 0 on success, a negative value otherwise. 2905 */ 2906 int 2907 mlx5_devx_cmd_query_lag(void *ctx, 2908 struct mlx5_devx_lag_context *lag_ctx) 2909 { 2910 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 2911 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 2912 void *lctx; 2913 int rc; 2914 2915 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 2916 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 2917 if (rc) 2918 goto error; 2919 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 2920 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 2921 fdb_selection_mode); 2922 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 2923 port_select_mode); 2924 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 2925 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 2926 tx_remap_affinity_2); 2927 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 2928 tx_remap_affinity_1); 2929 return 0; 2930 error: 2931 rc = (rc > 0) ? -rc : rc; 2932 return rc; 2933 } 2934