1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /* FW writes status value to the OUT buffer at offset 00H */ 17 #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status) 18 /* FW writes syndrome value to the OUT buffer at offset 04H */ 19 #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome) 20 21 #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1)) 22 23 #define DEVX_DRV_LOG(level, out, reason, param, value) \ 24 do { \ 25 /* \ 26 * Some (old) GCC compilers like 7.5.0 and aarch64 GCC 7.1-2017.08 \ 27 * do not expand correctly when the macro invoked when the `param` \ 28 * is `NULL`. \ 29 * Use `local_param` to avoid direct `NULL` expansion. \ 30 */ \ 31 const char *local_param = (const char *)param; \ 32 \ 33 rte_errno = errno; \ 34 if (!local_param) { \ 35 DRV_LOG(level, \ 36 "DevX %s failed errno=%d status=%#x syndrome=%#x", \ 37 (reason), errno, MLX5_FW_STATUS((out)), \ 38 MLX5_FW_SYNDROME((out))); \ 39 } else { \ 40 DRV_LOG(level, \ 41 "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x",\ 42 (reason), local_param, (value), errno, \ 43 MLX5_FW_STATUS((out)), MLX5_FW_SYNDROME((out))); \ 44 } \ 45 } while (0) 46 47 static void * 48 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, 49 int *err, uint32_t flags) 50 { 51 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); 52 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); 53 int rc; 54 55 memset(in, 0, size_in); 56 memset(out, 0, size_out); 57 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 58 MLX5_SET(query_hca_cap_in, in, op_mod, flags); 59 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); 60 if (rc || MLX5_FW_STATUS(out)) { 61 DEVX_DRV_LOG(ERR, out, "HCA capabilities", "func", flags >> 1); 62 if (err) 63 *err = MLX5_DEVX_ERR_RC(rc); 64 return NULL; 65 } 66 if (err) 67 *err = 0; 68 return MLX5_ADDR_OF(query_hca_cap_out, out, capability); 69 } 70 71 /** 72 * Perform read access to the registers. Reads data from register 73 * and writes ones to the specified buffer. 74 * 75 * @param[in] ctx 76 * Context returned from mlx5 open_device() glue function. 77 * @param[in] reg_id 78 * Register identifier according to the PRM. 79 * @param[in] arg 80 * Register access auxiliary parameter according to the PRM. 81 * @param[out] data 82 * Pointer to the buffer to store read data. 83 * @param[in] dw_cnt 84 * Buffer size in double words. 85 * 86 * @return 87 * 0 on success, a negative value otherwise. 88 */ 89 int 90 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 91 uint32_t *data, uint32_t dw_cnt) 92 { 93 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 94 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 95 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 96 int rc; 97 98 MLX5_ASSERT(data && dw_cnt); 99 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 100 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 101 DRV_LOG(ERR, "Not enough buffer for register read data"); 102 return -1; 103 } 104 MLX5_SET(access_register_in, in, opcode, 105 MLX5_CMD_OP_ACCESS_REGISTER_USER); 106 MLX5_SET(access_register_in, in, op_mod, 107 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 108 MLX5_SET(access_register_in, in, register_id, reg_id); 109 MLX5_SET(access_register_in, in, argument, arg); 110 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 111 MLX5_ST_SZ_BYTES(access_register_out) + 112 sizeof(uint32_t) * dw_cnt); 113 if (rc || MLX5_FW_STATUS(out)) { 114 DEVX_DRV_LOG(ERR, out, "read access", "NIC register", reg_id); 115 return MLX5_DEVX_ERR_RC(rc); 116 } 117 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 118 dw_cnt * sizeof(uint32_t)); 119 return 0; 120 } 121 122 /** 123 * Perform write access to the registers. 124 * 125 * @param[in] ctx 126 * Context returned from mlx5 open_device() glue function. 127 * @param[in] reg_id 128 * Register identifier according to the PRM. 129 * @param[in] arg 130 * Register access auxiliary parameter according to the PRM. 131 * @param[out] data 132 * Pointer to the buffer containing data to write. 133 * @param[in] dw_cnt 134 * Buffer size in double words (32bit units). 135 * 136 * @return 137 * 0 on success, a negative value otherwise. 138 */ 139 int 140 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 141 uint32_t *data, uint32_t dw_cnt) 142 { 143 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 144 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 145 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 146 int rc; 147 void *ptr; 148 149 MLX5_ASSERT(data && dw_cnt); 150 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 151 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 152 DRV_LOG(ERR, "Data to write exceeds max size"); 153 return -1; 154 } 155 MLX5_SET(access_register_in, in, opcode, 156 MLX5_CMD_OP_ACCESS_REGISTER_USER); 157 MLX5_SET(access_register_in, in, op_mod, 158 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 159 MLX5_SET(access_register_in, in, register_id, reg_id); 160 MLX5_SET(access_register_in, in, argument, arg); 161 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 162 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 163 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 164 if (rc || MLX5_FW_STATUS(out)) { 165 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 166 return MLX5_DEVX_ERR_RC(rc); 167 } 168 rc = mlx5_glue->devx_general_cmd(ctx, in, 169 MLX5_ST_SZ_BYTES(access_register_in) + 170 dw_cnt * sizeof(uint32_t), 171 out, sizeof(out)); 172 if (rc || MLX5_FW_STATUS(out)) { 173 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 174 return MLX5_DEVX_ERR_RC(rc); 175 } 176 return 0; 177 } 178 179 /** 180 * Allocate flow counters via devx interface. 181 * 182 * @param[in] ctx 183 * Context returned from mlx5 open_device() glue function. 184 * @param dcs 185 * Pointer to counters properties structure to be filled by the routine. 186 * @param bulk_n_128 187 * Bulk counter numbers in 128 counters units. 188 * 189 * @return 190 * Pointer to counter object on success, a negative value otherwise and 191 * rte_errno is set. 192 */ 193 struct mlx5_devx_obj * 194 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 195 { 196 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 197 0, SOCKET_ID_ANY); 198 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 199 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 200 201 if (!dcs) { 202 rte_errno = ENOMEM; 203 return NULL; 204 } 205 MLX5_SET(alloc_flow_counter_in, in, opcode, 206 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 207 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 208 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 209 sizeof(in), out, sizeof(out)); 210 if (!dcs->obj) { 211 DEVX_DRV_LOG(ERR, out, "allocate counters", NULL, 0); 212 mlx5_free(dcs); 213 return NULL; 214 } 215 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 216 return dcs; 217 } 218 219 /** 220 * Query flow counters values. 221 * 222 * @param[in] dcs 223 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 224 * @param[in] clear 225 * Whether hardware should clear the counters after the query or not. 226 * @param[in] n_counters 227 * 0 in case of 1 counter to read, otherwise the counter number to read. 228 * @param pkts 229 * The number of packets that matched the flow. 230 * @param bytes 231 * The number of bytes that matched the flow. 232 * @param mkey 233 * The mkey key for batch query. 234 * @param addr 235 * The address in the mkey range for batch query. 236 * @param cmd_comp 237 * The completion object for asynchronous batch query. 238 * @param async_id 239 * The ID to be returned in the asynchronous batch query response. 240 * 241 * @return 242 * 0 on success, a negative value otherwise. 243 */ 244 int 245 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 246 int clear, uint32_t n_counters, 247 uint64_t *pkts, uint64_t *bytes, 248 uint32_t mkey, void *addr, 249 void *cmd_comp, 250 uint64_t async_id) 251 { 252 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 253 MLX5_ST_SZ_BYTES(traffic_counter); 254 uint32_t out[out_len]; 255 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 256 void *stats; 257 int rc; 258 259 MLX5_SET(query_flow_counter_in, in, opcode, 260 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 261 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 262 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 263 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 264 265 if (n_counters) { 266 MLX5_SET(query_flow_counter_in, in, num_of_counters, 267 n_counters); 268 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 269 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 270 MLX5_SET64(query_flow_counter_in, in, address, 271 (uint64_t)(uintptr_t)addr); 272 } 273 if (!cmd_comp) 274 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 275 out_len); 276 else 277 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 278 out_len, async_id, 279 cmd_comp); 280 if (rc) { 281 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 282 rte_errno = rc; 283 return -rc; 284 } 285 if (!n_counters) { 286 stats = MLX5_ADDR_OF(query_flow_counter_out, 287 out, flow_statistics); 288 *pkts = MLX5_GET64(traffic_counter, stats, packets); 289 *bytes = MLX5_GET64(traffic_counter, stats, octets); 290 } 291 return 0; 292 } 293 294 /** 295 * Create a new mkey. 296 * 297 * @param[in] ctx 298 * Context returned from mlx5 open_device() glue function. 299 * @param[in] attr 300 * Attributes of the requested mkey. 301 * 302 * @return 303 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 304 * is set. 305 */ 306 struct mlx5_devx_obj * 307 mlx5_devx_cmd_mkey_create(void *ctx, 308 struct mlx5_devx_mkey_attr *attr) 309 { 310 struct mlx5_klm *klm_array = attr->klm_array; 311 int klm_num = attr->klm_num; 312 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 313 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 314 uint32_t in[in_size_dw]; 315 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 316 void *mkc; 317 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 318 0, SOCKET_ID_ANY); 319 size_t pgsize; 320 uint32_t translation_size; 321 322 if (!mkey) { 323 rte_errno = ENOMEM; 324 return NULL; 325 } 326 memset(in, 0, in_size_dw * 4); 327 pgsize = rte_mem_page_size(); 328 if (pgsize == (size_t)-1) { 329 mlx5_free(mkey); 330 DRV_LOG(ERR, "Failed to get page size"); 331 rte_errno = ENOMEM; 332 return NULL; 333 } 334 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 335 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 336 if (klm_num > 0) { 337 int i; 338 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 339 klm_pas_mtt); 340 translation_size = RTE_ALIGN(klm_num, 4); 341 for (i = 0; i < klm_num; i++) { 342 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 343 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 344 MLX5_SET64(klm, klm, address, klm_array[i].address); 345 klm += MLX5_ST_SZ_BYTES(klm); 346 } 347 for (; i < (int)translation_size; i++) { 348 MLX5_SET(klm, klm, mkey, 0x0); 349 MLX5_SET64(klm, klm, address, 0x0); 350 klm += MLX5_ST_SZ_BYTES(klm); 351 } 352 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 353 MLX5_MKC_ACCESS_MODE_KLM_FBS : 354 MLX5_MKC_ACCESS_MODE_KLM); 355 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 356 } else { 357 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 358 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 359 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 360 } 361 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 362 translation_size); 363 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 364 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 365 MLX5_SET(mkc, mkc, lw, 0x1); 366 MLX5_SET(mkc, mkc, lr, 0x1); 367 if (attr->set_remote_rw) { 368 MLX5_SET(mkc, mkc, rw, 0x1); 369 MLX5_SET(mkc, mkc, rr, 0x1); 370 } 371 MLX5_SET(mkc, mkc, qpn, 0xffffff); 372 MLX5_SET(mkc, mkc, pd, attr->pd); 373 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 374 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 375 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 376 MLX5_SET(mkc, mkc, relaxed_ordering_write, 377 attr->relaxed_ordering_write); 378 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 379 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 380 MLX5_SET64(mkc, mkc, len, attr->size); 381 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 382 if (attr->crypto_en) { 383 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 384 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 385 } 386 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 387 sizeof(out)); 388 if (!mkey->obj) { 389 DEVX_DRV_LOG(ERR, out, klm_num ? "create indirect mkey" 390 : "create direct key", NULL, 0); 391 mlx5_free(mkey); 392 return NULL; 393 } 394 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 395 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 396 return mkey; 397 } 398 399 /** 400 * Get status of devx command response. 401 * Mainly used for asynchronous commands. 402 * 403 * @param[in] out 404 * The out response buffer. 405 * 406 * @return 407 * 0 on success, non-zero value otherwise. 408 */ 409 int 410 mlx5_devx_get_out_command_status(void *out) 411 { 412 int status; 413 414 if (!out) 415 return -EINVAL; 416 status = MLX5_GET(query_flow_counter_out, out, status); 417 if (status) { 418 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 419 420 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 421 syndrome); 422 } 423 return status; 424 } 425 426 /** 427 * Destroy any object allocated by a Devx API. 428 * 429 * @param[in] obj 430 * Pointer to a general object. 431 * 432 * @return 433 * 0 on success, a negative value otherwise. 434 */ 435 int 436 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 437 { 438 int ret; 439 440 if (!obj) 441 return 0; 442 ret = mlx5_glue->devx_obj_destroy(obj->obj); 443 mlx5_free(obj); 444 return ret; 445 } 446 447 /** 448 * Query NIC vport context. 449 * Fills minimal inline attribute. 450 * 451 * @param[in] ctx 452 * ibv contexts returned from mlx5dv_open_device. 453 * @param[in] vport 454 * vport index 455 * @param[out] attr 456 * Attributes device values. 457 * 458 * @return 459 * 0 on success, a negative value otherwise. 460 */ 461 static int 462 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 463 unsigned int vport, 464 struct mlx5_hca_attr *attr) 465 { 466 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 467 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 468 void *vctx; 469 int rc; 470 471 /* Query NIC vport context to determine inline mode. */ 472 MLX5_SET(query_nic_vport_context_in, in, opcode, 473 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 474 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 475 if (vport) 476 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 477 rc = mlx5_glue->devx_general_cmd(ctx, 478 in, sizeof(in), 479 out, sizeof(out)); 480 if (rc || MLX5_FW_STATUS(out)) { 481 DEVX_DRV_LOG(ERR, out, "query NIC vport context", NULL, 0); 482 return MLX5_DEVX_ERR_RC(rc); 483 } 484 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 485 nic_vport_context); 486 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 487 min_wqe_inline_mode); 488 return 0; 489 } 490 491 /** 492 * Query NIC vDPA attributes. 493 * 494 * @param[in] ctx 495 * Context returned from mlx5 open_device() glue function. 496 * @param[out] vdpa_attr 497 * vDPA Attributes structure to fill. 498 */ 499 static void 500 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 501 struct mlx5_hca_vdpa_attr *vdpa_attr) 502 { 503 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 504 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 505 void *hcattr; 506 507 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, 508 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 509 MLX5_HCA_CAP_OPMOD_GET_CUR); 510 if (!hcattr) { 511 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities"); 512 vdpa_attr->valid = 0; 513 } else { 514 vdpa_attr->valid = 1; 515 vdpa_attr->desc_tunnel_offload_type = 516 MLX5_GET(virtio_emulation_cap, hcattr, 517 desc_tunnel_offload_type); 518 vdpa_attr->eth_frame_offload_type = 519 MLX5_GET(virtio_emulation_cap, hcattr, 520 eth_frame_offload_type); 521 vdpa_attr->virtio_version_1_0 = 522 MLX5_GET(virtio_emulation_cap, hcattr, 523 virtio_version_1_0); 524 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 525 tso_ipv4); 526 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 527 tso_ipv6); 528 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 529 tx_csum); 530 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 531 rx_csum); 532 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 533 event_mode); 534 vdpa_attr->virtio_queue_type = 535 MLX5_GET(virtio_emulation_cap, hcattr, 536 virtio_queue_type); 537 vdpa_attr->log_doorbell_stride = 538 MLX5_GET(virtio_emulation_cap, hcattr, 539 log_doorbell_stride); 540 vdpa_attr->vnet_modify_ext = 541 MLX5_GET(virtio_emulation_cap, hcattr, 542 vnet_modify_ext); 543 vdpa_attr->virtio_net_q_addr_modify = 544 MLX5_GET(virtio_emulation_cap, hcattr, 545 virtio_net_q_addr_modify); 546 vdpa_attr->virtio_q_index_modify = 547 MLX5_GET(virtio_emulation_cap, hcattr, 548 virtio_q_index_modify); 549 vdpa_attr->log_doorbell_bar_size = 550 MLX5_GET(virtio_emulation_cap, hcattr, 551 log_doorbell_bar_size); 552 vdpa_attr->doorbell_bar_offset = 553 MLX5_GET64(virtio_emulation_cap, hcattr, 554 doorbell_bar_offset); 555 vdpa_attr->max_num_virtio_queues = 556 MLX5_GET(virtio_emulation_cap, hcattr, 557 max_num_virtio_queues); 558 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 559 umem_1_buffer_param_a); 560 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 561 umem_1_buffer_param_b); 562 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 563 umem_2_buffer_param_a); 564 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 565 umem_2_buffer_param_b); 566 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 567 umem_3_buffer_param_a); 568 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 569 umem_3_buffer_param_b); 570 } 571 } 572 573 int 574 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 575 uint32_t ids[], uint32_t num) 576 { 577 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 578 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 579 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 580 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 581 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 582 int ret; 583 uint32_t idx = 0; 584 uint32_t i; 585 586 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 587 rte_errno = EINVAL; 588 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 589 return -rte_errno; 590 } 591 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 592 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 593 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 594 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 595 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 596 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 597 out, sizeof(out)); 598 if (ret) { 599 rte_errno = ret; 600 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 601 (void *)flex_obj); 602 return -rte_errno; 603 } 604 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 605 void *s_off = (void *)((char *)sample + i * 606 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 607 uint32_t en; 608 609 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 610 flow_match_sample_en); 611 if (!en) 612 continue; 613 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 614 flow_match_sample_field_id); 615 } 616 if (num != idx) { 617 rte_errno = EINVAL; 618 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 619 return -rte_errno; 620 } 621 return ret; 622 } 623 624 struct mlx5_devx_obj * 625 mlx5_devx_cmd_create_flex_parser(void *ctx, 626 struct mlx5_devx_graph_node_attr *data) 627 { 628 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 629 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 630 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 631 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 632 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 633 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 634 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 635 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 636 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 637 uint32_t i; 638 639 if (!parse_flex_obj) { 640 DRV_LOG(ERR, "Failed to allocate flex parser data."); 641 rte_errno = ENOMEM; 642 return NULL; 643 } 644 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 645 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 646 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 647 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 648 MLX5_SET(parse_graph_flex, flex, header_length_mode, 649 data->header_length_mode); 650 MLX5_SET64(parse_graph_flex, flex, modify_field_select, 651 data->modify_field_select); 652 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 653 data->header_length_base_value); 654 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 655 data->header_length_field_offset); 656 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 657 data->header_length_field_shift); 658 MLX5_SET(parse_graph_flex, flex, next_header_field_offset, 659 data->next_header_field_offset); 660 MLX5_SET(parse_graph_flex, flex, next_header_field_size, 661 data->next_header_field_size); 662 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 663 data->header_length_field_mask); 664 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 665 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 666 void *s_off = (void *)((char *)sample + i * 667 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 668 669 if (!s->flow_match_sample_en) 670 continue; 671 MLX5_SET(parse_graph_flow_match_sample, s_off, 672 flow_match_sample_en, !!s->flow_match_sample_en); 673 MLX5_SET(parse_graph_flow_match_sample, s_off, 674 flow_match_sample_field_offset, 675 s->flow_match_sample_field_offset); 676 MLX5_SET(parse_graph_flow_match_sample, s_off, 677 flow_match_sample_offset_mode, 678 s->flow_match_sample_offset_mode); 679 MLX5_SET(parse_graph_flow_match_sample, s_off, 680 flow_match_sample_field_offset_mask, 681 s->flow_match_sample_field_offset_mask); 682 MLX5_SET(parse_graph_flow_match_sample, s_off, 683 flow_match_sample_field_offset_shift, 684 s->flow_match_sample_field_offset_shift); 685 MLX5_SET(parse_graph_flow_match_sample, s_off, 686 flow_match_sample_field_base_offset, 687 s->flow_match_sample_field_base_offset); 688 MLX5_SET(parse_graph_flow_match_sample, s_off, 689 flow_match_sample_tunnel_mode, 690 s->flow_match_sample_tunnel_mode); 691 } 692 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 693 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 694 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 695 void *in_off = (void *)((char *)in_arc + i * 696 MLX5_ST_SZ_BYTES(parse_graph_arc)); 697 void *out_off = (void *)((char *)out_arc + i * 698 MLX5_ST_SZ_BYTES(parse_graph_arc)); 699 700 if (ia->arc_parse_graph_node != 0) { 701 MLX5_SET(parse_graph_arc, in_off, 702 compare_condition_value, 703 ia->compare_condition_value); 704 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 705 ia->start_inner_tunnel); 706 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 707 ia->arc_parse_graph_node); 708 MLX5_SET(parse_graph_arc, in_off, 709 parse_graph_node_handle, 710 ia->parse_graph_node_handle); 711 } 712 if (oa->arc_parse_graph_node != 0) { 713 MLX5_SET(parse_graph_arc, out_off, 714 compare_condition_value, 715 oa->compare_condition_value); 716 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 717 oa->start_inner_tunnel); 718 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 719 oa->arc_parse_graph_node); 720 MLX5_SET(parse_graph_arc, out_off, 721 parse_graph_node_handle, 722 oa->parse_graph_node_handle); 723 } 724 } 725 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 726 out, sizeof(out)); 727 if (!parse_flex_obj->obj) { 728 DEVX_DRV_LOG(ERR, out, "create FLEX PARSE GRAPH", NULL, 0); 729 mlx5_free(parse_flex_obj); 730 return NULL; 731 } 732 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 733 return parse_flex_obj; 734 } 735 736 static int 737 mlx5_devx_cmd_query_hca_parse_graph_node_cap 738 (void *ctx, struct mlx5_hca_flex_attr *attr) 739 { 740 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 741 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 742 void *hcattr; 743 int rc; 744 745 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 746 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | 747 MLX5_HCA_CAP_OPMOD_GET_CUR); 748 if (!hcattr) 749 return rc; 750 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); 751 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); 752 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, 753 header_length_mode); 754 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, 755 sample_offset_mode); 756 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, 757 max_num_arc_in); 758 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, 759 max_num_arc_out); 760 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, 761 max_num_sample); 762 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, 763 sample_id_in_out); 764 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, 765 max_base_header_length); 766 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, 767 max_sample_base_offset); 768 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, 769 max_next_header_offset); 770 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, 771 header_length_mask_width); 772 /* Get the max supported samples from HCA CAP 2 */ 773 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 774 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 775 MLX5_HCA_CAP_OPMOD_GET_CUR); 776 if (!hcattr) 777 return rc; 778 attr->max_num_prog_sample = 779 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); 780 return 0; 781 } 782 783 static int 784 mlx5_devx_query_pkt_integrity_match(void *hcattr) 785 { 786 return MLX5_GET(flow_table_nic_cap, hcattr, 787 ft_field_support_2_nic_receive.inner_l3_ok) && 788 MLX5_GET(flow_table_nic_cap, hcattr, 789 ft_field_support_2_nic_receive.inner_l4_ok) && 790 MLX5_GET(flow_table_nic_cap, hcattr, 791 ft_field_support_2_nic_receive.outer_l3_ok) && 792 MLX5_GET(flow_table_nic_cap, hcattr, 793 ft_field_support_2_nic_receive.outer_l4_ok) && 794 MLX5_GET(flow_table_nic_cap, hcattr, 795 ft_field_support_2_nic_receive 796 .inner_ipv4_checksum_ok) && 797 MLX5_GET(flow_table_nic_cap, hcattr, 798 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 799 MLX5_GET(flow_table_nic_cap, hcattr, 800 ft_field_support_2_nic_receive 801 .outer_ipv4_checksum_ok) && 802 MLX5_GET(flow_table_nic_cap, hcattr, 803 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 804 } 805 806 /** 807 * Query HCA attributes. 808 * Using those attributes we can check on run time if the device 809 * is having the required capabilities. 810 * 811 * @param[in] ctx 812 * Context returned from mlx5 open_device() glue function. 813 * @param[out] attr 814 * Attributes device values. 815 * 816 * @return 817 * 0 on success, a negative value otherwise. 818 */ 819 int 820 mlx5_devx_cmd_query_hca_attr(void *ctx, 821 struct mlx5_hca_attr *attr) 822 { 823 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 824 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 825 bool hca_cap_2_sup; 826 uint64_t general_obj_types_supported = 0; 827 void *hcattr; 828 int rc, i; 829 830 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 831 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 832 MLX5_HCA_CAP_OPMOD_GET_CUR); 833 if (!hcattr) 834 return rc; 835 hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2); 836 attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq); 837 attr->flow_counter_bulk_alloc_bitmap = 838 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 839 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 840 flow_counters_dump); 841 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp); 842 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp); 843 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 844 log_max_rqt_size); 845 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 846 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 847 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 848 log_max_hairpin_queues); 849 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 850 log_max_hairpin_wq_data_sz); 851 attr->log_max_hairpin_num_packets = MLX5_GET 852 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 853 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 854 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 855 relaxed_ordering_write); 856 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 857 relaxed_ordering_read); 858 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 859 access_register_user); 860 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 861 eth_net_offloads); 862 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 863 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 864 flex_parser_protocols); 865 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 866 max_geneve_tlv_options); 867 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 868 max_geneve_tlv_option_data_len); 869 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 870 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 871 general_obj_types) & 872 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 873 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 874 general_obj_types) & 875 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 876 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 877 general_obj_types) & 878 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 879 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 880 general_obj_types) & 881 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 882 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 883 wqe_index_ignore_cap); 884 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 885 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 886 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 887 log_max_static_sq_wq); 888 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 889 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 890 device_frequency_khz); 891 attr->scatter_fcs_w_decap_disable = 892 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 893 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 894 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 895 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 896 attr->steering_format_version = 897 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 898 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 899 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 900 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 901 regexp_num_of_engines); 902 /* Read the general_obj_types bitmap and extract the relevant bits. */ 903 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 904 general_obj_types); 905 attr->vdpa.valid = !!(general_obj_types_supported & 906 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 907 attr->vdpa.queue_counters_valid = 908 !!(general_obj_types_supported & 909 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 910 attr->parse_graph_flex_node = 911 !!(general_obj_types_supported & 912 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 913 attr->flow_hit_aso = !!(general_obj_types_supported & 914 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 915 attr->geneve_tlv_opt = !!(general_obj_types_supported & 916 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 917 attr->dek = !!(general_obj_types_supported & 918 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 919 attr->import_kek = !!(general_obj_types_supported & 920 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 921 attr->credential = !!(general_obj_types_supported & 922 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 923 attr->crypto_login = !!(general_obj_types_supported & 924 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 925 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 926 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 927 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 928 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 929 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 930 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 931 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 932 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 933 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 934 attr->reg_c_preserve = 935 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 936 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 937 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 938 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 939 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 940 compress_mmo_sq); 941 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 942 decompress_mmo_sq); 943 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 944 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 945 compress_mmo_qp); 946 attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 947 decompress_mmo_qp); 948 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 949 compress_min_block_size); 950 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 951 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 952 log_compress_mmo_size); 953 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 954 log_decompress_mmo_size); 955 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 956 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 957 mini_cqe_resp_flow_tag); 958 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 959 mini_cqe_resp_l3_l4_tag); 960 attr->umr_indirect_mkey_disabled = 961 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 962 attr->umr_modify_entity_size_disabled = 963 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 964 attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time); 965 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 966 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 967 general_obj_types) & 968 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 969 attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); 970 if (attr->crypto) { 971 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts); 972 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 973 MLX5_GET_HCA_CAP_OP_MOD_CRYPTO | 974 MLX5_HCA_CAP_OPMOD_GET_CUR); 975 if (!hcattr) 976 return -1; 977 attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps, 978 hcattr, wrapped_import_method) 979 & 1 << 2); 980 } 981 if (hca_cap_2_sup) { 982 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 983 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 984 MLX5_HCA_CAP_OPMOD_GET_CUR); 985 if (!hcattr) { 986 DRV_LOG(DEBUG, 987 "Failed to query DevX HCA capabilities 2."); 988 return rc; 989 } 990 attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, 991 log_min_stride_wqe_sz); 992 attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr, 993 hairpin_sq_wqe_bb_size); 994 attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr, 995 hairpin_sq_wq_in_host_mem); 996 attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr, 997 hairpin_data_buffer_locked); 998 } 999 if (attr->log_min_stride_wqe_sz == 0) 1000 attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 1001 if (attr->qos.sup) { 1002 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1003 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 1004 MLX5_HCA_CAP_OPMOD_GET_CUR); 1005 if (!hcattr) { 1006 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); 1007 return rc; 1008 } 1009 attr->qos.flow_meter_old = 1010 MLX5_GET(qos_cap, hcattr, flow_meter_old); 1011 attr->qos.log_max_flow_meter = 1012 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 1013 attr->qos.flow_meter_reg_c_ids = 1014 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 1015 attr->qos.flow_meter = 1016 MLX5_GET(qos_cap, hcattr, flow_meter); 1017 attr->qos.packet_pacing = 1018 MLX5_GET(qos_cap, hcattr, packet_pacing); 1019 attr->qos.wqe_rate_pp = 1020 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 1021 if (attr->qos.flow_meter_aso_sup) { 1022 attr->qos.log_meter_aso_granularity = 1023 MLX5_GET(qos_cap, hcattr, 1024 log_meter_aso_granularity); 1025 attr->qos.log_meter_aso_max_alloc = 1026 MLX5_GET(qos_cap, hcattr, 1027 log_meter_aso_max_alloc); 1028 attr->qos.log_max_num_meter_aso = 1029 MLX5_GET(qos_cap, hcattr, 1030 log_max_num_meter_aso); 1031 } 1032 } 1033 /* 1034 * Flex item support needs max_num_prog_sample_field 1035 * from the Capabilities 2 table for PARSE_GRAPH_NODE 1036 */ 1037 if (attr->parse_graph_flex_node) { 1038 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap 1039 (ctx, &attr->flex); 1040 if (rc) 1041 return -1; 1042 } 1043 if (attr->vdpa.valid) 1044 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 1045 if (!attr->eth_net_offloads) 1046 return 0; 1047 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 1048 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1049 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 1050 MLX5_HCA_CAP_OPMOD_GET_CUR); 1051 if (!hcattr) { 1052 attr->log_max_ft_sampler_num = 0; 1053 return rc; 1054 } 1055 attr->log_max_ft_sampler_num = MLX5_GET 1056 (flow_table_nic_cap, hcattr, 1057 flow_table_properties_nic_receive.log_max_ft_sampler_num); 1058 attr->flow.tunnel_header_0_1 = MLX5_GET 1059 (flow_table_nic_cap, hcattr, 1060 ft_field_support_2_nic_receive.tunnel_header_0_1); 1061 attr->flow.tunnel_header_2_3 = MLX5_GET 1062 (flow_table_nic_cap, hcattr, 1063 ft_field_support_2_nic_receive.tunnel_header_2_3); 1064 attr->modify_outer_ip_ecn = MLX5_GET 1065 (flow_table_nic_cap, hcattr, 1066 ft_header_modify_nic_receive.outer_ip_ecn); 1067 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 1068 attr->inner_ipv4_ihl = MLX5_GET 1069 (flow_table_nic_cap, hcattr, 1070 ft_field_support_2_nic_receive.inner_ipv4_ihl); 1071 attr->outer_ipv4_ihl = MLX5_GET 1072 (flow_table_nic_cap, hcattr, 1073 ft_field_support_2_nic_receive.outer_ipv4_ihl); 1074 /* Query HCA offloads for Ethernet protocol. */ 1075 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1076 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 1077 MLX5_HCA_CAP_OPMOD_GET_CUR); 1078 if (!hcattr) { 1079 attr->eth_net_offloads = 0; 1080 return rc; 1081 } 1082 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 1083 hcattr, wqe_vlan_insert); 1084 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 1085 hcattr, csum_cap); 1086 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 1087 hcattr, vlan_cap); 1088 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1089 lro_cap); 1090 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1091 hcattr, max_lso_cap); 1092 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1093 hcattr, scatter_fcs); 1094 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1095 hcattr, tunnel_lro_gre); 1096 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1097 hcattr, tunnel_lro_vxlan); 1098 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1099 hcattr, swp); 1100 attr->tunnel_stateless_gre = 1101 MLX5_GET(per_protocol_networking_offload_caps, 1102 hcattr, tunnel_stateless_gre); 1103 attr->tunnel_stateless_vxlan = 1104 MLX5_GET(per_protocol_networking_offload_caps, 1105 hcattr, tunnel_stateless_vxlan); 1106 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1107 hcattr, swp_csum); 1108 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1109 hcattr, swp_lso); 1110 attr->lro_max_msg_sz_mode = MLX5_GET 1111 (per_protocol_networking_offload_caps, 1112 hcattr, lro_max_msg_sz_mode); 1113 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1114 attr->lro_timer_supported_periods[i] = 1115 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1116 lro_timer_supported_periods[i]); 1117 } 1118 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1119 hcattr, lro_min_mss_size); 1120 attr->tunnel_stateless_geneve_rx = 1121 MLX5_GET(per_protocol_networking_offload_caps, 1122 hcattr, tunnel_stateless_geneve_rx); 1123 attr->geneve_max_opt_len = 1124 MLX5_GET(per_protocol_networking_offload_caps, 1125 hcattr, max_geneve_opt_len); 1126 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1127 hcattr, wqe_inline_mode); 1128 attr->tunnel_stateless_gtp = MLX5_GET 1129 (per_protocol_networking_offload_caps, 1130 hcattr, tunnel_stateless_gtp); 1131 attr->rss_ind_tbl_cap = MLX5_GET 1132 (per_protocol_networking_offload_caps, 1133 hcattr, rss_ind_tbl_cap); 1134 /* Query HCA attribute for ROCE. */ 1135 if (attr->roce) { 1136 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1137 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1138 MLX5_HCA_CAP_OPMOD_GET_CUR); 1139 if (!hcattr) { 1140 DRV_LOG(DEBUG, 1141 "Failed to query devx HCA ROCE capabilities"); 1142 return rc; 1143 } 1144 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1145 } 1146 if (attr->eth_virt && 1147 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1148 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1149 if (rc) { 1150 attr->eth_virt = 0; 1151 goto error; 1152 } 1153 } 1154 if (attr->eswitch_manager) { 1155 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1156 MLX5_SET_HCA_CAP_OP_MOD_ESW | 1157 MLX5_HCA_CAP_OPMOD_GET_CUR); 1158 if (!hcattr) 1159 return rc; 1160 attr->esw_mgr_vport_id_valid = 1161 MLX5_GET(esw_cap, hcattr, 1162 esw_manager_vport_number_valid); 1163 attr->esw_mgr_vport_id = 1164 MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); 1165 } 1166 return 0; 1167 error: 1168 rc = (rc > 0) ? -rc : rc; 1169 return rc; 1170 } 1171 1172 /** 1173 * Query TIS transport domain from QP verbs object using DevX API. 1174 * 1175 * @param[in] qp 1176 * Pointer to verbs QP returned by ibv_create_qp . 1177 * @param[in] tis_num 1178 * TIS number of TIS to query. 1179 * @param[out] tis_td 1180 * Pointer to TIS transport domain variable, to be set by the routine. 1181 * 1182 * @return 1183 * 0 on success, a negative value otherwise. 1184 */ 1185 int 1186 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1187 uint32_t *tis_td) 1188 { 1189 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1190 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1191 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1192 int rc; 1193 void *tis_ctx; 1194 1195 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1196 MLX5_SET(query_tis_in, in, tisn, tis_num); 1197 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1198 if (rc) { 1199 DRV_LOG(ERR, "Failed to query QP using DevX"); 1200 return -rc; 1201 }; 1202 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1203 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1204 return 0; 1205 #else 1206 (void)qp; 1207 (void)tis_num; 1208 (void)tis_td; 1209 return -ENOTSUP; 1210 #endif 1211 } 1212 1213 /** 1214 * Fill WQ data for DevX API command. 1215 * Utility function for use when creating DevX objects containing a WQ. 1216 * 1217 * @param[in] wq_ctx 1218 * Pointer to WQ context to fill with data. 1219 * @param [in] wq_attr 1220 * Pointer to WQ attributes structure to fill in WQ context. 1221 */ 1222 static void 1223 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1224 { 1225 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1226 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1227 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1228 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1229 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1230 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1231 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1232 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1233 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1234 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1235 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1236 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1237 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1238 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1239 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1240 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1241 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1242 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1243 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1244 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1245 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1246 wq_attr->log_hairpin_num_packets); 1247 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1248 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1249 wq_attr->single_wqe_log_num_of_strides); 1250 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1251 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1252 wq_attr->single_stride_log_num_of_bytes); 1253 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1254 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1255 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1256 } 1257 1258 /** 1259 * Create RQ using DevX API. 1260 * 1261 * @param[in] ctx 1262 * Context returned from mlx5 open_device() glue function. 1263 * @param [in] rq_attr 1264 * Pointer to create RQ attributes structure. 1265 * @param [in] socket 1266 * CPU socket ID for allocations. 1267 * 1268 * @return 1269 * The DevX object created, NULL otherwise and rte_errno is set. 1270 */ 1271 struct mlx5_devx_obj * 1272 mlx5_devx_cmd_create_rq(void *ctx, 1273 struct mlx5_devx_create_rq_attr *rq_attr, 1274 int socket) 1275 { 1276 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1277 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1278 void *rq_ctx, *wq_ctx; 1279 struct mlx5_devx_wq_attr *wq_attr; 1280 struct mlx5_devx_obj *rq = NULL; 1281 1282 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1283 if (!rq) { 1284 DRV_LOG(ERR, "Failed to allocate RQ data"); 1285 rte_errno = ENOMEM; 1286 return NULL; 1287 } 1288 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1289 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1290 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1291 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1292 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1293 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1294 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1295 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1296 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1297 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1298 MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type); 1299 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1300 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1301 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1302 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1303 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1304 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1305 wq_attr = &rq_attr->wq_attr; 1306 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1307 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1308 out, sizeof(out)); 1309 if (!rq->obj) { 1310 DEVX_DRV_LOG(ERR, out, "create RQ", NULL, 0); 1311 mlx5_free(rq); 1312 return NULL; 1313 } 1314 rq->id = MLX5_GET(create_rq_out, out, rqn); 1315 return rq; 1316 } 1317 1318 /** 1319 * Modify RQ using DevX API. 1320 * 1321 * @param[in] rq 1322 * Pointer to RQ object structure. 1323 * @param [in] rq_attr 1324 * Pointer to modify RQ attributes structure. 1325 * 1326 * @return 1327 * 0 on success, a negative errno value otherwise and rte_errno is set. 1328 */ 1329 int 1330 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1331 struct mlx5_devx_modify_rq_attr *rq_attr) 1332 { 1333 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1334 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1335 void *rq_ctx, *wq_ctx; 1336 int ret; 1337 1338 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1339 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1340 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1341 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1342 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1343 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1344 if (rq_attr->modify_bitmask & 1345 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1346 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1347 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1348 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1349 if (rq_attr->modify_bitmask & 1350 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1351 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1352 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1353 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1354 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1355 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1356 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1357 } 1358 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1359 out, sizeof(out)); 1360 if (ret) { 1361 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1362 rte_errno = errno; 1363 return -errno; 1364 } 1365 return ret; 1366 } 1367 1368 /** 1369 * Create RMP using DevX API. 1370 * 1371 * @param[in] ctx 1372 * Context returned from mlx5 open_device() glue function. 1373 * @param [in] rmp_attr 1374 * Pointer to create RMP attributes structure. 1375 * @param [in] socket 1376 * CPU socket ID for allocations. 1377 * 1378 * @return 1379 * The DevX object created, NULL otherwise and rte_errno is set. 1380 */ 1381 struct mlx5_devx_obj * 1382 mlx5_devx_cmd_create_rmp(void *ctx, 1383 struct mlx5_devx_create_rmp_attr *rmp_attr, 1384 int socket) 1385 { 1386 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0}; 1387 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0}; 1388 void *rmp_ctx, *wq_ctx; 1389 struct mlx5_devx_wq_attr *wq_attr; 1390 struct mlx5_devx_obj *rmp = NULL; 1391 1392 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket); 1393 if (!rmp) { 1394 DRV_LOG(ERR, "Failed to allocate RMP data"); 1395 rte_errno = ENOMEM; 1396 return NULL; 1397 } 1398 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP); 1399 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx); 1400 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state); 1401 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe, 1402 rmp_attr->basic_cyclic_rcv_wqe); 1403 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq); 1404 wq_attr = &rmp_attr->wq_attr; 1405 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1406 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1407 sizeof(out)); 1408 if (!rmp->obj) { 1409 DEVX_DRV_LOG(ERR, out, "create RMP", NULL, 0); 1410 mlx5_free(rmp); 1411 return NULL; 1412 } 1413 rmp->id = MLX5_GET(create_rmp_out, out, rmpn); 1414 return rmp; 1415 } 1416 1417 /* 1418 * Create TIR using DevX API. 1419 * 1420 * @param[in] ctx 1421 * Context returned from mlx5 open_device() glue function. 1422 * @param [in] tir_attr 1423 * Pointer to TIR attributes structure. 1424 * 1425 * @return 1426 * The DevX object created, NULL otherwise and rte_errno is set. 1427 */ 1428 struct mlx5_devx_obj * 1429 mlx5_devx_cmd_create_tir(void *ctx, 1430 struct mlx5_devx_tir_attr *tir_attr) 1431 { 1432 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1433 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1434 void *tir_ctx, *outer, *inner, *rss_key; 1435 struct mlx5_devx_obj *tir = NULL; 1436 1437 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1438 if (!tir) { 1439 DRV_LOG(ERR, "Failed to allocate TIR data"); 1440 rte_errno = ENOMEM; 1441 return NULL; 1442 } 1443 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1444 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1445 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1446 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1447 tir_attr->lro_timeout_period_usecs); 1448 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1449 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1450 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1451 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1452 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1453 tir_attr->tunneled_offload_en); 1454 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1455 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1456 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1457 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1458 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1459 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1460 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1461 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1462 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1463 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1464 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1465 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1466 tir_attr->rx_hash_field_selector_outer.selected_fields); 1467 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1468 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1469 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1470 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1471 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1472 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1473 tir_attr->rx_hash_field_selector_inner.selected_fields); 1474 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1475 out, sizeof(out)); 1476 if (!tir->obj) { 1477 DEVX_DRV_LOG(ERR, out, "create TIR", NULL, 0); 1478 mlx5_free(tir); 1479 return NULL; 1480 } 1481 tir->id = MLX5_GET(create_tir_out, out, tirn); 1482 return tir; 1483 } 1484 1485 /** 1486 * Modify TIR using DevX API. 1487 * 1488 * @param[in] tir 1489 * Pointer to TIR DevX object structure. 1490 * @param [in] modify_tir_attr 1491 * Pointer to TIR modification attributes structure. 1492 * 1493 * @return 1494 * 0 on success, a negative errno value otherwise and rte_errno is set. 1495 */ 1496 int 1497 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1498 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1499 { 1500 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1501 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1502 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1503 void *tir_ctx; 1504 int ret; 1505 1506 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1507 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1508 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1509 modify_tir_attr->modify_bitmask); 1510 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1511 if (modify_tir_attr->modify_bitmask & 1512 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1513 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1514 tir_attr->lro_timeout_period_usecs); 1515 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1516 tir_attr->lro_enable_mask); 1517 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1518 tir_attr->lro_max_msg_sz); 1519 } 1520 if (modify_tir_attr->modify_bitmask & 1521 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1522 MLX5_SET(tirc, tir_ctx, indirect_table, 1523 tir_attr->indirect_table); 1524 if (modify_tir_attr->modify_bitmask & 1525 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1526 int i; 1527 void *outer, *inner; 1528 1529 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1530 tir_attr->rx_hash_symmetric); 1531 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1532 for (i = 0; i < 10; i++) { 1533 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1534 tir_attr->rx_hash_toeplitz_key[i]); 1535 } 1536 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1537 rx_hash_field_selector_outer); 1538 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1539 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1540 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1541 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1542 MLX5_SET 1543 (rx_hash_field_select, outer, selected_fields, 1544 tir_attr->rx_hash_field_selector_outer.selected_fields); 1545 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1546 rx_hash_field_selector_inner); 1547 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1548 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1549 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1550 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1551 MLX5_SET 1552 (rx_hash_field_select, inner, selected_fields, 1553 tir_attr->rx_hash_field_selector_inner.selected_fields); 1554 } 1555 if (modify_tir_attr->modify_bitmask & 1556 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1557 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1558 } 1559 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1560 out, sizeof(out)); 1561 if (ret) { 1562 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1563 rte_errno = errno; 1564 return -errno; 1565 } 1566 return ret; 1567 } 1568 1569 /** 1570 * Create RQT using DevX API. 1571 * 1572 * @param[in] ctx 1573 * Context returned from mlx5 open_device() glue function. 1574 * @param [in] rqt_attr 1575 * Pointer to RQT attributes structure. 1576 * 1577 * @return 1578 * The DevX object created, NULL otherwise and rte_errno is set. 1579 */ 1580 struct mlx5_devx_obj * 1581 mlx5_devx_cmd_create_rqt(void *ctx, 1582 struct mlx5_devx_rqt_attr *rqt_attr) 1583 { 1584 uint32_t *in = NULL; 1585 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1586 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1587 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1588 void *rqt_ctx; 1589 struct mlx5_devx_obj *rqt = NULL; 1590 int i; 1591 1592 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1593 if (!in) { 1594 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1595 rte_errno = ENOMEM; 1596 return NULL; 1597 } 1598 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1599 if (!rqt) { 1600 DRV_LOG(ERR, "Failed to allocate RQT data"); 1601 rte_errno = ENOMEM; 1602 mlx5_free(in); 1603 return NULL; 1604 } 1605 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1606 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1607 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1608 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1609 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1610 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1611 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1612 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1613 mlx5_free(in); 1614 if (!rqt->obj) { 1615 DEVX_DRV_LOG(ERR, out, "create RQT", NULL, 0); 1616 mlx5_free(rqt); 1617 return NULL; 1618 } 1619 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1620 return rqt; 1621 } 1622 1623 /** 1624 * Modify RQT using DevX API. 1625 * 1626 * @param[in] rqt 1627 * Pointer to RQT DevX object structure. 1628 * @param [in] rqt_attr 1629 * Pointer to RQT attributes structure. 1630 * 1631 * @return 1632 * 0 on success, a negative errno value otherwise and rte_errno is set. 1633 */ 1634 int 1635 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1636 struct mlx5_devx_rqt_attr *rqt_attr) 1637 { 1638 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1639 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1640 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1641 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1642 void *rqt_ctx; 1643 int i; 1644 int ret; 1645 1646 if (!in) { 1647 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1648 rte_errno = ENOMEM; 1649 return -ENOMEM; 1650 } 1651 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1652 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1653 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1654 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1655 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1656 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1657 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1658 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1659 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1660 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1661 mlx5_free(in); 1662 if (ret) { 1663 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1664 rte_errno = errno; 1665 return -rte_errno; 1666 } 1667 return ret; 1668 } 1669 1670 /** 1671 * Create SQ using DevX API. 1672 * 1673 * @param[in] ctx 1674 * Context returned from mlx5 open_device() glue function. 1675 * @param [in] sq_attr 1676 * Pointer to SQ attributes structure. 1677 * @param [in] socket 1678 * CPU socket ID for allocations. 1679 * 1680 * @return 1681 * The DevX object created, NULL otherwise and rte_errno is set. 1682 **/ 1683 struct mlx5_devx_obj * 1684 mlx5_devx_cmd_create_sq(void *ctx, 1685 struct mlx5_devx_create_sq_attr *sq_attr) 1686 { 1687 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1688 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1689 void *sq_ctx; 1690 void *wq_ctx; 1691 struct mlx5_devx_wq_attr *wq_attr; 1692 struct mlx5_devx_obj *sq = NULL; 1693 1694 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1695 if (!sq) { 1696 DRV_LOG(ERR, "Failed to allocate SQ data"); 1697 rte_errno = ENOMEM; 1698 return NULL; 1699 } 1700 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1701 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1702 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1703 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1704 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1705 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1706 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1707 sq_attr->allow_multi_pkt_send_wqe); 1708 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1709 sq_attr->min_wqe_inline_mode); 1710 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1711 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1712 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1713 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1714 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1715 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1716 MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type); 1717 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1718 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1719 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1720 sq_attr->packet_pacing_rate_limit_index); 1721 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1722 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1723 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1724 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1725 wq_attr = &sq_attr->wq_attr; 1726 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1727 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1728 out, sizeof(out)); 1729 if (!sq->obj) { 1730 DEVX_DRV_LOG(ERR, out, "create SQ", NULL, 0); 1731 mlx5_free(sq); 1732 return NULL; 1733 } 1734 sq->id = MLX5_GET(create_sq_out, out, sqn); 1735 return sq; 1736 } 1737 1738 /** 1739 * Modify SQ using DevX API. 1740 * 1741 * @param[in] sq 1742 * Pointer to SQ object structure. 1743 * @param [in] sq_attr 1744 * Pointer to SQ attributes structure. 1745 * 1746 * @return 1747 * 0 on success, a negative errno value otherwise and rte_errno is set. 1748 */ 1749 int 1750 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1751 struct mlx5_devx_modify_sq_attr *sq_attr) 1752 { 1753 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1754 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1755 void *sq_ctx; 1756 int ret; 1757 1758 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1759 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1760 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1761 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1762 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1763 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1764 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1765 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1766 out, sizeof(out)); 1767 if (ret) { 1768 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1769 rte_errno = errno; 1770 return -rte_errno; 1771 } 1772 return ret; 1773 } 1774 1775 /** 1776 * Create TIS using DevX API. 1777 * 1778 * @param[in] ctx 1779 * Context returned from mlx5 open_device() glue function. 1780 * @param [in] tis_attr 1781 * Pointer to TIS attributes structure. 1782 * 1783 * @return 1784 * The DevX object created, NULL otherwise and rte_errno is set. 1785 */ 1786 struct mlx5_devx_obj * 1787 mlx5_devx_cmd_create_tis(void *ctx, 1788 struct mlx5_devx_tis_attr *tis_attr) 1789 { 1790 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1791 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1792 struct mlx5_devx_obj *tis = NULL; 1793 void *tis_ctx; 1794 1795 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1796 if (!tis) { 1797 DRV_LOG(ERR, "Failed to allocate TIS object"); 1798 rte_errno = ENOMEM; 1799 return NULL; 1800 } 1801 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1802 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1803 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1804 tis_attr->strict_lag_tx_port_affinity); 1805 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1806 tis_attr->lag_tx_port_affinity); 1807 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1808 MLX5_SET(tisc, tis_ctx, transport_domain, 1809 tis_attr->transport_domain); 1810 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1811 out, sizeof(out)); 1812 if (!tis->obj) { 1813 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 1814 mlx5_free(tis); 1815 return NULL; 1816 } 1817 tis->id = MLX5_GET(create_tis_out, out, tisn); 1818 return tis; 1819 } 1820 1821 /** 1822 * Create transport domain using DevX API. 1823 * 1824 * @param[in] ctx 1825 * Context returned from mlx5 open_device() glue function. 1826 * @return 1827 * The DevX object created, NULL otherwise and rte_errno is set. 1828 */ 1829 struct mlx5_devx_obj * 1830 mlx5_devx_cmd_create_td(void *ctx) 1831 { 1832 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1833 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1834 struct mlx5_devx_obj *td = NULL; 1835 1836 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1837 if (!td) { 1838 DRV_LOG(ERR, "Failed to allocate TD object"); 1839 rte_errno = ENOMEM; 1840 return NULL; 1841 } 1842 MLX5_SET(alloc_transport_domain_in, in, opcode, 1843 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1844 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1845 out, sizeof(out)); 1846 if (!td->obj) { 1847 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 1848 mlx5_free(td); 1849 return NULL; 1850 } 1851 td->id = MLX5_GET(alloc_transport_domain_out, out, 1852 transport_domain); 1853 return td; 1854 } 1855 1856 /** 1857 * Dump all flows to file. 1858 * 1859 * @param[in] fdb_domain 1860 * FDB domain. 1861 * @param[in] rx_domain 1862 * RX domain. 1863 * @param[in] tx_domain 1864 * TX domain. 1865 * @param[out] file 1866 * Pointer to file stream. 1867 * 1868 * @return 1869 * 0 on success, a negative value otherwise. 1870 */ 1871 int 1872 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1873 void *rx_domain __rte_unused, 1874 void *tx_domain __rte_unused, FILE *file __rte_unused) 1875 { 1876 int ret = 0; 1877 1878 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1879 if (fdb_domain) { 1880 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1881 if (ret) 1882 return ret; 1883 } 1884 MLX5_ASSERT(rx_domain); 1885 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1886 if (ret) 1887 return ret; 1888 MLX5_ASSERT(tx_domain); 1889 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1890 #else 1891 ret = ENOTSUP; 1892 #endif 1893 return -ret; 1894 } 1895 1896 int 1897 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 1898 FILE *file __rte_unused) 1899 { 1900 int ret = 0; 1901 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 1902 if (rule_info) 1903 ret = mlx5_glue->dr_dump_rule(file, rule_info); 1904 #else 1905 ret = ENOTSUP; 1906 #endif 1907 return -ret; 1908 } 1909 1910 /* 1911 * Create CQ using DevX API. 1912 * 1913 * @param[in] ctx 1914 * Context returned from mlx5 open_device() glue function. 1915 * @param [in] attr 1916 * Pointer to CQ attributes structure. 1917 * 1918 * @return 1919 * The DevX object created, NULL otherwise and rte_errno is set. 1920 */ 1921 struct mlx5_devx_obj * 1922 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1923 { 1924 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1925 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1926 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1927 sizeof(*cq_obj), 1928 0, SOCKET_ID_ANY); 1929 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1930 1931 if (!cq_obj) { 1932 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1933 rte_errno = ENOMEM; 1934 return NULL; 1935 } 1936 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1937 if (attr->db_umem_valid) { 1938 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1939 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1940 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1941 } else { 1942 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1943 } 1944 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1945 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1946 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1947 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1948 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1949 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1950 MLX5_SET(cqc, cqctx, log_page_size, 1951 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1952 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1953 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1954 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1955 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1956 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1957 attr->mini_cqe_res_format_ext); 1958 if (attr->q_umem_valid) { 1959 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1960 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1961 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1962 attr->q_umem_offset); 1963 } 1964 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1965 sizeof(out)); 1966 if (!cq_obj->obj) { 1967 DEVX_DRV_LOG(ERR, out, "create CQ", NULL, 0); 1968 mlx5_free(cq_obj); 1969 return NULL; 1970 } 1971 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1972 return cq_obj; 1973 } 1974 1975 /** 1976 * Create VIRTQ using DevX API. 1977 * 1978 * @param[in] ctx 1979 * Context returned from mlx5 open_device() glue function. 1980 * @param [in] attr 1981 * Pointer to VIRTQ attributes structure. 1982 * 1983 * @return 1984 * The DevX object created, NULL otherwise and rte_errno is set. 1985 */ 1986 struct mlx5_devx_obj * 1987 mlx5_devx_cmd_create_virtq(void *ctx, 1988 struct mlx5_devx_virtq_attr *attr) 1989 { 1990 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1991 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1992 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1993 sizeof(*virtq_obj), 1994 0, SOCKET_ID_ANY); 1995 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1996 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1997 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1998 1999 if (!virtq_obj) { 2000 DRV_LOG(ERR, "Failed to allocate virtq data."); 2001 rte_errno = ENOMEM; 2002 return NULL; 2003 } 2004 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2005 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2006 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2007 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2008 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2009 attr->hw_available_index); 2010 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 2011 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2012 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2013 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2014 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2015 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2016 attr->virtio_version_1_0); 2017 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2018 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2019 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2020 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2021 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 2022 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2023 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 2024 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2025 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 2026 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 2027 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 2028 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 2029 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 2030 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 2031 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 2032 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 2033 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 2034 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 2035 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 2036 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 2037 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 2038 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 2039 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 2040 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2041 sizeof(out)); 2042 if (!virtq_obj->obj) { 2043 DEVX_DRV_LOG(ERR, out, "create VIRTQ", NULL, 0); 2044 mlx5_free(virtq_obj); 2045 return NULL; 2046 } 2047 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2048 return virtq_obj; 2049 } 2050 2051 /** 2052 * Modify VIRTQ using DevX API. 2053 * 2054 * @param[in] virtq_obj 2055 * Pointer to virtq object structure. 2056 * @param [in] attr 2057 * Pointer to modify virtq attributes structure. 2058 * 2059 * @return 2060 * 0 on success, a negative errno value otherwise and rte_errno is set. 2061 */ 2062 int 2063 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 2064 struct mlx5_devx_virtq_attr *attr) 2065 { 2066 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2067 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2068 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2069 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2070 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2071 int ret; 2072 2073 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2074 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 2075 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2076 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2077 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2078 MLX5_SET64(virtio_net_q, virtq, modify_field_select, 2079 attr->mod_fields_bitmap); 2080 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2081 if (!attr->mod_fields_bitmap) { 2082 DRV_LOG(ERR, "Failed to modify VIRTQ for no type set."); 2083 rte_errno = EINVAL; 2084 return -rte_errno; 2085 } 2086 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE) 2087 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 2088 if (attr->mod_fields_bitmap & 2089 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) { 2090 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 2091 attr->dirty_bitmap_mkey); 2092 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 2093 attr->dirty_bitmap_addr); 2094 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 2095 attr->dirty_bitmap_size); 2096 } 2097 if (attr->mod_fields_bitmap & 2098 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE) 2099 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 2100 attr->dirty_bitmap_dump_enable); 2101 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) { 2102 MLX5_SET(virtio_q, virtctx, queue_period_mode, 2103 attr->hw_latency_mode); 2104 MLX5_SET(virtio_q, virtctx, queue_period_us, 2105 attr->hw_max_latency_us); 2106 MLX5_SET(virtio_q, virtctx, queue_max_count, 2107 attr->hw_max_pending_comp); 2108 } 2109 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) { 2110 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2111 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2112 MLX5_SET64(virtio_q, virtctx, available_addr, 2113 attr->available_addr); 2114 } 2115 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX) 2116 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2117 attr->hw_available_index); 2118 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX) 2119 MLX5_SET16(virtio_net_q, virtq, hw_used_index, 2120 attr->hw_used_index); 2121 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE) 2122 MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type); 2123 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0) 2124 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2125 attr->virtio_version_1_0); 2126 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY) 2127 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2128 if (attr->mod_fields_bitmap & 2129 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) { 2130 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2131 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2132 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2133 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2134 } 2135 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) { 2136 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2137 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2138 } 2139 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 2140 out, sizeof(out)); 2141 if (ret) { 2142 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2143 rte_errno = errno; 2144 return -rte_errno; 2145 } 2146 return ret; 2147 } 2148 2149 /** 2150 * Query VIRTQ using DevX API. 2151 * 2152 * @param[in] virtq_obj 2153 * Pointer to virtq object structure. 2154 * @param [in/out] attr 2155 * Pointer to virtq attributes structure. 2156 * 2157 * @return 2158 * 0 on success, a negative errno value otherwise and rte_errno is set. 2159 */ 2160 int 2161 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 2162 struct mlx5_devx_virtq_attr *attr) 2163 { 2164 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2165 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 2166 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 2167 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 2168 int ret; 2169 2170 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2171 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2172 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2173 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2174 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2175 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2176 out, sizeof(out)); 2177 if (ret) { 2178 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2179 rte_errno = errno; 2180 return -errno; 2181 } 2182 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2183 hw_available_index); 2184 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2185 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2186 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2187 virtio_q_context.error_type); 2188 return ret; 2189 } 2190 2191 /** 2192 * Create QP using DevX API. 2193 * 2194 * @param[in] ctx 2195 * Context returned from mlx5 open_device() glue function. 2196 * @param [in] attr 2197 * Pointer to QP attributes structure. 2198 * 2199 * @return 2200 * The DevX object created, NULL otherwise and rte_errno is set. 2201 */ 2202 struct mlx5_devx_obj * 2203 mlx5_devx_cmd_create_qp(void *ctx, 2204 struct mlx5_devx_qp_attr *attr) 2205 { 2206 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2207 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2208 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2209 sizeof(*qp_obj), 2210 0, SOCKET_ID_ANY); 2211 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2212 2213 if (!qp_obj) { 2214 DRV_LOG(ERR, "Failed to allocate QP data."); 2215 rte_errno = ENOMEM; 2216 return NULL; 2217 } 2218 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2219 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2220 MLX5_SET(qpc, qpc, pd, attr->pd); 2221 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2222 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2223 if (attr->uar_index) { 2224 if (attr->mmo) { 2225 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2226 in, qpc_extension_and_pas_list); 2227 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2228 qpc_ext_and_pas_list, qpc_data_extension); 2229 2230 MLX5_SET(create_qp_in, in, qpc_ext, 1); 2231 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2232 } 2233 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2234 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2235 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2236 MLX5_SET(qpc, qpc, log_page_size, 2237 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2238 if (attr->num_of_send_wqbbs) { 2239 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs)); 2240 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2241 MLX5_SET(qpc, qpc, log_sq_size, 2242 rte_log2_u32(attr->num_of_send_wqbbs)); 2243 } else { 2244 MLX5_SET(qpc, qpc, no_sq, 1); 2245 } 2246 if (attr->num_of_receive_wqes) { 2247 MLX5_ASSERT(RTE_IS_POWER_OF_2( 2248 attr->num_of_receive_wqes)); 2249 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2250 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2251 MLX5_LOG_RQ_STRIDE_SHIFT); 2252 MLX5_SET(qpc, qpc, log_rq_size, 2253 rte_log2_u32(attr->num_of_receive_wqes)); 2254 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2255 } else { 2256 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2257 } 2258 if (attr->dbr_umem_valid) { 2259 MLX5_SET(qpc, qpc, dbr_umem_valid, 2260 attr->dbr_umem_valid); 2261 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2262 } 2263 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2264 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2265 attr->wq_umem_offset); 2266 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2267 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2268 } else { 2269 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2270 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2271 MLX5_SET(qpc, qpc, no_sq, 1); 2272 } 2273 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2274 sizeof(out)); 2275 if (!qp_obj->obj) { 2276 DEVX_DRV_LOG(ERR, out, "create QP", NULL, 0); 2277 mlx5_free(qp_obj); 2278 return NULL; 2279 } 2280 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2281 return qp_obj; 2282 } 2283 2284 /** 2285 * Modify QP using DevX API. 2286 * Currently supports only force loop-back QP. 2287 * 2288 * @param[in] qp 2289 * Pointer to QP object structure. 2290 * @param [in] qp_st_mod_op 2291 * The QP state modification operation. 2292 * @param [in] remote_qp_id 2293 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2294 * 2295 * @return 2296 * 0 on success, a negative errno value otherwise and rte_errno is set. 2297 */ 2298 int 2299 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2300 uint32_t remote_qp_id) 2301 { 2302 union { 2303 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2304 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2305 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2306 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)]; 2307 } in; 2308 union { 2309 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2310 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2311 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2312 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)]; 2313 } out; 2314 void *qpc; 2315 int ret; 2316 unsigned int inlen; 2317 unsigned int outlen; 2318 2319 memset(&in, 0, sizeof(in)); 2320 memset(&out, 0, sizeof(out)); 2321 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2322 switch (qp_st_mod_op) { 2323 case MLX5_CMD_OP_RST2INIT_QP: 2324 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2325 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2326 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2327 MLX5_SET(qpc, qpc, rre, 1); 2328 MLX5_SET(qpc, qpc, rwe, 1); 2329 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2330 inlen = sizeof(in.rst2init); 2331 outlen = sizeof(out.rst2init); 2332 break; 2333 case MLX5_CMD_OP_INIT2RTR_QP: 2334 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2335 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2336 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2337 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2338 MLX5_SET(qpc, qpc, mtu, 1); 2339 MLX5_SET(qpc, qpc, log_msg_max, 30); 2340 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2341 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2342 inlen = sizeof(in.init2rtr); 2343 outlen = sizeof(out.init2rtr); 2344 break; 2345 case MLX5_CMD_OP_RTR2RTS_QP: 2346 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2347 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2348 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16); 2349 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2350 MLX5_SET(qpc, qpc, retry_count, 7); 2351 MLX5_SET(qpc, qpc, rnr_retry, 7); 2352 inlen = sizeof(in.rtr2rts); 2353 outlen = sizeof(out.rtr2rts); 2354 break; 2355 case MLX5_CMD_OP_QP_2RST: 2356 MLX5_SET(2rst_qp_in, &in, qpn, qp->id); 2357 inlen = sizeof(in.qp2rst); 2358 outlen = sizeof(out.qp2rst); 2359 break; 2360 default: 2361 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2362 qp_st_mod_op); 2363 rte_errno = EINVAL; 2364 return -rte_errno; 2365 } 2366 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2367 if (ret) { 2368 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2369 rte_errno = errno; 2370 return -rte_errno; 2371 } 2372 return ret; 2373 } 2374 2375 struct mlx5_devx_obj * 2376 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2377 { 2378 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2379 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2380 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2381 sizeof(*couners_obj), 0, 2382 SOCKET_ID_ANY); 2383 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2384 2385 if (!couners_obj) { 2386 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2387 rte_errno = ENOMEM; 2388 return NULL; 2389 } 2390 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2391 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2392 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2393 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2394 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2395 sizeof(out)); 2396 if (!couners_obj->obj) { 2397 DEVX_DRV_LOG(ERR, out, "create virtio queue counters Obj", NULL, 2398 0); 2399 mlx5_free(couners_obj); 2400 return NULL; 2401 } 2402 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2403 return couners_obj; 2404 } 2405 2406 int 2407 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2408 struct mlx5_devx_virtio_q_couners_attr *attr) 2409 { 2410 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2411 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2412 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2413 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2414 virtio_q_counters); 2415 int ret; 2416 2417 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2418 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2419 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2420 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2421 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2422 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2423 sizeof(out)); 2424 if (ret) { 2425 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2426 rte_errno = errno; 2427 return -errno; 2428 } 2429 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2430 received_desc); 2431 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2432 completed_desc); 2433 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2434 error_cqes); 2435 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2436 bad_desc_errors); 2437 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2438 exceed_max_chain); 2439 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2440 invalid_buffer); 2441 return ret; 2442 } 2443 2444 /** 2445 * Create general object of type FLOW_HIT_ASO using DevX API. 2446 * 2447 * @param[in] ctx 2448 * Context returned from mlx5 open_device() glue function. 2449 * @param [in] pd 2450 * PD value to associate the FLOW_HIT_ASO object with. 2451 * 2452 * @return 2453 * The DevX object created, NULL otherwise and rte_errno is set. 2454 */ 2455 struct mlx5_devx_obj * 2456 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2457 { 2458 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2459 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2460 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2461 void *ptr = NULL; 2462 2463 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2464 0, SOCKET_ID_ANY); 2465 if (!flow_hit_aso_obj) { 2466 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2467 rte_errno = ENOMEM; 2468 return NULL; 2469 } 2470 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2471 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2472 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2473 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2474 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2475 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2476 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2477 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2478 out, sizeof(out)); 2479 if (!flow_hit_aso_obj->obj) { 2480 DEVX_DRV_LOG(ERR, out, "create FLOW_HIT_ASO", NULL, 0); 2481 mlx5_free(flow_hit_aso_obj); 2482 return NULL; 2483 } 2484 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2485 return flow_hit_aso_obj; 2486 } 2487 2488 /* 2489 * Create PD using DevX API. 2490 * 2491 * @param[in] ctx 2492 * Context returned from mlx5 open_device() glue function. 2493 * 2494 * @return 2495 * The DevX object created, NULL otherwise and rte_errno is set. 2496 */ 2497 struct mlx5_devx_obj * 2498 mlx5_devx_cmd_alloc_pd(void *ctx) 2499 { 2500 struct mlx5_devx_obj *ppd = 2501 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2502 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2503 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2504 2505 if (!ppd) { 2506 DRV_LOG(ERR, "Failed to allocate PD data."); 2507 rte_errno = ENOMEM; 2508 return NULL; 2509 } 2510 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2511 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2512 out, sizeof(out)); 2513 if (!ppd->obj) { 2514 mlx5_free(ppd); 2515 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2516 rte_errno = errno; 2517 return NULL; 2518 } 2519 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2520 return ppd; 2521 } 2522 2523 /** 2524 * Create general object of type FLOW_METER_ASO using DevX API. 2525 * 2526 * @param[in] ctx 2527 * Context returned from mlx5 open_device() glue function. 2528 * @param [in] pd 2529 * PD value to associate the FLOW_METER_ASO object with. 2530 * @param [in] log_obj_size 2531 * log_obj_size define to allocate number of 2 * meters 2532 * in one FLOW_METER_ASO object. 2533 * 2534 * @return 2535 * The DevX object created, NULL otherwise and rte_errno is set. 2536 */ 2537 struct mlx5_devx_obj * 2538 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2539 uint32_t log_obj_size) 2540 { 2541 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2542 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2543 struct mlx5_devx_obj *flow_meter_aso_obj; 2544 void *ptr; 2545 2546 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2547 sizeof(*flow_meter_aso_obj), 2548 0, SOCKET_ID_ANY); 2549 if (!flow_meter_aso_obj) { 2550 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2551 rte_errno = ENOMEM; 2552 return NULL; 2553 } 2554 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2555 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2556 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2557 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2558 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2559 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2560 log_obj_size); 2561 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2562 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2563 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2564 ctx, in, sizeof(in), 2565 out, sizeof(out)); 2566 if (!flow_meter_aso_obj->obj) { 2567 DEVX_DRV_LOG(ERR, out, "create FLOW_METTER_ASO", NULL, 0); 2568 mlx5_free(flow_meter_aso_obj); 2569 return NULL; 2570 } 2571 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2572 out, obj_id); 2573 return flow_meter_aso_obj; 2574 } 2575 2576 /* 2577 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2578 * 2579 * @param[in] ctx 2580 * Context returned from mlx5 open_device() glue function. 2581 * @param [in] pd 2582 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2583 * @param [in] log_obj_size 2584 * log_obj_size to allocate its power of 2 * objects 2585 * in one CONN_TRACK_OFFLOAD bulk allocation. 2586 * 2587 * @return 2588 * The DevX object created, NULL otherwise and rte_errno is set. 2589 */ 2590 struct mlx5_devx_obj * 2591 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2592 uint32_t log_obj_size) 2593 { 2594 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2595 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2596 struct mlx5_devx_obj *ct_aso_obj; 2597 void *ptr; 2598 2599 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2600 0, SOCKET_ID_ANY); 2601 if (!ct_aso_obj) { 2602 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2603 rte_errno = ENOMEM; 2604 return NULL; 2605 } 2606 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2607 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2608 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2609 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2610 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2611 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2612 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2613 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2614 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2615 out, sizeof(out)); 2616 if (!ct_aso_obj->obj) { 2617 DEVX_DRV_LOG(ERR, out, "create CONN_TRACK_OFFLOAD", NULL, 0); 2618 mlx5_free(ct_aso_obj); 2619 return NULL; 2620 } 2621 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2622 return ct_aso_obj; 2623 } 2624 2625 /** 2626 * Create general object of type GENEVE TLV option using DevX API. 2627 * 2628 * @param[in] ctx 2629 * Context returned from mlx5 open_device() glue function. 2630 * @param [in] class 2631 * TLV option variable value of class 2632 * @param [in] type 2633 * TLV option variable value of type 2634 * @param [in] len 2635 * TLV option variable value of len 2636 * 2637 * @return 2638 * The DevX object created, NULL otherwise and rte_errno is set. 2639 */ 2640 struct mlx5_devx_obj * 2641 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2642 uint16_t class, uint8_t type, uint8_t len) 2643 { 2644 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2645 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2646 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2647 sizeof(*geneve_tlv_opt_obj), 2648 0, SOCKET_ID_ANY); 2649 2650 if (!geneve_tlv_opt_obj) { 2651 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2652 rte_errno = ENOMEM; 2653 return NULL; 2654 } 2655 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2656 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2657 geneve_tlv_opt); 2658 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2659 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2660 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2661 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2662 MLX5_SET(geneve_tlv_option, opt, option_class, 2663 rte_be_to_cpu_16(class)); 2664 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2665 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2666 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2667 sizeof(in), out, sizeof(out)); 2668 if (!geneve_tlv_opt_obj->obj) { 2669 DEVX_DRV_LOG(ERR, out, "create GENEVE TLV", NULL, 0); 2670 mlx5_free(geneve_tlv_opt_obj); 2671 return NULL; 2672 } 2673 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2674 return geneve_tlv_opt_obj; 2675 } 2676 2677 int 2678 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2679 { 2680 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2681 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2682 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2683 int rc; 2684 void *rq_ctx; 2685 2686 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2687 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2688 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2689 if (rc) { 2690 rte_errno = errno; 2691 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2692 "rc = %d, errno = %d.", rc, errno); 2693 return -rc; 2694 }; 2695 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2696 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2697 return 0; 2698 #else 2699 (void)wq; 2700 (void)counter_set_id; 2701 return -ENOTSUP; 2702 #endif 2703 } 2704 2705 /* 2706 * Allocate queue counters via devx interface. 2707 * 2708 * @param[in] ctx 2709 * Context returned from mlx5 open_device() glue function. 2710 * 2711 * @return 2712 * Pointer to counter object on success, a NULL value otherwise and 2713 * rte_errno is set. 2714 */ 2715 struct mlx5_devx_obj * 2716 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2717 { 2718 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2719 SOCKET_ID_ANY); 2720 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2721 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2722 2723 if (!dcs) { 2724 rte_errno = ENOMEM; 2725 return NULL; 2726 } 2727 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2728 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2729 sizeof(out)); 2730 if (!dcs->obj) { 2731 DEVX_DRV_LOG(DEBUG, out, "create q counter set", NULL, 0); 2732 mlx5_free(dcs); 2733 return NULL; 2734 } 2735 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2736 return dcs; 2737 } 2738 2739 /** 2740 * Query queue counters values. 2741 * 2742 * @param[in] dcs 2743 * devx object of the queue counter set. 2744 * @param[in] clear 2745 * Whether hardware should clear the counters after the query or not. 2746 * @param[out] out_of_buffers 2747 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2748 * 2749 * @return 2750 * 0 on success, a negative value otherwise. 2751 */ 2752 int 2753 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2754 uint32_t *out_of_buffers) 2755 { 2756 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2757 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2758 int rc; 2759 2760 MLX5_SET(query_q_counter_in, in, opcode, 2761 MLX5_CMD_OP_QUERY_Q_COUNTER); 2762 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2763 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2764 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2765 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2766 sizeof(out)); 2767 if (rc) { 2768 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2769 rte_errno = rc; 2770 return -rc; 2771 } 2772 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2773 return 0; 2774 } 2775 2776 /** 2777 * Create general object of type DEK using DevX API. 2778 * 2779 * @param[in] ctx 2780 * Context returned from mlx5 open_device() glue function. 2781 * @param [in] attr 2782 * Pointer to DEK attributes structure. 2783 * 2784 * @return 2785 * The DevX object created, NULL otherwise and rte_errno is set. 2786 */ 2787 struct mlx5_devx_obj * 2788 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2789 { 2790 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2791 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2792 struct mlx5_devx_obj *dek_obj = NULL; 2793 void *ptr = NULL, *key_addr = NULL; 2794 2795 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2796 0, SOCKET_ID_ANY); 2797 if (dek_obj == NULL) { 2798 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2799 rte_errno = ENOMEM; 2800 return NULL; 2801 } 2802 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2803 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2804 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2805 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2806 MLX5_GENERAL_OBJ_TYPE_DEK); 2807 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2808 MLX5_SET(dek, ptr, key_size, attr->key_size); 2809 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2810 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2811 MLX5_SET(dek, ptr, pd, attr->pd); 2812 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2813 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2814 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2815 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2816 out, sizeof(out)); 2817 if (dek_obj->obj == NULL) { 2818 DEVX_DRV_LOG(ERR, out, "create DEK", NULL, 0); 2819 mlx5_free(dek_obj); 2820 return NULL; 2821 } 2822 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2823 return dek_obj; 2824 } 2825 2826 /** 2827 * Create general object of type IMPORT_KEK using DevX API. 2828 * 2829 * @param[in] ctx 2830 * Context returned from mlx5 open_device() glue function. 2831 * @param [in] attr 2832 * Pointer to IMPORT_KEK attributes structure. 2833 * 2834 * @return 2835 * The DevX object created, NULL otherwise and rte_errno is set. 2836 */ 2837 struct mlx5_devx_obj * 2838 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 2839 struct mlx5_devx_import_kek_attr *attr) 2840 { 2841 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 2842 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2843 struct mlx5_devx_obj *import_kek_obj = NULL; 2844 void *ptr = NULL, *key_addr = NULL; 2845 2846 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 2847 0, SOCKET_ID_ANY); 2848 if (import_kek_obj == NULL) { 2849 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 2850 rte_errno = ENOMEM; 2851 return NULL; 2852 } 2853 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 2854 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2855 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2856 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2857 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 2858 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 2859 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 2860 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 2861 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2862 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2863 out, sizeof(out)); 2864 if (import_kek_obj->obj == NULL) { 2865 DEVX_DRV_LOG(ERR, out, "create IMPORT_KEK", NULL, 0); 2866 mlx5_free(import_kek_obj); 2867 return NULL; 2868 } 2869 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2870 return import_kek_obj; 2871 } 2872 2873 /** 2874 * Create general object of type CREDENTIAL using DevX API. 2875 * 2876 * @param[in] ctx 2877 * Context returned from mlx5 open_device() glue function. 2878 * @param [in] attr 2879 * Pointer to CREDENTIAL attributes structure. 2880 * 2881 * @return 2882 * The DevX object created, NULL otherwise and rte_errno is set. 2883 */ 2884 struct mlx5_devx_obj * 2885 mlx5_devx_cmd_create_credential_obj(void *ctx, 2886 struct mlx5_devx_credential_attr *attr) 2887 { 2888 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 2889 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2890 struct mlx5_devx_obj *credential_obj = NULL; 2891 void *ptr = NULL, *credential_addr = NULL; 2892 2893 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 2894 0, SOCKET_ID_ANY); 2895 if (credential_obj == NULL) { 2896 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 2897 rte_errno = ENOMEM; 2898 return NULL; 2899 } 2900 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 2901 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2902 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2903 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2904 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 2905 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 2906 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 2907 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 2908 memcpy(credential_addr, (void *)(attr->credential), 2909 MLX5_CRYPTO_CREDENTIAL_SIZE); 2910 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2911 out, sizeof(out)); 2912 if (credential_obj->obj == NULL) { 2913 DEVX_DRV_LOG(ERR, out, "create CREDENTIAL", NULL, 0); 2914 mlx5_free(credential_obj); 2915 return NULL; 2916 } 2917 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2918 return credential_obj; 2919 } 2920 2921 /** 2922 * Create general object of type CRYPTO_LOGIN using DevX API. 2923 * 2924 * @param[in] ctx 2925 * Context returned from mlx5 open_device() glue function. 2926 * @param [in] attr 2927 * Pointer to CRYPTO_LOGIN attributes structure. 2928 * 2929 * @return 2930 * The DevX object created, NULL otherwise and rte_errno is set. 2931 */ 2932 struct mlx5_devx_obj * 2933 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 2934 struct mlx5_devx_crypto_login_attr *attr) 2935 { 2936 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 2937 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2938 struct mlx5_devx_obj *crypto_login_obj = NULL; 2939 void *ptr = NULL, *credential_addr = NULL; 2940 2941 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 2942 0, SOCKET_ID_ANY); 2943 if (crypto_login_obj == NULL) { 2944 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 2945 rte_errno = ENOMEM; 2946 return NULL; 2947 } 2948 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 2949 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2950 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2951 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2952 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 2953 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 2954 MLX5_SET(crypto_login, ptr, credential_pointer, 2955 attr->credential_pointer); 2956 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 2957 attr->session_import_kek_ptr); 2958 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 2959 memcpy(credential_addr, (void *)(attr->credential), 2960 MLX5_CRYPTO_CREDENTIAL_SIZE); 2961 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2962 out, sizeof(out)); 2963 if (crypto_login_obj->obj == NULL) { 2964 DEVX_DRV_LOG(ERR, out, "create CRYPTO_LOGIN", NULL, 0); 2965 mlx5_free(crypto_login_obj); 2966 return NULL; 2967 } 2968 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2969 return crypto_login_obj; 2970 } 2971 2972 /** 2973 * Query LAG context. 2974 * 2975 * @param[in] ctx 2976 * Pointer to ibv_context, returned from mlx5dv_open_device. 2977 * @param[out] lag_ctx 2978 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 2979 * 2980 * @return 2981 * 0 on success, a negative value otherwise. 2982 */ 2983 int 2984 mlx5_devx_cmd_query_lag(void *ctx, 2985 struct mlx5_devx_lag_context *lag_ctx) 2986 { 2987 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 2988 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 2989 void *lctx; 2990 int rc; 2991 2992 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 2993 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 2994 if (rc) 2995 goto error; 2996 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 2997 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 2998 fdb_selection_mode); 2999 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 3000 port_select_mode); 3001 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 3002 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 3003 tx_remap_affinity_2); 3004 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 3005 tx_remap_affinity_1); 3006 return 0; 3007 error: 3008 rc = (rc > 0) ? -rc : rc; 3009 return rc; 3010 } 3011