1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /* FW writes status value to the OUT buffer at offset 00H */ 17 #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status) 18 /* FW writes syndrome value to the OUT buffer at offset 04H */ 19 #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome) 20 21 #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1)) 22 23 #define DEVX_DRV_LOG(level, out, reason, param, value) \ 24 do { \ 25 /* \ 26 * Some (old) GCC compilers like 7.5.0 and aarch64 GCC 7.1-2017.08 \ 27 * do not expand correctly when the macro invoked when the `param` \ 28 * is `NULL`. \ 29 * Use `local_param` to avoid direct `NULL` expansion. \ 30 */ \ 31 const char *local_param = (const char *)param; \ 32 \ 33 rte_errno = errno; \ 34 if (!local_param) { \ 35 DRV_LOG(level, \ 36 "DevX %s failed errno=%d status=%#x syndrome=%#x", \ 37 (reason), errno, MLX5_FW_STATUS((out)), \ 38 MLX5_FW_SYNDROME((out))); \ 39 } else { \ 40 DRV_LOG(level, \ 41 "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x",\ 42 (reason), local_param, (value), errno, \ 43 MLX5_FW_STATUS((out)), MLX5_FW_SYNDROME((out))); \ 44 } \ 45 } while (0) 46 47 static void * 48 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, 49 int *err, uint32_t flags) 50 { 51 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); 52 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); 53 int rc; 54 55 memset(in, 0, size_in); 56 memset(out, 0, size_out); 57 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 58 MLX5_SET(query_hca_cap_in, in, op_mod, flags); 59 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); 60 if (rc || MLX5_FW_STATUS(out)) { 61 DEVX_DRV_LOG(ERR, out, "HCA capabilities", "func", flags >> 1); 62 if (err) 63 *err = MLX5_DEVX_ERR_RC(rc); 64 return NULL; 65 } 66 if (err) 67 *err = 0; 68 return MLX5_ADDR_OF(query_hca_cap_out, out, capability); 69 } 70 71 /** 72 * Perform read access to the registers. Reads data from register 73 * and writes ones to the specified buffer. 74 * 75 * @param[in] ctx 76 * Context returned from mlx5 open_device() glue function. 77 * @param[in] reg_id 78 * Register identifier according to the PRM. 79 * @param[in] arg 80 * Register access auxiliary parameter according to the PRM. 81 * @param[out] data 82 * Pointer to the buffer to store read data. 83 * @param[in] dw_cnt 84 * Buffer size in double words. 85 * 86 * @return 87 * 0 on success, a negative value otherwise. 88 */ 89 int 90 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 91 uint32_t *data, uint32_t dw_cnt) 92 { 93 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 94 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 95 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 96 int rc; 97 98 MLX5_ASSERT(data && dw_cnt); 99 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 100 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 101 DRV_LOG(ERR, "Not enough buffer for register read data"); 102 return -1; 103 } 104 MLX5_SET(access_register_in, in, opcode, 105 MLX5_CMD_OP_ACCESS_REGISTER_USER); 106 MLX5_SET(access_register_in, in, op_mod, 107 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 108 MLX5_SET(access_register_in, in, register_id, reg_id); 109 MLX5_SET(access_register_in, in, argument, arg); 110 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 111 MLX5_ST_SZ_BYTES(access_register_out) + 112 sizeof(uint32_t) * dw_cnt); 113 if (rc || MLX5_FW_STATUS(out)) { 114 DEVX_DRV_LOG(DEBUG, out, "read access", "NIC register", reg_id); 115 return MLX5_DEVX_ERR_RC(rc); 116 } 117 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 118 dw_cnt * sizeof(uint32_t)); 119 return 0; 120 } 121 122 /** 123 * Perform write access to the registers. 124 * 125 * @param[in] ctx 126 * Context returned from mlx5 open_device() glue function. 127 * @param[in] reg_id 128 * Register identifier according to the PRM. 129 * @param[in] arg 130 * Register access auxiliary parameter according to the PRM. 131 * @param[out] data 132 * Pointer to the buffer containing data to write. 133 * @param[in] dw_cnt 134 * Buffer size in double words (32bit units). 135 * 136 * @return 137 * 0 on success, a negative value otherwise. 138 */ 139 int 140 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 141 uint32_t *data, uint32_t dw_cnt) 142 { 143 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 144 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 145 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 146 int rc; 147 void *ptr; 148 149 MLX5_ASSERT(data && dw_cnt); 150 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 151 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 152 DRV_LOG(ERR, "Data to write exceeds max size"); 153 return -1; 154 } 155 MLX5_SET(access_register_in, in, opcode, 156 MLX5_CMD_OP_ACCESS_REGISTER_USER); 157 MLX5_SET(access_register_in, in, op_mod, 158 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 159 MLX5_SET(access_register_in, in, register_id, reg_id); 160 MLX5_SET(access_register_in, in, argument, arg); 161 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 162 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 163 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 164 if (rc || MLX5_FW_STATUS(out)) { 165 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 166 return MLX5_DEVX_ERR_RC(rc); 167 } 168 rc = mlx5_glue->devx_general_cmd(ctx, in, 169 MLX5_ST_SZ_BYTES(access_register_in) + 170 dw_cnt * sizeof(uint32_t), 171 out, sizeof(out)); 172 if (rc || MLX5_FW_STATUS(out)) { 173 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 174 return MLX5_DEVX_ERR_RC(rc); 175 } 176 return 0; 177 } 178 179 struct mlx5_devx_obj * 180 mlx5_devx_cmd_flow_counter_alloc_general(void *ctx, 181 struct mlx5_devx_counter_attr *attr) 182 { 183 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 184 0, SOCKET_ID_ANY); 185 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 186 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 187 188 if (!dcs) { 189 rte_errno = ENOMEM; 190 return NULL; 191 } 192 MLX5_SET(alloc_flow_counter_in, in, opcode, 193 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 194 if (attr->bulk_log_max_alloc) 195 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk_log_size, 196 attr->flow_counter_bulk_log_size); 197 else 198 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, 199 attr->bulk_n_128); 200 if (attr->pd_valid) 201 MLX5_SET(alloc_flow_counter_in, in, pd, attr->pd); 202 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 203 sizeof(in), out, sizeof(out)); 204 if (!dcs->obj) { 205 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 206 rte_errno = errno; 207 mlx5_free(dcs); 208 return NULL; 209 } 210 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 211 return dcs; 212 } 213 214 /** 215 * Allocate flow counters via devx interface. 216 * 217 * @param[in] ctx 218 * Context returned from mlx5 open_device() glue function. 219 * @param dcs 220 * Pointer to counters properties structure to be filled by the routine. 221 * @param bulk_n_128 222 * Bulk counter numbers in 128 counters units. 223 * 224 * @return 225 * Pointer to counter object on success, a negative value otherwise and 226 * rte_errno is set. 227 */ 228 struct mlx5_devx_obj * 229 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 230 { 231 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 232 0, SOCKET_ID_ANY); 233 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 234 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 235 236 if (!dcs) { 237 rte_errno = ENOMEM; 238 return NULL; 239 } 240 MLX5_SET(alloc_flow_counter_in, in, opcode, 241 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 242 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 243 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 244 sizeof(in), out, sizeof(out)); 245 if (!dcs->obj) { 246 DEVX_DRV_LOG(ERR, out, "allocate counters", NULL, 0); 247 mlx5_free(dcs); 248 return NULL; 249 } 250 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 251 return dcs; 252 } 253 254 /** 255 * Query flow counters values. 256 * 257 * @param[in] dcs 258 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 259 * @param[in] clear 260 * Whether hardware should clear the counters after the query or not. 261 * @param[in] n_counters 262 * 0 in case of 1 counter to read, otherwise the counter number to read. 263 * @param pkts 264 * The number of packets that matched the flow. 265 * @param bytes 266 * The number of bytes that matched the flow. 267 * @param mkey 268 * The mkey key for batch query. 269 * @param addr 270 * The address in the mkey range for batch query. 271 * @param cmd_comp 272 * The completion object for asynchronous batch query. 273 * @param async_id 274 * The ID to be returned in the asynchronous batch query response. 275 * 276 * @return 277 * 0 on success, a negative value otherwise. 278 */ 279 int 280 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 281 int clear, uint32_t n_counters, 282 uint64_t *pkts, uint64_t *bytes, 283 uint32_t mkey, void *addr, 284 void *cmd_comp, 285 uint64_t async_id) 286 { 287 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 288 MLX5_ST_SZ_BYTES(traffic_counter); 289 uint32_t out[out_len]; 290 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 291 void *stats; 292 int rc; 293 294 MLX5_SET(query_flow_counter_in, in, opcode, 295 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 296 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 297 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 298 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 299 300 if (n_counters) { 301 MLX5_SET(query_flow_counter_in, in, num_of_counters, 302 n_counters); 303 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 304 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 305 MLX5_SET64(query_flow_counter_in, in, address, 306 (uint64_t)(uintptr_t)addr); 307 } 308 if (!cmd_comp) 309 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 310 out_len); 311 else 312 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 313 out_len, async_id, 314 cmd_comp); 315 if (rc) { 316 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 317 rte_errno = rc; 318 return -rc; 319 } 320 if (!n_counters) { 321 stats = MLX5_ADDR_OF(query_flow_counter_out, 322 out, flow_statistics); 323 *pkts = MLX5_GET64(traffic_counter, stats, packets); 324 *bytes = MLX5_GET64(traffic_counter, stats, octets); 325 } 326 return 0; 327 } 328 329 /** 330 * Create a new mkey. 331 * 332 * @param[in] ctx 333 * Context returned from mlx5 open_device() glue function. 334 * @param[in] attr 335 * Attributes of the requested mkey. 336 * 337 * @return 338 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 339 * is set. 340 */ 341 struct mlx5_devx_obj * 342 mlx5_devx_cmd_mkey_create(void *ctx, 343 struct mlx5_devx_mkey_attr *attr) 344 { 345 struct mlx5_klm *klm_array = attr->klm_array; 346 int klm_num = attr->klm_num; 347 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 348 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 349 uint32_t in[in_size_dw]; 350 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 351 void *mkc; 352 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 353 0, SOCKET_ID_ANY); 354 size_t pgsize; 355 uint32_t translation_size; 356 357 if (!mkey) { 358 rte_errno = ENOMEM; 359 return NULL; 360 } 361 memset(in, 0, in_size_dw * 4); 362 pgsize = rte_mem_page_size(); 363 if (pgsize == (size_t)-1) { 364 mlx5_free(mkey); 365 DRV_LOG(ERR, "Failed to get page size"); 366 rte_errno = ENOMEM; 367 return NULL; 368 } 369 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 370 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 371 if (klm_num > 0) { 372 int i; 373 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 374 klm_pas_mtt); 375 translation_size = RTE_ALIGN(klm_num, 4); 376 for (i = 0; i < klm_num; i++) { 377 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 378 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 379 MLX5_SET64(klm, klm, address, klm_array[i].address); 380 klm += MLX5_ST_SZ_BYTES(klm); 381 } 382 for (; i < (int)translation_size; i++) { 383 MLX5_SET(klm, klm, mkey, 0x0); 384 MLX5_SET64(klm, klm, address, 0x0); 385 klm += MLX5_ST_SZ_BYTES(klm); 386 } 387 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 388 MLX5_MKC_ACCESS_MODE_KLM_FBS : 389 MLX5_MKC_ACCESS_MODE_KLM); 390 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 391 } else { 392 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 393 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 394 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 395 } 396 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 397 translation_size); 398 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 399 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 400 MLX5_SET(mkc, mkc, lw, 0x1); 401 MLX5_SET(mkc, mkc, lr, 0x1); 402 if (attr->set_remote_rw) { 403 MLX5_SET(mkc, mkc, rw, 0x1); 404 MLX5_SET(mkc, mkc, rr, 0x1); 405 } 406 MLX5_SET(mkc, mkc, qpn, 0xffffff); 407 MLX5_SET(mkc, mkc, pd, attr->pd); 408 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 409 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 410 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 411 MLX5_SET(mkc, mkc, relaxed_ordering_write, 412 attr->relaxed_ordering_write); 413 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 414 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 415 MLX5_SET64(mkc, mkc, len, attr->size); 416 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 417 if (attr->crypto_en) { 418 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 419 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 420 } 421 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 422 sizeof(out)); 423 if (!mkey->obj) { 424 DEVX_DRV_LOG(ERR, out, klm_num ? "create indirect mkey" 425 : "create direct key", NULL, 0); 426 mlx5_free(mkey); 427 return NULL; 428 } 429 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 430 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 431 return mkey; 432 } 433 434 /** 435 * Get status of devx command response. 436 * Mainly used for asynchronous commands. 437 * 438 * @param[in] out 439 * The out response buffer. 440 * 441 * @return 442 * 0 on success, non-zero value otherwise. 443 */ 444 int 445 mlx5_devx_get_out_command_status(void *out) 446 { 447 int status; 448 449 if (!out) 450 return -EINVAL; 451 status = MLX5_GET(query_flow_counter_out, out, status); 452 if (status) { 453 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 454 455 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 456 syndrome); 457 } 458 return status; 459 } 460 461 /** 462 * Destroy any object allocated by a Devx API. 463 * 464 * @param[in] obj 465 * Pointer to a general object. 466 * 467 * @return 468 * 0 on success, a negative value otherwise. 469 */ 470 int 471 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 472 { 473 int ret; 474 475 if (!obj) 476 return 0; 477 ret = mlx5_glue->devx_obj_destroy(obj->obj); 478 mlx5_free(obj); 479 return ret; 480 } 481 482 /** 483 * Query NIC vport context. 484 * Fills minimal inline attribute. 485 * 486 * @param[in] ctx 487 * ibv contexts returned from mlx5dv_open_device. 488 * @param[in] vport 489 * vport index 490 * @param[out] attr 491 * Attributes device values. 492 * 493 * @return 494 * 0 on success, a negative value otherwise. 495 */ 496 static int 497 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 498 unsigned int vport, 499 struct mlx5_hca_attr *attr) 500 { 501 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 502 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 503 void *vctx; 504 int rc; 505 506 /* Query NIC vport context to determine inline mode. */ 507 MLX5_SET(query_nic_vport_context_in, in, opcode, 508 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 509 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 510 if (vport) 511 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 512 rc = mlx5_glue->devx_general_cmd(ctx, 513 in, sizeof(in), 514 out, sizeof(out)); 515 if (rc || MLX5_FW_STATUS(out)) { 516 DEVX_DRV_LOG(ERR, out, "query NIC vport context", NULL, 0); 517 return MLX5_DEVX_ERR_RC(rc); 518 } 519 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 520 nic_vport_context); 521 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 522 min_wqe_inline_mode); 523 return 0; 524 } 525 526 /** 527 * Query NIC vDPA attributes. 528 * 529 * @param[in] ctx 530 * Context returned from mlx5 open_device() glue function. 531 * @param[out] vdpa_attr 532 * vDPA Attributes structure to fill. 533 */ 534 static void 535 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 536 struct mlx5_hca_vdpa_attr *vdpa_attr) 537 { 538 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 539 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 540 void *hcattr; 541 542 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, 543 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 544 MLX5_HCA_CAP_OPMOD_GET_CUR); 545 if (!hcattr) { 546 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities"); 547 vdpa_attr->valid = 0; 548 } else { 549 vdpa_attr->valid = 1; 550 vdpa_attr->desc_tunnel_offload_type = 551 MLX5_GET(virtio_emulation_cap, hcattr, 552 desc_tunnel_offload_type); 553 vdpa_attr->eth_frame_offload_type = 554 MLX5_GET(virtio_emulation_cap, hcattr, 555 eth_frame_offload_type); 556 vdpa_attr->virtio_version_1_0 = 557 MLX5_GET(virtio_emulation_cap, hcattr, 558 virtio_version_1_0); 559 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 560 tso_ipv4); 561 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 562 tso_ipv6); 563 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 564 tx_csum); 565 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 566 rx_csum); 567 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 568 event_mode); 569 vdpa_attr->virtio_queue_type = 570 MLX5_GET(virtio_emulation_cap, hcattr, 571 virtio_queue_type); 572 vdpa_attr->log_doorbell_stride = 573 MLX5_GET(virtio_emulation_cap, hcattr, 574 log_doorbell_stride); 575 vdpa_attr->vnet_modify_ext = 576 MLX5_GET(virtio_emulation_cap, hcattr, 577 vnet_modify_ext); 578 vdpa_attr->virtio_net_q_addr_modify = 579 MLX5_GET(virtio_emulation_cap, hcattr, 580 virtio_net_q_addr_modify); 581 vdpa_attr->virtio_q_index_modify = 582 MLX5_GET(virtio_emulation_cap, hcattr, 583 virtio_q_index_modify); 584 vdpa_attr->log_doorbell_bar_size = 585 MLX5_GET(virtio_emulation_cap, hcattr, 586 log_doorbell_bar_size); 587 vdpa_attr->doorbell_bar_offset = 588 MLX5_GET64(virtio_emulation_cap, hcattr, 589 doorbell_bar_offset); 590 vdpa_attr->max_num_virtio_queues = 591 MLX5_GET(virtio_emulation_cap, hcattr, 592 max_num_virtio_queues); 593 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 594 umem_1_buffer_param_a); 595 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 596 umem_1_buffer_param_b); 597 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 598 umem_2_buffer_param_a); 599 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 600 umem_2_buffer_param_b); 601 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 602 umem_3_buffer_param_a); 603 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 604 umem_3_buffer_param_b); 605 } 606 } 607 608 int 609 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 610 struct mlx5_ext_sample_id *ids, 611 uint32_t num, uint8_t *anchor) 612 { 613 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 614 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 615 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 616 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 617 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 618 int ret; 619 uint32_t idx = 0; 620 uint32_t i; 621 622 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 623 rte_errno = EINVAL; 624 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 625 return -rte_errno; 626 } 627 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 628 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 629 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 630 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 631 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 632 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 633 out, sizeof(out)); 634 if (ret) { 635 rte_errno = ret; 636 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 637 (void *)flex_obj); 638 return -rte_errno; 639 } 640 if (anchor) 641 *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id); 642 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx <= num; i++) { 643 void *s_off = (void *)((char *)sample + i * 644 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 645 uint32_t en; 646 647 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 648 flow_match_sample_en); 649 if (!en) 650 continue; 651 ids[idx++].id = MLX5_GET(parse_graph_flow_match_sample, s_off, 652 flow_match_sample_field_id); 653 } 654 if (num != idx) { 655 rte_errno = EINVAL; 656 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 657 return -rte_errno; 658 } 659 return ret; 660 } 661 662 struct mlx5_devx_obj * 663 mlx5_devx_cmd_create_flex_parser(void *ctx, 664 struct mlx5_devx_graph_node_attr *data) 665 { 666 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 667 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 668 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 669 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 670 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 671 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 672 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 673 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 674 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 675 uint32_t i; 676 677 if (!parse_flex_obj) { 678 DRV_LOG(ERR, "Failed to allocate flex parser data."); 679 rte_errno = ENOMEM; 680 return NULL; 681 } 682 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 683 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 684 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 685 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 686 MLX5_SET(parse_graph_flex, flex, header_length_mode, 687 data->header_length_mode); 688 MLX5_SET64(parse_graph_flex, flex, modify_field_select, 689 data->modify_field_select); 690 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 691 data->header_length_base_value); 692 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 693 data->header_length_field_offset); 694 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 695 data->header_length_field_shift); 696 MLX5_SET(parse_graph_flex, flex, next_header_field_offset, 697 data->next_header_field_offset); 698 MLX5_SET(parse_graph_flex, flex, next_header_field_size, 699 data->next_header_field_size); 700 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 701 data->header_length_field_mask); 702 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 703 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 704 void *s_off = (void *)((char *)sample + i * 705 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 706 707 if (!s->flow_match_sample_en) 708 continue; 709 MLX5_SET(parse_graph_flow_match_sample, s_off, 710 flow_match_sample_en, !!s->flow_match_sample_en); 711 MLX5_SET(parse_graph_flow_match_sample, s_off, 712 flow_match_sample_field_offset, 713 s->flow_match_sample_field_offset); 714 MLX5_SET(parse_graph_flow_match_sample, s_off, 715 flow_match_sample_offset_mode, 716 s->flow_match_sample_offset_mode); 717 MLX5_SET(parse_graph_flow_match_sample, s_off, 718 flow_match_sample_field_offset_mask, 719 s->flow_match_sample_field_offset_mask); 720 MLX5_SET(parse_graph_flow_match_sample, s_off, 721 flow_match_sample_field_offset_shift, 722 s->flow_match_sample_field_offset_shift); 723 MLX5_SET(parse_graph_flow_match_sample, s_off, 724 flow_match_sample_field_base_offset, 725 s->flow_match_sample_field_base_offset); 726 MLX5_SET(parse_graph_flow_match_sample, s_off, 727 flow_match_sample_tunnel_mode, 728 s->flow_match_sample_tunnel_mode); 729 } 730 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 731 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 732 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 733 void *in_off = (void *)((char *)in_arc + i * 734 MLX5_ST_SZ_BYTES(parse_graph_arc)); 735 void *out_off = (void *)((char *)out_arc + i * 736 MLX5_ST_SZ_BYTES(parse_graph_arc)); 737 738 if (ia->arc_parse_graph_node != 0) { 739 MLX5_SET(parse_graph_arc, in_off, 740 compare_condition_value, 741 ia->compare_condition_value); 742 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 743 ia->start_inner_tunnel); 744 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 745 ia->arc_parse_graph_node); 746 MLX5_SET(parse_graph_arc, in_off, 747 parse_graph_node_handle, 748 ia->parse_graph_node_handle); 749 } 750 if (oa->arc_parse_graph_node != 0) { 751 MLX5_SET(parse_graph_arc, out_off, 752 compare_condition_value, 753 oa->compare_condition_value); 754 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 755 oa->start_inner_tunnel); 756 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 757 oa->arc_parse_graph_node); 758 MLX5_SET(parse_graph_arc, out_off, 759 parse_graph_node_handle, 760 oa->parse_graph_node_handle); 761 } 762 } 763 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 764 out, sizeof(out)); 765 if (!parse_flex_obj->obj) { 766 DEVX_DRV_LOG(ERR, out, "create FLEX PARSE GRAPH", NULL, 0); 767 mlx5_free(parse_flex_obj); 768 return NULL; 769 } 770 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 771 return parse_flex_obj; 772 } 773 774 static int 775 mlx5_devx_cmd_query_hca_parse_graph_node_cap 776 (void *ctx, struct mlx5_hca_flex_attr *attr) 777 { 778 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 779 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 780 void *hcattr; 781 int rc; 782 783 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 784 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | 785 MLX5_HCA_CAP_OPMOD_GET_CUR); 786 if (!hcattr) 787 return rc; 788 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); 789 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); 790 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, 791 header_length_mode); 792 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, 793 sample_offset_mode); 794 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, 795 max_num_arc_in); 796 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, 797 max_num_arc_out); 798 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, 799 max_num_sample); 800 attr->anchor_en = MLX5_GET(parse_graph_node_cap, hcattr, anchor_en); 801 attr->ext_sample_id = MLX5_GET(parse_graph_node_cap, hcattr, ext_sample_id); 802 attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr, 803 sample_tunnel_inner2); 804 attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr, 805 zero_size_supported); 806 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, 807 sample_id_in_out); 808 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, 809 max_base_header_length); 810 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, 811 max_sample_base_offset); 812 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, 813 max_next_header_offset); 814 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, 815 header_length_mask_width); 816 /* Get the max supported samples from HCA CAP 2 */ 817 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 818 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 819 MLX5_HCA_CAP_OPMOD_GET_CUR); 820 if (!hcattr) 821 return rc; 822 attr->max_num_prog_sample = 823 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); 824 return 0; 825 } 826 827 static int 828 mlx5_devx_query_pkt_integrity_match(void *hcattr) 829 { 830 return MLX5_GET(flow_table_nic_cap, hcattr, 831 ft_field_support_2_nic_receive.inner_l3_ok) && 832 MLX5_GET(flow_table_nic_cap, hcattr, 833 ft_field_support_2_nic_receive.inner_l4_ok) && 834 MLX5_GET(flow_table_nic_cap, hcattr, 835 ft_field_support_2_nic_receive.outer_l3_ok) && 836 MLX5_GET(flow_table_nic_cap, hcattr, 837 ft_field_support_2_nic_receive.outer_l4_ok) && 838 MLX5_GET(flow_table_nic_cap, hcattr, 839 ft_field_support_2_nic_receive 840 .inner_ipv4_checksum_ok) && 841 MLX5_GET(flow_table_nic_cap, hcattr, 842 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 843 MLX5_GET(flow_table_nic_cap, hcattr, 844 ft_field_support_2_nic_receive 845 .outer_ipv4_checksum_ok) && 846 MLX5_GET(flow_table_nic_cap, hcattr, 847 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 848 } 849 850 /** 851 * Query HCA attributes. 852 * Using those attributes we can check on run time if the device 853 * is having the required capabilities. 854 * 855 * @param[in] ctx 856 * Context returned from mlx5 open_device() glue function. 857 * @param[out] attr 858 * Attributes device values. 859 * 860 * @return 861 * 0 on success, a negative value otherwise. 862 */ 863 int 864 mlx5_devx_cmd_query_hca_attr(void *ctx, 865 struct mlx5_hca_attr *attr) 866 { 867 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 868 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 869 bool hca_cap_2_sup; 870 uint64_t general_obj_types_supported = 0; 871 void *hcattr; 872 int rc, i; 873 874 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 875 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 876 MLX5_HCA_CAP_OPMOD_GET_CUR); 877 if (!hcattr) 878 return rc; 879 hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2); 880 attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq); 881 attr->flow_counter_bulk_alloc_bitmap = 882 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 883 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 884 flow_counters_dump); 885 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp); 886 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp); 887 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 888 log_max_rqt_size); 889 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 890 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 891 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 892 log_max_hairpin_queues); 893 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 894 log_max_hairpin_wq_data_sz); 895 attr->log_max_hairpin_num_packets = MLX5_GET 896 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 897 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 898 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 899 relaxed_ordering_write); 900 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 901 relaxed_ordering_read); 902 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 903 access_register_user); 904 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 905 eth_net_offloads); 906 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 907 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 908 flex_parser_protocols); 909 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 910 max_geneve_tlv_options); 911 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 912 max_geneve_tlv_option_data_len); 913 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 914 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 915 general_obj_types) & 916 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 917 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 918 general_obj_types) & 919 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 920 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 921 general_obj_types) & 922 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 923 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 924 general_obj_types) & 925 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 926 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 927 wqe_index_ignore_cap); 928 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 929 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 930 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 931 log_max_static_sq_wq); 932 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 933 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 934 device_frequency_khz); 935 attr->scatter_fcs_w_decap_disable = 936 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 937 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 938 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 939 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 940 attr->steering_format_version = 941 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 942 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 943 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 944 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 945 regexp_num_of_engines); 946 /* Read the general_obj_types bitmap and extract the relevant bits. */ 947 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 948 general_obj_types); 949 attr->vdpa.valid = !!(general_obj_types_supported & 950 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 951 attr->vdpa.queue_counters_valid = 952 !!(general_obj_types_supported & 953 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 954 attr->parse_graph_flex_node = 955 !!(general_obj_types_supported & 956 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 957 attr->flow_hit_aso = !!(general_obj_types_supported & 958 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 959 attr->geneve_tlv_opt = !!(general_obj_types_supported & 960 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 961 attr->dek = !!(general_obj_types_supported & 962 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 963 attr->import_kek = !!(general_obj_types_supported & 964 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 965 attr->credential = !!(general_obj_types_supported & 966 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 967 attr->crypto_login = !!(general_obj_types_supported & 968 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 969 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 970 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 971 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 972 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 973 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 974 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 975 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 976 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 977 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 978 attr->reg_c_preserve = 979 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 980 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 981 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 982 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 983 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 984 compress_mmo_sq); 985 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 986 decompress_mmo_sq); 987 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 988 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 989 compress_mmo_qp); 990 attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 991 decompress_mmo_qp); 992 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 993 compress_min_block_size); 994 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 995 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 996 log_compress_mmo_size); 997 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 998 log_decompress_mmo_size); 999 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 1000 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 1001 mini_cqe_resp_flow_tag); 1002 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 1003 mini_cqe_resp_l3_l4_tag); 1004 attr->umr_indirect_mkey_disabled = 1005 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 1006 attr->umr_modify_entity_size_disabled = 1007 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 1008 attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time); 1009 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 1010 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 1011 general_obj_types) & 1012 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 1013 attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); 1014 attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr, 1015 max_flow_counter_15_0); 1016 attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr, 1017 max_flow_counter_31_16); 1018 attr->alloc_flow_counter_pd = MLX5_GET(cmd_hca_cap, hcattr, 1019 alloc_flow_counter_pd); 1020 attr->flow_counter_access_aso = MLX5_GET(cmd_hca_cap, hcattr, 1021 flow_counter_access_aso); 1022 attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr, 1023 flow_access_aso_opc_mod); 1024 if (attr->crypto) { 1025 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) || 1026 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_multi_block_be_tweak) || 1027 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_single_block_le_tweak); 1028 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1029 MLX5_GET_HCA_CAP_OP_MOD_CRYPTO | 1030 MLX5_HCA_CAP_OPMOD_GET_CUR); 1031 if (!hcattr) 1032 return -1; 1033 attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps, 1034 hcattr, wrapped_import_method) 1035 & 1 << 2); 1036 } 1037 if (hca_cap_2_sup) { 1038 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1039 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 1040 MLX5_HCA_CAP_OPMOD_GET_CUR); 1041 if (!hcattr) { 1042 DRV_LOG(DEBUG, 1043 "Failed to query DevX HCA capabilities 2."); 1044 return rc; 1045 } 1046 attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, 1047 log_min_stride_wqe_sz); 1048 attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr, 1049 hairpin_sq_wqe_bb_size); 1050 attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr, 1051 hairpin_sq_wq_in_host_mem); 1052 attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr, 1053 hairpin_data_buffer_locked); 1054 attr->flow_counter_bulk_log_max_alloc = MLX5_GET(cmd_hca_cap_2, 1055 hcattr, flow_counter_bulk_log_max_alloc); 1056 attr->flow_counter_bulk_log_granularity = 1057 MLX5_GET(cmd_hca_cap_2, hcattr, 1058 flow_counter_bulk_log_granularity); 1059 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1060 cross_vhca_object_to_object_supported); 1061 attr->cross_vhca = 1062 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR) && 1063 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT) && 1064 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT) && 1065 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC); 1066 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1067 allowed_object_for_other_vhca_access); 1068 attr->cross_vhca = attr->cross_vhca && 1069 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR) && 1070 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_FT) && 1071 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC); 1072 } 1073 if (attr->log_min_stride_wqe_sz == 0) 1074 attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 1075 if (attr->qos.sup) { 1076 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1077 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 1078 MLX5_HCA_CAP_OPMOD_GET_CUR); 1079 if (!hcattr) { 1080 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); 1081 return rc; 1082 } 1083 attr->qos.flow_meter_old = 1084 MLX5_GET(qos_cap, hcattr, flow_meter_old); 1085 attr->qos.log_max_flow_meter = 1086 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 1087 attr->qos.flow_meter_reg_c_ids = 1088 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 1089 attr->qos.flow_meter = 1090 MLX5_GET(qos_cap, hcattr, flow_meter); 1091 attr->qos.packet_pacing = 1092 MLX5_GET(qos_cap, hcattr, packet_pacing); 1093 attr->qos.wqe_rate_pp = 1094 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 1095 if (attr->qos.flow_meter_aso_sup) { 1096 attr->qos.log_meter_aso_granularity = 1097 MLX5_GET(qos_cap, hcattr, 1098 log_meter_aso_granularity); 1099 attr->qos.log_meter_aso_max_alloc = 1100 MLX5_GET(qos_cap, hcattr, 1101 log_meter_aso_max_alloc); 1102 attr->qos.log_max_num_meter_aso = 1103 MLX5_GET(qos_cap, hcattr, 1104 log_max_num_meter_aso); 1105 } 1106 } 1107 /* 1108 * Flex item support needs max_num_prog_sample_field 1109 * from the Capabilities 2 table for PARSE_GRAPH_NODE 1110 */ 1111 if (attr->parse_graph_flex_node) { 1112 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap 1113 (ctx, &attr->flex); 1114 if (rc) 1115 return -1; 1116 } 1117 if (attr->vdpa.valid) 1118 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 1119 if (!attr->eth_net_offloads) 1120 return 0; 1121 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 1122 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1123 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 1124 MLX5_HCA_CAP_OPMOD_GET_CUR); 1125 if (!hcattr) { 1126 attr->log_max_ft_sampler_num = 0; 1127 return rc; 1128 } 1129 attr->log_max_ft_sampler_num = MLX5_GET 1130 (flow_table_nic_cap, hcattr, 1131 flow_table_properties_nic_receive.log_max_ft_sampler_num); 1132 attr->flow.tunnel_header_0_1 = MLX5_GET 1133 (flow_table_nic_cap, hcattr, 1134 ft_field_support_2_nic_receive.tunnel_header_0_1); 1135 attr->flow.tunnel_header_2_3 = MLX5_GET 1136 (flow_table_nic_cap, hcattr, 1137 ft_field_support_2_nic_receive.tunnel_header_2_3); 1138 attr->modify_outer_ip_ecn = MLX5_GET 1139 (flow_table_nic_cap, hcattr, 1140 ft_header_modify_nic_receive.outer_ip_ecn); 1141 attr->set_reg_c = 0xff; 1142 if (attr->nic_flow_table) { 1143 #define GET_RX_REG_X_BITS \ 1144 MLX5_GET(flow_table_nic_cap, hcattr, \ 1145 ft_header_modify_nic_receive.metadata_reg_c_x) 1146 #define GET_TX_REG_X_BITS \ 1147 MLX5_GET(flow_table_nic_cap, hcattr, \ 1148 ft_header_modify_nic_transmit.metadata_reg_c_x) 1149 1150 uint32_t tx_reg, rx_reg; 1151 1152 tx_reg = GET_TX_REG_X_BITS; 1153 rx_reg = GET_RX_REG_X_BITS; 1154 attr->set_reg_c &= (rx_reg & tx_reg); 1155 1156 #undef GET_RX_REG_X_BITS 1157 #undef GET_TX_REG_X_BITS 1158 } 1159 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 1160 attr->inner_ipv4_ihl = MLX5_GET 1161 (flow_table_nic_cap, hcattr, 1162 ft_field_support_2_nic_receive.inner_ipv4_ihl); 1163 attr->outer_ipv4_ihl = MLX5_GET 1164 (flow_table_nic_cap, hcattr, 1165 ft_field_support_2_nic_receive.outer_ipv4_ihl); 1166 /* Query HCA offloads for Ethernet protocol. */ 1167 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1168 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 1169 MLX5_HCA_CAP_OPMOD_GET_CUR); 1170 if (!hcattr) { 1171 attr->eth_net_offloads = 0; 1172 return rc; 1173 } 1174 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 1175 hcattr, wqe_vlan_insert); 1176 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 1177 hcattr, csum_cap); 1178 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 1179 hcattr, vlan_cap); 1180 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1181 lro_cap); 1182 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1183 hcattr, max_lso_cap); 1184 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1185 hcattr, scatter_fcs); 1186 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1187 hcattr, tunnel_lro_gre); 1188 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1189 hcattr, tunnel_lro_vxlan); 1190 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1191 hcattr, swp); 1192 attr->tunnel_stateless_gre = 1193 MLX5_GET(per_protocol_networking_offload_caps, 1194 hcattr, tunnel_stateless_gre); 1195 attr->tunnel_stateless_vxlan = 1196 MLX5_GET(per_protocol_networking_offload_caps, 1197 hcattr, tunnel_stateless_vxlan); 1198 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1199 hcattr, swp_csum); 1200 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1201 hcattr, swp_lso); 1202 attr->lro_max_msg_sz_mode = MLX5_GET 1203 (per_protocol_networking_offload_caps, 1204 hcattr, lro_max_msg_sz_mode); 1205 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1206 attr->lro_timer_supported_periods[i] = 1207 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1208 lro_timer_supported_periods[i]); 1209 } 1210 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1211 hcattr, lro_min_mss_size); 1212 attr->tunnel_stateless_geneve_rx = 1213 MLX5_GET(per_protocol_networking_offload_caps, 1214 hcattr, tunnel_stateless_geneve_rx); 1215 attr->geneve_max_opt_len = 1216 MLX5_GET(per_protocol_networking_offload_caps, 1217 hcattr, max_geneve_opt_len); 1218 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1219 hcattr, wqe_inline_mode); 1220 attr->tunnel_stateless_gtp = MLX5_GET 1221 (per_protocol_networking_offload_caps, 1222 hcattr, tunnel_stateless_gtp); 1223 attr->rss_ind_tbl_cap = MLX5_GET 1224 (per_protocol_networking_offload_caps, 1225 hcattr, rss_ind_tbl_cap); 1226 /* Query HCA attribute for ROCE. */ 1227 if (attr->roce) { 1228 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1229 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1230 MLX5_HCA_CAP_OPMOD_GET_CUR); 1231 if (!hcattr) { 1232 DRV_LOG(DEBUG, 1233 "Failed to query devx HCA ROCE capabilities"); 1234 return rc; 1235 } 1236 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1237 } 1238 if (attr->eth_virt && 1239 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1240 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1241 if (rc) { 1242 attr->eth_virt = 0; 1243 goto error; 1244 } 1245 } 1246 if (attr->eswitch_manager) { 1247 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1248 MLX5_SET_HCA_CAP_OP_MOD_ESW | 1249 MLX5_HCA_CAP_OPMOD_GET_CUR); 1250 if (!hcattr) 1251 return rc; 1252 attr->esw_mgr_vport_id_valid = 1253 MLX5_GET(esw_cap, hcattr, 1254 esw_manager_vport_number_valid); 1255 attr->esw_mgr_vport_id = 1256 MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); 1257 } 1258 if (attr->eswitch_manager) { 1259 uint32_t esw_reg; 1260 1261 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1262 MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE | 1263 MLX5_HCA_CAP_OPMOD_GET_CUR); 1264 if (!hcattr) 1265 return rc; 1266 esw_reg = MLX5_GET(flow_table_esw_cap, hcattr, 1267 ft_header_modify_esw_fdb.metadata_reg_c_x); 1268 attr->set_reg_c &= esw_reg; 1269 } 1270 return 0; 1271 error: 1272 rc = (rc > 0) ? -rc : rc; 1273 return rc; 1274 } 1275 1276 /** 1277 * Query TIS transport domain from QP verbs object using DevX API. 1278 * 1279 * @param[in] qp 1280 * Pointer to verbs QP returned by ibv_create_qp . 1281 * @param[in] tis_num 1282 * TIS number of TIS to query. 1283 * @param[out] tis_td 1284 * Pointer to TIS transport domain variable, to be set by the routine. 1285 * 1286 * @return 1287 * 0 on success, a negative value otherwise. 1288 */ 1289 int 1290 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1291 uint32_t *tis_td) 1292 { 1293 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1294 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1295 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1296 int rc; 1297 void *tis_ctx; 1298 1299 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1300 MLX5_SET(query_tis_in, in, tisn, tis_num); 1301 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1302 if (rc) { 1303 DRV_LOG(ERR, "Failed to query QP using DevX"); 1304 return -rc; 1305 }; 1306 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1307 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1308 return 0; 1309 #else 1310 (void)qp; 1311 (void)tis_num; 1312 (void)tis_td; 1313 return -ENOTSUP; 1314 #endif 1315 } 1316 1317 /** 1318 * Fill WQ data for DevX API command. 1319 * Utility function for use when creating DevX objects containing a WQ. 1320 * 1321 * @param[in] wq_ctx 1322 * Pointer to WQ context to fill with data. 1323 * @param [in] wq_attr 1324 * Pointer to WQ attributes structure to fill in WQ context. 1325 */ 1326 static void 1327 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1328 { 1329 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1330 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1331 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1332 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1333 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1334 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1335 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1336 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1337 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1338 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1339 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1340 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1341 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1342 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1343 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1344 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1345 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1346 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1347 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1348 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1349 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1350 wq_attr->log_hairpin_num_packets); 1351 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1352 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1353 wq_attr->single_wqe_log_num_of_strides); 1354 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1355 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1356 wq_attr->single_stride_log_num_of_bytes); 1357 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1358 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1359 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1360 } 1361 1362 /** 1363 * Create RQ using DevX API. 1364 * 1365 * @param[in] ctx 1366 * Context returned from mlx5 open_device() glue function. 1367 * @param [in] rq_attr 1368 * Pointer to create RQ attributes structure. 1369 * @param [in] socket 1370 * CPU socket ID for allocations. 1371 * 1372 * @return 1373 * The DevX object created, NULL otherwise and rte_errno is set. 1374 */ 1375 struct mlx5_devx_obj * 1376 mlx5_devx_cmd_create_rq(void *ctx, 1377 struct mlx5_devx_create_rq_attr *rq_attr, 1378 int socket) 1379 { 1380 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1381 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1382 void *rq_ctx, *wq_ctx; 1383 struct mlx5_devx_wq_attr *wq_attr; 1384 struct mlx5_devx_obj *rq = NULL; 1385 1386 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1387 if (!rq) { 1388 DRV_LOG(ERR, "Failed to allocate RQ data"); 1389 rte_errno = ENOMEM; 1390 return NULL; 1391 } 1392 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1393 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1394 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1395 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1396 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1397 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1398 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1399 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1400 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1401 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1402 MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type); 1403 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1404 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1405 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1406 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1407 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1408 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1409 wq_attr = &rq_attr->wq_attr; 1410 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1411 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1412 out, sizeof(out)); 1413 if (!rq->obj) { 1414 DEVX_DRV_LOG(ERR, out, "create RQ", NULL, 0); 1415 mlx5_free(rq); 1416 return NULL; 1417 } 1418 rq->id = MLX5_GET(create_rq_out, out, rqn); 1419 return rq; 1420 } 1421 1422 /** 1423 * Modify RQ using DevX API. 1424 * 1425 * @param[in] rq 1426 * Pointer to RQ object structure. 1427 * @param [in] rq_attr 1428 * Pointer to modify RQ attributes structure. 1429 * 1430 * @return 1431 * 0 on success, a negative errno value otherwise and rte_errno is set. 1432 */ 1433 int 1434 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1435 struct mlx5_devx_modify_rq_attr *rq_attr) 1436 { 1437 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1438 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1439 void *rq_ctx, *wq_ctx; 1440 int ret; 1441 1442 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1443 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1444 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1445 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1446 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1447 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1448 if (rq_attr->modify_bitmask & 1449 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1450 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1451 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1452 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1453 if (rq_attr->modify_bitmask & 1454 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1455 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1456 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1457 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1458 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1459 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1460 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1461 } 1462 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1463 out, sizeof(out)); 1464 if (ret) { 1465 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1466 rte_errno = errno; 1467 return -errno; 1468 } 1469 return ret; 1470 } 1471 1472 /** 1473 * Create RMP using DevX API. 1474 * 1475 * @param[in] ctx 1476 * Context returned from mlx5 open_device() glue function. 1477 * @param [in] rmp_attr 1478 * Pointer to create RMP attributes structure. 1479 * @param [in] socket 1480 * CPU socket ID for allocations. 1481 * 1482 * @return 1483 * The DevX object created, NULL otherwise and rte_errno is set. 1484 */ 1485 struct mlx5_devx_obj * 1486 mlx5_devx_cmd_create_rmp(void *ctx, 1487 struct mlx5_devx_create_rmp_attr *rmp_attr, 1488 int socket) 1489 { 1490 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0}; 1491 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0}; 1492 void *rmp_ctx, *wq_ctx; 1493 struct mlx5_devx_wq_attr *wq_attr; 1494 struct mlx5_devx_obj *rmp = NULL; 1495 1496 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket); 1497 if (!rmp) { 1498 DRV_LOG(ERR, "Failed to allocate RMP data"); 1499 rte_errno = ENOMEM; 1500 return NULL; 1501 } 1502 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP); 1503 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx); 1504 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state); 1505 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe, 1506 rmp_attr->basic_cyclic_rcv_wqe); 1507 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq); 1508 wq_attr = &rmp_attr->wq_attr; 1509 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1510 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1511 sizeof(out)); 1512 if (!rmp->obj) { 1513 DEVX_DRV_LOG(ERR, out, "create RMP", NULL, 0); 1514 mlx5_free(rmp); 1515 return NULL; 1516 } 1517 rmp->id = MLX5_GET(create_rmp_out, out, rmpn); 1518 return rmp; 1519 } 1520 1521 /* 1522 * Create TIR using DevX API. 1523 * 1524 * @param[in] ctx 1525 * Context returned from mlx5 open_device() glue function. 1526 * @param [in] tir_attr 1527 * Pointer to TIR attributes structure. 1528 * 1529 * @return 1530 * The DevX object created, NULL otherwise and rte_errno is set. 1531 */ 1532 struct mlx5_devx_obj * 1533 mlx5_devx_cmd_create_tir(void *ctx, 1534 struct mlx5_devx_tir_attr *tir_attr) 1535 { 1536 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1537 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1538 void *tir_ctx, *outer, *inner, *rss_key; 1539 struct mlx5_devx_obj *tir = NULL; 1540 1541 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1542 if (!tir) { 1543 DRV_LOG(ERR, "Failed to allocate TIR data"); 1544 rte_errno = ENOMEM; 1545 return NULL; 1546 } 1547 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1548 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1549 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1550 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1551 tir_attr->lro_timeout_period_usecs); 1552 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1553 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1554 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1555 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1556 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1557 tir_attr->tunneled_offload_en); 1558 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1559 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1560 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1561 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1562 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1563 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1564 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1565 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1566 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1567 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1568 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1569 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1570 tir_attr->rx_hash_field_selector_outer.selected_fields); 1571 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1572 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1573 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1574 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1575 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1576 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1577 tir_attr->rx_hash_field_selector_inner.selected_fields); 1578 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1579 out, sizeof(out)); 1580 if (!tir->obj) { 1581 DEVX_DRV_LOG(ERR, out, "create TIR", NULL, 0); 1582 mlx5_free(tir); 1583 return NULL; 1584 } 1585 tir->id = MLX5_GET(create_tir_out, out, tirn); 1586 return tir; 1587 } 1588 1589 /** 1590 * Modify TIR using DevX API. 1591 * 1592 * @param[in] tir 1593 * Pointer to TIR DevX object structure. 1594 * @param [in] modify_tir_attr 1595 * Pointer to TIR modification attributes structure. 1596 * 1597 * @return 1598 * 0 on success, a negative errno value otherwise and rte_errno is set. 1599 */ 1600 int 1601 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1602 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1603 { 1604 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1605 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1606 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1607 void *tir_ctx; 1608 int ret; 1609 1610 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1611 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1612 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1613 modify_tir_attr->modify_bitmask); 1614 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1615 if (modify_tir_attr->modify_bitmask & 1616 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1617 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1618 tir_attr->lro_timeout_period_usecs); 1619 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1620 tir_attr->lro_enable_mask); 1621 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1622 tir_attr->lro_max_msg_sz); 1623 } 1624 if (modify_tir_attr->modify_bitmask & 1625 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1626 MLX5_SET(tirc, tir_ctx, indirect_table, 1627 tir_attr->indirect_table); 1628 if (modify_tir_attr->modify_bitmask & 1629 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1630 int i; 1631 void *outer, *inner; 1632 1633 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1634 tir_attr->rx_hash_symmetric); 1635 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1636 for (i = 0; i < 10; i++) { 1637 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1638 tir_attr->rx_hash_toeplitz_key[i]); 1639 } 1640 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1641 rx_hash_field_selector_outer); 1642 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1643 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1644 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1645 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1646 MLX5_SET 1647 (rx_hash_field_select, outer, selected_fields, 1648 tir_attr->rx_hash_field_selector_outer.selected_fields); 1649 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1650 rx_hash_field_selector_inner); 1651 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1652 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1653 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1654 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1655 MLX5_SET 1656 (rx_hash_field_select, inner, selected_fields, 1657 tir_attr->rx_hash_field_selector_inner.selected_fields); 1658 } 1659 if (modify_tir_attr->modify_bitmask & 1660 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1661 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1662 } 1663 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1664 out, sizeof(out)); 1665 if (ret) { 1666 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1667 rte_errno = errno; 1668 return -errno; 1669 } 1670 return ret; 1671 } 1672 1673 /** 1674 * Create RQT using DevX API. 1675 * 1676 * @param[in] ctx 1677 * Context returned from mlx5 open_device() glue function. 1678 * @param [in] rqt_attr 1679 * Pointer to RQT attributes structure. 1680 * 1681 * @return 1682 * The DevX object created, NULL otherwise and rte_errno is set. 1683 */ 1684 struct mlx5_devx_obj * 1685 mlx5_devx_cmd_create_rqt(void *ctx, 1686 struct mlx5_devx_rqt_attr *rqt_attr) 1687 { 1688 uint32_t *in = NULL; 1689 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1690 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1691 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1692 void *rqt_ctx; 1693 struct mlx5_devx_obj *rqt = NULL; 1694 int i; 1695 1696 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1697 if (!in) { 1698 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1699 rte_errno = ENOMEM; 1700 return NULL; 1701 } 1702 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1703 if (!rqt) { 1704 DRV_LOG(ERR, "Failed to allocate RQT data"); 1705 rte_errno = ENOMEM; 1706 mlx5_free(in); 1707 return NULL; 1708 } 1709 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1710 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1711 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1712 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1713 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1714 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1715 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1716 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1717 mlx5_free(in); 1718 if (!rqt->obj) { 1719 DEVX_DRV_LOG(ERR, out, "create RQT", NULL, 0); 1720 mlx5_free(rqt); 1721 return NULL; 1722 } 1723 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1724 return rqt; 1725 } 1726 1727 /** 1728 * Modify RQT using DevX API. 1729 * 1730 * @param[in] rqt 1731 * Pointer to RQT DevX object structure. 1732 * @param [in] rqt_attr 1733 * Pointer to RQT attributes structure. 1734 * 1735 * @return 1736 * 0 on success, a negative errno value otherwise and rte_errno is set. 1737 */ 1738 int 1739 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1740 struct mlx5_devx_rqt_attr *rqt_attr) 1741 { 1742 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1743 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1744 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1745 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1746 void *rqt_ctx; 1747 int i; 1748 int ret; 1749 1750 if (!in) { 1751 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1752 rte_errno = ENOMEM; 1753 return -ENOMEM; 1754 } 1755 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1756 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1757 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1758 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1759 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1760 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1761 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1762 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1763 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1764 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1765 mlx5_free(in); 1766 if (ret) { 1767 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1768 rte_errno = errno; 1769 return -rte_errno; 1770 } 1771 return ret; 1772 } 1773 1774 /** 1775 * Create SQ using DevX API. 1776 * 1777 * @param[in] ctx 1778 * Context returned from mlx5 open_device() glue function. 1779 * @param [in] sq_attr 1780 * Pointer to SQ attributes structure. 1781 * @param [in] socket 1782 * CPU socket ID for allocations. 1783 * 1784 * @return 1785 * The DevX object created, NULL otherwise and rte_errno is set. 1786 **/ 1787 struct mlx5_devx_obj * 1788 mlx5_devx_cmd_create_sq(void *ctx, 1789 struct mlx5_devx_create_sq_attr *sq_attr) 1790 { 1791 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1792 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1793 void *sq_ctx; 1794 void *wq_ctx; 1795 struct mlx5_devx_wq_attr *wq_attr; 1796 struct mlx5_devx_obj *sq = NULL; 1797 1798 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1799 if (!sq) { 1800 DRV_LOG(ERR, "Failed to allocate SQ data"); 1801 rte_errno = ENOMEM; 1802 return NULL; 1803 } 1804 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1805 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1806 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1807 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1808 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1809 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1810 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1811 sq_attr->allow_multi_pkt_send_wqe); 1812 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1813 sq_attr->min_wqe_inline_mode); 1814 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1815 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1816 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1817 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1818 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1819 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1820 MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type); 1821 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1822 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1823 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1824 sq_attr->packet_pacing_rate_limit_index); 1825 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1826 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1827 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1828 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1829 wq_attr = &sq_attr->wq_attr; 1830 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1831 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1832 out, sizeof(out)); 1833 if (!sq->obj) { 1834 DEVX_DRV_LOG(ERR, out, "create SQ", NULL, 0); 1835 mlx5_free(sq); 1836 return NULL; 1837 } 1838 sq->id = MLX5_GET(create_sq_out, out, sqn); 1839 return sq; 1840 } 1841 1842 /** 1843 * Modify SQ using DevX API. 1844 * 1845 * @param[in] sq 1846 * Pointer to SQ object structure. 1847 * @param [in] sq_attr 1848 * Pointer to SQ attributes structure. 1849 * 1850 * @return 1851 * 0 on success, a negative errno value otherwise and rte_errno is set. 1852 */ 1853 int 1854 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1855 struct mlx5_devx_modify_sq_attr *sq_attr) 1856 { 1857 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1858 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1859 void *sq_ctx; 1860 int ret; 1861 1862 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1863 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1864 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1865 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1866 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1867 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1868 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1869 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1870 out, sizeof(out)); 1871 if (ret) { 1872 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1873 rte_errno = errno; 1874 return -rte_errno; 1875 } 1876 return ret; 1877 } 1878 1879 /** 1880 * Create TIS using DevX API. 1881 * 1882 * @param[in] ctx 1883 * Context returned from mlx5 open_device() glue function. 1884 * @param [in] tis_attr 1885 * Pointer to TIS attributes structure. 1886 * 1887 * @return 1888 * The DevX object created, NULL otherwise and rte_errno is set. 1889 */ 1890 struct mlx5_devx_obj * 1891 mlx5_devx_cmd_create_tis(void *ctx, 1892 struct mlx5_devx_tis_attr *tis_attr) 1893 { 1894 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1895 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1896 struct mlx5_devx_obj *tis = NULL; 1897 void *tis_ctx; 1898 1899 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1900 if (!tis) { 1901 DRV_LOG(ERR, "Failed to allocate TIS object"); 1902 rte_errno = ENOMEM; 1903 return NULL; 1904 } 1905 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1906 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1907 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1908 tis_attr->strict_lag_tx_port_affinity); 1909 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1910 tis_attr->lag_tx_port_affinity); 1911 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1912 MLX5_SET(tisc, tis_ctx, transport_domain, 1913 tis_attr->transport_domain); 1914 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1915 out, sizeof(out)); 1916 if (!tis->obj) { 1917 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 1918 mlx5_free(tis); 1919 return NULL; 1920 } 1921 tis->id = MLX5_GET(create_tis_out, out, tisn); 1922 return tis; 1923 } 1924 1925 /** 1926 * Create transport domain using DevX API. 1927 * 1928 * @param[in] ctx 1929 * Context returned from mlx5 open_device() glue function. 1930 * @return 1931 * The DevX object created, NULL otherwise and rte_errno is set. 1932 */ 1933 struct mlx5_devx_obj * 1934 mlx5_devx_cmd_create_td(void *ctx) 1935 { 1936 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1937 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1938 struct mlx5_devx_obj *td = NULL; 1939 1940 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1941 if (!td) { 1942 DRV_LOG(ERR, "Failed to allocate TD object"); 1943 rte_errno = ENOMEM; 1944 return NULL; 1945 } 1946 MLX5_SET(alloc_transport_domain_in, in, opcode, 1947 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1948 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1949 out, sizeof(out)); 1950 if (!td->obj) { 1951 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 1952 mlx5_free(td); 1953 return NULL; 1954 } 1955 td->id = MLX5_GET(alloc_transport_domain_out, out, 1956 transport_domain); 1957 return td; 1958 } 1959 1960 /** 1961 * Dump all flows to file. 1962 * 1963 * @param[in] fdb_domain 1964 * FDB domain. 1965 * @param[in] rx_domain 1966 * RX domain. 1967 * @param[in] tx_domain 1968 * TX domain. 1969 * @param[out] file 1970 * Pointer to file stream. 1971 * 1972 * @return 1973 * 0 on success, a negative value otherwise. 1974 */ 1975 int 1976 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1977 void *rx_domain __rte_unused, 1978 void *tx_domain __rte_unused, FILE *file __rte_unused) 1979 { 1980 int ret = 0; 1981 1982 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1983 if (fdb_domain) { 1984 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1985 if (ret) 1986 return ret; 1987 } 1988 MLX5_ASSERT(rx_domain); 1989 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1990 if (ret) 1991 return ret; 1992 MLX5_ASSERT(tx_domain); 1993 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1994 #else 1995 ret = ENOTSUP; 1996 #endif 1997 return -ret; 1998 } 1999 2000 int 2001 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 2002 FILE *file __rte_unused) 2003 { 2004 int ret = 0; 2005 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 2006 if (rule_info) 2007 ret = mlx5_glue->dr_dump_rule(file, rule_info); 2008 #else 2009 ret = ENOTSUP; 2010 #endif 2011 return -ret; 2012 } 2013 2014 /* 2015 * Create CQ using DevX API. 2016 * 2017 * @param[in] ctx 2018 * Context returned from mlx5 open_device() glue function. 2019 * @param [in] attr 2020 * Pointer to CQ attributes structure. 2021 * 2022 * @return 2023 * The DevX object created, NULL otherwise and rte_errno is set. 2024 */ 2025 struct mlx5_devx_obj * 2026 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 2027 { 2028 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 2029 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 2030 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2031 sizeof(*cq_obj), 2032 0, SOCKET_ID_ANY); 2033 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 2034 2035 if (!cq_obj) { 2036 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 2037 rte_errno = ENOMEM; 2038 return NULL; 2039 } 2040 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 2041 if (attr->db_umem_valid) { 2042 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 2043 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 2044 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 2045 } else { 2046 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 2047 } 2048 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 2049 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 2050 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 2051 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 2052 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 2053 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2054 MLX5_SET(cqc, cqctx, log_page_size, 2055 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2056 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 2057 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 2058 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 2059 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 2060 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 2061 attr->mini_cqe_res_format_ext); 2062 if (attr->q_umem_valid) { 2063 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 2064 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 2065 MLX5_SET64(create_cq_in, in, cq_umem_offset, 2066 attr->q_umem_offset); 2067 } 2068 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2069 sizeof(out)); 2070 if (!cq_obj->obj) { 2071 DEVX_DRV_LOG(ERR, out, "create CQ", NULL, 0); 2072 mlx5_free(cq_obj); 2073 return NULL; 2074 } 2075 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 2076 return cq_obj; 2077 } 2078 2079 /** 2080 * Create VIRTQ using DevX API. 2081 * 2082 * @param[in] ctx 2083 * Context returned from mlx5 open_device() glue function. 2084 * @param [in] attr 2085 * Pointer to VIRTQ attributes structure. 2086 * 2087 * @return 2088 * The DevX object created, NULL otherwise and rte_errno is set. 2089 */ 2090 struct mlx5_devx_obj * 2091 mlx5_devx_cmd_create_virtq(void *ctx, 2092 struct mlx5_devx_virtq_attr *attr) 2093 { 2094 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2095 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2096 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2097 sizeof(*virtq_obj), 2098 0, SOCKET_ID_ANY); 2099 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2100 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2101 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2102 2103 if (!virtq_obj) { 2104 DRV_LOG(ERR, "Failed to allocate virtq data."); 2105 rte_errno = ENOMEM; 2106 return NULL; 2107 } 2108 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2109 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2110 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2111 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2112 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2113 attr->hw_available_index); 2114 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 2115 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2116 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2117 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2118 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2119 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2120 attr->virtio_version_1_0); 2121 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2122 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2123 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2124 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2125 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 2126 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2127 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 2128 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2129 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 2130 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 2131 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 2132 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 2133 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 2134 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 2135 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 2136 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 2137 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 2138 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 2139 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 2140 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 2141 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 2142 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 2143 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 2144 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2145 sizeof(out)); 2146 if (!virtq_obj->obj) { 2147 DEVX_DRV_LOG(ERR, out, "create VIRTQ", NULL, 0); 2148 mlx5_free(virtq_obj); 2149 return NULL; 2150 } 2151 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2152 return virtq_obj; 2153 } 2154 2155 /** 2156 * Modify VIRTQ using DevX API. 2157 * 2158 * @param[in] virtq_obj 2159 * Pointer to virtq object structure. 2160 * @param [in] attr 2161 * Pointer to modify virtq attributes structure. 2162 * 2163 * @return 2164 * 0 on success, a negative errno value otherwise and rte_errno is set. 2165 */ 2166 int 2167 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 2168 struct mlx5_devx_virtq_attr *attr) 2169 { 2170 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2171 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2172 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2173 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2174 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2175 int ret; 2176 2177 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2178 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 2179 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2180 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2181 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2182 MLX5_SET64(virtio_net_q, virtq, modify_field_select, 2183 attr->mod_fields_bitmap); 2184 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2185 if (!attr->mod_fields_bitmap) { 2186 DRV_LOG(ERR, "Failed to modify VIRTQ for no type set."); 2187 rte_errno = EINVAL; 2188 return -rte_errno; 2189 } 2190 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE) 2191 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 2192 if (attr->mod_fields_bitmap & 2193 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) { 2194 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 2195 attr->dirty_bitmap_mkey); 2196 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 2197 attr->dirty_bitmap_addr); 2198 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 2199 attr->dirty_bitmap_size); 2200 } 2201 if (attr->mod_fields_bitmap & 2202 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE) 2203 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 2204 attr->dirty_bitmap_dump_enable); 2205 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) { 2206 MLX5_SET(virtio_q, virtctx, queue_period_mode, 2207 attr->hw_latency_mode); 2208 MLX5_SET(virtio_q, virtctx, queue_period_us, 2209 attr->hw_max_latency_us); 2210 MLX5_SET(virtio_q, virtctx, queue_max_count, 2211 attr->hw_max_pending_comp); 2212 } 2213 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) { 2214 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2215 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2216 MLX5_SET64(virtio_q, virtctx, available_addr, 2217 attr->available_addr); 2218 } 2219 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX) 2220 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2221 attr->hw_available_index); 2222 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX) 2223 MLX5_SET16(virtio_net_q, virtq, hw_used_index, 2224 attr->hw_used_index); 2225 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE) 2226 MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type); 2227 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0) 2228 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2229 attr->virtio_version_1_0); 2230 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY) 2231 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2232 if (attr->mod_fields_bitmap & 2233 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) { 2234 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2235 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2236 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2237 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2238 } 2239 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) { 2240 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2241 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2242 } 2243 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 2244 out, sizeof(out)); 2245 if (ret) { 2246 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2247 rte_errno = errno; 2248 return -rte_errno; 2249 } 2250 return ret; 2251 } 2252 2253 /** 2254 * Query VIRTQ using DevX API. 2255 * 2256 * @param[in] virtq_obj 2257 * Pointer to virtq object structure. 2258 * @param [in/out] attr 2259 * Pointer to virtq attributes structure. 2260 * 2261 * @return 2262 * 0 on success, a negative errno value otherwise and rte_errno is set. 2263 */ 2264 int 2265 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 2266 struct mlx5_devx_virtq_attr *attr) 2267 { 2268 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2269 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 2270 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 2271 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 2272 int ret; 2273 2274 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2275 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2276 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2277 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2278 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2279 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2280 out, sizeof(out)); 2281 if (ret) { 2282 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2283 rte_errno = errno; 2284 return -errno; 2285 } 2286 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2287 hw_available_index); 2288 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2289 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2290 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2291 virtio_q_context.error_type); 2292 return ret; 2293 } 2294 2295 /** 2296 * Create QP using DevX API. 2297 * 2298 * @param[in] ctx 2299 * Context returned from mlx5 open_device() glue function. 2300 * @param [in] attr 2301 * Pointer to QP attributes structure. 2302 * 2303 * @return 2304 * The DevX object created, NULL otherwise and rte_errno is set. 2305 */ 2306 struct mlx5_devx_obj * 2307 mlx5_devx_cmd_create_qp(void *ctx, 2308 struct mlx5_devx_qp_attr *attr) 2309 { 2310 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2311 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2312 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2313 sizeof(*qp_obj), 2314 0, SOCKET_ID_ANY); 2315 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2316 2317 if (!qp_obj) { 2318 DRV_LOG(ERR, "Failed to allocate QP data."); 2319 rte_errno = ENOMEM; 2320 return NULL; 2321 } 2322 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2323 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2324 MLX5_SET(qpc, qpc, pd, attr->pd); 2325 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2326 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2327 if (attr->uar_index) { 2328 if (attr->mmo) { 2329 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2330 in, qpc_extension_and_pas_list); 2331 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2332 qpc_ext_and_pas_list, qpc_data_extension); 2333 2334 MLX5_SET(create_qp_in, in, qpc_ext, 1); 2335 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2336 } 2337 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2338 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2339 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2340 MLX5_SET(qpc, qpc, log_page_size, 2341 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2342 if (attr->num_of_send_wqbbs) { 2343 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs)); 2344 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2345 MLX5_SET(qpc, qpc, log_sq_size, 2346 rte_log2_u32(attr->num_of_send_wqbbs)); 2347 } else { 2348 MLX5_SET(qpc, qpc, no_sq, 1); 2349 } 2350 if (attr->num_of_receive_wqes) { 2351 MLX5_ASSERT(RTE_IS_POWER_OF_2( 2352 attr->num_of_receive_wqes)); 2353 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2354 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2355 MLX5_LOG_RQ_STRIDE_SHIFT); 2356 MLX5_SET(qpc, qpc, log_rq_size, 2357 rte_log2_u32(attr->num_of_receive_wqes)); 2358 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2359 } else { 2360 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2361 } 2362 if (attr->dbr_umem_valid) { 2363 MLX5_SET(qpc, qpc, dbr_umem_valid, 2364 attr->dbr_umem_valid); 2365 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2366 } 2367 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2368 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2369 attr->wq_umem_offset); 2370 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2371 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2372 } else { 2373 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2374 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2375 MLX5_SET(qpc, qpc, no_sq, 1); 2376 } 2377 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2378 sizeof(out)); 2379 if (!qp_obj->obj) { 2380 DEVX_DRV_LOG(ERR, out, "create QP", NULL, 0); 2381 mlx5_free(qp_obj); 2382 return NULL; 2383 } 2384 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2385 return qp_obj; 2386 } 2387 2388 /** 2389 * Modify QP using DevX API. 2390 * Currently supports only force loop-back QP. 2391 * 2392 * @param[in] qp 2393 * Pointer to QP object structure. 2394 * @param [in] qp_st_mod_op 2395 * The QP state modification operation. 2396 * @param [in] remote_qp_id 2397 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2398 * 2399 * @return 2400 * 0 on success, a negative errno value otherwise and rte_errno is set. 2401 */ 2402 int 2403 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2404 uint32_t remote_qp_id) 2405 { 2406 union { 2407 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2408 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2409 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2410 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)]; 2411 } in; 2412 union { 2413 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2414 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2415 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2416 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)]; 2417 } out; 2418 void *qpc; 2419 int ret; 2420 unsigned int inlen; 2421 unsigned int outlen; 2422 2423 memset(&in, 0, sizeof(in)); 2424 memset(&out, 0, sizeof(out)); 2425 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2426 switch (qp_st_mod_op) { 2427 case MLX5_CMD_OP_RST2INIT_QP: 2428 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2429 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2430 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2431 MLX5_SET(qpc, qpc, rre, 1); 2432 MLX5_SET(qpc, qpc, rwe, 1); 2433 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2434 inlen = sizeof(in.rst2init); 2435 outlen = sizeof(out.rst2init); 2436 break; 2437 case MLX5_CMD_OP_INIT2RTR_QP: 2438 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2439 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2440 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2441 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2442 MLX5_SET(qpc, qpc, mtu, 1); 2443 MLX5_SET(qpc, qpc, log_msg_max, 30); 2444 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2445 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2446 inlen = sizeof(in.init2rtr); 2447 outlen = sizeof(out.init2rtr); 2448 break; 2449 case MLX5_CMD_OP_RTR2RTS_QP: 2450 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2451 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2452 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16); 2453 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2454 MLX5_SET(qpc, qpc, retry_count, 7); 2455 MLX5_SET(qpc, qpc, rnr_retry, 7); 2456 inlen = sizeof(in.rtr2rts); 2457 outlen = sizeof(out.rtr2rts); 2458 break; 2459 case MLX5_CMD_OP_QP_2RST: 2460 MLX5_SET(2rst_qp_in, &in, qpn, qp->id); 2461 inlen = sizeof(in.qp2rst); 2462 outlen = sizeof(out.qp2rst); 2463 break; 2464 default: 2465 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2466 qp_st_mod_op); 2467 rte_errno = EINVAL; 2468 return -rte_errno; 2469 } 2470 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2471 if (ret) { 2472 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2473 rte_errno = errno; 2474 return -rte_errno; 2475 } 2476 return ret; 2477 } 2478 2479 struct mlx5_devx_obj * 2480 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2481 { 2482 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2483 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2484 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2485 sizeof(*couners_obj), 0, 2486 SOCKET_ID_ANY); 2487 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2488 2489 if (!couners_obj) { 2490 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2491 rte_errno = ENOMEM; 2492 return NULL; 2493 } 2494 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2495 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2496 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2497 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2498 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2499 sizeof(out)); 2500 if (!couners_obj->obj) { 2501 DEVX_DRV_LOG(ERR, out, "create virtio queue counters Obj", NULL, 2502 0); 2503 mlx5_free(couners_obj); 2504 return NULL; 2505 } 2506 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2507 return couners_obj; 2508 } 2509 2510 int 2511 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2512 struct mlx5_devx_virtio_q_couners_attr *attr) 2513 { 2514 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2515 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2516 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2517 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2518 virtio_q_counters); 2519 int ret; 2520 2521 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2522 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2523 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2524 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2525 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2526 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2527 sizeof(out)); 2528 if (ret) { 2529 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2530 rte_errno = errno; 2531 return -errno; 2532 } 2533 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2534 received_desc); 2535 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2536 completed_desc); 2537 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2538 error_cqes); 2539 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2540 bad_desc_errors); 2541 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2542 exceed_max_chain); 2543 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2544 invalid_buffer); 2545 return ret; 2546 } 2547 2548 /** 2549 * Create general object of type FLOW_HIT_ASO using DevX API. 2550 * 2551 * @param[in] ctx 2552 * Context returned from mlx5 open_device() glue function. 2553 * @param [in] pd 2554 * PD value to associate the FLOW_HIT_ASO object with. 2555 * 2556 * @return 2557 * The DevX object created, NULL otherwise and rte_errno is set. 2558 */ 2559 struct mlx5_devx_obj * 2560 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2561 { 2562 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2563 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2564 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2565 void *ptr = NULL; 2566 2567 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2568 0, SOCKET_ID_ANY); 2569 if (!flow_hit_aso_obj) { 2570 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2571 rte_errno = ENOMEM; 2572 return NULL; 2573 } 2574 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2575 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2576 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2577 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2578 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2579 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2580 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2581 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2582 out, sizeof(out)); 2583 if (!flow_hit_aso_obj->obj) { 2584 DEVX_DRV_LOG(ERR, out, "create FLOW_HIT_ASO", NULL, 0); 2585 mlx5_free(flow_hit_aso_obj); 2586 return NULL; 2587 } 2588 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2589 return flow_hit_aso_obj; 2590 } 2591 2592 /* 2593 * Create PD using DevX API. 2594 * 2595 * @param[in] ctx 2596 * Context returned from mlx5 open_device() glue function. 2597 * 2598 * @return 2599 * The DevX object created, NULL otherwise and rte_errno is set. 2600 */ 2601 struct mlx5_devx_obj * 2602 mlx5_devx_cmd_alloc_pd(void *ctx) 2603 { 2604 struct mlx5_devx_obj *ppd = 2605 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2606 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2607 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2608 2609 if (!ppd) { 2610 DRV_LOG(ERR, "Failed to allocate PD data."); 2611 rte_errno = ENOMEM; 2612 return NULL; 2613 } 2614 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2615 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2616 out, sizeof(out)); 2617 if (!ppd->obj) { 2618 mlx5_free(ppd); 2619 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2620 rte_errno = errno; 2621 return NULL; 2622 } 2623 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2624 return ppd; 2625 } 2626 2627 /** 2628 * Create general object of type FLOW_METER_ASO using DevX API. 2629 * 2630 * @param[in] ctx 2631 * Context returned from mlx5 open_device() glue function. 2632 * @param [in] pd 2633 * PD value to associate the FLOW_METER_ASO object with. 2634 * @param [in] log_obj_size 2635 * log_obj_size define to allocate number of 2 * meters 2636 * in one FLOW_METER_ASO object. 2637 * 2638 * @return 2639 * The DevX object created, NULL otherwise and rte_errno is set. 2640 */ 2641 struct mlx5_devx_obj * 2642 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2643 uint32_t log_obj_size) 2644 { 2645 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2646 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2647 struct mlx5_devx_obj *flow_meter_aso_obj; 2648 void *ptr; 2649 2650 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2651 sizeof(*flow_meter_aso_obj), 2652 0, SOCKET_ID_ANY); 2653 if (!flow_meter_aso_obj) { 2654 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2655 rte_errno = ENOMEM; 2656 return NULL; 2657 } 2658 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2659 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2660 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2661 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2662 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2663 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2664 log_obj_size); 2665 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2666 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2667 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2668 ctx, in, sizeof(in), 2669 out, sizeof(out)); 2670 if (!flow_meter_aso_obj->obj) { 2671 DEVX_DRV_LOG(ERR, out, "create FLOW_METTER_ASO", NULL, 0); 2672 mlx5_free(flow_meter_aso_obj); 2673 return NULL; 2674 } 2675 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2676 out, obj_id); 2677 return flow_meter_aso_obj; 2678 } 2679 2680 /* 2681 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2682 * 2683 * @param[in] ctx 2684 * Context returned from mlx5 open_device() glue function. 2685 * @param [in] pd 2686 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2687 * @param [in] log_obj_size 2688 * log_obj_size to allocate its power of 2 * objects 2689 * in one CONN_TRACK_OFFLOAD bulk allocation. 2690 * 2691 * @return 2692 * The DevX object created, NULL otherwise and rte_errno is set. 2693 */ 2694 struct mlx5_devx_obj * 2695 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2696 uint32_t log_obj_size) 2697 { 2698 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2699 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2700 struct mlx5_devx_obj *ct_aso_obj; 2701 void *ptr; 2702 2703 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2704 0, SOCKET_ID_ANY); 2705 if (!ct_aso_obj) { 2706 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2707 rte_errno = ENOMEM; 2708 return NULL; 2709 } 2710 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2711 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2712 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2713 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2714 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2715 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2716 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2717 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2718 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2719 out, sizeof(out)); 2720 if (!ct_aso_obj->obj) { 2721 DEVX_DRV_LOG(ERR, out, "create CONN_TRACK_OFFLOAD", NULL, 0); 2722 mlx5_free(ct_aso_obj); 2723 return NULL; 2724 } 2725 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2726 return ct_aso_obj; 2727 } 2728 2729 /** 2730 * Create general object of type GENEVE TLV option using DevX API. 2731 * 2732 * @param[in] ctx 2733 * Context returned from mlx5 open_device() glue function. 2734 * @param [in] class 2735 * TLV option variable value of class 2736 * @param [in] type 2737 * TLV option variable value of type 2738 * @param [in] len 2739 * TLV option variable value of len 2740 * 2741 * @return 2742 * The DevX object created, NULL otherwise and rte_errno is set. 2743 */ 2744 struct mlx5_devx_obj * 2745 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2746 uint16_t class, uint8_t type, uint8_t len) 2747 { 2748 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2749 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2750 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2751 sizeof(*geneve_tlv_opt_obj), 2752 0, SOCKET_ID_ANY); 2753 2754 if (!geneve_tlv_opt_obj) { 2755 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2756 rte_errno = ENOMEM; 2757 return NULL; 2758 } 2759 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2760 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2761 geneve_tlv_opt); 2762 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2763 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2764 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2765 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2766 MLX5_SET(geneve_tlv_option, opt, option_class, 2767 rte_be_to_cpu_16(class)); 2768 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2769 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2770 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2771 sizeof(in), out, sizeof(out)); 2772 if (!geneve_tlv_opt_obj->obj) { 2773 DEVX_DRV_LOG(ERR, out, "create GENEVE TLV", NULL, 0); 2774 mlx5_free(geneve_tlv_opt_obj); 2775 return NULL; 2776 } 2777 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2778 return geneve_tlv_opt_obj; 2779 } 2780 2781 int 2782 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2783 { 2784 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2785 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2786 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2787 int rc; 2788 void *rq_ctx; 2789 2790 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2791 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2792 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2793 if (rc) { 2794 rte_errno = errno; 2795 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2796 "rc = %d, errno = %d.", rc, errno); 2797 return -rc; 2798 }; 2799 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2800 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2801 return 0; 2802 #else 2803 (void)wq; 2804 (void)counter_set_id; 2805 return -ENOTSUP; 2806 #endif 2807 } 2808 2809 /* 2810 * Allocate queue counters via devx interface. 2811 * 2812 * @param[in] ctx 2813 * Context returned from mlx5 open_device() glue function. 2814 * 2815 * @return 2816 * Pointer to counter object on success, a NULL value otherwise and 2817 * rte_errno is set. 2818 */ 2819 struct mlx5_devx_obj * 2820 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2821 { 2822 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2823 SOCKET_ID_ANY); 2824 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2825 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2826 2827 if (!dcs) { 2828 rte_errno = ENOMEM; 2829 return NULL; 2830 } 2831 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2832 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2833 sizeof(out)); 2834 if (!dcs->obj) { 2835 DEVX_DRV_LOG(DEBUG, out, "create q counter set", NULL, 0); 2836 mlx5_free(dcs); 2837 return NULL; 2838 } 2839 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2840 return dcs; 2841 } 2842 2843 /** 2844 * Query queue counters values. 2845 * 2846 * @param[in] dcs 2847 * devx object of the queue counter set. 2848 * @param[in] clear 2849 * Whether hardware should clear the counters after the query or not. 2850 * @param[out] out_of_buffers 2851 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2852 * 2853 * @return 2854 * 0 on success, a negative value otherwise. 2855 */ 2856 int 2857 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2858 uint32_t *out_of_buffers) 2859 { 2860 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2861 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2862 int rc; 2863 2864 MLX5_SET(query_q_counter_in, in, opcode, 2865 MLX5_CMD_OP_QUERY_Q_COUNTER); 2866 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2867 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2868 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2869 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2870 sizeof(out)); 2871 if (rc) { 2872 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2873 rte_errno = rc; 2874 return -rc; 2875 } 2876 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2877 return 0; 2878 } 2879 2880 /** 2881 * Create general object of type DEK using DevX API. 2882 * 2883 * @param[in] ctx 2884 * Context returned from mlx5 open_device() glue function. 2885 * @param [in] attr 2886 * Pointer to DEK attributes structure. 2887 * 2888 * @return 2889 * The DevX object created, NULL otherwise and rte_errno is set. 2890 */ 2891 struct mlx5_devx_obj * 2892 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2893 { 2894 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2895 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2896 struct mlx5_devx_obj *dek_obj = NULL; 2897 void *ptr = NULL, *key_addr = NULL; 2898 2899 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2900 0, SOCKET_ID_ANY); 2901 if (dek_obj == NULL) { 2902 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2903 rte_errno = ENOMEM; 2904 return NULL; 2905 } 2906 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2907 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2908 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2909 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2910 MLX5_GENERAL_OBJ_TYPE_DEK); 2911 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2912 MLX5_SET(dek, ptr, key_size, attr->key_size); 2913 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2914 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2915 MLX5_SET(dek, ptr, pd, attr->pd); 2916 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2917 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2918 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2919 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2920 out, sizeof(out)); 2921 if (dek_obj->obj == NULL) { 2922 DEVX_DRV_LOG(ERR, out, "create DEK", NULL, 0); 2923 mlx5_free(dek_obj); 2924 return NULL; 2925 } 2926 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2927 return dek_obj; 2928 } 2929 2930 /** 2931 * Create general object of type IMPORT_KEK using DevX API. 2932 * 2933 * @param[in] ctx 2934 * Context returned from mlx5 open_device() glue function. 2935 * @param [in] attr 2936 * Pointer to IMPORT_KEK attributes structure. 2937 * 2938 * @return 2939 * The DevX object created, NULL otherwise and rte_errno is set. 2940 */ 2941 struct mlx5_devx_obj * 2942 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 2943 struct mlx5_devx_import_kek_attr *attr) 2944 { 2945 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 2946 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2947 struct mlx5_devx_obj *import_kek_obj = NULL; 2948 void *ptr = NULL, *key_addr = NULL; 2949 2950 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 2951 0, SOCKET_ID_ANY); 2952 if (import_kek_obj == NULL) { 2953 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 2954 rte_errno = ENOMEM; 2955 return NULL; 2956 } 2957 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 2958 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2959 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2960 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2961 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 2962 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 2963 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 2964 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 2965 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2966 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2967 out, sizeof(out)); 2968 if (import_kek_obj->obj == NULL) { 2969 DEVX_DRV_LOG(ERR, out, "create IMPORT_KEK", NULL, 0); 2970 mlx5_free(import_kek_obj); 2971 return NULL; 2972 } 2973 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2974 return import_kek_obj; 2975 } 2976 2977 /** 2978 * Create general object of type CREDENTIAL using DevX API. 2979 * 2980 * @param[in] ctx 2981 * Context returned from mlx5 open_device() glue function. 2982 * @param [in] attr 2983 * Pointer to CREDENTIAL attributes structure. 2984 * 2985 * @return 2986 * The DevX object created, NULL otherwise and rte_errno is set. 2987 */ 2988 struct mlx5_devx_obj * 2989 mlx5_devx_cmd_create_credential_obj(void *ctx, 2990 struct mlx5_devx_credential_attr *attr) 2991 { 2992 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 2993 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2994 struct mlx5_devx_obj *credential_obj = NULL; 2995 void *ptr = NULL, *credential_addr = NULL; 2996 2997 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 2998 0, SOCKET_ID_ANY); 2999 if (credential_obj == NULL) { 3000 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 3001 rte_errno = ENOMEM; 3002 return NULL; 3003 } 3004 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 3005 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3006 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3007 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3008 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 3009 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 3010 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 3011 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 3012 memcpy(credential_addr, (void *)(attr->credential), 3013 MLX5_CRYPTO_CREDENTIAL_SIZE); 3014 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3015 out, sizeof(out)); 3016 if (credential_obj->obj == NULL) { 3017 DEVX_DRV_LOG(ERR, out, "create CREDENTIAL", NULL, 0); 3018 mlx5_free(credential_obj); 3019 return NULL; 3020 } 3021 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3022 return credential_obj; 3023 } 3024 3025 /** 3026 * Create general object of type CRYPTO_LOGIN using DevX API. 3027 * 3028 * @param[in] ctx 3029 * Context returned from mlx5 open_device() glue function. 3030 * @param [in] attr 3031 * Pointer to CRYPTO_LOGIN attributes structure. 3032 * 3033 * @return 3034 * The DevX object created, NULL otherwise and rte_errno is set. 3035 */ 3036 struct mlx5_devx_obj * 3037 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 3038 struct mlx5_devx_crypto_login_attr *attr) 3039 { 3040 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 3041 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3042 struct mlx5_devx_obj *crypto_login_obj = NULL; 3043 void *ptr = NULL, *credential_addr = NULL; 3044 3045 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 3046 0, SOCKET_ID_ANY); 3047 if (crypto_login_obj == NULL) { 3048 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 3049 rte_errno = ENOMEM; 3050 return NULL; 3051 } 3052 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 3053 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3054 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3055 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3056 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 3057 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 3058 MLX5_SET(crypto_login, ptr, credential_pointer, 3059 attr->credential_pointer); 3060 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 3061 attr->session_import_kek_ptr); 3062 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 3063 memcpy(credential_addr, (void *)(attr->credential), 3064 MLX5_CRYPTO_CREDENTIAL_SIZE); 3065 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3066 out, sizeof(out)); 3067 if (crypto_login_obj->obj == NULL) { 3068 DEVX_DRV_LOG(ERR, out, "create CRYPTO_LOGIN", NULL, 0); 3069 mlx5_free(crypto_login_obj); 3070 return NULL; 3071 } 3072 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3073 return crypto_login_obj; 3074 } 3075 3076 /** 3077 * Query LAG context. 3078 * 3079 * @param[in] ctx 3080 * Pointer to ibv_context, returned from mlx5dv_open_device. 3081 * @param[out] lag_ctx 3082 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 3083 * 3084 * @return 3085 * 0 on success, a negative value otherwise. 3086 */ 3087 int 3088 mlx5_devx_cmd_query_lag(void *ctx, 3089 struct mlx5_devx_lag_context *lag_ctx) 3090 { 3091 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 3092 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 3093 void *lctx; 3094 int rc; 3095 3096 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 3097 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 3098 if (rc) 3099 goto error; 3100 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 3101 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 3102 fdb_selection_mode); 3103 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 3104 port_select_mode); 3105 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 3106 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 3107 tx_remap_affinity_2); 3108 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 3109 tx_remap_affinity_1); 3110 return 0; 3111 error: 3112 rc = (rc > 0) ? -rc : rc; 3113 return rc; 3114 } 3115