1 // SPDX-License-Identifier: BSD-3-Clause 2 /* Copyright 2018 Mellanox Technologies, Ltd */ 3 4 #include <unistd.h> 5 6 #include <rte_errno.h> 7 #include <rte_malloc.h> 8 #include <rte_eal_paging.h> 9 10 #include "mlx5_prm.h" 11 #include "mlx5_devx_cmds.h" 12 #include "mlx5_common_utils.h" 13 #include "mlx5_malloc.h" 14 15 16 /** 17 * Perform read access to the registers. Reads data from register 18 * and writes ones to the specified buffer. 19 * 20 * @param[in] ctx 21 * Context returned from mlx5 open_device() glue function. 22 * @param[in] reg_id 23 * Register identifier according to the PRM. 24 * @param[in] arg 25 * Register access auxiliary parameter according to the PRM. 26 * @param[out] data 27 * Pointer to the buffer to store read data. 28 * @param[in] dw_cnt 29 * Buffer size in double words. 30 * 31 * @return 32 * 0 on success, a negative value otherwise. 33 */ 34 int 35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 36 uint32_t *data, uint32_t dw_cnt) 37 { 38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 41 int status, rc; 42 43 MLX5_ASSERT(data && dw_cnt); 44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 46 DRV_LOG(ERR, "Not enough buffer for register read data"); 47 return -1; 48 } 49 MLX5_SET(access_register_in, in, opcode, 50 MLX5_CMD_OP_ACCESS_REGISTER_USER); 51 MLX5_SET(access_register_in, in, op_mod, 52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 53 MLX5_SET(access_register_in, in, register_id, reg_id); 54 MLX5_SET(access_register_in, in, argument, arg); 55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 56 MLX5_ST_SZ_DW(access_register_out) * 57 sizeof(uint32_t) + dw_cnt); 58 if (rc) 59 goto error; 60 status = MLX5_GET(access_register_out, out, status); 61 if (status) { 62 int syndrome = MLX5_GET(access_register_out, out, syndrome); 63 64 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, " 65 "status %x, syndrome = %x", 66 reg_id, status, syndrome); 67 return -1; 68 } 69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 70 dw_cnt * sizeof(uint32_t)); 71 return 0; 72 error: 73 rc = (rc > 0) ? -rc : rc; 74 return rc; 75 } 76 77 /** 78 * Allocate flow counters via devx interface. 79 * 80 * @param[in] ctx 81 * Context returned from mlx5 open_device() glue function. 82 * @param dcs 83 * Pointer to counters properties structure to be filled by the routine. 84 * @param bulk_n_128 85 * Bulk counter numbers in 128 counters units. 86 * 87 * @return 88 * Pointer to counter object on success, a negative value otherwise and 89 * rte_errno is set. 90 */ 91 struct mlx5_devx_obj * 92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 93 { 94 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 95 0, SOCKET_ID_ANY); 96 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 97 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 98 99 if (!dcs) { 100 rte_errno = ENOMEM; 101 return NULL; 102 } 103 MLX5_SET(alloc_flow_counter_in, in, opcode, 104 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 105 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 106 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 107 sizeof(in), out, sizeof(out)); 108 if (!dcs->obj) { 109 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 110 rte_errno = errno; 111 mlx5_free(dcs); 112 return NULL; 113 } 114 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 115 return dcs; 116 } 117 118 /** 119 * Query flow counters values. 120 * 121 * @param[in] dcs 122 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 123 * @param[in] clear 124 * Whether hardware should clear the counters after the query or not. 125 * @param[in] n_counters 126 * 0 in case of 1 counter to read, otherwise the counter number to read. 127 * @param pkts 128 * The number of packets that matched the flow. 129 * @param bytes 130 * The number of bytes that matched the flow. 131 * @param mkey 132 * The mkey key for batch query. 133 * @param addr 134 * The address in the mkey range for batch query. 135 * @param cmd_comp 136 * The completion object for asynchronous batch query. 137 * @param async_id 138 * The ID to be returned in the asynchronous batch query response. 139 * 140 * @return 141 * 0 on success, a negative value otherwise. 142 */ 143 int 144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 145 int clear, uint32_t n_counters, 146 uint64_t *pkts, uint64_t *bytes, 147 uint32_t mkey, void *addr, 148 void *cmd_comp, 149 uint64_t async_id) 150 { 151 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 152 MLX5_ST_SZ_BYTES(traffic_counter); 153 uint32_t out[out_len]; 154 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 155 void *stats; 156 int rc; 157 158 MLX5_SET(query_flow_counter_in, in, opcode, 159 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 160 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 161 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 162 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 163 164 if (n_counters) { 165 MLX5_SET(query_flow_counter_in, in, num_of_counters, 166 n_counters); 167 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 168 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 169 MLX5_SET64(query_flow_counter_in, in, address, 170 (uint64_t)(uintptr_t)addr); 171 } 172 if (!cmd_comp) 173 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 174 out_len); 175 else 176 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 177 out_len, async_id, 178 cmd_comp); 179 if (rc) { 180 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 181 rte_errno = rc; 182 return -rc; 183 } 184 if (!n_counters) { 185 stats = MLX5_ADDR_OF(query_flow_counter_out, 186 out, flow_statistics); 187 *pkts = MLX5_GET64(traffic_counter, stats, packets); 188 *bytes = MLX5_GET64(traffic_counter, stats, octets); 189 } 190 return 0; 191 } 192 193 /** 194 * Create a new mkey. 195 * 196 * @param[in] ctx 197 * Context returned from mlx5 open_device() glue function. 198 * @param[in] attr 199 * Attributes of the requested mkey. 200 * 201 * @return 202 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 203 * is set. 204 */ 205 struct mlx5_devx_obj * 206 mlx5_devx_cmd_mkey_create(void *ctx, 207 struct mlx5_devx_mkey_attr *attr) 208 { 209 struct mlx5_klm *klm_array = attr->klm_array; 210 int klm_num = attr->klm_num; 211 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 212 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 213 uint32_t in[in_size_dw]; 214 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 215 void *mkc; 216 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 217 0, SOCKET_ID_ANY); 218 size_t pgsize; 219 uint32_t translation_size; 220 221 if (!mkey) { 222 rte_errno = ENOMEM; 223 return NULL; 224 } 225 memset(in, 0, in_size_dw * 4); 226 pgsize = rte_mem_page_size(); 227 if (pgsize == (size_t)-1) { 228 mlx5_free(mkey); 229 DRV_LOG(ERR, "Failed to get page size"); 230 rte_errno = ENOMEM; 231 return NULL; 232 } 233 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 234 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 235 if (klm_num > 0) { 236 int i; 237 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 238 klm_pas_mtt); 239 translation_size = RTE_ALIGN(klm_num, 4); 240 for (i = 0; i < klm_num; i++) { 241 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 242 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 243 MLX5_SET64(klm, klm, address, klm_array[i].address); 244 klm += MLX5_ST_SZ_BYTES(klm); 245 } 246 for (; i < (int)translation_size; i++) { 247 MLX5_SET(klm, klm, mkey, 0x0); 248 MLX5_SET64(klm, klm, address, 0x0); 249 klm += MLX5_ST_SZ_BYTES(klm); 250 } 251 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 252 MLX5_MKC_ACCESS_MODE_KLM_FBS : 253 MLX5_MKC_ACCESS_MODE_KLM); 254 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 255 } else { 256 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 257 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 258 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 259 } 260 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 261 translation_size); 262 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 263 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 264 MLX5_SET(mkc, mkc, lw, 0x1); 265 MLX5_SET(mkc, mkc, lr, 0x1); 266 MLX5_SET(mkc, mkc, qpn, 0xffffff); 267 MLX5_SET(mkc, mkc, pd, attr->pd); 268 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 269 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 270 MLX5_SET(mkc, mkc, relaxed_ordering_write, 271 attr->relaxed_ordering_write); 272 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 273 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 274 MLX5_SET64(mkc, mkc, len, attr->size); 275 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 276 sizeof(out)); 277 if (!mkey->obj) { 278 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d\n", 279 klm_num ? "an in" : "a ", errno); 280 rte_errno = errno; 281 mlx5_free(mkey); 282 return NULL; 283 } 284 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 285 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 286 return mkey; 287 } 288 289 /** 290 * Get status of devx command response. 291 * Mainly used for asynchronous commands. 292 * 293 * @param[in] out 294 * The out response buffer. 295 * 296 * @return 297 * 0 on success, non-zero value otherwise. 298 */ 299 int 300 mlx5_devx_get_out_command_status(void *out) 301 { 302 int status; 303 304 if (!out) 305 return -EINVAL; 306 status = MLX5_GET(query_flow_counter_out, out, status); 307 if (status) { 308 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 309 310 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 311 syndrome); 312 } 313 return status; 314 } 315 316 /** 317 * Destroy any object allocated by a Devx API. 318 * 319 * @param[in] obj 320 * Pointer to a general object. 321 * 322 * @return 323 * 0 on success, a negative value otherwise. 324 */ 325 int 326 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 327 { 328 int ret; 329 330 if (!obj) 331 return 0; 332 ret = mlx5_glue->devx_obj_destroy(obj->obj); 333 mlx5_free(obj); 334 return ret; 335 } 336 337 /** 338 * Query NIC vport context. 339 * Fills minimal inline attribute. 340 * 341 * @param[in] ctx 342 * ibv contexts returned from mlx5dv_open_device. 343 * @param[in] vport 344 * vport index 345 * @param[out] attr 346 * Attributes device values. 347 * 348 * @return 349 * 0 on success, a negative value otherwise. 350 */ 351 static int 352 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 353 unsigned int vport, 354 struct mlx5_hca_attr *attr) 355 { 356 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 357 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 358 void *vctx; 359 int status, syndrome, rc; 360 361 /* Query NIC vport context to determine inline mode. */ 362 MLX5_SET(query_nic_vport_context_in, in, opcode, 363 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 364 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 365 if (vport) 366 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 367 rc = mlx5_glue->devx_general_cmd(ctx, 368 in, sizeof(in), 369 out, sizeof(out)); 370 if (rc) 371 goto error; 372 status = MLX5_GET(query_nic_vport_context_out, out, status); 373 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 374 if (status) { 375 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 376 "status %x, syndrome = %x", status, syndrome); 377 return -1; 378 } 379 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 380 nic_vport_context); 381 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 382 min_wqe_inline_mode); 383 return 0; 384 error: 385 rc = (rc > 0) ? -rc : rc; 386 return rc; 387 } 388 389 /** 390 * Query NIC vDPA attributes. 391 * 392 * @param[in] ctx 393 * Context returned from mlx5 open_device() glue function. 394 * @param[out] vdpa_attr 395 * vDPA Attributes structure to fill. 396 */ 397 static void 398 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 399 struct mlx5_hca_vdpa_attr *vdpa_attr) 400 { 401 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 402 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 403 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 404 int status, syndrome, rc; 405 406 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 407 MLX5_SET(query_hca_cap_in, in, op_mod, 408 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 409 MLX5_HCA_CAP_OPMOD_GET_CUR); 410 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 411 status = MLX5_GET(query_hca_cap_out, out, status); 412 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 413 if (rc || status) { 414 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities," 415 " status %x, syndrome = %x", status, syndrome); 416 vdpa_attr->valid = 0; 417 } else { 418 vdpa_attr->valid = 1; 419 vdpa_attr->desc_tunnel_offload_type = 420 MLX5_GET(virtio_emulation_cap, hcattr, 421 desc_tunnel_offload_type); 422 vdpa_attr->eth_frame_offload_type = 423 MLX5_GET(virtio_emulation_cap, hcattr, 424 eth_frame_offload_type); 425 vdpa_attr->virtio_version_1_0 = 426 MLX5_GET(virtio_emulation_cap, hcattr, 427 virtio_version_1_0); 428 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 429 tso_ipv4); 430 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 431 tso_ipv6); 432 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 433 tx_csum); 434 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 435 rx_csum); 436 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 437 event_mode); 438 vdpa_attr->virtio_queue_type = 439 MLX5_GET(virtio_emulation_cap, hcattr, 440 virtio_queue_type); 441 vdpa_attr->log_doorbell_stride = 442 MLX5_GET(virtio_emulation_cap, hcattr, 443 log_doorbell_stride); 444 vdpa_attr->log_doorbell_bar_size = 445 MLX5_GET(virtio_emulation_cap, hcattr, 446 log_doorbell_bar_size); 447 vdpa_attr->doorbell_bar_offset = 448 MLX5_GET64(virtio_emulation_cap, hcattr, 449 doorbell_bar_offset); 450 vdpa_attr->max_num_virtio_queues = 451 MLX5_GET(virtio_emulation_cap, hcattr, 452 max_num_virtio_queues); 453 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 454 umem_1_buffer_param_a); 455 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 456 umem_1_buffer_param_b); 457 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 458 umem_2_buffer_param_a); 459 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 460 umem_2_buffer_param_b); 461 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 462 umem_3_buffer_param_a); 463 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 464 umem_3_buffer_param_b); 465 } 466 } 467 468 int 469 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 470 uint32_t ids[], uint32_t num) 471 { 472 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 473 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 474 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 475 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 476 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 477 int ret; 478 uint32_t idx = 0; 479 uint32_t i; 480 481 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 482 rte_errno = EINVAL; 483 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 484 return -rte_errno; 485 } 486 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 487 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 488 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 489 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 490 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 491 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 492 out, sizeof(out)); 493 if (ret) { 494 rte_errno = ret; 495 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 496 (void *)flex_obj); 497 return -rte_errno; 498 } 499 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 500 void *s_off = (void *)((char *)sample + i * 501 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 502 uint32_t en; 503 504 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 505 flow_match_sample_en); 506 if (!en) 507 continue; 508 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 509 flow_match_sample_field_id); 510 } 511 if (num != idx) { 512 rte_errno = EINVAL; 513 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 514 return -rte_errno; 515 } 516 return ret; 517 } 518 519 520 struct mlx5_devx_obj * 521 mlx5_devx_cmd_create_flex_parser(void *ctx, 522 struct mlx5_devx_graph_node_attr *data) 523 { 524 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 525 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 526 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 527 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 528 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 529 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 530 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 531 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 532 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 533 uint32_t i; 534 535 if (!parse_flex_obj) { 536 DRV_LOG(ERR, "Failed to allocate flex parser data."); 537 rte_errno = ENOMEM; 538 return NULL; 539 } 540 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 541 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 542 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 543 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 544 MLX5_SET(parse_graph_flex, flex, header_length_mode, 545 data->header_length_mode); 546 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 547 data->header_length_base_value); 548 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 549 data->header_length_field_offset); 550 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 551 data->header_length_field_shift); 552 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 553 data->header_length_field_mask); 554 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 555 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 556 void *s_off = (void *)((char *)sample + i * 557 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 558 559 if (!s->flow_match_sample_en) 560 continue; 561 MLX5_SET(parse_graph_flow_match_sample, s_off, 562 flow_match_sample_en, !!s->flow_match_sample_en); 563 MLX5_SET(parse_graph_flow_match_sample, s_off, 564 flow_match_sample_field_offset, 565 s->flow_match_sample_field_offset); 566 MLX5_SET(parse_graph_flow_match_sample, s_off, 567 flow_match_sample_offset_mode, 568 s->flow_match_sample_offset_mode); 569 MLX5_SET(parse_graph_flow_match_sample, s_off, 570 flow_match_sample_field_offset_mask, 571 s->flow_match_sample_field_offset_mask); 572 MLX5_SET(parse_graph_flow_match_sample, s_off, 573 flow_match_sample_field_offset_shift, 574 s->flow_match_sample_field_offset_shift); 575 MLX5_SET(parse_graph_flow_match_sample, s_off, 576 flow_match_sample_field_base_offset, 577 s->flow_match_sample_field_base_offset); 578 MLX5_SET(parse_graph_flow_match_sample, s_off, 579 flow_match_sample_tunnel_mode, 580 s->flow_match_sample_tunnel_mode); 581 } 582 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 583 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 584 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 585 void *in_off = (void *)((char *)in_arc + i * 586 MLX5_ST_SZ_BYTES(parse_graph_arc)); 587 void *out_off = (void *)((char *)out_arc + i * 588 MLX5_ST_SZ_BYTES(parse_graph_arc)); 589 590 if (ia->arc_parse_graph_node != 0) { 591 MLX5_SET(parse_graph_arc, in_off, 592 compare_condition_value, 593 ia->compare_condition_value); 594 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 595 ia->start_inner_tunnel); 596 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 597 ia->arc_parse_graph_node); 598 MLX5_SET(parse_graph_arc, in_off, 599 parse_graph_node_handle, 600 ia->parse_graph_node_handle); 601 } 602 if (oa->arc_parse_graph_node != 0) { 603 MLX5_SET(parse_graph_arc, out_off, 604 compare_condition_value, 605 oa->compare_condition_value); 606 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 607 oa->start_inner_tunnel); 608 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 609 oa->arc_parse_graph_node); 610 MLX5_SET(parse_graph_arc, out_off, 611 parse_graph_node_handle, 612 oa->parse_graph_node_handle); 613 } 614 } 615 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 616 out, sizeof(out)); 617 if (!parse_flex_obj->obj) { 618 rte_errno = errno; 619 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 620 "by using DevX."); 621 mlx5_free(parse_flex_obj); 622 return NULL; 623 } 624 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 625 return parse_flex_obj; 626 } 627 628 /** 629 * Query HCA attributes. 630 * Using those attributes we can check on run time if the device 631 * is having the required capabilities. 632 * 633 * @param[in] ctx 634 * Context returned from mlx5 open_device() glue function. 635 * @param[out] attr 636 * Attributes device values. 637 * 638 * @return 639 * 0 on success, a negative value otherwise. 640 */ 641 int 642 mlx5_devx_cmd_query_hca_attr(void *ctx, 643 struct mlx5_hca_attr *attr) 644 { 645 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 646 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 647 void *hcattr; 648 int status, syndrome, rc, i; 649 650 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 651 MLX5_SET(query_hca_cap_in, in, op_mod, 652 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 653 MLX5_HCA_CAP_OPMOD_GET_CUR); 654 655 rc = mlx5_glue->devx_general_cmd(ctx, 656 in, sizeof(in), out, sizeof(out)); 657 if (rc) 658 goto error; 659 status = MLX5_GET(query_hca_cap_out, out, status); 660 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 661 if (status) { 662 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 663 "status %x, syndrome = %x", status, syndrome); 664 return -1; 665 } 666 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 667 attr->flow_counter_bulk_alloc_bitmap = 668 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 669 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 670 flow_counters_dump); 671 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 672 log_max_rqt_size); 673 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 674 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 675 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 676 log_max_hairpin_queues); 677 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 678 log_max_hairpin_wq_data_sz); 679 attr->log_max_hairpin_num_packets = MLX5_GET 680 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 681 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 682 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 683 relaxed_ordering_write); 684 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 685 relaxed_ordering_read); 686 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 687 access_register_user); 688 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 689 eth_net_offloads); 690 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 691 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 692 flex_parser_protocols); 693 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 694 max_geneve_tlv_options); 695 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 696 max_geneve_tlv_option_data_len); 697 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 698 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 699 general_obj_types) & 700 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 701 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 702 general_obj_types) & 703 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 704 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 705 general_obj_types) & 706 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 707 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 708 wqe_index_ignore_cap); 709 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 710 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 711 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 712 log_max_static_sq_wq); 713 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 714 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 715 device_frequency_khz); 716 attr->scatter_fcs_w_decap_disable = 717 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 718 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp); 719 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 720 regexp_num_of_engines); 721 attr->flow_hit_aso = !!(MLX5_GET64(cmd_hca_cap, hcattr, 722 general_obj_types) & 723 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 724 attr->geneve_tlv_opt = !!(MLX5_GET64(cmd_hca_cap, hcattr, 725 general_obj_types) & 726 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 727 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 728 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 729 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 730 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 731 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 732 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 733 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 734 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 735 if (attr->qos.sup) { 736 MLX5_SET(query_hca_cap_in, in, op_mod, 737 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 738 MLX5_HCA_CAP_OPMOD_GET_CUR); 739 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 740 out, sizeof(out)); 741 if (rc) 742 goto error; 743 if (status) { 744 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities," 745 " status %x, syndrome = %x", status, syndrome); 746 return -1; 747 } 748 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 749 attr->qos.srtcm_sup = 750 MLX5_GET(qos_cap, hcattr, flow_meter_srtcm); 751 attr->qos.log_max_flow_meter = 752 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 753 attr->qos.flow_meter_reg_c_ids = 754 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 755 attr->qos.flow_meter_reg_share = 756 MLX5_GET(qos_cap, hcattr, flow_meter_reg_share); 757 attr->qos.packet_pacing = 758 MLX5_GET(qos_cap, hcattr, packet_pacing); 759 attr->qos.wqe_rate_pp = 760 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 761 } 762 if (attr->vdpa.valid) 763 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 764 if (!attr->eth_net_offloads) 765 return 0; 766 767 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 768 memset(in, 0, sizeof(in)); 769 memset(out, 0, sizeof(out)); 770 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 771 MLX5_SET(query_hca_cap_in, in, op_mod, 772 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 773 MLX5_HCA_CAP_OPMOD_GET_CUR); 774 775 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 776 if (rc) 777 goto error; 778 status = MLX5_GET(query_hca_cap_out, out, status); 779 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 780 if (status) { 781 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 782 "status %x, syndrome = %x", status, syndrome); 783 attr->log_max_ft_sampler_num = 0; 784 return -1; 785 } 786 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 787 attr->log_max_ft_sampler_num = 788 MLX5_GET(flow_table_nic_cap, 789 hcattr, flow_table_properties.log_max_ft_sampler_num); 790 791 /* Query HCA offloads for Ethernet protocol. */ 792 memset(in, 0, sizeof(in)); 793 memset(out, 0, sizeof(out)); 794 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 795 MLX5_SET(query_hca_cap_in, in, op_mod, 796 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 797 MLX5_HCA_CAP_OPMOD_GET_CUR); 798 799 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 800 if (rc) { 801 attr->eth_net_offloads = 0; 802 goto error; 803 } 804 status = MLX5_GET(query_hca_cap_out, out, status); 805 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 806 if (status) { 807 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 808 "status %x, syndrome = %x", status, syndrome); 809 attr->eth_net_offloads = 0; 810 return -1; 811 } 812 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 813 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 814 hcattr, wqe_vlan_insert); 815 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 816 lro_cap); 817 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 818 hcattr, tunnel_lro_gre); 819 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 820 hcattr, tunnel_lro_vxlan); 821 attr->lro_max_msg_sz_mode = MLX5_GET 822 (per_protocol_networking_offload_caps, 823 hcattr, lro_max_msg_sz_mode); 824 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 825 attr->lro_timer_supported_periods[i] = 826 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 827 lro_timer_supported_periods[i]); 828 } 829 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 830 hcattr, lro_min_mss_size); 831 attr->tunnel_stateless_geneve_rx = 832 MLX5_GET(per_protocol_networking_offload_caps, 833 hcattr, tunnel_stateless_geneve_rx); 834 attr->geneve_max_opt_len = 835 MLX5_GET(per_protocol_networking_offload_caps, 836 hcattr, max_geneve_opt_len); 837 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 838 hcattr, wqe_inline_mode); 839 attr->tunnel_stateless_gtp = MLX5_GET 840 (per_protocol_networking_offload_caps, 841 hcattr, tunnel_stateless_gtp); 842 attr->rss_ind_tbl_cap = MLX5_GET 843 (per_protocol_networking_offload_caps, 844 hcattr, rss_ind_tbl_cap); 845 if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) 846 return 0; 847 if (attr->eth_virt) { 848 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 849 if (rc) { 850 attr->eth_virt = 0; 851 goto error; 852 } 853 } 854 return 0; 855 error: 856 rc = (rc > 0) ? -rc : rc; 857 return rc; 858 } 859 860 /** 861 * Query TIS transport domain from QP verbs object using DevX API. 862 * 863 * @param[in] qp 864 * Pointer to verbs QP returned by ibv_create_qp . 865 * @param[in] tis_num 866 * TIS number of TIS to query. 867 * @param[out] tis_td 868 * Pointer to TIS transport domain variable, to be set by the routine. 869 * 870 * @return 871 * 0 on success, a negative value otherwise. 872 */ 873 int 874 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 875 uint32_t *tis_td) 876 { 877 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 878 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 879 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 880 int rc; 881 void *tis_ctx; 882 883 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 884 MLX5_SET(query_tis_in, in, tisn, tis_num); 885 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 886 if (rc) { 887 DRV_LOG(ERR, "Failed to query QP using DevX"); 888 return -rc; 889 }; 890 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 891 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 892 return 0; 893 #else 894 (void)qp; 895 (void)tis_num; 896 (void)tis_td; 897 return -ENOTSUP; 898 #endif 899 } 900 901 /** 902 * Fill WQ data for DevX API command. 903 * Utility function for use when creating DevX objects containing a WQ. 904 * 905 * @param[in] wq_ctx 906 * Pointer to WQ context to fill with data. 907 * @param [in] wq_attr 908 * Pointer to WQ attributes structure to fill in WQ context. 909 */ 910 static void 911 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 912 { 913 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 914 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 915 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 916 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 917 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 918 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 919 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 920 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 921 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 922 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 923 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 924 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 925 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 926 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 927 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 928 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 929 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 930 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 931 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 932 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 933 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 934 wq_attr->log_hairpin_num_packets); 935 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 936 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 937 wq_attr->single_wqe_log_num_of_strides); 938 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 939 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 940 wq_attr->single_stride_log_num_of_bytes); 941 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 942 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 943 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 944 } 945 946 /** 947 * Create RQ using DevX API. 948 * 949 * @param[in] ctx 950 * Context returned from mlx5 open_device() glue function. 951 * @param [in] rq_attr 952 * Pointer to create RQ attributes structure. 953 * @param [in] socket 954 * CPU socket ID for allocations. 955 * 956 * @return 957 * The DevX object created, NULL otherwise and rte_errno is set. 958 */ 959 struct mlx5_devx_obj * 960 mlx5_devx_cmd_create_rq(void *ctx, 961 struct mlx5_devx_create_rq_attr *rq_attr, 962 int socket) 963 { 964 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 965 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 966 void *rq_ctx, *wq_ctx; 967 struct mlx5_devx_wq_attr *wq_attr; 968 struct mlx5_devx_obj *rq = NULL; 969 970 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 971 if (!rq) { 972 DRV_LOG(ERR, "Failed to allocate RQ data"); 973 rte_errno = ENOMEM; 974 return NULL; 975 } 976 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 977 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 978 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 979 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 980 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 981 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 982 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 983 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 984 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 985 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 986 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 987 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 988 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 989 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 990 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 991 wq_attr = &rq_attr->wq_attr; 992 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 993 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 994 out, sizeof(out)); 995 if (!rq->obj) { 996 DRV_LOG(ERR, "Failed to create RQ using DevX"); 997 rte_errno = errno; 998 mlx5_free(rq); 999 return NULL; 1000 } 1001 rq->id = MLX5_GET(create_rq_out, out, rqn); 1002 return rq; 1003 } 1004 1005 /** 1006 * Modify RQ using DevX API. 1007 * 1008 * @param[in] rq 1009 * Pointer to RQ object structure. 1010 * @param [in] rq_attr 1011 * Pointer to modify RQ attributes structure. 1012 * 1013 * @return 1014 * 0 on success, a negative errno value otherwise and rte_errno is set. 1015 */ 1016 int 1017 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1018 struct mlx5_devx_modify_rq_attr *rq_attr) 1019 { 1020 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1021 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1022 void *rq_ctx, *wq_ctx; 1023 int ret; 1024 1025 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1026 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1027 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1028 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1029 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1030 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1031 if (rq_attr->modify_bitmask & 1032 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1033 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1034 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1035 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1036 if (rq_attr->modify_bitmask & 1037 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1038 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1039 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1040 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1041 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1042 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1043 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1044 } 1045 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1046 out, sizeof(out)); 1047 if (ret) { 1048 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1049 rte_errno = errno; 1050 return -errno; 1051 } 1052 return ret; 1053 } 1054 1055 /** 1056 * Create TIR using DevX API. 1057 * 1058 * @param[in] ctx 1059 * Context returned from mlx5 open_device() glue function. 1060 * @param [in] tir_attr 1061 * Pointer to TIR attributes structure. 1062 * 1063 * @return 1064 * The DevX object created, NULL otherwise and rte_errno is set. 1065 */ 1066 struct mlx5_devx_obj * 1067 mlx5_devx_cmd_create_tir(void *ctx, 1068 struct mlx5_devx_tir_attr *tir_attr) 1069 { 1070 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1071 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1072 void *tir_ctx, *outer, *inner, *rss_key; 1073 struct mlx5_devx_obj *tir = NULL; 1074 1075 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1076 if (!tir) { 1077 DRV_LOG(ERR, "Failed to allocate TIR data"); 1078 rte_errno = ENOMEM; 1079 return NULL; 1080 } 1081 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1082 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1083 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1084 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1085 tir_attr->lro_timeout_period_usecs); 1086 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1087 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1088 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1089 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1090 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1091 tir_attr->tunneled_offload_en); 1092 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1093 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1094 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1095 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1096 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1097 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1098 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1099 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1100 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1101 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1102 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1103 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1104 tir_attr->rx_hash_field_selector_outer.selected_fields); 1105 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1106 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1107 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1108 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1109 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1110 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1111 tir_attr->rx_hash_field_selector_inner.selected_fields); 1112 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1113 out, sizeof(out)); 1114 if (!tir->obj) { 1115 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1116 rte_errno = errno; 1117 mlx5_free(tir); 1118 return NULL; 1119 } 1120 tir->id = MLX5_GET(create_tir_out, out, tirn); 1121 return tir; 1122 } 1123 1124 /** 1125 * Modify TIR using DevX API. 1126 * 1127 * @param[in] tir 1128 * Pointer to TIR DevX object structure. 1129 * @param [in] modify_tir_attr 1130 * Pointer to TIR modification attributes structure. 1131 * 1132 * @return 1133 * 0 on success, a negative errno value otherwise and rte_errno is set. 1134 */ 1135 int 1136 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1137 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1138 { 1139 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1140 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1141 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1142 void *tir_ctx; 1143 int ret; 1144 1145 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1146 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1147 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1148 modify_tir_attr->modify_bitmask); 1149 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1150 if (modify_tir_attr->modify_bitmask & 1151 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1152 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1153 tir_attr->lro_timeout_period_usecs); 1154 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1155 tir_attr->lro_enable_mask); 1156 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1157 tir_attr->lro_max_msg_sz); 1158 } 1159 if (modify_tir_attr->modify_bitmask & 1160 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1161 MLX5_SET(tirc, tir_ctx, indirect_table, 1162 tir_attr->indirect_table); 1163 if (modify_tir_attr->modify_bitmask & 1164 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1165 int i; 1166 void *outer, *inner; 1167 1168 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1169 tir_attr->rx_hash_symmetric); 1170 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1171 for (i = 0; i < 10; i++) { 1172 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1173 tir_attr->rx_hash_toeplitz_key[i]); 1174 } 1175 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1176 rx_hash_field_selector_outer); 1177 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1178 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1179 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1180 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1181 MLX5_SET 1182 (rx_hash_field_select, outer, selected_fields, 1183 tir_attr->rx_hash_field_selector_outer.selected_fields); 1184 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1185 rx_hash_field_selector_inner); 1186 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1187 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1188 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1189 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1190 MLX5_SET 1191 (rx_hash_field_select, inner, selected_fields, 1192 tir_attr->rx_hash_field_selector_inner.selected_fields); 1193 } 1194 if (modify_tir_attr->modify_bitmask & 1195 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1196 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1197 } 1198 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1199 out, sizeof(out)); 1200 if (ret) { 1201 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1202 rte_errno = errno; 1203 return -errno; 1204 } 1205 return ret; 1206 } 1207 1208 /** 1209 * Create RQT using DevX API. 1210 * 1211 * @param[in] ctx 1212 * Context returned from mlx5 open_device() glue function. 1213 * @param [in] rqt_attr 1214 * Pointer to RQT attributes structure. 1215 * 1216 * @return 1217 * The DevX object created, NULL otherwise and rte_errno is set. 1218 */ 1219 struct mlx5_devx_obj * 1220 mlx5_devx_cmd_create_rqt(void *ctx, 1221 struct mlx5_devx_rqt_attr *rqt_attr) 1222 { 1223 uint32_t *in = NULL; 1224 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1225 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1226 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1227 void *rqt_ctx; 1228 struct mlx5_devx_obj *rqt = NULL; 1229 int i; 1230 1231 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1232 if (!in) { 1233 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1234 rte_errno = ENOMEM; 1235 return NULL; 1236 } 1237 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1238 if (!rqt) { 1239 DRV_LOG(ERR, "Failed to allocate RQT data"); 1240 rte_errno = ENOMEM; 1241 mlx5_free(in); 1242 return NULL; 1243 } 1244 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1245 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1246 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1247 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1248 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1249 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1250 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1251 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1252 mlx5_free(in); 1253 if (!rqt->obj) { 1254 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1255 rte_errno = errno; 1256 mlx5_free(rqt); 1257 return NULL; 1258 } 1259 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1260 return rqt; 1261 } 1262 1263 /** 1264 * Modify RQT using DevX API. 1265 * 1266 * @param[in] rqt 1267 * Pointer to RQT DevX object structure. 1268 * @param [in] rqt_attr 1269 * Pointer to RQT attributes structure. 1270 * 1271 * @return 1272 * 0 on success, a negative errno value otherwise and rte_errno is set. 1273 */ 1274 int 1275 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1276 struct mlx5_devx_rqt_attr *rqt_attr) 1277 { 1278 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1279 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1280 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1281 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1282 void *rqt_ctx; 1283 int i; 1284 int ret; 1285 1286 if (!in) { 1287 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1288 rte_errno = ENOMEM; 1289 return -ENOMEM; 1290 } 1291 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1292 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1293 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1294 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1295 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1296 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1297 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1298 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1299 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1300 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1301 mlx5_free(in); 1302 if (ret) { 1303 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1304 rte_errno = errno; 1305 return -rte_errno; 1306 } 1307 return ret; 1308 } 1309 1310 /** 1311 * Create SQ using DevX API. 1312 * 1313 * @param[in] ctx 1314 * Context returned from mlx5 open_device() glue function. 1315 * @param [in] sq_attr 1316 * Pointer to SQ attributes structure. 1317 * @param [in] socket 1318 * CPU socket ID for allocations. 1319 * 1320 * @return 1321 * The DevX object created, NULL otherwise and rte_errno is set. 1322 **/ 1323 struct mlx5_devx_obj * 1324 mlx5_devx_cmd_create_sq(void *ctx, 1325 struct mlx5_devx_create_sq_attr *sq_attr) 1326 { 1327 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1328 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1329 void *sq_ctx; 1330 void *wq_ctx; 1331 struct mlx5_devx_wq_attr *wq_attr; 1332 struct mlx5_devx_obj *sq = NULL; 1333 1334 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1335 if (!sq) { 1336 DRV_LOG(ERR, "Failed to allocate SQ data"); 1337 rte_errno = ENOMEM; 1338 return NULL; 1339 } 1340 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1341 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1342 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1343 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1344 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1345 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1346 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1347 sq_attr->allow_multi_pkt_send_wqe); 1348 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1349 sq_attr->min_wqe_inline_mode); 1350 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1351 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1352 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1353 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1354 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1355 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1356 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1357 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1358 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1359 sq_attr->packet_pacing_rate_limit_index); 1360 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1361 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1362 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1363 wq_attr = &sq_attr->wq_attr; 1364 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1365 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1366 out, sizeof(out)); 1367 if (!sq->obj) { 1368 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1369 rte_errno = errno; 1370 mlx5_free(sq); 1371 return NULL; 1372 } 1373 sq->id = MLX5_GET(create_sq_out, out, sqn); 1374 return sq; 1375 } 1376 1377 /** 1378 * Modify SQ using DevX API. 1379 * 1380 * @param[in] sq 1381 * Pointer to SQ object structure. 1382 * @param [in] sq_attr 1383 * Pointer to SQ attributes structure. 1384 * 1385 * @return 1386 * 0 on success, a negative errno value otherwise and rte_errno is set. 1387 */ 1388 int 1389 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1390 struct mlx5_devx_modify_sq_attr *sq_attr) 1391 { 1392 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1393 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1394 void *sq_ctx; 1395 int ret; 1396 1397 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1398 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1399 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1400 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1401 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1402 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1403 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1404 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1405 out, sizeof(out)); 1406 if (ret) { 1407 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1408 rte_errno = errno; 1409 return -rte_errno; 1410 } 1411 return ret; 1412 } 1413 1414 /** 1415 * Create TIS using DevX API. 1416 * 1417 * @param[in] ctx 1418 * Context returned from mlx5 open_device() glue function. 1419 * @param [in] tis_attr 1420 * Pointer to TIS attributes structure. 1421 * 1422 * @return 1423 * The DevX object created, NULL otherwise and rte_errno is set. 1424 */ 1425 struct mlx5_devx_obj * 1426 mlx5_devx_cmd_create_tis(void *ctx, 1427 struct mlx5_devx_tis_attr *tis_attr) 1428 { 1429 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1430 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1431 struct mlx5_devx_obj *tis = NULL; 1432 void *tis_ctx; 1433 1434 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1435 if (!tis) { 1436 DRV_LOG(ERR, "Failed to allocate TIS object"); 1437 rte_errno = ENOMEM; 1438 return NULL; 1439 } 1440 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1441 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1442 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1443 tis_attr->strict_lag_tx_port_affinity); 1444 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1445 tis_attr->lag_tx_port_affinity); 1446 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1447 MLX5_SET(tisc, tis_ctx, transport_domain, 1448 tis_attr->transport_domain); 1449 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1450 out, sizeof(out)); 1451 if (!tis->obj) { 1452 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1453 rte_errno = errno; 1454 mlx5_free(tis); 1455 return NULL; 1456 } 1457 tis->id = MLX5_GET(create_tis_out, out, tisn); 1458 return tis; 1459 } 1460 1461 /** 1462 * Create transport domain using DevX API. 1463 * 1464 * @param[in] ctx 1465 * Context returned from mlx5 open_device() glue function. 1466 * @return 1467 * The DevX object created, NULL otherwise and rte_errno is set. 1468 */ 1469 struct mlx5_devx_obj * 1470 mlx5_devx_cmd_create_td(void *ctx) 1471 { 1472 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1473 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1474 struct mlx5_devx_obj *td = NULL; 1475 1476 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1477 if (!td) { 1478 DRV_LOG(ERR, "Failed to allocate TD object"); 1479 rte_errno = ENOMEM; 1480 return NULL; 1481 } 1482 MLX5_SET(alloc_transport_domain_in, in, opcode, 1483 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1484 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1485 out, sizeof(out)); 1486 if (!td->obj) { 1487 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1488 rte_errno = errno; 1489 mlx5_free(td); 1490 return NULL; 1491 } 1492 td->id = MLX5_GET(alloc_transport_domain_out, out, 1493 transport_domain); 1494 return td; 1495 } 1496 1497 /** 1498 * Dump all flows to file. 1499 * 1500 * @param[in] fdb_domain 1501 * FDB domain. 1502 * @param[in] rx_domain 1503 * RX domain. 1504 * @param[in] tx_domain 1505 * TX domain. 1506 * @param[out] file 1507 * Pointer to file stream. 1508 * 1509 * @return 1510 * 0 on success, a nagative value otherwise. 1511 */ 1512 int 1513 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1514 void *rx_domain __rte_unused, 1515 void *tx_domain __rte_unused, FILE *file __rte_unused) 1516 { 1517 int ret = 0; 1518 1519 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1520 if (fdb_domain) { 1521 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1522 if (ret) 1523 return ret; 1524 } 1525 MLX5_ASSERT(rx_domain); 1526 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1527 if (ret) 1528 return ret; 1529 MLX5_ASSERT(tx_domain); 1530 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1531 #else 1532 ret = ENOTSUP; 1533 #endif 1534 return -ret; 1535 } 1536 1537 /* 1538 * Create CQ using DevX API. 1539 * 1540 * @param[in] ctx 1541 * Context returned from mlx5 open_device() glue function. 1542 * @param [in] attr 1543 * Pointer to CQ attributes structure. 1544 * 1545 * @return 1546 * The DevX object created, NULL otherwise and rte_errno is set. 1547 */ 1548 struct mlx5_devx_obj * 1549 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1550 { 1551 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1552 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1553 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1554 sizeof(*cq_obj), 1555 0, SOCKET_ID_ANY); 1556 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1557 1558 if (!cq_obj) { 1559 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1560 rte_errno = ENOMEM; 1561 return NULL; 1562 } 1563 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1564 if (attr->db_umem_valid) { 1565 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1566 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1567 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1568 } else { 1569 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1570 } 1571 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1572 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1573 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1574 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1575 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1576 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1577 MLX5_SET(cqc, cqctx, log_page_size, 1578 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1579 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1580 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1581 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1582 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1583 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1584 attr->mini_cqe_res_format_ext); 1585 if (attr->q_umem_valid) { 1586 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1587 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1588 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1589 attr->q_umem_offset); 1590 } 1591 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1592 sizeof(out)); 1593 if (!cq_obj->obj) { 1594 rte_errno = errno; 1595 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1596 mlx5_free(cq_obj); 1597 return NULL; 1598 } 1599 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1600 return cq_obj; 1601 } 1602 1603 /** 1604 * Create VIRTQ using DevX API. 1605 * 1606 * @param[in] ctx 1607 * Context returned from mlx5 open_device() glue function. 1608 * @param [in] attr 1609 * Pointer to VIRTQ attributes structure. 1610 * 1611 * @return 1612 * The DevX object created, NULL otherwise and rte_errno is set. 1613 */ 1614 struct mlx5_devx_obj * 1615 mlx5_devx_cmd_create_virtq(void *ctx, 1616 struct mlx5_devx_virtq_attr *attr) 1617 { 1618 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1619 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1620 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1621 sizeof(*virtq_obj), 1622 0, SOCKET_ID_ANY); 1623 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1624 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1625 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1626 1627 if (!virtq_obj) { 1628 DRV_LOG(ERR, "Failed to allocate virtq data."); 1629 rte_errno = ENOMEM; 1630 return NULL; 1631 } 1632 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1633 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1634 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1635 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1636 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1637 attr->hw_available_index); 1638 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1639 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1640 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1641 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1642 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1643 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1644 attr->virtio_version_1_0); 1645 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1646 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1647 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1648 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1649 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1650 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1651 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1652 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1653 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1654 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 1655 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 1656 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 1657 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 1658 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 1659 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 1660 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 1661 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 1662 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 1663 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 1664 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 1665 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 1666 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 1667 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 1668 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1669 sizeof(out)); 1670 if (!virtq_obj->obj) { 1671 rte_errno = errno; 1672 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 1673 mlx5_free(virtq_obj); 1674 return NULL; 1675 } 1676 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1677 return virtq_obj; 1678 } 1679 1680 /** 1681 * Modify VIRTQ using DevX API. 1682 * 1683 * @param[in] virtq_obj 1684 * Pointer to virtq object structure. 1685 * @param [in] attr 1686 * Pointer to modify virtq attributes structure. 1687 * 1688 * @return 1689 * 0 on success, a negative errno value otherwise and rte_errno is set. 1690 */ 1691 int 1692 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 1693 struct mlx5_devx_virtq_attr *attr) 1694 { 1695 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1696 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1697 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1698 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1699 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1700 int ret; 1701 1702 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1703 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 1704 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1705 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1706 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1707 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 1708 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1709 switch (attr->type) { 1710 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 1711 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 1712 break; 1713 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 1714 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 1715 attr->dirty_bitmap_mkey); 1716 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 1717 attr->dirty_bitmap_addr); 1718 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 1719 attr->dirty_bitmap_size); 1720 break; 1721 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 1722 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 1723 attr->dirty_bitmap_dump_enable); 1724 break; 1725 default: 1726 rte_errno = EINVAL; 1727 return -rte_errno; 1728 } 1729 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 1730 out, sizeof(out)); 1731 if (ret) { 1732 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1733 rte_errno = errno; 1734 return -rte_errno; 1735 } 1736 return ret; 1737 } 1738 1739 /** 1740 * Query VIRTQ using DevX API. 1741 * 1742 * @param[in] virtq_obj 1743 * Pointer to virtq object structure. 1744 * @param [in/out] attr 1745 * Pointer to virtq attributes structure. 1746 * 1747 * @return 1748 * 0 on success, a negative errno value otherwise and rte_errno is set. 1749 */ 1750 int 1751 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 1752 struct mlx5_devx_virtq_attr *attr) 1753 { 1754 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1755 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 1756 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 1757 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 1758 int ret; 1759 1760 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1761 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1762 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1763 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1764 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1765 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 1766 out, sizeof(out)); 1767 if (ret) { 1768 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1769 rte_errno = errno; 1770 return -errno; 1771 } 1772 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 1773 hw_available_index); 1774 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 1775 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 1776 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 1777 virtio_q_context.error_type); 1778 return ret; 1779 } 1780 1781 /** 1782 * Create QP using DevX API. 1783 * 1784 * @param[in] ctx 1785 * Context returned from mlx5 open_device() glue function. 1786 * @param [in] attr 1787 * Pointer to QP attributes structure. 1788 * 1789 * @return 1790 * The DevX object created, NULL otherwise and rte_errno is set. 1791 */ 1792 struct mlx5_devx_obj * 1793 mlx5_devx_cmd_create_qp(void *ctx, 1794 struct mlx5_devx_qp_attr *attr) 1795 { 1796 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 1797 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 1798 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 1799 sizeof(*qp_obj), 1800 0, SOCKET_ID_ANY); 1801 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1802 1803 if (!qp_obj) { 1804 DRV_LOG(ERR, "Failed to allocate QP data."); 1805 rte_errno = ENOMEM; 1806 return NULL; 1807 } 1808 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 1809 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 1810 MLX5_SET(qpc, qpc, pd, attr->pd); 1811 if (attr->uar_index) { 1812 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1813 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 1814 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1815 MLX5_SET(qpc, qpc, log_page_size, 1816 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1817 if (attr->sq_size) { 1818 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); 1819 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 1820 MLX5_SET(qpc, qpc, log_sq_size, 1821 rte_log2_u32(attr->sq_size)); 1822 } else { 1823 MLX5_SET(qpc, qpc, no_sq, 1); 1824 } 1825 if (attr->rq_size) { 1826 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); 1827 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 1828 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 1829 MLX5_LOG_RQ_STRIDE_SHIFT); 1830 MLX5_SET(qpc, qpc, log_rq_size, 1831 rte_log2_u32(attr->rq_size)); 1832 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 1833 } else { 1834 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1835 } 1836 if (attr->dbr_umem_valid) { 1837 MLX5_SET(qpc, qpc, dbr_umem_valid, 1838 attr->dbr_umem_valid); 1839 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 1840 } 1841 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 1842 MLX5_SET64(create_qp_in, in, wq_umem_offset, 1843 attr->wq_umem_offset); 1844 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 1845 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 1846 } else { 1847 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 1848 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1849 MLX5_SET(qpc, qpc, no_sq, 1); 1850 } 1851 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1852 sizeof(out)); 1853 if (!qp_obj->obj) { 1854 rte_errno = errno; 1855 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 1856 mlx5_free(qp_obj); 1857 return NULL; 1858 } 1859 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 1860 return qp_obj; 1861 } 1862 1863 /** 1864 * Modify QP using DevX API. 1865 * Currently supports only force loop-back QP. 1866 * 1867 * @param[in] qp 1868 * Pointer to QP object structure. 1869 * @param [in] qp_st_mod_op 1870 * The QP state modification operation. 1871 * @param [in] remote_qp_id 1872 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 1873 * 1874 * @return 1875 * 0 on success, a negative errno value otherwise and rte_errno is set. 1876 */ 1877 int 1878 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 1879 uint32_t remote_qp_id) 1880 { 1881 union { 1882 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 1883 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 1884 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 1885 } in; 1886 union { 1887 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 1888 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 1889 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 1890 } out; 1891 void *qpc; 1892 int ret; 1893 unsigned int inlen; 1894 unsigned int outlen; 1895 1896 memset(&in, 0, sizeof(in)); 1897 memset(&out, 0, sizeof(out)); 1898 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 1899 switch (qp_st_mod_op) { 1900 case MLX5_CMD_OP_RST2INIT_QP: 1901 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 1902 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 1903 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1904 MLX5_SET(qpc, qpc, rre, 1); 1905 MLX5_SET(qpc, qpc, rwe, 1); 1906 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1907 inlen = sizeof(in.rst2init); 1908 outlen = sizeof(out.rst2init); 1909 break; 1910 case MLX5_CMD_OP_INIT2RTR_QP: 1911 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 1912 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 1913 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 1914 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1915 MLX5_SET(qpc, qpc, mtu, 1); 1916 MLX5_SET(qpc, qpc, log_msg_max, 30); 1917 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 1918 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 1919 inlen = sizeof(in.init2rtr); 1920 outlen = sizeof(out.init2rtr); 1921 break; 1922 case MLX5_CMD_OP_RTR2RTS_QP: 1923 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 1924 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 1925 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 1926 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 1927 MLX5_SET(qpc, qpc, retry_count, 7); 1928 MLX5_SET(qpc, qpc, rnr_retry, 7); 1929 inlen = sizeof(in.rtr2rts); 1930 outlen = sizeof(out.rtr2rts); 1931 break; 1932 default: 1933 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 1934 qp_st_mod_op); 1935 rte_errno = EINVAL; 1936 return -rte_errno; 1937 } 1938 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 1939 if (ret) { 1940 DRV_LOG(ERR, "Failed to modify QP using DevX."); 1941 rte_errno = errno; 1942 return -rte_errno; 1943 } 1944 return ret; 1945 } 1946 1947 struct mlx5_devx_obj * 1948 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 1949 { 1950 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 1951 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1952 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 1953 sizeof(*couners_obj), 0, 1954 SOCKET_ID_ANY); 1955 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 1956 1957 if (!couners_obj) { 1958 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 1959 rte_errno = ENOMEM; 1960 return NULL; 1961 } 1962 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1963 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1964 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1965 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 1966 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1967 sizeof(out)); 1968 if (!couners_obj->obj) { 1969 rte_errno = errno; 1970 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 1971 " DevX."); 1972 mlx5_free(couners_obj); 1973 return NULL; 1974 } 1975 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1976 return couners_obj; 1977 } 1978 1979 int 1980 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 1981 struct mlx5_devx_virtio_q_couners_attr *attr) 1982 { 1983 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1984 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 1985 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 1986 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 1987 virtio_q_counters); 1988 int ret; 1989 1990 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1991 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1992 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1993 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 1994 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 1995 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 1996 sizeof(out)); 1997 if (ret) { 1998 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 1999 rte_errno = errno; 2000 return -errno; 2001 } 2002 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2003 received_desc); 2004 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2005 completed_desc); 2006 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2007 error_cqes); 2008 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2009 bad_desc_errors); 2010 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2011 exceed_max_chain); 2012 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2013 invalid_buffer); 2014 return ret; 2015 } 2016 2017 /** 2018 * Create general object of type FLOW_HIT_ASO using DevX API. 2019 * 2020 * @param[in] ctx 2021 * Context returned from mlx5 open_device() glue function. 2022 * @param [in] pd 2023 * PD value to associate the FLOW_HIT_ASO object with. 2024 * 2025 * @return 2026 * The DevX object created, NULL otherwise and rte_errno is set. 2027 */ 2028 struct mlx5_devx_obj * 2029 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2030 { 2031 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2032 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2033 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2034 void *ptr = NULL; 2035 2036 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2037 0, SOCKET_ID_ANY); 2038 if (!flow_hit_aso_obj) { 2039 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2040 rte_errno = ENOMEM; 2041 return NULL; 2042 } 2043 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2044 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2045 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2046 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2047 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2048 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2049 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2050 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2051 out, sizeof(out)); 2052 if (!flow_hit_aso_obj->obj) { 2053 rte_errno = errno; 2054 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX."); 2055 mlx5_free(flow_hit_aso_obj); 2056 return NULL; 2057 } 2058 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2059 return flow_hit_aso_obj; 2060 } 2061 2062 /* 2063 * Create PD using DevX API. 2064 * 2065 * @param[in] ctx 2066 * Context returned from mlx5 open_device() glue function. 2067 * 2068 * @return 2069 * The DevX object created, NULL otherwise and rte_errno is set. 2070 */ 2071 struct mlx5_devx_obj * 2072 mlx5_devx_cmd_alloc_pd(void *ctx) 2073 { 2074 struct mlx5_devx_obj *ppd = 2075 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2076 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2077 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2078 2079 if (!ppd) { 2080 DRV_LOG(ERR, "Failed to allocate PD data."); 2081 rte_errno = ENOMEM; 2082 return NULL; 2083 } 2084 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2085 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2086 out, sizeof(out)); 2087 if (!ppd->obj) { 2088 mlx5_free(ppd); 2089 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2090 rte_errno = errno; 2091 return NULL; 2092 } 2093 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2094 return ppd; 2095 } 2096 2097 /** 2098 * Create general object of type GENEVE TLV option using DevX API. 2099 * 2100 * @param[in] ctx 2101 * Context returned from mlx5 open_device() glue function. 2102 * @param [in] class 2103 * TLV option variable value of class 2104 * @param [in] type 2105 * TLV option variable value of type 2106 * @param [in] len 2107 * TLV option variable value of len 2108 * 2109 * @return 2110 * The DevX object created, NULL otherwise and rte_errno is set. 2111 */ 2112 struct mlx5_devx_obj * 2113 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2114 uint16_t class, uint8_t type, uint8_t len) 2115 { 2116 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2117 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2118 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2119 sizeof(*geneve_tlv_opt_obj), 2120 0, SOCKET_ID_ANY); 2121 2122 if (!geneve_tlv_opt_obj) { 2123 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2124 rte_errno = ENOMEM; 2125 return NULL; 2126 } 2127 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2128 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2129 geneve_tlv_opt); 2130 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2131 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2132 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2133 MLX5_OBJ_TYPE_GENEVE_TLV_OPT); 2134 MLX5_SET(geneve_tlv_option, opt, option_class, 2135 rte_be_to_cpu_16(class)); 2136 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2137 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2138 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2139 sizeof(in), out, sizeof(out)); 2140 if (!geneve_tlv_opt_obj->obj) { 2141 rte_errno = errno; 2142 DRV_LOG(ERR, "Failed to create Geneve tlv option " 2143 "Obj using DevX."); 2144 mlx5_free(geneve_tlv_opt_obj); 2145 return NULL; 2146 } 2147 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2148 return geneve_tlv_opt_obj; 2149 } 2150 2151