1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /* FW writes status value to the OUT buffer at offset 00H */ 17 #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status) 18 /* FW writes syndrome value to the OUT buffer at offset 04H */ 19 #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome) 20 21 #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1)) 22 23 #define DEVX_DRV_LOG(level, out, reason, param, value) \ 24 do { \ 25 /* \ 26 * Some (old) GCC compilers like 7.5.0 and aarch64 GCC 7.1-2017.08 \ 27 * do not expand correctly when the macro invoked when the `param` \ 28 * is `NULL`. \ 29 * Use `local_param` to avoid direct `NULL` expansion. \ 30 */ \ 31 const char *local_param = (const char *)param; \ 32 \ 33 rte_errno = errno; \ 34 if (!local_param) { \ 35 DRV_LOG(level, \ 36 "DevX %s failed errno=%d status=%#x syndrome=%#x", \ 37 (reason), errno, MLX5_FW_STATUS((out)), \ 38 MLX5_FW_SYNDROME((out))); \ 39 } else { \ 40 DRV_LOG(level, \ 41 "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x",\ 42 (reason), local_param, (value), errno, \ 43 MLX5_FW_STATUS((out)), MLX5_FW_SYNDROME((out))); \ 44 } \ 45 } while (0) 46 47 static void * 48 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, 49 int *err, uint32_t flags) 50 { 51 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); 52 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); 53 int rc; 54 55 memset(in, 0, size_in); 56 memset(out, 0, size_out); 57 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 58 MLX5_SET(query_hca_cap_in, in, op_mod, flags); 59 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); 60 if (rc || MLX5_FW_STATUS(out)) { 61 DEVX_DRV_LOG(ERR, out, "HCA capabilities", "func", flags >> 1); 62 if (err) 63 *err = MLX5_DEVX_ERR_RC(rc); 64 return NULL; 65 } 66 if (err) 67 *err = 0; 68 return MLX5_ADDR_OF(query_hca_cap_out, out, capability); 69 } 70 71 /** 72 * Perform read access to the registers. Reads data from register 73 * and writes ones to the specified buffer. 74 * 75 * @param[in] ctx 76 * Context returned from mlx5 open_device() glue function. 77 * @param[in] reg_id 78 * Register identifier according to the PRM. 79 * @param[in] arg 80 * Register access auxiliary parameter according to the PRM. 81 * @param[out] data 82 * Pointer to the buffer to store read data. 83 * @param[in] dw_cnt 84 * Buffer size in double words. 85 * 86 * @return 87 * 0 on success, a negative value otherwise. 88 */ 89 int 90 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 91 uint32_t *data, uint32_t dw_cnt) 92 { 93 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 94 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 95 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 96 int rc; 97 98 MLX5_ASSERT(data && dw_cnt); 99 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 100 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 101 DRV_LOG(ERR, "Not enough buffer for register read data"); 102 return -1; 103 } 104 MLX5_SET(access_register_in, in, opcode, 105 MLX5_CMD_OP_ACCESS_REGISTER_USER); 106 MLX5_SET(access_register_in, in, op_mod, 107 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 108 MLX5_SET(access_register_in, in, register_id, reg_id); 109 MLX5_SET(access_register_in, in, argument, arg); 110 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 111 MLX5_ST_SZ_BYTES(access_register_out) + 112 sizeof(uint32_t) * dw_cnt); 113 if (rc || MLX5_FW_STATUS(out)) { 114 DEVX_DRV_LOG(DEBUG, out, "read access", "NIC register", reg_id); 115 return MLX5_DEVX_ERR_RC(rc); 116 } 117 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 118 dw_cnt * sizeof(uint32_t)); 119 return 0; 120 } 121 122 /** 123 * Perform write access to the registers. 124 * 125 * @param[in] ctx 126 * Context returned from mlx5 open_device() glue function. 127 * @param[in] reg_id 128 * Register identifier according to the PRM. 129 * @param[in] arg 130 * Register access auxiliary parameter according to the PRM. 131 * @param[out] data 132 * Pointer to the buffer containing data to write. 133 * @param[in] dw_cnt 134 * Buffer size in double words (32bit units). 135 * 136 * @return 137 * 0 on success, a negative value otherwise. 138 */ 139 int 140 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 141 uint32_t *data, uint32_t dw_cnt) 142 { 143 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 144 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 145 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 146 int rc; 147 void *ptr; 148 149 MLX5_ASSERT(data && dw_cnt); 150 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 151 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 152 DRV_LOG(ERR, "Data to write exceeds max size"); 153 return -1; 154 } 155 MLX5_SET(access_register_in, in, opcode, 156 MLX5_CMD_OP_ACCESS_REGISTER_USER); 157 MLX5_SET(access_register_in, in, op_mod, 158 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 159 MLX5_SET(access_register_in, in, register_id, reg_id); 160 MLX5_SET(access_register_in, in, argument, arg); 161 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 162 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 163 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 164 if (rc || MLX5_FW_STATUS(out)) { 165 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 166 return MLX5_DEVX_ERR_RC(rc); 167 } 168 rc = mlx5_glue->devx_general_cmd(ctx, in, 169 MLX5_ST_SZ_BYTES(access_register_in) + 170 dw_cnt * sizeof(uint32_t), 171 out, sizeof(out)); 172 if (rc || MLX5_FW_STATUS(out)) { 173 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 174 return MLX5_DEVX_ERR_RC(rc); 175 } 176 return 0; 177 } 178 179 struct mlx5_devx_obj * 180 mlx5_devx_cmd_flow_counter_alloc_general(void *ctx, 181 struct mlx5_devx_counter_attr *attr) 182 { 183 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 184 0, SOCKET_ID_ANY); 185 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 186 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 187 188 if (!dcs) { 189 rte_errno = ENOMEM; 190 return NULL; 191 } 192 MLX5_SET(alloc_flow_counter_in, in, opcode, 193 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 194 if (attr->bulk_log_max_alloc) 195 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk_log_size, 196 attr->flow_counter_bulk_log_size); 197 else 198 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, 199 attr->bulk_n_128); 200 if (attr->pd_valid) 201 MLX5_SET(alloc_flow_counter_in, in, pd, attr->pd); 202 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 203 sizeof(in), out, sizeof(out)); 204 if (!dcs->obj) { 205 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 206 rte_errno = errno; 207 mlx5_free(dcs); 208 return NULL; 209 } 210 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 211 return dcs; 212 } 213 214 /** 215 * Allocate flow counters via devx interface. 216 * 217 * @param[in] ctx 218 * Context returned from mlx5 open_device() glue function. 219 * @param dcs 220 * Pointer to counters properties structure to be filled by the routine. 221 * @param bulk_n_128 222 * Bulk counter numbers in 128 counters units. 223 * 224 * @return 225 * Pointer to counter object on success, a negative value otherwise and 226 * rte_errno is set. 227 */ 228 struct mlx5_devx_obj * 229 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 230 { 231 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 232 0, SOCKET_ID_ANY); 233 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 234 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 235 236 if (!dcs) { 237 rte_errno = ENOMEM; 238 return NULL; 239 } 240 MLX5_SET(alloc_flow_counter_in, in, opcode, 241 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 242 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 243 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 244 sizeof(in), out, sizeof(out)); 245 if (!dcs->obj) { 246 DEVX_DRV_LOG(ERR, out, "allocate counters", NULL, 0); 247 mlx5_free(dcs); 248 return NULL; 249 } 250 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 251 return dcs; 252 } 253 254 /** 255 * Query flow counters values. 256 * 257 * @param[in] dcs 258 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 259 * @param[in] clear 260 * Whether hardware should clear the counters after the query or not. 261 * @param[in] n_counters 262 * 0 in case of 1 counter to read, otherwise the counter number to read. 263 * @param pkts 264 * The number of packets that matched the flow. 265 * @param bytes 266 * The number of bytes that matched the flow. 267 * @param mkey 268 * The mkey key for batch query. 269 * @param addr 270 * The address in the mkey range for batch query. 271 * @param cmd_comp 272 * The completion object for asynchronous batch query. 273 * @param async_id 274 * The ID to be returned in the asynchronous batch query response. 275 * 276 * @return 277 * 0 on success, a negative value otherwise. 278 */ 279 int 280 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 281 int clear, uint32_t n_counters, 282 uint64_t *pkts, uint64_t *bytes, 283 uint32_t mkey, void *addr, 284 void *cmd_comp, 285 uint64_t async_id) 286 { 287 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 288 MLX5_ST_SZ_BYTES(traffic_counter); 289 uint32_t out[out_len]; 290 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 291 void *stats; 292 int rc; 293 294 MLX5_SET(query_flow_counter_in, in, opcode, 295 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 296 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 297 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 298 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 299 300 if (n_counters) { 301 MLX5_SET(query_flow_counter_in, in, num_of_counters, 302 n_counters); 303 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 304 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 305 MLX5_SET64(query_flow_counter_in, in, address, 306 (uint64_t)(uintptr_t)addr); 307 } 308 if (!cmd_comp) 309 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 310 out_len); 311 else 312 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 313 out_len, async_id, 314 cmd_comp); 315 if (rc) { 316 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 317 rte_errno = rc; 318 return -rc; 319 } 320 if (!n_counters) { 321 stats = MLX5_ADDR_OF(query_flow_counter_out, 322 out, flow_statistics); 323 *pkts = MLX5_GET64(traffic_counter, stats, packets); 324 *bytes = MLX5_GET64(traffic_counter, stats, octets); 325 } 326 return 0; 327 } 328 329 /** 330 * Create a new mkey. 331 * 332 * @param[in] ctx 333 * Context returned from mlx5 open_device() glue function. 334 * @param[in] attr 335 * Attributes of the requested mkey. 336 * 337 * @return 338 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 339 * is set. 340 */ 341 struct mlx5_devx_obj * 342 mlx5_devx_cmd_mkey_create(void *ctx, 343 struct mlx5_devx_mkey_attr *attr) 344 { 345 struct mlx5_klm *klm_array = attr->klm_array; 346 int klm_num = attr->klm_num; 347 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 348 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 349 uint32_t in[in_size_dw]; 350 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 351 void *mkc; 352 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 353 0, SOCKET_ID_ANY); 354 size_t pgsize; 355 uint32_t translation_size; 356 357 if (!mkey) { 358 rte_errno = ENOMEM; 359 return NULL; 360 } 361 memset(in, 0, in_size_dw * 4); 362 pgsize = rte_mem_page_size(); 363 if (pgsize == (size_t)-1) { 364 mlx5_free(mkey); 365 DRV_LOG(ERR, "Failed to get page size"); 366 rte_errno = ENOMEM; 367 return NULL; 368 } 369 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 370 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 371 if (klm_num > 0) { 372 int i; 373 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 374 klm_pas_mtt); 375 translation_size = RTE_ALIGN(klm_num, 4); 376 for (i = 0; i < klm_num; i++) { 377 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 378 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 379 MLX5_SET64(klm, klm, address, klm_array[i].address); 380 klm += MLX5_ST_SZ_BYTES(klm); 381 } 382 for (; i < (int)translation_size; i++) { 383 MLX5_SET(klm, klm, mkey, 0x0); 384 MLX5_SET64(klm, klm, address, 0x0); 385 klm += MLX5_ST_SZ_BYTES(klm); 386 } 387 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 388 MLX5_MKC_ACCESS_MODE_KLM_FBS : 389 MLX5_MKC_ACCESS_MODE_KLM); 390 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 391 } else { 392 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 393 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 394 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 395 } 396 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 397 translation_size); 398 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 399 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 400 MLX5_SET(mkc, mkc, lw, 0x1); 401 MLX5_SET(mkc, mkc, lr, 0x1); 402 if (attr->set_remote_rw) { 403 MLX5_SET(mkc, mkc, rw, 0x1); 404 MLX5_SET(mkc, mkc, rr, 0x1); 405 } 406 MLX5_SET(mkc, mkc, qpn, 0xffffff); 407 MLX5_SET(mkc, mkc, pd, attr->pd); 408 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 409 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 410 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 411 MLX5_SET(mkc, mkc, relaxed_ordering_write, 412 attr->relaxed_ordering_write); 413 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 414 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 415 MLX5_SET64(mkc, mkc, len, attr->size); 416 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 417 if (attr->crypto_en) { 418 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 419 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 420 } 421 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 422 sizeof(out)); 423 if (!mkey->obj) { 424 DEVX_DRV_LOG(ERR, out, klm_num ? "create indirect mkey" 425 : "create direct key", NULL, 0); 426 mlx5_free(mkey); 427 return NULL; 428 } 429 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 430 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 431 return mkey; 432 } 433 434 /** 435 * Get status of devx command response. 436 * Mainly used for asynchronous commands. 437 * 438 * @param[in] out 439 * The out response buffer. 440 * 441 * @return 442 * 0 on success, non-zero value otherwise. 443 */ 444 int 445 mlx5_devx_get_out_command_status(void *out) 446 { 447 int status; 448 449 if (!out) 450 return -EINVAL; 451 status = MLX5_GET(query_flow_counter_out, out, status); 452 if (status) { 453 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 454 455 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 456 syndrome); 457 } 458 return status; 459 } 460 461 /** 462 * Destroy any object allocated by a Devx API. 463 * 464 * @param[in] obj 465 * Pointer to a general object. 466 * 467 * @return 468 * 0 on success, a negative value otherwise. 469 */ 470 int 471 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 472 { 473 int ret; 474 475 if (!obj) 476 return 0; 477 ret = mlx5_glue->devx_obj_destroy(obj->obj); 478 mlx5_free(obj); 479 return ret; 480 } 481 482 /** 483 * Query NIC vport context. 484 * Fills minimal inline attribute. 485 * 486 * @param[in] ctx 487 * ibv contexts returned from mlx5dv_open_device. 488 * @param[in] vport 489 * vport index 490 * @param[out] attr 491 * Attributes device values. 492 * 493 * @return 494 * 0 on success, a negative value otherwise. 495 */ 496 static int 497 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 498 unsigned int vport, 499 struct mlx5_hca_attr *attr) 500 { 501 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 502 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 503 void *vctx; 504 int rc; 505 506 /* Query NIC vport context to determine inline mode. */ 507 MLX5_SET(query_nic_vport_context_in, in, opcode, 508 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 509 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 510 if (vport) 511 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 512 rc = mlx5_glue->devx_general_cmd(ctx, 513 in, sizeof(in), 514 out, sizeof(out)); 515 if (rc || MLX5_FW_STATUS(out)) { 516 DEVX_DRV_LOG(ERR, out, "query NIC vport context", NULL, 0); 517 return MLX5_DEVX_ERR_RC(rc); 518 } 519 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 520 nic_vport_context); 521 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 522 min_wqe_inline_mode); 523 return 0; 524 } 525 526 /** 527 * Query NIC vDPA attributes. 528 * 529 * @param[in] ctx 530 * Context returned from mlx5 open_device() glue function. 531 * @param[out] vdpa_attr 532 * vDPA Attributes structure to fill. 533 */ 534 static void 535 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 536 struct mlx5_hca_vdpa_attr *vdpa_attr) 537 { 538 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 539 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 540 void *hcattr; 541 542 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, 543 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 544 MLX5_HCA_CAP_OPMOD_GET_CUR); 545 if (!hcattr) { 546 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities"); 547 vdpa_attr->valid = 0; 548 } else { 549 vdpa_attr->valid = 1; 550 vdpa_attr->desc_tunnel_offload_type = 551 MLX5_GET(virtio_emulation_cap, hcattr, 552 desc_tunnel_offload_type); 553 vdpa_attr->eth_frame_offload_type = 554 MLX5_GET(virtio_emulation_cap, hcattr, 555 eth_frame_offload_type); 556 vdpa_attr->virtio_version_1_0 = 557 MLX5_GET(virtio_emulation_cap, hcattr, 558 virtio_version_1_0); 559 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 560 tso_ipv4); 561 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 562 tso_ipv6); 563 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 564 tx_csum); 565 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 566 rx_csum); 567 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 568 event_mode); 569 vdpa_attr->virtio_queue_type = 570 MLX5_GET(virtio_emulation_cap, hcattr, 571 virtio_queue_type); 572 vdpa_attr->log_doorbell_stride = 573 MLX5_GET(virtio_emulation_cap, hcattr, 574 log_doorbell_stride); 575 vdpa_attr->vnet_modify_ext = 576 MLX5_GET(virtio_emulation_cap, hcattr, 577 vnet_modify_ext); 578 vdpa_attr->virtio_net_q_addr_modify = 579 MLX5_GET(virtio_emulation_cap, hcattr, 580 virtio_net_q_addr_modify); 581 vdpa_attr->virtio_q_index_modify = 582 MLX5_GET(virtio_emulation_cap, hcattr, 583 virtio_q_index_modify); 584 vdpa_attr->log_doorbell_bar_size = 585 MLX5_GET(virtio_emulation_cap, hcattr, 586 log_doorbell_bar_size); 587 vdpa_attr->doorbell_bar_offset = 588 MLX5_GET64(virtio_emulation_cap, hcattr, 589 doorbell_bar_offset); 590 vdpa_attr->max_num_virtio_queues = 591 MLX5_GET(virtio_emulation_cap, hcattr, 592 max_num_virtio_queues); 593 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 594 umem_1_buffer_param_a); 595 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 596 umem_1_buffer_param_b); 597 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 598 umem_2_buffer_param_a); 599 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 600 umem_2_buffer_param_b); 601 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 602 umem_3_buffer_param_a); 603 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 604 umem_3_buffer_param_b); 605 } 606 } 607 608 /** 609 * Query match sample handle parameters. 610 * 611 * This command allows translating a field sample handle returned by either 612 * PARSE_GRAPH_FLOW_MATCH_SAMPLE or by GENEVE TLV OPTION object into values 613 * used for header modification or header matching/hashing. 614 * 615 * @param[in] ctx 616 * Context used to create either GENEVE TLV option or FLEX PARSE GRAPH object. 617 * @param[in] sample_field_id 618 * Field sample handle returned by either PARSE_GRAPH_FLOW_MATCH_SAMPLE 619 * or by GENEVE TLV OPTION object. 620 * @param[out] attr 621 * Pointer to match sample info attributes structure. 622 * 623 * @return 624 * 0 on success, a negative errno otherwise and rte_errno is set. 625 */ 626 int 627 mlx5_devx_cmd_match_sample_info_query(void *ctx, uint32_t sample_field_id, 628 struct mlx5_devx_match_sample_info_query_attr *attr) 629 { 630 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 631 uint32_t out[MLX5_ST_SZ_DW(query_match_sample_info_out)] = {0}; 632 uint32_t in[MLX5_ST_SZ_DW(query_match_sample_info_in)] = {0}; 633 int rc; 634 635 MLX5_SET(query_match_sample_info_in, in, opcode, 636 MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO); 637 MLX5_SET(query_match_sample_info_in, in, op_mod, 0); 638 MLX5_SET(query_match_sample_info_in, in, sample_field_id, 639 sample_field_id); 640 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 641 if (rc) { 642 DRV_LOG(ERR, "Failed to query match sample info using DevX: %s", 643 strerror(rc)); 644 rte_errno = rc; 645 return -rc; 646 } 647 attr->modify_field_id = MLX5_GET(query_match_sample_info_out, out, 648 modify_field_id); 649 attr->sample_dw_data = MLX5_GET(query_match_sample_info_out, out, 650 field_format_select_dw); 651 attr->sample_dw_ok_bit = MLX5_GET(query_match_sample_info_out, out, 652 ok_bit_format_select_dw); 653 attr->sample_dw_ok_bit_offset = MLX5_GET(query_match_sample_info_out, 654 out, ok_bit_offset); 655 return 0; 656 #else 657 (void)ctx; 658 (void)sample_field_id; 659 (void)attr; 660 return -ENOTSUP; 661 #endif 662 } 663 664 int 665 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 666 uint32_t *ids, 667 uint32_t num, uint8_t *anchor) 668 { 669 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 670 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 671 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 672 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 673 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 674 int ret; 675 uint32_t idx = 0; 676 uint32_t i; 677 678 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 679 rte_errno = EINVAL; 680 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 681 return -rte_errno; 682 } 683 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 684 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 685 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 686 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 687 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 688 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 689 out, sizeof(out)); 690 if (ret) { 691 rte_errno = ret; 692 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 693 (void *)flex_obj); 694 return -rte_errno; 695 } 696 if (anchor) 697 *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id); 698 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx < num; i++) { 699 void *s_off = (void *)((char *)sample + i * 700 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 701 uint32_t en; 702 703 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 704 flow_match_sample_en); 705 if (!en) 706 continue; 707 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 708 flow_match_sample_field_id); 709 } 710 if (num != idx) { 711 rte_errno = EINVAL; 712 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 713 return -rte_errno; 714 } 715 return ret; 716 } 717 718 struct mlx5_devx_obj * 719 mlx5_devx_cmd_create_flex_parser(void *ctx, 720 struct mlx5_devx_graph_node_attr *data) 721 { 722 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 723 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 724 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 725 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 726 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 727 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 728 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 729 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 730 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 731 uint32_t i; 732 733 if (!parse_flex_obj) { 734 DRV_LOG(ERR, "Failed to allocate flex parser data."); 735 rte_errno = ENOMEM; 736 return NULL; 737 } 738 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 739 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 740 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 741 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 742 MLX5_SET(parse_graph_flex, flex, header_length_mode, 743 data->header_length_mode); 744 MLX5_SET64(parse_graph_flex, flex, modify_field_select, 745 data->modify_field_select); 746 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 747 data->header_length_base_value); 748 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 749 data->header_length_field_offset); 750 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 751 data->header_length_field_shift); 752 MLX5_SET(parse_graph_flex, flex, next_header_field_offset, 753 data->next_header_field_offset); 754 MLX5_SET(parse_graph_flex, flex, next_header_field_size, 755 data->next_header_field_size); 756 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 757 data->header_length_field_mask); 758 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 759 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 760 void *s_off = (void *)((char *)sample + i * 761 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 762 763 if (!s->flow_match_sample_en) 764 continue; 765 MLX5_SET(parse_graph_flow_match_sample, s_off, 766 flow_match_sample_en, !!s->flow_match_sample_en); 767 MLX5_SET(parse_graph_flow_match_sample, s_off, 768 flow_match_sample_field_offset, 769 s->flow_match_sample_field_offset); 770 MLX5_SET(parse_graph_flow_match_sample, s_off, 771 flow_match_sample_offset_mode, 772 s->flow_match_sample_offset_mode); 773 MLX5_SET(parse_graph_flow_match_sample, s_off, 774 flow_match_sample_field_offset_mask, 775 s->flow_match_sample_field_offset_mask); 776 MLX5_SET(parse_graph_flow_match_sample, s_off, 777 flow_match_sample_field_offset_shift, 778 s->flow_match_sample_field_offset_shift); 779 MLX5_SET(parse_graph_flow_match_sample, s_off, 780 flow_match_sample_field_base_offset, 781 s->flow_match_sample_field_base_offset); 782 MLX5_SET(parse_graph_flow_match_sample, s_off, 783 flow_match_sample_tunnel_mode, 784 s->flow_match_sample_tunnel_mode); 785 } 786 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 787 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 788 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 789 void *in_off = (void *)((char *)in_arc + i * 790 MLX5_ST_SZ_BYTES(parse_graph_arc)); 791 void *out_off = (void *)((char *)out_arc + i * 792 MLX5_ST_SZ_BYTES(parse_graph_arc)); 793 794 if (ia->arc_parse_graph_node != 0) { 795 MLX5_SET(parse_graph_arc, in_off, 796 compare_condition_value, 797 ia->compare_condition_value); 798 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 799 ia->start_inner_tunnel); 800 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 801 ia->arc_parse_graph_node); 802 MLX5_SET(parse_graph_arc, in_off, 803 parse_graph_node_handle, 804 ia->parse_graph_node_handle); 805 } 806 if (oa->arc_parse_graph_node != 0) { 807 MLX5_SET(parse_graph_arc, out_off, 808 compare_condition_value, 809 oa->compare_condition_value); 810 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 811 oa->start_inner_tunnel); 812 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 813 oa->arc_parse_graph_node); 814 MLX5_SET(parse_graph_arc, out_off, 815 parse_graph_node_handle, 816 oa->parse_graph_node_handle); 817 } 818 } 819 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 820 out, sizeof(out)); 821 if (!parse_flex_obj->obj) { 822 DEVX_DRV_LOG(ERR, out, "create FLEX PARSE GRAPH", NULL, 0); 823 mlx5_free(parse_flex_obj); 824 return NULL; 825 } 826 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 827 return parse_flex_obj; 828 } 829 830 static int 831 mlx5_devx_cmd_query_hca_parse_graph_node_cap 832 (void *ctx, struct mlx5_hca_flex_attr *attr) 833 { 834 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 835 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 836 void *hcattr; 837 int rc; 838 839 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 840 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | 841 MLX5_HCA_CAP_OPMOD_GET_CUR); 842 if (!hcattr) 843 return rc; 844 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); 845 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); 846 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, 847 header_length_mode); 848 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, 849 sample_offset_mode); 850 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, 851 max_num_arc_in); 852 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, 853 max_num_arc_out); 854 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, 855 max_num_sample); 856 attr->parse_graph_anchor = MLX5_GET(parse_graph_node_cap, hcattr, parse_graph_anchor); 857 attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr, 858 sample_tunnel_inner2); 859 attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr, 860 zero_size_supported); 861 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, 862 sample_id_in_out); 863 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, 864 max_base_header_length); 865 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, 866 max_sample_base_offset); 867 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, 868 max_next_header_offset); 869 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, 870 header_length_mask_width); 871 /* Get the max supported samples from HCA CAP 2 */ 872 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 873 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 874 MLX5_HCA_CAP_OPMOD_GET_CUR); 875 if (!hcattr) 876 return rc; 877 attr->max_num_prog_sample = 878 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); 879 return 0; 880 } 881 882 static int 883 mlx5_devx_query_pkt_integrity_match(void *hcattr) 884 { 885 return MLX5_GET(flow_table_nic_cap, hcattr, 886 ft_field_support_2_nic_receive.inner_l3_ok) && 887 MLX5_GET(flow_table_nic_cap, hcattr, 888 ft_field_support_2_nic_receive.inner_l4_ok) && 889 MLX5_GET(flow_table_nic_cap, hcattr, 890 ft_field_support_2_nic_receive.outer_l3_ok) && 891 MLX5_GET(flow_table_nic_cap, hcattr, 892 ft_field_support_2_nic_receive.outer_l4_ok) && 893 MLX5_GET(flow_table_nic_cap, hcattr, 894 ft_field_support_2_nic_receive 895 .inner_ipv4_checksum_ok) && 896 MLX5_GET(flow_table_nic_cap, hcattr, 897 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 898 MLX5_GET(flow_table_nic_cap, hcattr, 899 ft_field_support_2_nic_receive 900 .outer_ipv4_checksum_ok) && 901 MLX5_GET(flow_table_nic_cap, hcattr, 902 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 903 } 904 905 /** 906 * Query HCA attributes. 907 * Using those attributes we can check on run time if the device 908 * is having the required capabilities. 909 * 910 * @param[in] ctx 911 * Context returned from mlx5 open_device() glue function. 912 * @param[out] attr 913 * Attributes device values. 914 * 915 * @return 916 * 0 on success, a negative value otherwise. 917 */ 918 int 919 mlx5_devx_cmd_query_hca_attr(void *ctx, 920 struct mlx5_hca_attr *attr) 921 { 922 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 923 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 924 bool hca_cap_2_sup; 925 uint64_t general_obj_types_supported = 0; 926 void *hcattr; 927 int rc, i; 928 929 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 930 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 931 MLX5_HCA_CAP_OPMOD_GET_CUR); 932 if (!hcattr) 933 return rc; 934 hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2); 935 attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq); 936 attr->flow_counter_bulk_alloc_bitmap = 937 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 938 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 939 flow_counters_dump); 940 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp); 941 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp); 942 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 943 log_max_rqt_size); 944 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 945 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 946 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 947 log_max_hairpin_queues); 948 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 949 log_max_hairpin_wq_data_sz); 950 attr->log_max_hairpin_num_packets = MLX5_GET 951 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 952 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 953 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 954 relaxed_ordering_write); 955 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 956 relaxed_ordering_read); 957 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 958 access_register_user); 959 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 960 eth_net_offloads); 961 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 962 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 963 flex_parser_protocols); 964 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 965 max_geneve_tlv_options); 966 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 967 max_geneve_tlv_option_data_len); 968 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 969 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 970 general_obj_types) & 971 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 972 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 973 general_obj_types) & 974 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 975 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 976 general_obj_types) & 977 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 978 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 979 general_obj_types) & 980 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 981 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 982 wqe_index_ignore_cap); 983 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 984 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 985 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 986 log_max_static_sq_wq); 987 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 988 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 989 device_frequency_khz); 990 attr->scatter_fcs_w_decap_disable = 991 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 992 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 993 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 994 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 995 attr->steering_format_version = 996 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 997 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 998 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 999 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 1000 regexp_num_of_engines); 1001 /* Read the general_obj_types bitmap and extract the relevant bits. */ 1002 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 1003 general_obj_types); 1004 attr->vdpa.valid = !!(general_obj_types_supported & 1005 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 1006 attr->vdpa.queue_counters_valid = 1007 !!(general_obj_types_supported & 1008 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 1009 attr->parse_graph_flex_node = 1010 !!(general_obj_types_supported & 1011 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 1012 attr->flow_hit_aso = !!(general_obj_types_supported & 1013 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 1014 attr->geneve_tlv_opt = !!(general_obj_types_supported & 1015 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 1016 attr->dek = !!(general_obj_types_supported & 1017 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 1018 attr->import_kek = !!(general_obj_types_supported & 1019 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 1020 attr->credential = !!(general_obj_types_supported & 1021 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 1022 attr->crypto_login = !!(general_obj_types_supported & 1023 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 1024 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 1025 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 1026 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 1027 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 1028 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 1029 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 1030 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 1031 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 1032 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 1033 attr->reg_c_preserve = 1034 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 1035 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 1036 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 1037 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 1038 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 1039 compress_mmo_sq); 1040 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 1041 decompress_mmo_sq); 1042 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 1043 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 1044 compress_mmo_qp); 1045 attr->decomp_deflate_v1_en = MLX5_GET(cmd_hca_cap, hcattr, 1046 decompress_deflate_v1); 1047 attr->decomp_deflate_v2_en = MLX5_GET(cmd_hca_cap, hcattr, 1048 decompress_deflate_v2); 1049 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 1050 compress_min_block_size); 1051 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 1052 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 1053 log_compress_mmo_size); 1054 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 1055 log_decompress_mmo_size); 1056 attr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr, 1057 decompress_lz4_data_only_v2); 1058 attr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, 1059 decompress_lz4_no_checksum_v2); 1060 attr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, 1061 decompress_lz4_checksum_v2); 1062 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 1063 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 1064 mini_cqe_resp_flow_tag); 1065 attr->cqe_compression_128 = MLX5_GET(cmd_hca_cap, hcattr, 1066 cqe_compression_128); 1067 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 1068 mini_cqe_resp_l3_l4_tag); 1069 attr->enhanced_cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, 1070 enhanced_cqe_compression); 1071 attr->umr_indirect_mkey_disabled = 1072 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 1073 attr->umr_modify_entity_size_disabled = 1074 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 1075 attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time); 1076 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 1077 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 1078 general_obj_types) & 1079 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 1080 attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); 1081 attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table); 1082 attr->striding_rq = MLX5_GET(cmd_hca_cap, hcattr, striding_rq); 1083 attr->ext_stride_num_range = 1084 MLX5_GET(cmd_hca_cap, hcattr, ext_stride_num_range); 1085 attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr, 1086 max_flow_counter_15_0); 1087 attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr, 1088 max_flow_counter_31_16); 1089 attr->alloc_flow_counter_pd = MLX5_GET(cmd_hca_cap, hcattr, 1090 alloc_flow_counter_pd); 1091 attr->flow_counter_access_aso = MLX5_GET(cmd_hca_cap, hcattr, 1092 flow_counter_access_aso); 1093 attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr, 1094 flow_access_aso_opc_mod); 1095 attr->wqe_based_flow_table_sup = MLX5_GET(cmd_hca_cap, hcattr, 1096 wqe_based_flow_table_update_cap); 1097 /* 1098 * Flex item support needs max_num_prog_sample_field 1099 * from the Capabilities 2 table for PARSE_GRAPH_NODE 1100 */ 1101 if (attr->parse_graph_flex_node) { 1102 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap 1103 (ctx, &attr->flex); 1104 if (rc) 1105 return -1; 1106 attr->flex.query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr, 1107 query_match_sample_info); 1108 } 1109 if (attr->crypto) { 1110 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) || 1111 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_multi_block_be_tweak) || 1112 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_single_block_le_tweak); 1113 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1114 MLX5_GET_HCA_CAP_OP_MOD_CRYPTO | 1115 MLX5_HCA_CAP_OPMOD_GET_CUR); 1116 if (!hcattr) 1117 return -1; 1118 attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps, 1119 hcattr, wrapped_import_method) 1120 & 1 << 2); 1121 attr->crypto_mmo.crypto_mmo_qp = MLX5_GET(crypto_caps, hcattr, crypto_mmo_qp); 1122 attr->crypto_mmo.gcm_256_encrypt = 1123 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_encrypt); 1124 attr->crypto_mmo.gcm_128_encrypt = 1125 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_encrypt); 1126 attr->crypto_mmo.gcm_256_decrypt = 1127 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_decrypt); 1128 attr->crypto_mmo.gcm_128_decrypt = 1129 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_decrypt); 1130 attr->crypto_mmo.gcm_auth_tag_128 = 1131 MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_128); 1132 attr->crypto_mmo.gcm_auth_tag_96 = 1133 MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_96); 1134 attr->crypto_mmo.log_crypto_mmo_max_size = 1135 MLX5_GET(crypto_caps, hcattr, log_crypto_mmo_max_size); 1136 } 1137 if (hca_cap_2_sup) { 1138 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1139 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 1140 MLX5_HCA_CAP_OPMOD_GET_CUR); 1141 if (!hcattr) { 1142 DRV_LOG(DEBUG, 1143 "Failed to query DevX HCA capabilities 2."); 1144 return rc; 1145 } 1146 attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, 1147 log_min_stride_wqe_sz); 1148 attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr, 1149 hairpin_sq_wqe_bb_size); 1150 attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr, 1151 hairpin_sq_wq_in_host_mem); 1152 attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr, 1153 hairpin_data_buffer_locked); 1154 attr->flow_counter_bulk_log_max_alloc = MLX5_GET(cmd_hca_cap_2, 1155 hcattr, flow_counter_bulk_log_max_alloc); 1156 attr->flow_counter_bulk_log_granularity = 1157 MLX5_GET(cmd_hca_cap_2, hcattr, 1158 flow_counter_bulk_log_granularity); 1159 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1160 cross_vhca_object_to_object_supported); 1161 attr->cross_vhca = 1162 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR) && 1163 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT) && 1164 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT) && 1165 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC); 1166 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1167 allowed_object_for_other_vhca_access); 1168 attr->cross_vhca = attr->cross_vhca && 1169 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR) && 1170 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_FT) && 1171 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC); 1172 } 1173 if (attr->log_min_stride_wqe_sz == 0) 1174 attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 1175 if (attr->qos.sup) { 1176 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1177 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 1178 MLX5_HCA_CAP_OPMOD_GET_CUR); 1179 if (!hcattr) { 1180 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); 1181 return rc; 1182 } 1183 attr->qos.flow_meter_old = 1184 MLX5_GET(qos_cap, hcattr, flow_meter_old); 1185 attr->qos.log_max_flow_meter = 1186 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 1187 attr->qos.flow_meter_reg_c_ids = 1188 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 1189 attr->qos.flow_meter = 1190 MLX5_GET(qos_cap, hcattr, flow_meter); 1191 attr->qos.packet_pacing = 1192 MLX5_GET(qos_cap, hcattr, packet_pacing); 1193 attr->qos.wqe_rate_pp = 1194 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 1195 if (attr->qos.flow_meter_aso_sup) { 1196 attr->qos.log_meter_aso_granularity = 1197 MLX5_GET(qos_cap, hcattr, 1198 log_meter_aso_granularity); 1199 attr->qos.log_meter_aso_max_alloc = 1200 MLX5_GET(qos_cap, hcattr, 1201 log_meter_aso_max_alloc); 1202 attr->qos.log_max_num_meter_aso = 1203 MLX5_GET(qos_cap, hcattr, 1204 log_max_num_meter_aso); 1205 } 1206 } 1207 if (attr->vdpa.valid) 1208 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 1209 if (!attr->eth_net_offloads) 1210 return 0; 1211 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 1212 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1213 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 1214 MLX5_HCA_CAP_OPMOD_GET_CUR); 1215 if (!hcattr) { 1216 attr->log_max_ft_sampler_num = 0; 1217 return rc; 1218 } 1219 attr->log_max_ft_sampler_num = MLX5_GET 1220 (flow_table_nic_cap, hcattr, 1221 flow_table_properties_nic_receive.log_max_ft_sampler_num); 1222 attr->flow.tunnel_header_0_1 = MLX5_GET 1223 (flow_table_nic_cap, hcattr, 1224 ft_field_support_2_nic_receive.tunnel_header_0_1); 1225 attr->flow.tunnel_header_2_3 = MLX5_GET 1226 (flow_table_nic_cap, hcattr, 1227 ft_field_support_2_nic_receive.tunnel_header_2_3); 1228 attr->modify_outer_ip_ecn = MLX5_GET 1229 (flow_table_nic_cap, hcattr, 1230 ft_header_modify_nic_receive.outer_ip_ecn); 1231 attr->set_reg_c = 0xff; 1232 if (attr->nic_flow_table) { 1233 #define GET_RX_REG_X_BITS \ 1234 MLX5_GET(flow_table_nic_cap, hcattr, \ 1235 ft_header_modify_nic_receive.metadata_reg_c_x) 1236 #define GET_TX_REG_X_BITS \ 1237 MLX5_GET(flow_table_nic_cap, hcattr, \ 1238 ft_header_modify_nic_transmit.metadata_reg_c_x) 1239 1240 uint32_t tx_reg, rx_reg; 1241 1242 tx_reg = GET_TX_REG_X_BITS; 1243 rx_reg = GET_RX_REG_X_BITS; 1244 attr->set_reg_c &= (rx_reg & tx_reg); 1245 1246 #undef GET_RX_REG_X_BITS 1247 #undef GET_TX_REG_X_BITS 1248 } 1249 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 1250 attr->inner_ipv4_ihl = MLX5_GET 1251 (flow_table_nic_cap, hcattr, 1252 ft_field_support_2_nic_receive.inner_ipv4_ihl); 1253 attr->outer_ipv4_ihl = MLX5_GET 1254 (flow_table_nic_cap, hcattr, 1255 ft_field_support_2_nic_receive.outer_ipv4_ihl); 1256 attr->lag_rx_port_affinity = MLX5_GET 1257 (flow_table_nic_cap, hcattr, 1258 ft_field_support_2_nic_receive.lag_rx_port_affinity); 1259 /* Query HCA offloads for Ethernet protocol. */ 1260 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1261 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 1262 MLX5_HCA_CAP_OPMOD_GET_CUR); 1263 if (!hcattr) { 1264 attr->eth_net_offloads = 0; 1265 return rc; 1266 } 1267 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 1268 hcattr, wqe_vlan_insert); 1269 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 1270 hcattr, csum_cap); 1271 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 1272 hcattr, vlan_cap); 1273 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1274 lro_cap); 1275 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1276 hcattr, max_lso_cap); 1277 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1278 hcattr, scatter_fcs); 1279 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1280 hcattr, tunnel_lro_gre); 1281 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1282 hcattr, tunnel_lro_vxlan); 1283 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1284 hcattr, swp); 1285 attr->tunnel_stateless_gre = 1286 MLX5_GET(per_protocol_networking_offload_caps, 1287 hcattr, tunnel_stateless_gre); 1288 attr->tunnel_stateless_vxlan = 1289 MLX5_GET(per_protocol_networking_offload_caps, 1290 hcattr, tunnel_stateless_vxlan); 1291 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1292 hcattr, swp_csum); 1293 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1294 hcattr, swp_lso); 1295 attr->lro_max_msg_sz_mode = MLX5_GET 1296 (per_protocol_networking_offload_caps, 1297 hcattr, lro_max_msg_sz_mode); 1298 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1299 attr->lro_timer_supported_periods[i] = 1300 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1301 lro_timer_supported_periods[i]); 1302 } 1303 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1304 hcattr, lro_min_mss_size); 1305 attr->tunnel_stateless_geneve_rx = 1306 MLX5_GET(per_protocol_networking_offload_caps, 1307 hcattr, tunnel_stateless_geneve_rx); 1308 attr->geneve_max_opt_len = 1309 MLX5_GET(per_protocol_networking_offload_caps, 1310 hcattr, max_geneve_opt_len); 1311 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1312 hcattr, wqe_inline_mode); 1313 attr->tunnel_stateless_gtp = MLX5_GET 1314 (per_protocol_networking_offload_caps, 1315 hcattr, tunnel_stateless_gtp); 1316 attr->rss_ind_tbl_cap = MLX5_GET 1317 (per_protocol_networking_offload_caps, 1318 hcattr, rss_ind_tbl_cap); 1319 attr->multi_pkt_send_wqe = MLX5_GET 1320 (per_protocol_networking_offload_caps, 1321 hcattr, multi_pkt_send_wqe); 1322 attr->enhanced_multi_pkt_send_wqe = MLX5_GET 1323 (per_protocol_networking_offload_caps, 1324 hcattr, enhanced_multi_pkt_send_wqe); 1325 if (attr->wqe_based_flow_table_sup) { 1326 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1327 MLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE | 1328 MLX5_HCA_CAP_OPMOD_GET_CUR); 1329 if (!hcattr) { 1330 DRV_LOG(DEBUG, "Failed to query WQE Based Flow table capabilities"); 1331 return rc; 1332 } 1333 attr->max_header_modify_pattern_length = MLX5_GET(wqe_based_flow_table_cap, 1334 hcattr, 1335 max_header_modify_pattern_length); 1336 } 1337 /* Query HCA attribute for ROCE. */ 1338 if (attr->roce) { 1339 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1340 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1341 MLX5_HCA_CAP_OPMOD_GET_CUR); 1342 if (!hcattr) { 1343 DRV_LOG(DEBUG, 1344 "Failed to query devx HCA ROCE capabilities"); 1345 return rc; 1346 } 1347 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1348 } 1349 if (attr->eth_virt && 1350 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1351 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1352 if (rc) { 1353 attr->eth_virt = 0; 1354 goto error; 1355 } 1356 } 1357 if (attr->eswitch_manager) { 1358 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1359 MLX5_SET_HCA_CAP_OP_MOD_ESW | 1360 MLX5_HCA_CAP_OPMOD_GET_CUR); 1361 if (!hcattr) 1362 return rc; 1363 attr->esw_mgr_vport_id_valid = 1364 MLX5_GET(esw_cap, hcattr, 1365 esw_manager_vport_number_valid); 1366 attr->esw_mgr_vport_id = 1367 MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); 1368 } 1369 if (attr->eswitch_manager) { 1370 uint32_t esw_reg; 1371 1372 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1373 MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE | 1374 MLX5_HCA_CAP_OPMOD_GET_CUR); 1375 if (!hcattr) 1376 return rc; 1377 esw_reg = MLX5_GET(flow_table_esw_cap, hcattr, 1378 ft_header_modify_esw_fdb.metadata_reg_c_x); 1379 attr->set_reg_c &= esw_reg; 1380 } 1381 return 0; 1382 error: 1383 rc = (rc > 0) ? -rc : rc; 1384 return rc; 1385 } 1386 1387 /** 1388 * Query TIS transport domain from QP verbs object using DevX API. 1389 * 1390 * @param[in] qp 1391 * Pointer to verbs QP returned by ibv_create_qp . 1392 * @param[in] tis_num 1393 * TIS number of TIS to query. 1394 * @param[out] tis_td 1395 * Pointer to TIS transport domain variable, to be set by the routine. 1396 * 1397 * @return 1398 * 0 on success, a negative value otherwise. 1399 */ 1400 int 1401 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1402 uint32_t *tis_td) 1403 { 1404 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1405 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1406 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1407 int rc; 1408 void *tis_ctx; 1409 1410 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1411 MLX5_SET(query_tis_in, in, tisn, tis_num); 1412 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1413 if (rc) { 1414 DRV_LOG(ERR, "Failed to query QP using DevX"); 1415 return -rc; 1416 }; 1417 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1418 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1419 return 0; 1420 #else 1421 (void)qp; 1422 (void)tis_num; 1423 (void)tis_td; 1424 return -ENOTSUP; 1425 #endif 1426 } 1427 1428 /** 1429 * Fill WQ data for DevX API command. 1430 * Utility function for use when creating DevX objects containing a WQ. 1431 * 1432 * @param[in] wq_ctx 1433 * Pointer to WQ context to fill with data. 1434 * @param [in] wq_attr 1435 * Pointer to WQ attributes structure to fill in WQ context. 1436 */ 1437 static void 1438 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1439 { 1440 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1441 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1442 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1443 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1444 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1445 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1446 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1447 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1448 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1449 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1450 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1451 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1452 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1453 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1454 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1455 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1456 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1457 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1458 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1459 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1460 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1461 wq_attr->log_hairpin_num_packets); 1462 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1463 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1464 wq_attr->single_wqe_log_num_of_strides); 1465 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1466 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1467 wq_attr->single_stride_log_num_of_bytes); 1468 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1469 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1470 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1471 } 1472 1473 /** 1474 * Create RQ using DevX API. 1475 * 1476 * @param[in] ctx 1477 * Context returned from mlx5 open_device() glue function. 1478 * @param [in] rq_attr 1479 * Pointer to create RQ attributes structure. 1480 * @param [in] socket 1481 * CPU socket ID for allocations. 1482 * 1483 * @return 1484 * The DevX object created, NULL otherwise and rte_errno is set. 1485 */ 1486 struct mlx5_devx_obj * 1487 mlx5_devx_cmd_create_rq(void *ctx, 1488 struct mlx5_devx_create_rq_attr *rq_attr, 1489 int socket) 1490 { 1491 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1492 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1493 void *rq_ctx, *wq_ctx; 1494 struct mlx5_devx_wq_attr *wq_attr; 1495 struct mlx5_devx_obj *rq = NULL; 1496 1497 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1498 if (!rq) { 1499 DRV_LOG(ERR, "Failed to allocate RQ data"); 1500 rte_errno = ENOMEM; 1501 return NULL; 1502 } 1503 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1504 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1505 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1506 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1507 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1508 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1509 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1510 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1511 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1512 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1513 MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type); 1514 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1515 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1516 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1517 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1518 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1519 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1520 wq_attr = &rq_attr->wq_attr; 1521 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1522 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1523 out, sizeof(out)); 1524 if (!rq->obj) { 1525 DEVX_DRV_LOG(ERR, out, "create RQ", NULL, 0); 1526 mlx5_free(rq); 1527 return NULL; 1528 } 1529 rq->id = MLX5_GET(create_rq_out, out, rqn); 1530 return rq; 1531 } 1532 1533 /** 1534 * Modify RQ using DevX API. 1535 * 1536 * @param[in] rq 1537 * Pointer to RQ object structure. 1538 * @param [in] rq_attr 1539 * Pointer to modify RQ attributes structure. 1540 * 1541 * @return 1542 * 0 on success, a negative errno value otherwise and rte_errno is set. 1543 */ 1544 int 1545 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1546 struct mlx5_devx_modify_rq_attr *rq_attr) 1547 { 1548 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1549 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1550 void *rq_ctx, *wq_ctx; 1551 int ret; 1552 1553 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1554 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1555 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1556 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1557 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1558 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1559 if (rq_attr->modify_bitmask & 1560 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1561 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1562 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1563 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1564 if (rq_attr->modify_bitmask & 1565 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1566 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1567 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1568 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1569 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1570 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1571 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1572 } 1573 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1574 out, sizeof(out)); 1575 if (ret) { 1576 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1577 rte_errno = errno; 1578 return -errno; 1579 } 1580 return ret; 1581 } 1582 1583 /** 1584 * Create RMP using DevX API. 1585 * 1586 * @param[in] ctx 1587 * Context returned from mlx5 open_device() glue function. 1588 * @param [in] rmp_attr 1589 * Pointer to create RMP attributes structure. 1590 * @param [in] socket 1591 * CPU socket ID for allocations. 1592 * 1593 * @return 1594 * The DevX object created, NULL otherwise and rte_errno is set. 1595 */ 1596 struct mlx5_devx_obj * 1597 mlx5_devx_cmd_create_rmp(void *ctx, 1598 struct mlx5_devx_create_rmp_attr *rmp_attr, 1599 int socket) 1600 { 1601 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0}; 1602 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0}; 1603 void *rmp_ctx, *wq_ctx; 1604 struct mlx5_devx_wq_attr *wq_attr; 1605 struct mlx5_devx_obj *rmp = NULL; 1606 1607 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket); 1608 if (!rmp) { 1609 DRV_LOG(ERR, "Failed to allocate RMP data"); 1610 rte_errno = ENOMEM; 1611 return NULL; 1612 } 1613 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP); 1614 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx); 1615 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state); 1616 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe, 1617 rmp_attr->basic_cyclic_rcv_wqe); 1618 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq); 1619 wq_attr = &rmp_attr->wq_attr; 1620 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1621 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1622 sizeof(out)); 1623 if (!rmp->obj) { 1624 DEVX_DRV_LOG(ERR, out, "create RMP", NULL, 0); 1625 mlx5_free(rmp); 1626 return NULL; 1627 } 1628 rmp->id = MLX5_GET(create_rmp_out, out, rmpn); 1629 return rmp; 1630 } 1631 1632 /* 1633 * Create TIR using DevX API. 1634 * 1635 * @param[in] ctx 1636 * Context returned from mlx5 open_device() glue function. 1637 * @param [in] tir_attr 1638 * Pointer to TIR attributes structure. 1639 * 1640 * @return 1641 * The DevX object created, NULL otherwise and rte_errno is set. 1642 */ 1643 struct mlx5_devx_obj * 1644 mlx5_devx_cmd_create_tir(void *ctx, 1645 struct mlx5_devx_tir_attr *tir_attr) 1646 { 1647 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1648 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1649 void *tir_ctx, *outer, *inner, *rss_key; 1650 struct mlx5_devx_obj *tir = NULL; 1651 1652 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1653 if (!tir) { 1654 DRV_LOG(ERR, "Failed to allocate TIR data"); 1655 rte_errno = ENOMEM; 1656 return NULL; 1657 } 1658 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1659 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1660 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1661 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1662 tir_attr->lro_timeout_period_usecs); 1663 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1664 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1665 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1666 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1667 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1668 tir_attr->tunneled_offload_en); 1669 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1670 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1671 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1672 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1673 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1674 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1675 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1676 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1677 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1678 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1679 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1680 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1681 tir_attr->rx_hash_field_selector_outer.selected_fields); 1682 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1683 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1684 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1685 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1686 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1687 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1688 tir_attr->rx_hash_field_selector_inner.selected_fields); 1689 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1690 out, sizeof(out)); 1691 if (!tir->obj) { 1692 DEVX_DRV_LOG(ERR, out, "create TIR", NULL, 0); 1693 mlx5_free(tir); 1694 return NULL; 1695 } 1696 tir->id = MLX5_GET(create_tir_out, out, tirn); 1697 return tir; 1698 } 1699 1700 /** 1701 * Modify TIR using DevX API. 1702 * 1703 * @param[in] tir 1704 * Pointer to TIR DevX object structure. 1705 * @param [in] modify_tir_attr 1706 * Pointer to TIR modification attributes structure. 1707 * 1708 * @return 1709 * 0 on success, a negative errno value otherwise and rte_errno is set. 1710 */ 1711 int 1712 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1713 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1714 { 1715 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1716 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1717 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1718 void *tir_ctx; 1719 int ret; 1720 1721 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1722 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1723 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1724 modify_tir_attr->modify_bitmask); 1725 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1726 if (modify_tir_attr->modify_bitmask & 1727 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1728 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1729 tir_attr->lro_timeout_period_usecs); 1730 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1731 tir_attr->lro_enable_mask); 1732 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1733 tir_attr->lro_max_msg_sz); 1734 } 1735 if (modify_tir_attr->modify_bitmask & 1736 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1737 MLX5_SET(tirc, tir_ctx, indirect_table, 1738 tir_attr->indirect_table); 1739 if (modify_tir_attr->modify_bitmask & 1740 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1741 int i; 1742 void *outer, *inner; 1743 1744 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1745 tir_attr->rx_hash_symmetric); 1746 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1747 for (i = 0; i < 10; i++) { 1748 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1749 tir_attr->rx_hash_toeplitz_key[i]); 1750 } 1751 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1752 rx_hash_field_selector_outer); 1753 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1754 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1755 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1756 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1757 MLX5_SET 1758 (rx_hash_field_select, outer, selected_fields, 1759 tir_attr->rx_hash_field_selector_outer.selected_fields); 1760 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1761 rx_hash_field_selector_inner); 1762 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1763 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1764 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1765 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1766 MLX5_SET 1767 (rx_hash_field_select, inner, selected_fields, 1768 tir_attr->rx_hash_field_selector_inner.selected_fields); 1769 } 1770 if (modify_tir_attr->modify_bitmask & 1771 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1772 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1773 } 1774 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1775 out, sizeof(out)); 1776 if (ret) { 1777 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1778 rte_errno = errno; 1779 return -errno; 1780 } 1781 return ret; 1782 } 1783 1784 /** 1785 * Create RQT using DevX API. 1786 * 1787 * @param[in] ctx 1788 * Context returned from mlx5 open_device() glue function. 1789 * @param [in] rqt_attr 1790 * Pointer to RQT attributes structure. 1791 * 1792 * @return 1793 * The DevX object created, NULL otherwise and rte_errno is set. 1794 */ 1795 struct mlx5_devx_obj * 1796 mlx5_devx_cmd_create_rqt(void *ctx, 1797 struct mlx5_devx_rqt_attr *rqt_attr) 1798 { 1799 uint32_t *in = NULL; 1800 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1801 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1802 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1803 void *rqt_ctx; 1804 struct mlx5_devx_obj *rqt = NULL; 1805 int i; 1806 1807 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1808 if (!in) { 1809 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1810 rte_errno = ENOMEM; 1811 return NULL; 1812 } 1813 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1814 if (!rqt) { 1815 DRV_LOG(ERR, "Failed to allocate RQT data"); 1816 rte_errno = ENOMEM; 1817 mlx5_free(in); 1818 return NULL; 1819 } 1820 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1821 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1822 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1823 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1824 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1825 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1826 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1827 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1828 mlx5_free(in); 1829 if (!rqt->obj) { 1830 DEVX_DRV_LOG(ERR, out, "create RQT", NULL, 0); 1831 mlx5_free(rqt); 1832 return NULL; 1833 } 1834 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1835 return rqt; 1836 } 1837 1838 /** 1839 * Modify RQT using DevX API. 1840 * 1841 * @param[in] rqt 1842 * Pointer to RQT DevX object structure. 1843 * @param [in] rqt_attr 1844 * Pointer to RQT attributes structure. 1845 * 1846 * @return 1847 * 0 on success, a negative errno value otherwise and rte_errno is set. 1848 */ 1849 int 1850 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1851 struct mlx5_devx_rqt_attr *rqt_attr) 1852 { 1853 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1854 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1855 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1856 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1857 void *rqt_ctx; 1858 int i; 1859 int ret; 1860 1861 if (!in) { 1862 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1863 rte_errno = ENOMEM; 1864 return -ENOMEM; 1865 } 1866 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1867 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1868 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1869 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1870 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1871 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1872 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1873 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1874 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1875 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1876 mlx5_free(in); 1877 if (ret) { 1878 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1879 rte_errno = errno; 1880 return -rte_errno; 1881 } 1882 return ret; 1883 } 1884 1885 /** 1886 * Create SQ using DevX API. 1887 * 1888 * @param[in] ctx 1889 * Context returned from mlx5 open_device() glue function. 1890 * @param [in] sq_attr 1891 * Pointer to SQ attributes structure. 1892 * @param [in] socket 1893 * CPU socket ID for allocations. 1894 * 1895 * @return 1896 * The DevX object created, NULL otherwise and rte_errno is set. 1897 **/ 1898 struct mlx5_devx_obj * 1899 mlx5_devx_cmd_create_sq(void *ctx, 1900 struct mlx5_devx_create_sq_attr *sq_attr) 1901 { 1902 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1903 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1904 void *sq_ctx; 1905 void *wq_ctx; 1906 struct mlx5_devx_wq_attr *wq_attr; 1907 struct mlx5_devx_obj *sq = NULL; 1908 1909 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1910 if (!sq) { 1911 DRV_LOG(ERR, "Failed to allocate SQ data"); 1912 rte_errno = ENOMEM; 1913 return NULL; 1914 } 1915 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1916 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1917 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1918 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1919 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1920 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1921 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1922 sq_attr->allow_multi_pkt_send_wqe); 1923 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1924 sq_attr->min_wqe_inline_mode); 1925 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1926 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1927 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1928 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1929 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1930 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1931 MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type); 1932 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1933 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1934 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1935 sq_attr->packet_pacing_rate_limit_index); 1936 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1937 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1938 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1939 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1940 wq_attr = &sq_attr->wq_attr; 1941 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1942 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1943 out, sizeof(out)); 1944 if (!sq->obj) { 1945 DEVX_DRV_LOG(ERR, out, "create SQ", NULL, 0); 1946 mlx5_free(sq); 1947 return NULL; 1948 } 1949 sq->id = MLX5_GET(create_sq_out, out, sqn); 1950 return sq; 1951 } 1952 1953 /** 1954 * Modify SQ using DevX API. 1955 * 1956 * @param[in] sq 1957 * Pointer to SQ object structure. 1958 * @param [in] sq_attr 1959 * Pointer to SQ attributes structure. 1960 * 1961 * @return 1962 * 0 on success, a negative errno value otherwise and rte_errno is set. 1963 */ 1964 int 1965 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1966 struct mlx5_devx_modify_sq_attr *sq_attr) 1967 { 1968 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1969 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1970 void *sq_ctx; 1971 int ret; 1972 1973 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1974 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1975 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1976 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1977 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1978 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1979 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1980 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1981 out, sizeof(out)); 1982 if (ret) { 1983 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1984 rte_errno = errno; 1985 return -rte_errno; 1986 } 1987 return ret; 1988 } 1989 1990 /** 1991 * Create TIS using DevX API. 1992 * 1993 * @param[in] ctx 1994 * Context returned from mlx5 open_device() glue function. 1995 * @param [in] tis_attr 1996 * Pointer to TIS attributes structure. 1997 * 1998 * @return 1999 * The DevX object created, NULL otherwise and rte_errno is set. 2000 */ 2001 struct mlx5_devx_obj * 2002 mlx5_devx_cmd_create_tis(void *ctx, 2003 struct mlx5_devx_tis_attr *tis_attr) 2004 { 2005 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 2006 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 2007 struct mlx5_devx_obj *tis = NULL; 2008 void *tis_ctx; 2009 2010 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 2011 if (!tis) { 2012 DRV_LOG(ERR, "Failed to allocate TIS object"); 2013 rte_errno = ENOMEM; 2014 return NULL; 2015 } 2016 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 2017 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 2018 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 2019 tis_attr->strict_lag_tx_port_affinity); 2020 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 2021 tis_attr->lag_tx_port_affinity); 2022 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 2023 MLX5_SET(tisc, tis_ctx, transport_domain, 2024 tis_attr->transport_domain); 2025 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2026 out, sizeof(out)); 2027 if (!tis->obj) { 2028 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 2029 mlx5_free(tis); 2030 return NULL; 2031 } 2032 tis->id = MLX5_GET(create_tis_out, out, tisn); 2033 return tis; 2034 } 2035 2036 /** 2037 * Create transport domain using DevX API. 2038 * 2039 * @param[in] ctx 2040 * Context returned from mlx5 open_device() glue function. 2041 * @return 2042 * The DevX object created, NULL otherwise and rte_errno is set. 2043 */ 2044 struct mlx5_devx_obj * 2045 mlx5_devx_cmd_create_td(void *ctx) 2046 { 2047 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 2048 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 2049 struct mlx5_devx_obj *td = NULL; 2050 2051 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 2052 if (!td) { 2053 DRV_LOG(ERR, "Failed to allocate TD object"); 2054 rte_errno = ENOMEM; 2055 return NULL; 2056 } 2057 MLX5_SET(alloc_transport_domain_in, in, opcode, 2058 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 2059 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2060 out, sizeof(out)); 2061 if (!td->obj) { 2062 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 2063 mlx5_free(td); 2064 return NULL; 2065 } 2066 td->id = MLX5_GET(alloc_transport_domain_out, out, 2067 transport_domain); 2068 return td; 2069 } 2070 2071 /** 2072 * Dump all flows to file. 2073 * 2074 * @param[in] fdb_domain 2075 * FDB domain. 2076 * @param[in] rx_domain 2077 * RX domain. 2078 * @param[in] tx_domain 2079 * TX domain. 2080 * @param[out] file 2081 * Pointer to file stream. 2082 * 2083 * @return 2084 * 0 on success, a negative value otherwise. 2085 */ 2086 int 2087 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 2088 void *rx_domain __rte_unused, 2089 void *tx_domain __rte_unused, FILE *file __rte_unused) 2090 { 2091 int ret = 0; 2092 2093 #ifdef HAVE_MLX5_DR_FLOW_DUMP 2094 if (fdb_domain) { 2095 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 2096 if (ret) 2097 return ret; 2098 } 2099 MLX5_ASSERT(rx_domain); 2100 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 2101 if (ret) 2102 return ret; 2103 MLX5_ASSERT(tx_domain); 2104 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 2105 #else 2106 ret = ENOTSUP; 2107 #endif 2108 return -ret; 2109 } 2110 2111 int 2112 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 2113 FILE *file __rte_unused) 2114 { 2115 int ret = 0; 2116 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 2117 if (rule_info) 2118 ret = mlx5_glue->dr_dump_rule(file, rule_info); 2119 #else 2120 ret = ENOTSUP; 2121 #endif 2122 return -ret; 2123 } 2124 2125 /* 2126 * Create CQ using DevX API. 2127 * 2128 * @param[in] ctx 2129 * Context returned from mlx5 open_device() glue function. 2130 * @param [in] attr 2131 * Pointer to CQ attributes structure. 2132 * 2133 * @return 2134 * The DevX object created, NULL otherwise and rte_errno is set. 2135 */ 2136 struct mlx5_devx_obj * 2137 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 2138 { 2139 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 2140 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 2141 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2142 sizeof(*cq_obj), 2143 0, SOCKET_ID_ANY); 2144 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 2145 2146 if (!cq_obj) { 2147 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 2148 rte_errno = ENOMEM; 2149 return NULL; 2150 } 2151 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 2152 if (attr->db_umem_valid) { 2153 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 2154 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 2155 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 2156 } else { 2157 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 2158 } 2159 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 2160 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 2161 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 2162 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 2163 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 2164 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2165 MLX5_SET(cqc, cqctx, log_page_size, 2166 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2167 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 2168 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 2169 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 2170 MLX5_SET(cqc, cqctx, cqe_comp_layout, !!attr->cqe_comp_layout); 2171 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 2172 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 2173 attr->mini_cqe_res_format_ext); 2174 if (attr->q_umem_valid) { 2175 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 2176 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 2177 MLX5_SET64(create_cq_in, in, cq_umem_offset, 2178 attr->q_umem_offset); 2179 } 2180 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2181 sizeof(out)); 2182 if (!cq_obj->obj) { 2183 DEVX_DRV_LOG(ERR, out, "create CQ", NULL, 0); 2184 mlx5_free(cq_obj); 2185 return NULL; 2186 } 2187 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 2188 return cq_obj; 2189 } 2190 2191 /** 2192 * Create VIRTQ using DevX API. 2193 * 2194 * @param[in] ctx 2195 * Context returned from mlx5 open_device() glue function. 2196 * @param [in] attr 2197 * Pointer to VIRTQ attributes structure. 2198 * 2199 * @return 2200 * The DevX object created, NULL otherwise and rte_errno is set. 2201 */ 2202 struct mlx5_devx_obj * 2203 mlx5_devx_cmd_create_virtq(void *ctx, 2204 struct mlx5_devx_virtq_attr *attr) 2205 { 2206 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2207 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2208 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2209 sizeof(*virtq_obj), 2210 0, SOCKET_ID_ANY); 2211 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2212 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2213 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2214 2215 if (!virtq_obj) { 2216 DRV_LOG(ERR, "Failed to allocate virtq data."); 2217 rte_errno = ENOMEM; 2218 return NULL; 2219 } 2220 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2221 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2222 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2223 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2224 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2225 attr->hw_available_index); 2226 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 2227 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2228 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2229 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2230 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2231 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2232 attr->virtio_version_1_0); 2233 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2234 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2235 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2236 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2237 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 2238 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2239 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 2240 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2241 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 2242 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 2243 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 2244 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 2245 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 2246 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 2247 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 2248 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 2249 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 2250 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 2251 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 2252 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 2253 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 2254 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 2255 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 2256 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2257 sizeof(out)); 2258 if (!virtq_obj->obj) { 2259 DEVX_DRV_LOG(ERR, out, "create VIRTQ", NULL, 0); 2260 mlx5_free(virtq_obj); 2261 return NULL; 2262 } 2263 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2264 return virtq_obj; 2265 } 2266 2267 /** 2268 * Modify VIRTQ using DevX API. 2269 * 2270 * @param[in] virtq_obj 2271 * Pointer to virtq object structure. 2272 * @param [in] attr 2273 * Pointer to modify virtq attributes structure. 2274 * 2275 * @return 2276 * 0 on success, a negative errno value otherwise and rte_errno is set. 2277 */ 2278 int 2279 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 2280 struct mlx5_devx_virtq_attr *attr) 2281 { 2282 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2283 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2284 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2285 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2286 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2287 int ret; 2288 2289 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2290 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 2291 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2292 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2293 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2294 MLX5_SET64(virtio_net_q, virtq, modify_field_select, 2295 attr->mod_fields_bitmap); 2296 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2297 if (!attr->mod_fields_bitmap) { 2298 DRV_LOG(ERR, "Failed to modify VIRTQ for no type set."); 2299 rte_errno = EINVAL; 2300 return -rte_errno; 2301 } 2302 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE) 2303 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 2304 if (attr->mod_fields_bitmap & 2305 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) { 2306 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 2307 attr->dirty_bitmap_mkey); 2308 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 2309 attr->dirty_bitmap_addr); 2310 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 2311 attr->dirty_bitmap_size); 2312 } 2313 if (attr->mod_fields_bitmap & 2314 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE) 2315 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 2316 attr->dirty_bitmap_dump_enable); 2317 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) { 2318 MLX5_SET(virtio_q, virtctx, queue_period_mode, 2319 attr->hw_latency_mode); 2320 MLX5_SET(virtio_q, virtctx, queue_period_us, 2321 attr->hw_max_latency_us); 2322 MLX5_SET(virtio_q, virtctx, queue_max_count, 2323 attr->hw_max_pending_comp); 2324 } 2325 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) { 2326 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2327 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2328 MLX5_SET64(virtio_q, virtctx, available_addr, 2329 attr->available_addr); 2330 } 2331 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX) 2332 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2333 attr->hw_available_index); 2334 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX) 2335 MLX5_SET16(virtio_net_q, virtq, hw_used_index, 2336 attr->hw_used_index); 2337 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE) 2338 MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type); 2339 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0) 2340 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2341 attr->virtio_version_1_0); 2342 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY) 2343 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2344 if (attr->mod_fields_bitmap & 2345 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) { 2346 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2347 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2348 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2349 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2350 } 2351 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) { 2352 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2353 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2354 } 2355 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 2356 out, sizeof(out)); 2357 if (ret) { 2358 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2359 rte_errno = errno; 2360 return -rte_errno; 2361 } 2362 return ret; 2363 } 2364 2365 /** 2366 * Query VIRTQ using DevX API. 2367 * 2368 * @param[in] virtq_obj 2369 * Pointer to virtq object structure. 2370 * @param [in/out] attr 2371 * Pointer to virtq attributes structure. 2372 * 2373 * @return 2374 * 0 on success, a negative errno value otherwise and rte_errno is set. 2375 */ 2376 int 2377 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 2378 struct mlx5_devx_virtq_attr *attr) 2379 { 2380 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2381 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 2382 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 2383 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 2384 int ret; 2385 2386 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2387 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2388 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2389 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2390 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2391 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2392 out, sizeof(out)); 2393 if (ret) { 2394 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2395 rte_errno = errno; 2396 return -errno; 2397 } 2398 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2399 hw_available_index); 2400 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2401 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2402 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2403 virtio_q_context.error_type); 2404 return ret; 2405 } 2406 2407 /** 2408 * Create QP using DevX API. 2409 * 2410 * @param[in] ctx 2411 * Context returned from mlx5 open_device() glue function. 2412 * @param [in] attr 2413 * Pointer to QP attributes structure. 2414 * 2415 * @return 2416 * The DevX object created, NULL otherwise and rte_errno is set. 2417 */ 2418 struct mlx5_devx_obj * 2419 mlx5_devx_cmd_create_qp(void *ctx, 2420 struct mlx5_devx_qp_attr *attr) 2421 { 2422 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2423 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2424 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2425 sizeof(*qp_obj), 2426 0, SOCKET_ID_ANY); 2427 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2428 2429 if (!qp_obj) { 2430 DRV_LOG(ERR, "Failed to allocate QP data."); 2431 rte_errno = ENOMEM; 2432 return NULL; 2433 } 2434 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2435 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2436 MLX5_SET(qpc, qpc, pd, attr->pd); 2437 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2438 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2439 if (attr->uar_index) { 2440 if (attr->mmo) { 2441 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2442 in, qpc_extension_and_pas_list); 2443 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2444 qpc_ext_and_pas_list, qpc_data_extension); 2445 2446 MLX5_SET(create_qp_in, in, qpc_ext, 1); 2447 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2448 } 2449 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2450 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2451 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2452 MLX5_SET(qpc, qpc, log_page_size, 2453 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2454 if (attr->num_of_send_wqbbs) { 2455 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs)); 2456 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2457 MLX5_SET(qpc, qpc, log_sq_size, 2458 rte_log2_u32(attr->num_of_send_wqbbs)); 2459 } else { 2460 MLX5_SET(qpc, qpc, no_sq, 1); 2461 } 2462 if (attr->num_of_receive_wqes) { 2463 MLX5_ASSERT(RTE_IS_POWER_OF_2( 2464 attr->num_of_receive_wqes)); 2465 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2466 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2467 MLX5_LOG_RQ_STRIDE_SHIFT); 2468 MLX5_SET(qpc, qpc, log_rq_size, 2469 rte_log2_u32(attr->num_of_receive_wqes)); 2470 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2471 } else { 2472 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2473 } 2474 if (attr->dbr_umem_valid) { 2475 MLX5_SET(qpc, qpc, dbr_umem_valid, 2476 attr->dbr_umem_valid); 2477 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2478 } 2479 if (attr->cd_master) 2480 MLX5_SET(qpc, qpc, cd_master, attr->cd_master); 2481 if (attr->cd_slave_send) 2482 MLX5_SET(qpc, qpc, cd_slave_send, attr->cd_slave_send); 2483 if (attr->cd_slave_recv) 2484 MLX5_SET(qpc, qpc, cd_slave_receive, attr->cd_slave_recv); 2485 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2486 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2487 attr->wq_umem_offset); 2488 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2489 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2490 } else { 2491 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2492 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2493 MLX5_SET(qpc, qpc, no_sq, 1); 2494 } 2495 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2496 sizeof(out)); 2497 if (!qp_obj->obj) { 2498 DEVX_DRV_LOG(ERR, out, "create QP", NULL, 0); 2499 mlx5_free(qp_obj); 2500 return NULL; 2501 } 2502 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2503 return qp_obj; 2504 } 2505 2506 /** 2507 * Modify QP using DevX API. 2508 * Currently supports only force loop-back QP. 2509 * 2510 * @param[in] qp 2511 * Pointer to QP object structure. 2512 * @param [in] qp_st_mod_op 2513 * The QP state modification operation. 2514 * @param [in] remote_qp_id 2515 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2516 * 2517 * @return 2518 * 0 on success, a negative errno value otherwise and rte_errno is set. 2519 */ 2520 int 2521 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2522 uint32_t remote_qp_id) 2523 { 2524 union { 2525 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2526 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2527 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2528 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)]; 2529 } in; 2530 union { 2531 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2532 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2533 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2534 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)]; 2535 } out; 2536 void *qpc; 2537 int ret; 2538 unsigned int inlen; 2539 unsigned int outlen; 2540 2541 memset(&in, 0, sizeof(in)); 2542 memset(&out, 0, sizeof(out)); 2543 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2544 switch (qp_st_mod_op) { 2545 case MLX5_CMD_OP_RST2INIT_QP: 2546 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2547 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2548 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2549 MLX5_SET(qpc, qpc, rre, 1); 2550 MLX5_SET(qpc, qpc, rwe, 1); 2551 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2552 inlen = sizeof(in.rst2init); 2553 outlen = sizeof(out.rst2init); 2554 break; 2555 case MLX5_CMD_OP_INIT2RTR_QP: 2556 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2557 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2558 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2559 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2560 MLX5_SET(qpc, qpc, mtu, 1); 2561 MLX5_SET(qpc, qpc, log_msg_max, 30); 2562 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2563 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2564 inlen = sizeof(in.init2rtr); 2565 outlen = sizeof(out.init2rtr); 2566 break; 2567 case MLX5_CMD_OP_RTR2RTS_QP: 2568 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2569 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2570 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16); 2571 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2572 MLX5_SET(qpc, qpc, retry_count, 7); 2573 MLX5_SET(qpc, qpc, rnr_retry, 7); 2574 inlen = sizeof(in.rtr2rts); 2575 outlen = sizeof(out.rtr2rts); 2576 break; 2577 case MLX5_CMD_OP_QP_2RST: 2578 MLX5_SET(2rst_qp_in, &in, qpn, qp->id); 2579 inlen = sizeof(in.qp2rst); 2580 outlen = sizeof(out.qp2rst); 2581 break; 2582 default: 2583 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2584 qp_st_mod_op); 2585 rte_errno = EINVAL; 2586 return -rte_errno; 2587 } 2588 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2589 if (ret) { 2590 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2591 rte_errno = errno; 2592 return -rte_errno; 2593 } 2594 return ret; 2595 } 2596 2597 struct mlx5_devx_obj * 2598 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2599 { 2600 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2601 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2602 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2603 sizeof(*couners_obj), 0, 2604 SOCKET_ID_ANY); 2605 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2606 2607 if (!couners_obj) { 2608 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2609 rte_errno = ENOMEM; 2610 return NULL; 2611 } 2612 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2613 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2614 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2615 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2616 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2617 sizeof(out)); 2618 if (!couners_obj->obj) { 2619 DEVX_DRV_LOG(ERR, out, "create virtio queue counters Obj", NULL, 2620 0); 2621 mlx5_free(couners_obj); 2622 return NULL; 2623 } 2624 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2625 return couners_obj; 2626 } 2627 2628 int 2629 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2630 struct mlx5_devx_virtio_q_couners_attr *attr) 2631 { 2632 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2633 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2634 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2635 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2636 virtio_q_counters); 2637 int ret; 2638 2639 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2640 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2641 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2642 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2643 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2644 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2645 sizeof(out)); 2646 if (ret) { 2647 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2648 rte_errno = errno; 2649 return -errno; 2650 } 2651 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2652 received_desc); 2653 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2654 completed_desc); 2655 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2656 error_cqes); 2657 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2658 bad_desc_errors); 2659 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2660 exceed_max_chain); 2661 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2662 invalid_buffer); 2663 return ret; 2664 } 2665 2666 /** 2667 * Create general object of type FLOW_HIT_ASO using DevX API. 2668 * 2669 * @param[in] ctx 2670 * Context returned from mlx5 open_device() glue function. 2671 * @param [in] pd 2672 * PD value to associate the FLOW_HIT_ASO object with. 2673 * 2674 * @return 2675 * The DevX object created, NULL otherwise and rte_errno is set. 2676 */ 2677 struct mlx5_devx_obj * 2678 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2679 { 2680 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2681 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2682 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2683 void *ptr = NULL; 2684 2685 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2686 0, SOCKET_ID_ANY); 2687 if (!flow_hit_aso_obj) { 2688 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2689 rte_errno = ENOMEM; 2690 return NULL; 2691 } 2692 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2693 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2694 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2695 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2696 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2697 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2698 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2699 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2700 out, sizeof(out)); 2701 if (!flow_hit_aso_obj->obj) { 2702 DEVX_DRV_LOG(ERR, out, "create FLOW_HIT_ASO", NULL, 0); 2703 mlx5_free(flow_hit_aso_obj); 2704 return NULL; 2705 } 2706 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2707 return flow_hit_aso_obj; 2708 } 2709 2710 /* 2711 * Create PD using DevX API. 2712 * 2713 * @param[in] ctx 2714 * Context returned from mlx5 open_device() glue function. 2715 * 2716 * @return 2717 * The DevX object created, NULL otherwise and rte_errno is set. 2718 */ 2719 struct mlx5_devx_obj * 2720 mlx5_devx_cmd_alloc_pd(void *ctx) 2721 { 2722 struct mlx5_devx_obj *ppd = 2723 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2724 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2725 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2726 2727 if (!ppd) { 2728 DRV_LOG(ERR, "Failed to allocate PD data."); 2729 rte_errno = ENOMEM; 2730 return NULL; 2731 } 2732 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2733 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2734 out, sizeof(out)); 2735 if (!ppd->obj) { 2736 mlx5_free(ppd); 2737 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2738 rte_errno = errno; 2739 return NULL; 2740 } 2741 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2742 return ppd; 2743 } 2744 2745 /** 2746 * Create general object of type FLOW_METER_ASO using DevX API. 2747 * 2748 * @param[in] ctx 2749 * Context returned from mlx5 open_device() glue function. 2750 * @param [in] pd 2751 * PD value to associate the FLOW_METER_ASO object with. 2752 * @param [in] log_obj_size 2753 * log_obj_size define to allocate number of 2 * meters 2754 * in one FLOW_METER_ASO object. 2755 * 2756 * @return 2757 * The DevX object created, NULL otherwise and rte_errno is set. 2758 */ 2759 struct mlx5_devx_obj * 2760 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2761 uint32_t log_obj_size) 2762 { 2763 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2764 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2765 struct mlx5_devx_obj *flow_meter_aso_obj; 2766 void *ptr; 2767 2768 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2769 sizeof(*flow_meter_aso_obj), 2770 0, SOCKET_ID_ANY); 2771 if (!flow_meter_aso_obj) { 2772 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2773 rte_errno = ENOMEM; 2774 return NULL; 2775 } 2776 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2777 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2778 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2779 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2780 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2781 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2782 log_obj_size); 2783 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2784 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2785 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2786 ctx, in, sizeof(in), 2787 out, sizeof(out)); 2788 if (!flow_meter_aso_obj->obj) { 2789 DEVX_DRV_LOG(ERR, out, "create FLOW_METTER_ASO", NULL, 0); 2790 mlx5_free(flow_meter_aso_obj); 2791 return NULL; 2792 } 2793 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2794 out, obj_id); 2795 return flow_meter_aso_obj; 2796 } 2797 2798 /* 2799 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2800 * 2801 * @param[in] ctx 2802 * Context returned from mlx5 open_device() glue function. 2803 * @param [in] pd 2804 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2805 * @param [in] log_obj_size 2806 * log_obj_size to allocate its power of 2 * objects 2807 * in one CONN_TRACK_OFFLOAD bulk allocation. 2808 * 2809 * @return 2810 * The DevX object created, NULL otherwise and rte_errno is set. 2811 */ 2812 struct mlx5_devx_obj * 2813 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2814 uint32_t log_obj_size) 2815 { 2816 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2817 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2818 struct mlx5_devx_obj *ct_aso_obj; 2819 void *ptr; 2820 2821 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2822 0, SOCKET_ID_ANY); 2823 if (!ct_aso_obj) { 2824 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2825 rte_errno = ENOMEM; 2826 return NULL; 2827 } 2828 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2829 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2830 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2831 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2832 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2833 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2834 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2835 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2836 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2837 out, sizeof(out)); 2838 if (!ct_aso_obj->obj) { 2839 DEVX_DRV_LOG(ERR, out, "create CONN_TRACK_OFFLOAD", NULL, 0); 2840 mlx5_free(ct_aso_obj); 2841 return NULL; 2842 } 2843 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2844 return ct_aso_obj; 2845 } 2846 2847 /** 2848 * Create general object of type GENEVE TLV option using DevX API. 2849 * 2850 * @param[in] ctx 2851 * Context returned from mlx5 open_device() glue function. 2852 * @param [in] class 2853 * TLV option variable value of class 2854 * @param [in] type 2855 * TLV option variable value of type 2856 * @param [in] len 2857 * TLV option variable value of len 2858 * 2859 * @return 2860 * The DevX object created, NULL otherwise and rte_errno is set. 2861 */ 2862 struct mlx5_devx_obj * 2863 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2864 uint16_t class, uint8_t type, uint8_t len) 2865 { 2866 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2867 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2868 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2869 sizeof(*geneve_tlv_opt_obj), 2870 0, SOCKET_ID_ANY); 2871 2872 if (!geneve_tlv_opt_obj) { 2873 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2874 rte_errno = ENOMEM; 2875 return NULL; 2876 } 2877 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2878 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2879 geneve_tlv_opt); 2880 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2881 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2882 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2883 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2884 MLX5_SET(geneve_tlv_option, opt, option_class, 2885 rte_be_to_cpu_16(class)); 2886 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2887 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2888 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2889 sizeof(in), out, sizeof(out)); 2890 if (!geneve_tlv_opt_obj->obj) { 2891 DEVX_DRV_LOG(ERR, out, "create GENEVE TLV", NULL, 0); 2892 mlx5_free(geneve_tlv_opt_obj); 2893 return NULL; 2894 } 2895 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2896 return geneve_tlv_opt_obj; 2897 } 2898 2899 int 2900 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2901 { 2902 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2903 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2904 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2905 int rc; 2906 void *rq_ctx; 2907 2908 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2909 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2910 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2911 if (rc) { 2912 rte_errno = errno; 2913 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2914 "rc = %d, errno = %d.", rc, errno); 2915 return -rc; 2916 }; 2917 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2918 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2919 return 0; 2920 #else 2921 (void)wq; 2922 (void)counter_set_id; 2923 return -ENOTSUP; 2924 #endif 2925 } 2926 2927 /* 2928 * Allocate queue counters via devx interface. 2929 * 2930 * @param[in] ctx 2931 * Context returned from mlx5 open_device() glue function. 2932 * 2933 * @return 2934 * Pointer to counter object on success, a NULL value otherwise and 2935 * rte_errno is set. 2936 */ 2937 struct mlx5_devx_obj * 2938 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2939 { 2940 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2941 SOCKET_ID_ANY); 2942 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2943 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2944 2945 if (!dcs) { 2946 rte_errno = ENOMEM; 2947 return NULL; 2948 } 2949 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2950 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2951 sizeof(out)); 2952 if (!dcs->obj) { 2953 DEVX_DRV_LOG(DEBUG, out, "create q counter set", NULL, 0); 2954 mlx5_free(dcs); 2955 return NULL; 2956 } 2957 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2958 return dcs; 2959 } 2960 2961 /** 2962 * Query queue counters values. 2963 * 2964 * @param[in] dcs 2965 * devx object of the queue counter set. 2966 * @param[in] clear 2967 * Whether hardware should clear the counters after the query or not. 2968 * @param[out] out_of_buffers 2969 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2970 * 2971 * @return 2972 * 0 on success, a negative value otherwise. 2973 */ 2974 int 2975 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2976 uint32_t *out_of_buffers) 2977 { 2978 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2979 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2980 int rc; 2981 2982 MLX5_SET(query_q_counter_in, in, opcode, 2983 MLX5_CMD_OP_QUERY_Q_COUNTER); 2984 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2985 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2986 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2987 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2988 sizeof(out)); 2989 if (rc) { 2990 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2991 rte_errno = rc; 2992 return -rc; 2993 } 2994 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2995 return 0; 2996 } 2997 2998 /** 2999 * Create general object of type DEK using DevX API. 3000 * 3001 * @param[in] ctx 3002 * Context returned from mlx5 open_device() glue function. 3003 * @param [in] attr 3004 * Pointer to DEK attributes structure. 3005 * 3006 * @return 3007 * The DevX object created, NULL otherwise and rte_errno is set. 3008 */ 3009 struct mlx5_devx_obj * 3010 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 3011 { 3012 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 3013 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3014 struct mlx5_devx_obj *dek_obj = NULL; 3015 void *ptr = NULL, *key_addr = NULL; 3016 3017 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 3018 0, SOCKET_ID_ANY); 3019 if (dek_obj == NULL) { 3020 DRV_LOG(ERR, "Failed to allocate DEK object data"); 3021 rte_errno = ENOMEM; 3022 return NULL; 3023 } 3024 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 3025 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3026 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3027 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3028 MLX5_GENERAL_OBJ_TYPE_DEK); 3029 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 3030 MLX5_SET(dek, ptr, key_size, attr->key_size); 3031 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 3032 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 3033 MLX5_SET(dek, ptr, pd, attr->pd); 3034 MLX5_SET64(dek, ptr, opaque, attr->opaque); 3035 key_addr = MLX5_ADDR_OF(dek, ptr, key); 3036 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 3037 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3038 out, sizeof(out)); 3039 if (dek_obj->obj == NULL) { 3040 DEVX_DRV_LOG(ERR, out, "create DEK", NULL, 0); 3041 mlx5_free(dek_obj); 3042 return NULL; 3043 } 3044 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3045 return dek_obj; 3046 } 3047 3048 /** 3049 * Create general object of type IMPORT_KEK using DevX API. 3050 * 3051 * @param[in] ctx 3052 * Context returned from mlx5 open_device() glue function. 3053 * @param [in] attr 3054 * Pointer to IMPORT_KEK attributes structure. 3055 * 3056 * @return 3057 * The DevX object created, NULL otherwise and rte_errno is set. 3058 */ 3059 struct mlx5_devx_obj * 3060 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 3061 struct mlx5_devx_import_kek_attr *attr) 3062 { 3063 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 3064 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3065 struct mlx5_devx_obj *import_kek_obj = NULL; 3066 void *ptr = NULL, *key_addr = NULL; 3067 3068 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 3069 0, SOCKET_ID_ANY); 3070 if (import_kek_obj == NULL) { 3071 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 3072 rte_errno = ENOMEM; 3073 return NULL; 3074 } 3075 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 3076 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3077 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3078 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3079 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 3080 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 3081 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 3082 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 3083 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 3084 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3085 out, sizeof(out)); 3086 if (import_kek_obj->obj == NULL) { 3087 DEVX_DRV_LOG(ERR, out, "create IMPORT_KEK", NULL, 0); 3088 mlx5_free(import_kek_obj); 3089 return NULL; 3090 } 3091 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3092 return import_kek_obj; 3093 } 3094 3095 /** 3096 * Create general object of type CREDENTIAL using DevX API. 3097 * 3098 * @param[in] ctx 3099 * Context returned from mlx5 open_device() glue function. 3100 * @param [in] attr 3101 * Pointer to CREDENTIAL attributes structure. 3102 * 3103 * @return 3104 * The DevX object created, NULL otherwise and rte_errno is set. 3105 */ 3106 struct mlx5_devx_obj * 3107 mlx5_devx_cmd_create_credential_obj(void *ctx, 3108 struct mlx5_devx_credential_attr *attr) 3109 { 3110 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 3111 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3112 struct mlx5_devx_obj *credential_obj = NULL; 3113 void *ptr = NULL, *credential_addr = NULL; 3114 3115 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 3116 0, SOCKET_ID_ANY); 3117 if (credential_obj == NULL) { 3118 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 3119 rte_errno = ENOMEM; 3120 return NULL; 3121 } 3122 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 3123 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3124 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3125 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3126 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 3127 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 3128 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 3129 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 3130 memcpy(credential_addr, (void *)(attr->credential), 3131 MLX5_CRYPTO_CREDENTIAL_SIZE); 3132 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3133 out, sizeof(out)); 3134 if (credential_obj->obj == NULL) { 3135 DEVX_DRV_LOG(ERR, out, "create CREDENTIAL", NULL, 0); 3136 mlx5_free(credential_obj); 3137 return NULL; 3138 } 3139 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3140 return credential_obj; 3141 } 3142 3143 /** 3144 * Create general object of type CRYPTO_LOGIN using DevX API. 3145 * 3146 * @param[in] ctx 3147 * Context returned from mlx5 open_device() glue function. 3148 * @param [in] attr 3149 * Pointer to CRYPTO_LOGIN attributes structure. 3150 * 3151 * @return 3152 * The DevX object created, NULL otherwise and rte_errno is set. 3153 */ 3154 struct mlx5_devx_obj * 3155 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 3156 struct mlx5_devx_crypto_login_attr *attr) 3157 { 3158 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 3159 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3160 struct mlx5_devx_obj *crypto_login_obj = NULL; 3161 void *ptr = NULL, *credential_addr = NULL; 3162 3163 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 3164 0, SOCKET_ID_ANY); 3165 if (crypto_login_obj == NULL) { 3166 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 3167 rte_errno = ENOMEM; 3168 return NULL; 3169 } 3170 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 3171 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3172 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3173 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3174 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 3175 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 3176 MLX5_SET(crypto_login, ptr, credential_pointer, 3177 attr->credential_pointer); 3178 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 3179 attr->session_import_kek_ptr); 3180 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 3181 memcpy(credential_addr, (void *)(attr->credential), 3182 MLX5_CRYPTO_CREDENTIAL_SIZE); 3183 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3184 out, sizeof(out)); 3185 if (crypto_login_obj->obj == NULL) { 3186 DEVX_DRV_LOG(ERR, out, "create CRYPTO_LOGIN", NULL, 0); 3187 mlx5_free(crypto_login_obj); 3188 return NULL; 3189 } 3190 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3191 return crypto_login_obj; 3192 } 3193 3194 /** 3195 * Query LAG context. 3196 * 3197 * @param[in] ctx 3198 * Pointer to ibv_context, returned from mlx5dv_open_device. 3199 * @param[out] lag_ctx 3200 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 3201 * 3202 * @return 3203 * 0 on success, a negative value otherwise. 3204 */ 3205 int 3206 mlx5_devx_cmd_query_lag(void *ctx, 3207 struct mlx5_devx_lag_context *lag_ctx) 3208 { 3209 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 3210 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 3211 void *lctx; 3212 int rc; 3213 3214 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 3215 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 3216 if (rc) 3217 goto error; 3218 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 3219 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 3220 fdb_selection_mode); 3221 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 3222 port_select_mode); 3223 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 3224 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 3225 tx_remap_affinity_2); 3226 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 3227 tx_remap_affinity_1); 3228 return 0; 3229 error: 3230 rc = (rc > 0) ? -rc : rc; 3231 return rc; 3232 } 3233