1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /* FW writes status value to the OUT buffer at offset 00H */ 17 #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status) 18 /* FW writes syndrome value to the OUT buffer at offset 04H */ 19 #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome) 20 21 #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1)) 22 23 #define DEVX_DRV_LOG(level, out, reason, param, value) \ 24 do { \ 25 /* \ 26 * Some (old) GCC compilers like 7.5.0 and aarch64 GCC 7.1-2017.08 \ 27 * do not expand correctly when the macro invoked when the `param` \ 28 * is `NULL`. \ 29 * Use `local_param` to avoid direct `NULL` expansion. \ 30 */ \ 31 const char *local_param = (const char *)param; \ 32 \ 33 rte_errno = errno; \ 34 if (!local_param) { \ 35 DRV_LOG(level, \ 36 "DevX %s failed errno=%d status=%#x syndrome=%#x", \ 37 (reason), errno, MLX5_FW_STATUS((out)), \ 38 MLX5_FW_SYNDROME((out))); \ 39 } else { \ 40 DRV_LOG(level, \ 41 "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x",\ 42 (reason), local_param, (value), errno, \ 43 MLX5_FW_STATUS((out)), MLX5_FW_SYNDROME((out))); \ 44 } \ 45 } while (0) 46 47 static void * 48 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, 49 int *err, uint32_t flags) 50 { 51 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); 52 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); 53 int rc; 54 55 memset(in, 0, size_in); 56 memset(out, 0, size_out); 57 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 58 MLX5_SET(query_hca_cap_in, in, op_mod, flags); 59 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); 60 if (rc || MLX5_FW_STATUS(out)) { 61 DEVX_DRV_LOG(ERR, out, "HCA capabilities", "func", flags >> 1); 62 if (err) 63 *err = MLX5_DEVX_ERR_RC(rc); 64 return NULL; 65 } 66 if (err) 67 *err = 0; 68 return MLX5_ADDR_OF(query_hca_cap_out, out, capability); 69 } 70 71 /** 72 * Perform read access to the registers. Reads data from register 73 * and writes ones to the specified buffer. 74 * 75 * @param[in] ctx 76 * Context returned from mlx5 open_device() glue function. 77 * @param[in] reg_id 78 * Register identifier according to the PRM. 79 * @param[in] arg 80 * Register access auxiliary parameter according to the PRM. 81 * @param[out] data 82 * Pointer to the buffer to store read data. 83 * @param[in] dw_cnt 84 * Buffer size in double words. 85 * 86 * @return 87 * 0 on success, a negative value otherwise. 88 */ 89 int 90 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 91 uint32_t *data, uint32_t dw_cnt) 92 { 93 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 94 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 95 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 96 int rc; 97 98 MLX5_ASSERT(data && dw_cnt); 99 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 100 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 101 DRV_LOG(ERR, "Not enough buffer for register read data"); 102 return -1; 103 } 104 MLX5_SET(access_register_in, in, opcode, 105 MLX5_CMD_OP_ACCESS_REGISTER_USER); 106 MLX5_SET(access_register_in, in, op_mod, 107 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 108 MLX5_SET(access_register_in, in, register_id, reg_id); 109 MLX5_SET(access_register_in, in, argument, arg); 110 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 111 MLX5_ST_SZ_BYTES(access_register_out) + 112 sizeof(uint32_t) * dw_cnt); 113 if (rc || MLX5_FW_STATUS(out)) { 114 DEVX_DRV_LOG(ERR, out, "read access", "NIC register", reg_id); 115 return MLX5_DEVX_ERR_RC(rc); 116 } 117 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 118 dw_cnt * sizeof(uint32_t)); 119 return 0; 120 } 121 122 /** 123 * Perform write access to the registers. 124 * 125 * @param[in] ctx 126 * Context returned from mlx5 open_device() glue function. 127 * @param[in] reg_id 128 * Register identifier according to the PRM. 129 * @param[in] arg 130 * Register access auxiliary parameter according to the PRM. 131 * @param[out] data 132 * Pointer to the buffer containing data to write. 133 * @param[in] dw_cnt 134 * Buffer size in double words (32bit units). 135 * 136 * @return 137 * 0 on success, a negative value otherwise. 138 */ 139 int 140 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 141 uint32_t *data, uint32_t dw_cnt) 142 { 143 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 144 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 145 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 146 int rc; 147 void *ptr; 148 149 MLX5_ASSERT(data && dw_cnt); 150 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 151 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 152 DRV_LOG(ERR, "Data to write exceeds max size"); 153 return -1; 154 } 155 MLX5_SET(access_register_in, in, opcode, 156 MLX5_CMD_OP_ACCESS_REGISTER_USER); 157 MLX5_SET(access_register_in, in, op_mod, 158 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 159 MLX5_SET(access_register_in, in, register_id, reg_id); 160 MLX5_SET(access_register_in, in, argument, arg); 161 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 162 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 163 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 164 if (rc || MLX5_FW_STATUS(out)) { 165 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 166 return MLX5_DEVX_ERR_RC(rc); 167 } 168 rc = mlx5_glue->devx_general_cmd(ctx, in, 169 MLX5_ST_SZ_BYTES(access_register_in) + 170 dw_cnt * sizeof(uint32_t), 171 out, sizeof(out)); 172 if (rc || MLX5_FW_STATUS(out)) { 173 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 174 return MLX5_DEVX_ERR_RC(rc); 175 } 176 return 0; 177 } 178 179 /** 180 * Allocate flow counters via devx interface. 181 * 182 * @param[in] ctx 183 * Context returned from mlx5 open_device() glue function. 184 * @param dcs 185 * Pointer to counters properties structure to be filled by the routine. 186 * @param bulk_n_128 187 * Bulk counter numbers in 128 counters units. 188 * 189 * @return 190 * Pointer to counter object on success, a negative value otherwise and 191 * rte_errno is set. 192 */ 193 struct mlx5_devx_obj * 194 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 195 { 196 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 197 0, SOCKET_ID_ANY); 198 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 199 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 200 201 if (!dcs) { 202 rte_errno = ENOMEM; 203 return NULL; 204 } 205 MLX5_SET(alloc_flow_counter_in, in, opcode, 206 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 207 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 208 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 209 sizeof(in), out, sizeof(out)); 210 if (!dcs->obj) { 211 DEVX_DRV_LOG(ERR, out, "allocate counters", NULL, 0); 212 mlx5_free(dcs); 213 return NULL; 214 } 215 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 216 return dcs; 217 } 218 219 /** 220 * Query flow counters values. 221 * 222 * @param[in] dcs 223 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 224 * @param[in] clear 225 * Whether hardware should clear the counters after the query or not. 226 * @param[in] n_counters 227 * 0 in case of 1 counter to read, otherwise the counter number to read. 228 * @param pkts 229 * The number of packets that matched the flow. 230 * @param bytes 231 * The number of bytes that matched the flow. 232 * @param mkey 233 * The mkey key for batch query. 234 * @param addr 235 * The address in the mkey range for batch query. 236 * @param cmd_comp 237 * The completion object for asynchronous batch query. 238 * @param async_id 239 * The ID to be returned in the asynchronous batch query response. 240 * 241 * @return 242 * 0 on success, a negative value otherwise. 243 */ 244 int 245 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 246 int clear, uint32_t n_counters, 247 uint64_t *pkts, uint64_t *bytes, 248 uint32_t mkey, void *addr, 249 void *cmd_comp, 250 uint64_t async_id) 251 { 252 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 253 MLX5_ST_SZ_BYTES(traffic_counter); 254 uint32_t out[out_len]; 255 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 256 void *stats; 257 int rc; 258 259 MLX5_SET(query_flow_counter_in, in, opcode, 260 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 261 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 262 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 263 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 264 265 if (n_counters) { 266 MLX5_SET(query_flow_counter_in, in, num_of_counters, 267 n_counters); 268 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 269 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 270 MLX5_SET64(query_flow_counter_in, in, address, 271 (uint64_t)(uintptr_t)addr); 272 } 273 if (!cmd_comp) 274 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 275 out_len); 276 else 277 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 278 out_len, async_id, 279 cmd_comp); 280 if (rc) { 281 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 282 rte_errno = rc; 283 return -rc; 284 } 285 if (!n_counters) { 286 stats = MLX5_ADDR_OF(query_flow_counter_out, 287 out, flow_statistics); 288 *pkts = MLX5_GET64(traffic_counter, stats, packets); 289 *bytes = MLX5_GET64(traffic_counter, stats, octets); 290 } 291 return 0; 292 } 293 294 /** 295 * Create a new mkey. 296 * 297 * @param[in] ctx 298 * Context returned from mlx5 open_device() glue function. 299 * @param[in] attr 300 * Attributes of the requested mkey. 301 * 302 * @return 303 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 304 * is set. 305 */ 306 struct mlx5_devx_obj * 307 mlx5_devx_cmd_mkey_create(void *ctx, 308 struct mlx5_devx_mkey_attr *attr) 309 { 310 struct mlx5_klm *klm_array = attr->klm_array; 311 int klm_num = attr->klm_num; 312 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 313 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 314 uint32_t in[in_size_dw]; 315 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 316 void *mkc; 317 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 318 0, SOCKET_ID_ANY); 319 size_t pgsize; 320 uint32_t translation_size; 321 322 if (!mkey) { 323 rte_errno = ENOMEM; 324 return NULL; 325 } 326 memset(in, 0, in_size_dw * 4); 327 pgsize = rte_mem_page_size(); 328 if (pgsize == (size_t)-1) { 329 mlx5_free(mkey); 330 DRV_LOG(ERR, "Failed to get page size"); 331 rte_errno = ENOMEM; 332 return NULL; 333 } 334 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 335 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 336 if (klm_num > 0) { 337 int i; 338 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 339 klm_pas_mtt); 340 translation_size = RTE_ALIGN(klm_num, 4); 341 for (i = 0; i < klm_num; i++) { 342 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 343 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 344 MLX5_SET64(klm, klm, address, klm_array[i].address); 345 klm += MLX5_ST_SZ_BYTES(klm); 346 } 347 for (; i < (int)translation_size; i++) { 348 MLX5_SET(klm, klm, mkey, 0x0); 349 MLX5_SET64(klm, klm, address, 0x0); 350 klm += MLX5_ST_SZ_BYTES(klm); 351 } 352 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 353 MLX5_MKC_ACCESS_MODE_KLM_FBS : 354 MLX5_MKC_ACCESS_MODE_KLM); 355 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 356 } else { 357 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 358 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 359 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 360 } 361 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 362 translation_size); 363 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 364 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 365 MLX5_SET(mkc, mkc, lw, 0x1); 366 MLX5_SET(mkc, mkc, lr, 0x1); 367 if (attr->set_remote_rw) { 368 MLX5_SET(mkc, mkc, rw, 0x1); 369 MLX5_SET(mkc, mkc, rr, 0x1); 370 } 371 MLX5_SET(mkc, mkc, qpn, 0xffffff); 372 MLX5_SET(mkc, mkc, pd, attr->pd); 373 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 374 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 375 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 376 MLX5_SET(mkc, mkc, relaxed_ordering_write, 377 attr->relaxed_ordering_write); 378 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 379 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 380 MLX5_SET64(mkc, mkc, len, attr->size); 381 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 382 if (attr->crypto_en) { 383 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 384 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 385 } 386 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 387 sizeof(out)); 388 if (!mkey->obj) { 389 DEVX_DRV_LOG(ERR, out, klm_num ? "create indirect mkey" 390 : "create direct key", NULL, 0); 391 mlx5_free(mkey); 392 return NULL; 393 } 394 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 395 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 396 return mkey; 397 } 398 399 /** 400 * Get status of devx command response. 401 * Mainly used for asynchronous commands. 402 * 403 * @param[in] out 404 * The out response buffer. 405 * 406 * @return 407 * 0 on success, non-zero value otherwise. 408 */ 409 int 410 mlx5_devx_get_out_command_status(void *out) 411 { 412 int status; 413 414 if (!out) 415 return -EINVAL; 416 status = MLX5_GET(query_flow_counter_out, out, status); 417 if (status) { 418 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 419 420 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 421 syndrome); 422 } 423 return status; 424 } 425 426 /** 427 * Destroy any object allocated by a Devx API. 428 * 429 * @param[in] obj 430 * Pointer to a general object. 431 * 432 * @return 433 * 0 on success, a negative value otherwise. 434 */ 435 int 436 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 437 { 438 int ret; 439 440 if (!obj) 441 return 0; 442 ret = mlx5_glue->devx_obj_destroy(obj->obj); 443 mlx5_free(obj); 444 return ret; 445 } 446 447 /** 448 * Query NIC vport context. 449 * Fills minimal inline attribute. 450 * 451 * @param[in] ctx 452 * ibv contexts returned from mlx5dv_open_device. 453 * @param[in] vport 454 * vport index 455 * @param[out] attr 456 * Attributes device values. 457 * 458 * @return 459 * 0 on success, a negative value otherwise. 460 */ 461 static int 462 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 463 unsigned int vport, 464 struct mlx5_hca_attr *attr) 465 { 466 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 467 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 468 void *vctx; 469 int rc; 470 471 /* Query NIC vport context to determine inline mode. */ 472 MLX5_SET(query_nic_vport_context_in, in, opcode, 473 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 474 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 475 if (vport) 476 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 477 rc = mlx5_glue->devx_general_cmd(ctx, 478 in, sizeof(in), 479 out, sizeof(out)); 480 if (rc || MLX5_FW_STATUS(out)) { 481 DEVX_DRV_LOG(ERR, out, "query NIC vport context", NULL, 0); 482 return MLX5_DEVX_ERR_RC(rc); 483 } 484 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 485 nic_vport_context); 486 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 487 min_wqe_inline_mode); 488 return 0; 489 } 490 491 /** 492 * Query NIC vDPA attributes. 493 * 494 * @param[in] ctx 495 * Context returned from mlx5 open_device() glue function. 496 * @param[out] vdpa_attr 497 * vDPA Attributes structure to fill. 498 */ 499 static void 500 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 501 struct mlx5_hca_vdpa_attr *vdpa_attr) 502 { 503 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 504 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 505 void *hcattr; 506 507 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, 508 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 509 MLX5_HCA_CAP_OPMOD_GET_CUR); 510 if (!hcattr) { 511 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities"); 512 vdpa_attr->valid = 0; 513 } else { 514 vdpa_attr->valid = 1; 515 vdpa_attr->desc_tunnel_offload_type = 516 MLX5_GET(virtio_emulation_cap, hcattr, 517 desc_tunnel_offload_type); 518 vdpa_attr->eth_frame_offload_type = 519 MLX5_GET(virtio_emulation_cap, hcattr, 520 eth_frame_offload_type); 521 vdpa_attr->virtio_version_1_0 = 522 MLX5_GET(virtio_emulation_cap, hcattr, 523 virtio_version_1_0); 524 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 525 tso_ipv4); 526 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 527 tso_ipv6); 528 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 529 tx_csum); 530 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 531 rx_csum); 532 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 533 event_mode); 534 vdpa_attr->virtio_queue_type = 535 MLX5_GET(virtio_emulation_cap, hcattr, 536 virtio_queue_type); 537 vdpa_attr->log_doorbell_stride = 538 MLX5_GET(virtio_emulation_cap, hcattr, 539 log_doorbell_stride); 540 vdpa_attr->vnet_modify_ext = 541 MLX5_GET(virtio_emulation_cap, hcattr, 542 vnet_modify_ext); 543 vdpa_attr->virtio_net_q_addr_modify = 544 MLX5_GET(virtio_emulation_cap, hcattr, 545 virtio_net_q_addr_modify); 546 vdpa_attr->virtio_q_index_modify = 547 MLX5_GET(virtio_emulation_cap, hcattr, 548 virtio_q_index_modify); 549 vdpa_attr->log_doorbell_bar_size = 550 MLX5_GET(virtio_emulation_cap, hcattr, 551 log_doorbell_bar_size); 552 vdpa_attr->doorbell_bar_offset = 553 MLX5_GET64(virtio_emulation_cap, hcattr, 554 doorbell_bar_offset); 555 vdpa_attr->max_num_virtio_queues = 556 MLX5_GET(virtio_emulation_cap, hcattr, 557 max_num_virtio_queues); 558 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 559 umem_1_buffer_param_a); 560 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 561 umem_1_buffer_param_b); 562 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 563 umem_2_buffer_param_a); 564 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 565 umem_2_buffer_param_b); 566 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 567 umem_3_buffer_param_a); 568 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 569 umem_3_buffer_param_b); 570 } 571 } 572 573 int 574 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 575 uint32_t ids[], uint32_t num) 576 { 577 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 578 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 579 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 580 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 581 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 582 int ret; 583 uint32_t idx = 0; 584 uint32_t i; 585 586 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 587 rte_errno = EINVAL; 588 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 589 return -rte_errno; 590 } 591 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 592 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 593 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 594 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 595 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 596 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 597 out, sizeof(out)); 598 if (ret) { 599 rte_errno = ret; 600 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 601 (void *)flex_obj); 602 return -rte_errno; 603 } 604 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 605 void *s_off = (void *)((char *)sample + i * 606 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 607 uint32_t en; 608 609 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 610 flow_match_sample_en); 611 if (!en) 612 continue; 613 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 614 flow_match_sample_field_id); 615 } 616 if (num != idx) { 617 rte_errno = EINVAL; 618 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 619 return -rte_errno; 620 } 621 return ret; 622 } 623 624 struct mlx5_devx_obj * 625 mlx5_devx_cmd_create_flex_parser(void *ctx, 626 struct mlx5_devx_graph_node_attr *data) 627 { 628 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 629 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 630 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 631 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 632 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 633 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 634 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 635 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 636 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 637 uint32_t i; 638 639 if (!parse_flex_obj) { 640 DRV_LOG(ERR, "Failed to allocate flex parser data."); 641 rte_errno = ENOMEM; 642 return NULL; 643 } 644 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 645 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 646 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 647 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 648 MLX5_SET(parse_graph_flex, flex, header_length_mode, 649 data->header_length_mode); 650 MLX5_SET64(parse_graph_flex, flex, modify_field_select, 651 data->modify_field_select); 652 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 653 data->header_length_base_value); 654 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 655 data->header_length_field_offset); 656 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 657 data->header_length_field_shift); 658 MLX5_SET(parse_graph_flex, flex, next_header_field_offset, 659 data->next_header_field_offset); 660 MLX5_SET(parse_graph_flex, flex, next_header_field_size, 661 data->next_header_field_size); 662 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 663 data->header_length_field_mask); 664 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 665 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 666 void *s_off = (void *)((char *)sample + i * 667 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 668 669 if (!s->flow_match_sample_en) 670 continue; 671 MLX5_SET(parse_graph_flow_match_sample, s_off, 672 flow_match_sample_en, !!s->flow_match_sample_en); 673 MLX5_SET(parse_graph_flow_match_sample, s_off, 674 flow_match_sample_field_offset, 675 s->flow_match_sample_field_offset); 676 MLX5_SET(parse_graph_flow_match_sample, s_off, 677 flow_match_sample_offset_mode, 678 s->flow_match_sample_offset_mode); 679 MLX5_SET(parse_graph_flow_match_sample, s_off, 680 flow_match_sample_field_offset_mask, 681 s->flow_match_sample_field_offset_mask); 682 MLX5_SET(parse_graph_flow_match_sample, s_off, 683 flow_match_sample_field_offset_shift, 684 s->flow_match_sample_field_offset_shift); 685 MLX5_SET(parse_graph_flow_match_sample, s_off, 686 flow_match_sample_field_base_offset, 687 s->flow_match_sample_field_base_offset); 688 MLX5_SET(parse_graph_flow_match_sample, s_off, 689 flow_match_sample_tunnel_mode, 690 s->flow_match_sample_tunnel_mode); 691 } 692 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 693 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 694 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 695 void *in_off = (void *)((char *)in_arc + i * 696 MLX5_ST_SZ_BYTES(parse_graph_arc)); 697 void *out_off = (void *)((char *)out_arc + i * 698 MLX5_ST_SZ_BYTES(parse_graph_arc)); 699 700 if (ia->arc_parse_graph_node != 0) { 701 MLX5_SET(parse_graph_arc, in_off, 702 compare_condition_value, 703 ia->compare_condition_value); 704 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 705 ia->start_inner_tunnel); 706 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 707 ia->arc_parse_graph_node); 708 MLX5_SET(parse_graph_arc, in_off, 709 parse_graph_node_handle, 710 ia->parse_graph_node_handle); 711 } 712 if (oa->arc_parse_graph_node != 0) { 713 MLX5_SET(parse_graph_arc, out_off, 714 compare_condition_value, 715 oa->compare_condition_value); 716 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 717 oa->start_inner_tunnel); 718 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 719 oa->arc_parse_graph_node); 720 MLX5_SET(parse_graph_arc, out_off, 721 parse_graph_node_handle, 722 oa->parse_graph_node_handle); 723 } 724 } 725 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 726 out, sizeof(out)); 727 if (!parse_flex_obj->obj) { 728 DEVX_DRV_LOG(ERR, out, "create FLEX PARSE GRAPH", NULL, 0); 729 mlx5_free(parse_flex_obj); 730 return NULL; 731 } 732 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 733 return parse_flex_obj; 734 } 735 736 static int 737 mlx5_devx_cmd_query_hca_parse_graph_node_cap 738 (void *ctx, struct mlx5_hca_flex_attr *attr) 739 { 740 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 741 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 742 void *hcattr; 743 int rc; 744 745 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 746 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | 747 MLX5_HCA_CAP_OPMOD_GET_CUR); 748 if (!hcattr) 749 return rc; 750 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); 751 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); 752 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, 753 header_length_mode); 754 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, 755 sample_offset_mode); 756 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, 757 max_num_arc_in); 758 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, 759 max_num_arc_out); 760 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, 761 max_num_sample); 762 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, 763 sample_id_in_out); 764 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, 765 max_base_header_length); 766 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, 767 max_sample_base_offset); 768 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, 769 max_next_header_offset); 770 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, 771 header_length_mask_width); 772 /* Get the max supported samples from HCA CAP 2 */ 773 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 774 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 775 MLX5_HCA_CAP_OPMOD_GET_CUR); 776 if (!hcattr) 777 return rc; 778 attr->max_num_prog_sample = 779 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); 780 return 0; 781 } 782 783 static int 784 mlx5_devx_query_pkt_integrity_match(void *hcattr) 785 { 786 return MLX5_GET(flow_table_nic_cap, hcattr, 787 ft_field_support_2_nic_receive.inner_l3_ok) && 788 MLX5_GET(flow_table_nic_cap, hcattr, 789 ft_field_support_2_nic_receive.inner_l4_ok) && 790 MLX5_GET(flow_table_nic_cap, hcattr, 791 ft_field_support_2_nic_receive.outer_l3_ok) && 792 MLX5_GET(flow_table_nic_cap, hcattr, 793 ft_field_support_2_nic_receive.outer_l4_ok) && 794 MLX5_GET(flow_table_nic_cap, hcattr, 795 ft_field_support_2_nic_receive 796 .inner_ipv4_checksum_ok) && 797 MLX5_GET(flow_table_nic_cap, hcattr, 798 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 799 MLX5_GET(flow_table_nic_cap, hcattr, 800 ft_field_support_2_nic_receive 801 .outer_ipv4_checksum_ok) && 802 MLX5_GET(flow_table_nic_cap, hcattr, 803 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 804 } 805 806 /** 807 * Query HCA attributes. 808 * Using those attributes we can check on run time if the device 809 * is having the required capabilities. 810 * 811 * @param[in] ctx 812 * Context returned from mlx5 open_device() glue function. 813 * @param[out] attr 814 * Attributes device values. 815 * 816 * @return 817 * 0 on success, a negative value otherwise. 818 */ 819 int 820 mlx5_devx_cmd_query_hca_attr(void *ctx, 821 struct mlx5_hca_attr *attr) 822 { 823 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 824 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 825 bool hca_cap_2_sup; 826 uint64_t general_obj_types_supported = 0; 827 void *hcattr; 828 int rc, i; 829 830 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 831 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 832 MLX5_HCA_CAP_OPMOD_GET_CUR); 833 if (!hcattr) 834 return rc; 835 hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2); 836 attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq); 837 attr->flow_counter_bulk_alloc_bitmap = 838 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 839 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 840 flow_counters_dump); 841 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp); 842 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp); 843 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 844 log_max_rqt_size); 845 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 846 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 847 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 848 log_max_hairpin_queues); 849 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 850 log_max_hairpin_wq_data_sz); 851 attr->log_max_hairpin_num_packets = MLX5_GET 852 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 853 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 854 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 855 relaxed_ordering_write); 856 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 857 relaxed_ordering_read); 858 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 859 access_register_user); 860 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 861 eth_net_offloads); 862 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 863 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 864 flex_parser_protocols); 865 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 866 max_geneve_tlv_options); 867 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 868 max_geneve_tlv_option_data_len); 869 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 870 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 871 general_obj_types) & 872 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 873 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 874 general_obj_types) & 875 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 876 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 877 general_obj_types) & 878 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 879 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 880 general_obj_types) & 881 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 882 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 883 wqe_index_ignore_cap); 884 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 885 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 886 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 887 log_max_static_sq_wq); 888 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 889 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 890 device_frequency_khz); 891 attr->scatter_fcs_w_decap_disable = 892 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 893 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 894 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 895 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 896 attr->steering_format_version = 897 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 898 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 899 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 900 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 901 regexp_num_of_engines); 902 /* Read the general_obj_types bitmap and extract the relevant bits. */ 903 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 904 general_obj_types); 905 attr->vdpa.valid = !!(general_obj_types_supported & 906 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 907 attr->vdpa.queue_counters_valid = 908 !!(general_obj_types_supported & 909 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 910 attr->parse_graph_flex_node = 911 !!(general_obj_types_supported & 912 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 913 attr->flow_hit_aso = !!(general_obj_types_supported & 914 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 915 attr->geneve_tlv_opt = !!(general_obj_types_supported & 916 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 917 attr->dek = !!(general_obj_types_supported & 918 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 919 attr->import_kek = !!(general_obj_types_supported & 920 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 921 attr->credential = !!(general_obj_types_supported & 922 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 923 attr->crypto_login = !!(general_obj_types_supported & 924 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 925 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 926 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 927 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 928 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 929 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 930 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 931 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 932 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 933 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 934 attr->reg_c_preserve = 935 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 936 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 937 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 938 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 939 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 940 compress_mmo_sq); 941 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 942 decompress_mmo_sq); 943 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 944 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 945 compress_mmo_qp); 946 attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 947 decompress_mmo_qp); 948 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 949 compress_min_block_size); 950 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 951 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 952 log_compress_mmo_size); 953 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 954 log_decompress_mmo_size); 955 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 956 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 957 mini_cqe_resp_flow_tag); 958 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 959 mini_cqe_resp_l3_l4_tag); 960 attr->umr_indirect_mkey_disabled = 961 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 962 attr->umr_modify_entity_size_disabled = 963 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 964 attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time); 965 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 966 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 967 general_obj_types) & 968 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 969 attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); 970 if (attr->crypto) { 971 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts); 972 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 973 MLX5_GET_HCA_CAP_OP_MOD_CRYPTO | 974 MLX5_HCA_CAP_OPMOD_GET_CUR); 975 if (!hcattr) 976 return -1; 977 attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps, 978 hcattr, wrapped_import_method) 979 & 1 << 2); 980 } 981 if (hca_cap_2_sup) { 982 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 983 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 984 MLX5_HCA_CAP_OPMOD_GET_CUR); 985 if (!hcattr) { 986 DRV_LOG(DEBUG, 987 "Failed to query DevX HCA capabilities 2."); 988 return rc; 989 } 990 attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, 991 log_min_stride_wqe_sz); 992 } 993 if (attr->log_min_stride_wqe_sz == 0) 994 attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 995 if (attr->qos.sup) { 996 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 997 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 998 MLX5_HCA_CAP_OPMOD_GET_CUR); 999 if (!hcattr) { 1000 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); 1001 return rc; 1002 } 1003 attr->qos.flow_meter_old = 1004 MLX5_GET(qos_cap, hcattr, flow_meter_old); 1005 attr->qos.log_max_flow_meter = 1006 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 1007 attr->qos.flow_meter_reg_c_ids = 1008 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 1009 attr->qos.flow_meter = 1010 MLX5_GET(qos_cap, hcattr, flow_meter); 1011 attr->qos.packet_pacing = 1012 MLX5_GET(qos_cap, hcattr, packet_pacing); 1013 attr->qos.wqe_rate_pp = 1014 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 1015 if (attr->qos.flow_meter_aso_sup) { 1016 attr->qos.log_meter_aso_granularity = 1017 MLX5_GET(qos_cap, hcattr, 1018 log_meter_aso_granularity); 1019 attr->qos.log_meter_aso_max_alloc = 1020 MLX5_GET(qos_cap, hcattr, 1021 log_meter_aso_max_alloc); 1022 attr->qos.log_max_num_meter_aso = 1023 MLX5_GET(qos_cap, hcattr, 1024 log_max_num_meter_aso); 1025 } 1026 } 1027 /* 1028 * Flex item support needs max_num_prog_sample_field 1029 * from the Capabilities 2 table for PARSE_GRAPH_NODE 1030 */ 1031 if (attr->parse_graph_flex_node) { 1032 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap 1033 (ctx, &attr->flex); 1034 if (rc) 1035 return -1; 1036 } 1037 if (attr->vdpa.valid) 1038 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 1039 if (!attr->eth_net_offloads) 1040 return 0; 1041 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 1042 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1043 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 1044 MLX5_HCA_CAP_OPMOD_GET_CUR); 1045 if (!hcattr) { 1046 attr->log_max_ft_sampler_num = 0; 1047 return rc; 1048 } 1049 attr->log_max_ft_sampler_num = MLX5_GET 1050 (flow_table_nic_cap, hcattr, 1051 flow_table_properties_nic_receive.log_max_ft_sampler_num); 1052 attr->flow.tunnel_header_0_1 = MLX5_GET 1053 (flow_table_nic_cap, hcattr, 1054 ft_field_support_2_nic_receive.tunnel_header_0_1); 1055 attr->flow.tunnel_header_2_3 = MLX5_GET 1056 (flow_table_nic_cap, hcattr, 1057 ft_field_support_2_nic_receive.tunnel_header_2_3); 1058 attr->modify_outer_ip_ecn = MLX5_GET 1059 (flow_table_nic_cap, hcattr, 1060 ft_header_modify_nic_receive.outer_ip_ecn); 1061 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 1062 attr->inner_ipv4_ihl = MLX5_GET 1063 (flow_table_nic_cap, hcattr, 1064 ft_field_support_2_nic_receive.inner_ipv4_ihl); 1065 attr->outer_ipv4_ihl = MLX5_GET 1066 (flow_table_nic_cap, hcattr, 1067 ft_field_support_2_nic_receive.outer_ipv4_ihl); 1068 /* Query HCA offloads for Ethernet protocol. */ 1069 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1070 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 1071 MLX5_HCA_CAP_OPMOD_GET_CUR); 1072 if (!hcattr) { 1073 attr->eth_net_offloads = 0; 1074 return rc; 1075 } 1076 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 1077 hcattr, wqe_vlan_insert); 1078 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 1079 hcattr, csum_cap); 1080 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 1081 hcattr, vlan_cap); 1082 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1083 lro_cap); 1084 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1085 hcattr, max_lso_cap); 1086 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1087 hcattr, scatter_fcs); 1088 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1089 hcattr, tunnel_lro_gre); 1090 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1091 hcattr, tunnel_lro_vxlan); 1092 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1093 hcattr, swp); 1094 attr->tunnel_stateless_gre = 1095 MLX5_GET(per_protocol_networking_offload_caps, 1096 hcattr, tunnel_stateless_gre); 1097 attr->tunnel_stateless_vxlan = 1098 MLX5_GET(per_protocol_networking_offload_caps, 1099 hcattr, tunnel_stateless_vxlan); 1100 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1101 hcattr, swp_csum); 1102 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1103 hcattr, swp_lso); 1104 attr->lro_max_msg_sz_mode = MLX5_GET 1105 (per_protocol_networking_offload_caps, 1106 hcattr, lro_max_msg_sz_mode); 1107 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1108 attr->lro_timer_supported_periods[i] = 1109 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1110 lro_timer_supported_periods[i]); 1111 } 1112 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1113 hcattr, lro_min_mss_size); 1114 attr->tunnel_stateless_geneve_rx = 1115 MLX5_GET(per_protocol_networking_offload_caps, 1116 hcattr, tunnel_stateless_geneve_rx); 1117 attr->geneve_max_opt_len = 1118 MLX5_GET(per_protocol_networking_offload_caps, 1119 hcattr, max_geneve_opt_len); 1120 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1121 hcattr, wqe_inline_mode); 1122 attr->tunnel_stateless_gtp = MLX5_GET 1123 (per_protocol_networking_offload_caps, 1124 hcattr, tunnel_stateless_gtp); 1125 attr->rss_ind_tbl_cap = MLX5_GET 1126 (per_protocol_networking_offload_caps, 1127 hcattr, rss_ind_tbl_cap); 1128 /* Query HCA attribute for ROCE. */ 1129 if (attr->roce) { 1130 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1131 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1132 MLX5_HCA_CAP_OPMOD_GET_CUR); 1133 if (!hcattr) { 1134 DRV_LOG(DEBUG, 1135 "Failed to query devx HCA ROCE capabilities"); 1136 return rc; 1137 } 1138 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1139 } 1140 if (attr->eth_virt && 1141 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1142 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1143 if (rc) { 1144 attr->eth_virt = 0; 1145 goto error; 1146 } 1147 } 1148 if (attr->eswitch_manager) { 1149 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1150 MLX5_SET_HCA_CAP_OP_MOD_ESW | 1151 MLX5_HCA_CAP_OPMOD_GET_CUR); 1152 if (!hcattr) 1153 return rc; 1154 attr->esw_mgr_vport_id_valid = 1155 MLX5_GET(esw_cap, hcattr, 1156 esw_manager_vport_number_valid); 1157 attr->esw_mgr_vport_id = 1158 MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); 1159 } 1160 return 0; 1161 error: 1162 rc = (rc > 0) ? -rc : rc; 1163 return rc; 1164 } 1165 1166 /** 1167 * Query TIS transport domain from QP verbs object using DevX API. 1168 * 1169 * @param[in] qp 1170 * Pointer to verbs QP returned by ibv_create_qp . 1171 * @param[in] tis_num 1172 * TIS number of TIS to query. 1173 * @param[out] tis_td 1174 * Pointer to TIS transport domain variable, to be set by the routine. 1175 * 1176 * @return 1177 * 0 on success, a negative value otherwise. 1178 */ 1179 int 1180 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1181 uint32_t *tis_td) 1182 { 1183 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1184 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1185 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1186 int rc; 1187 void *tis_ctx; 1188 1189 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1190 MLX5_SET(query_tis_in, in, tisn, tis_num); 1191 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1192 if (rc) { 1193 DRV_LOG(ERR, "Failed to query QP using DevX"); 1194 return -rc; 1195 }; 1196 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1197 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1198 return 0; 1199 #else 1200 (void)qp; 1201 (void)tis_num; 1202 (void)tis_td; 1203 return -ENOTSUP; 1204 #endif 1205 } 1206 1207 /** 1208 * Fill WQ data for DevX API command. 1209 * Utility function for use when creating DevX objects containing a WQ. 1210 * 1211 * @param[in] wq_ctx 1212 * Pointer to WQ context to fill with data. 1213 * @param [in] wq_attr 1214 * Pointer to WQ attributes structure to fill in WQ context. 1215 */ 1216 static void 1217 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1218 { 1219 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1220 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1221 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1222 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1223 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1224 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1225 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1226 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1227 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1228 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1229 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1230 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1231 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1232 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1233 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1234 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1235 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1236 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1237 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1238 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1239 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1240 wq_attr->log_hairpin_num_packets); 1241 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1242 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1243 wq_attr->single_wqe_log_num_of_strides); 1244 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1245 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1246 wq_attr->single_stride_log_num_of_bytes); 1247 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1248 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1249 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1250 } 1251 1252 /** 1253 * Create RQ using DevX API. 1254 * 1255 * @param[in] ctx 1256 * Context returned from mlx5 open_device() glue function. 1257 * @param [in] rq_attr 1258 * Pointer to create RQ attributes structure. 1259 * @param [in] socket 1260 * CPU socket ID for allocations. 1261 * 1262 * @return 1263 * The DevX object created, NULL otherwise and rte_errno is set. 1264 */ 1265 struct mlx5_devx_obj * 1266 mlx5_devx_cmd_create_rq(void *ctx, 1267 struct mlx5_devx_create_rq_attr *rq_attr, 1268 int socket) 1269 { 1270 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1271 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1272 void *rq_ctx, *wq_ctx; 1273 struct mlx5_devx_wq_attr *wq_attr; 1274 struct mlx5_devx_obj *rq = NULL; 1275 1276 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1277 if (!rq) { 1278 DRV_LOG(ERR, "Failed to allocate RQ data"); 1279 rte_errno = ENOMEM; 1280 return NULL; 1281 } 1282 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1283 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1284 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1285 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1286 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1287 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1288 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1289 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1290 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1291 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1292 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1293 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1294 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1295 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1296 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1297 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1298 wq_attr = &rq_attr->wq_attr; 1299 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1300 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1301 out, sizeof(out)); 1302 if (!rq->obj) { 1303 DEVX_DRV_LOG(ERR, out, "create RQ", NULL, 0); 1304 mlx5_free(rq); 1305 return NULL; 1306 } 1307 rq->id = MLX5_GET(create_rq_out, out, rqn); 1308 return rq; 1309 } 1310 1311 /** 1312 * Modify RQ using DevX API. 1313 * 1314 * @param[in] rq 1315 * Pointer to RQ object structure. 1316 * @param [in] rq_attr 1317 * Pointer to modify RQ attributes structure. 1318 * 1319 * @return 1320 * 0 on success, a negative errno value otherwise and rte_errno is set. 1321 */ 1322 int 1323 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1324 struct mlx5_devx_modify_rq_attr *rq_attr) 1325 { 1326 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1327 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1328 void *rq_ctx, *wq_ctx; 1329 int ret; 1330 1331 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1332 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1333 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1334 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1335 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1336 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1337 if (rq_attr->modify_bitmask & 1338 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1339 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1340 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1341 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1342 if (rq_attr->modify_bitmask & 1343 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1344 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1345 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1346 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1347 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1348 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1349 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1350 } 1351 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1352 out, sizeof(out)); 1353 if (ret) { 1354 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1355 rte_errno = errno; 1356 return -errno; 1357 } 1358 return ret; 1359 } 1360 1361 /** 1362 * Create RMP using DevX API. 1363 * 1364 * @param[in] ctx 1365 * Context returned from mlx5 open_device() glue function. 1366 * @param [in] rmp_attr 1367 * Pointer to create RMP attributes structure. 1368 * @param [in] socket 1369 * CPU socket ID for allocations. 1370 * 1371 * @return 1372 * The DevX object created, NULL otherwise and rte_errno is set. 1373 */ 1374 struct mlx5_devx_obj * 1375 mlx5_devx_cmd_create_rmp(void *ctx, 1376 struct mlx5_devx_create_rmp_attr *rmp_attr, 1377 int socket) 1378 { 1379 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0}; 1380 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0}; 1381 void *rmp_ctx, *wq_ctx; 1382 struct mlx5_devx_wq_attr *wq_attr; 1383 struct mlx5_devx_obj *rmp = NULL; 1384 1385 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket); 1386 if (!rmp) { 1387 DRV_LOG(ERR, "Failed to allocate RMP data"); 1388 rte_errno = ENOMEM; 1389 return NULL; 1390 } 1391 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP); 1392 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx); 1393 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state); 1394 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe, 1395 rmp_attr->basic_cyclic_rcv_wqe); 1396 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq); 1397 wq_attr = &rmp_attr->wq_attr; 1398 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1399 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1400 sizeof(out)); 1401 if (!rmp->obj) { 1402 DEVX_DRV_LOG(ERR, out, "create RMP", NULL, 0); 1403 mlx5_free(rmp); 1404 return NULL; 1405 } 1406 rmp->id = MLX5_GET(create_rmp_out, out, rmpn); 1407 return rmp; 1408 } 1409 1410 /* 1411 * Create TIR using DevX API. 1412 * 1413 * @param[in] ctx 1414 * Context returned from mlx5 open_device() glue function. 1415 * @param [in] tir_attr 1416 * Pointer to TIR attributes structure. 1417 * 1418 * @return 1419 * The DevX object created, NULL otherwise and rte_errno is set. 1420 */ 1421 struct mlx5_devx_obj * 1422 mlx5_devx_cmd_create_tir(void *ctx, 1423 struct mlx5_devx_tir_attr *tir_attr) 1424 { 1425 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1426 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1427 void *tir_ctx, *outer, *inner, *rss_key; 1428 struct mlx5_devx_obj *tir = NULL; 1429 1430 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1431 if (!tir) { 1432 DRV_LOG(ERR, "Failed to allocate TIR data"); 1433 rte_errno = ENOMEM; 1434 return NULL; 1435 } 1436 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1437 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1438 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1439 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1440 tir_attr->lro_timeout_period_usecs); 1441 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1442 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1443 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1444 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1445 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1446 tir_attr->tunneled_offload_en); 1447 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1448 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1449 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1450 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1451 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1452 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1453 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1454 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1455 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1456 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1457 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1458 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1459 tir_attr->rx_hash_field_selector_outer.selected_fields); 1460 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1461 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1462 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1463 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1464 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1465 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1466 tir_attr->rx_hash_field_selector_inner.selected_fields); 1467 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1468 out, sizeof(out)); 1469 if (!tir->obj) { 1470 DEVX_DRV_LOG(ERR, out, "create TIR", NULL, 0); 1471 mlx5_free(tir); 1472 return NULL; 1473 } 1474 tir->id = MLX5_GET(create_tir_out, out, tirn); 1475 return tir; 1476 } 1477 1478 /** 1479 * Modify TIR using DevX API. 1480 * 1481 * @param[in] tir 1482 * Pointer to TIR DevX object structure. 1483 * @param [in] modify_tir_attr 1484 * Pointer to TIR modification attributes structure. 1485 * 1486 * @return 1487 * 0 on success, a negative errno value otherwise and rte_errno is set. 1488 */ 1489 int 1490 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1491 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1492 { 1493 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1494 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1495 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1496 void *tir_ctx; 1497 int ret; 1498 1499 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1500 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1501 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1502 modify_tir_attr->modify_bitmask); 1503 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1504 if (modify_tir_attr->modify_bitmask & 1505 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1506 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1507 tir_attr->lro_timeout_period_usecs); 1508 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1509 tir_attr->lro_enable_mask); 1510 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1511 tir_attr->lro_max_msg_sz); 1512 } 1513 if (modify_tir_attr->modify_bitmask & 1514 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1515 MLX5_SET(tirc, tir_ctx, indirect_table, 1516 tir_attr->indirect_table); 1517 if (modify_tir_attr->modify_bitmask & 1518 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1519 int i; 1520 void *outer, *inner; 1521 1522 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1523 tir_attr->rx_hash_symmetric); 1524 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1525 for (i = 0; i < 10; i++) { 1526 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1527 tir_attr->rx_hash_toeplitz_key[i]); 1528 } 1529 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1530 rx_hash_field_selector_outer); 1531 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1532 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1533 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1534 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1535 MLX5_SET 1536 (rx_hash_field_select, outer, selected_fields, 1537 tir_attr->rx_hash_field_selector_outer.selected_fields); 1538 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1539 rx_hash_field_selector_inner); 1540 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1541 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1542 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1543 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1544 MLX5_SET 1545 (rx_hash_field_select, inner, selected_fields, 1546 tir_attr->rx_hash_field_selector_inner.selected_fields); 1547 } 1548 if (modify_tir_attr->modify_bitmask & 1549 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1550 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1551 } 1552 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1553 out, sizeof(out)); 1554 if (ret) { 1555 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1556 rte_errno = errno; 1557 return -errno; 1558 } 1559 return ret; 1560 } 1561 1562 /** 1563 * Create RQT using DevX API. 1564 * 1565 * @param[in] ctx 1566 * Context returned from mlx5 open_device() glue function. 1567 * @param [in] rqt_attr 1568 * Pointer to RQT attributes structure. 1569 * 1570 * @return 1571 * The DevX object created, NULL otherwise and rte_errno is set. 1572 */ 1573 struct mlx5_devx_obj * 1574 mlx5_devx_cmd_create_rqt(void *ctx, 1575 struct mlx5_devx_rqt_attr *rqt_attr) 1576 { 1577 uint32_t *in = NULL; 1578 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1579 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1580 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1581 void *rqt_ctx; 1582 struct mlx5_devx_obj *rqt = NULL; 1583 int i; 1584 1585 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1586 if (!in) { 1587 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1588 rte_errno = ENOMEM; 1589 return NULL; 1590 } 1591 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1592 if (!rqt) { 1593 DRV_LOG(ERR, "Failed to allocate RQT data"); 1594 rte_errno = ENOMEM; 1595 mlx5_free(in); 1596 return NULL; 1597 } 1598 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1599 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1600 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1601 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1602 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1603 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1604 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1605 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1606 mlx5_free(in); 1607 if (!rqt->obj) { 1608 DEVX_DRV_LOG(ERR, out, "create RQT", NULL, 0); 1609 mlx5_free(rqt); 1610 return NULL; 1611 } 1612 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1613 return rqt; 1614 } 1615 1616 /** 1617 * Modify RQT using DevX API. 1618 * 1619 * @param[in] rqt 1620 * Pointer to RQT DevX object structure. 1621 * @param [in] rqt_attr 1622 * Pointer to RQT attributes structure. 1623 * 1624 * @return 1625 * 0 on success, a negative errno value otherwise and rte_errno is set. 1626 */ 1627 int 1628 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1629 struct mlx5_devx_rqt_attr *rqt_attr) 1630 { 1631 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1632 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1633 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1634 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1635 void *rqt_ctx; 1636 int i; 1637 int ret; 1638 1639 if (!in) { 1640 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1641 rte_errno = ENOMEM; 1642 return -ENOMEM; 1643 } 1644 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1645 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1646 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1647 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1648 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1649 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1650 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1651 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1652 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1653 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1654 mlx5_free(in); 1655 if (ret) { 1656 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1657 rte_errno = errno; 1658 return -rte_errno; 1659 } 1660 return ret; 1661 } 1662 1663 /** 1664 * Create SQ using DevX API. 1665 * 1666 * @param[in] ctx 1667 * Context returned from mlx5 open_device() glue function. 1668 * @param [in] sq_attr 1669 * Pointer to SQ attributes structure. 1670 * @param [in] socket 1671 * CPU socket ID for allocations. 1672 * 1673 * @return 1674 * The DevX object created, NULL otherwise and rte_errno is set. 1675 **/ 1676 struct mlx5_devx_obj * 1677 mlx5_devx_cmd_create_sq(void *ctx, 1678 struct mlx5_devx_create_sq_attr *sq_attr) 1679 { 1680 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1681 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1682 void *sq_ctx; 1683 void *wq_ctx; 1684 struct mlx5_devx_wq_attr *wq_attr; 1685 struct mlx5_devx_obj *sq = NULL; 1686 1687 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1688 if (!sq) { 1689 DRV_LOG(ERR, "Failed to allocate SQ data"); 1690 rte_errno = ENOMEM; 1691 return NULL; 1692 } 1693 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1694 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1695 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1696 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1697 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1698 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1699 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1700 sq_attr->allow_multi_pkt_send_wqe); 1701 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1702 sq_attr->min_wqe_inline_mode); 1703 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1704 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1705 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1706 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1707 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1708 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1709 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1710 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1711 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1712 sq_attr->packet_pacing_rate_limit_index); 1713 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1714 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1715 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1716 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1717 wq_attr = &sq_attr->wq_attr; 1718 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1719 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1720 out, sizeof(out)); 1721 if (!sq->obj) { 1722 DEVX_DRV_LOG(ERR, out, "create SQ", NULL, 0); 1723 mlx5_free(sq); 1724 return NULL; 1725 } 1726 sq->id = MLX5_GET(create_sq_out, out, sqn); 1727 return sq; 1728 } 1729 1730 /** 1731 * Modify SQ using DevX API. 1732 * 1733 * @param[in] sq 1734 * Pointer to SQ object structure. 1735 * @param [in] sq_attr 1736 * Pointer to SQ attributes structure. 1737 * 1738 * @return 1739 * 0 on success, a negative errno value otherwise and rte_errno is set. 1740 */ 1741 int 1742 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1743 struct mlx5_devx_modify_sq_attr *sq_attr) 1744 { 1745 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1746 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1747 void *sq_ctx; 1748 int ret; 1749 1750 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1751 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1752 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1753 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1754 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1755 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1756 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1757 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1758 out, sizeof(out)); 1759 if (ret) { 1760 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1761 rte_errno = errno; 1762 return -rte_errno; 1763 } 1764 return ret; 1765 } 1766 1767 /** 1768 * Create TIS using DevX API. 1769 * 1770 * @param[in] ctx 1771 * Context returned from mlx5 open_device() glue function. 1772 * @param [in] tis_attr 1773 * Pointer to TIS attributes structure. 1774 * 1775 * @return 1776 * The DevX object created, NULL otherwise and rte_errno is set. 1777 */ 1778 struct mlx5_devx_obj * 1779 mlx5_devx_cmd_create_tis(void *ctx, 1780 struct mlx5_devx_tis_attr *tis_attr) 1781 { 1782 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1783 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1784 struct mlx5_devx_obj *tis = NULL; 1785 void *tis_ctx; 1786 1787 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1788 if (!tis) { 1789 DRV_LOG(ERR, "Failed to allocate TIS object"); 1790 rte_errno = ENOMEM; 1791 return NULL; 1792 } 1793 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1794 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1795 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1796 tis_attr->strict_lag_tx_port_affinity); 1797 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1798 tis_attr->lag_tx_port_affinity); 1799 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1800 MLX5_SET(tisc, tis_ctx, transport_domain, 1801 tis_attr->transport_domain); 1802 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1803 out, sizeof(out)); 1804 if (!tis->obj) { 1805 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 1806 mlx5_free(tis); 1807 return NULL; 1808 } 1809 tis->id = MLX5_GET(create_tis_out, out, tisn); 1810 return tis; 1811 } 1812 1813 /** 1814 * Create transport domain using DevX API. 1815 * 1816 * @param[in] ctx 1817 * Context returned from mlx5 open_device() glue function. 1818 * @return 1819 * The DevX object created, NULL otherwise and rte_errno is set. 1820 */ 1821 struct mlx5_devx_obj * 1822 mlx5_devx_cmd_create_td(void *ctx) 1823 { 1824 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1825 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1826 struct mlx5_devx_obj *td = NULL; 1827 1828 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1829 if (!td) { 1830 DRV_LOG(ERR, "Failed to allocate TD object"); 1831 rte_errno = ENOMEM; 1832 return NULL; 1833 } 1834 MLX5_SET(alloc_transport_domain_in, in, opcode, 1835 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1836 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1837 out, sizeof(out)); 1838 if (!td->obj) { 1839 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 1840 mlx5_free(td); 1841 return NULL; 1842 } 1843 td->id = MLX5_GET(alloc_transport_domain_out, out, 1844 transport_domain); 1845 return td; 1846 } 1847 1848 /** 1849 * Dump all flows to file. 1850 * 1851 * @param[in] fdb_domain 1852 * FDB domain. 1853 * @param[in] rx_domain 1854 * RX domain. 1855 * @param[in] tx_domain 1856 * TX domain. 1857 * @param[out] file 1858 * Pointer to file stream. 1859 * 1860 * @return 1861 * 0 on success, a negative value otherwise. 1862 */ 1863 int 1864 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1865 void *rx_domain __rte_unused, 1866 void *tx_domain __rte_unused, FILE *file __rte_unused) 1867 { 1868 int ret = 0; 1869 1870 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1871 if (fdb_domain) { 1872 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1873 if (ret) 1874 return ret; 1875 } 1876 MLX5_ASSERT(rx_domain); 1877 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1878 if (ret) 1879 return ret; 1880 MLX5_ASSERT(tx_domain); 1881 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1882 #else 1883 ret = ENOTSUP; 1884 #endif 1885 return -ret; 1886 } 1887 1888 int 1889 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 1890 FILE *file __rte_unused) 1891 { 1892 int ret = 0; 1893 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 1894 if (rule_info) 1895 ret = mlx5_glue->dr_dump_rule(file, rule_info); 1896 #else 1897 ret = ENOTSUP; 1898 #endif 1899 return -ret; 1900 } 1901 1902 /* 1903 * Create CQ using DevX API. 1904 * 1905 * @param[in] ctx 1906 * Context returned from mlx5 open_device() glue function. 1907 * @param [in] attr 1908 * Pointer to CQ attributes structure. 1909 * 1910 * @return 1911 * The DevX object created, NULL otherwise and rte_errno is set. 1912 */ 1913 struct mlx5_devx_obj * 1914 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1915 { 1916 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1917 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1918 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1919 sizeof(*cq_obj), 1920 0, SOCKET_ID_ANY); 1921 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1922 1923 if (!cq_obj) { 1924 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1925 rte_errno = ENOMEM; 1926 return NULL; 1927 } 1928 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1929 if (attr->db_umem_valid) { 1930 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1931 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1932 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1933 } else { 1934 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1935 } 1936 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1937 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1938 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1939 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1940 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1941 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1942 MLX5_SET(cqc, cqctx, log_page_size, 1943 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1944 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1945 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1946 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1947 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1948 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1949 attr->mini_cqe_res_format_ext); 1950 if (attr->q_umem_valid) { 1951 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1952 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1953 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1954 attr->q_umem_offset); 1955 } 1956 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1957 sizeof(out)); 1958 if (!cq_obj->obj) { 1959 DEVX_DRV_LOG(ERR, out, "create CQ", NULL, 0); 1960 mlx5_free(cq_obj); 1961 return NULL; 1962 } 1963 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1964 return cq_obj; 1965 } 1966 1967 /** 1968 * Create VIRTQ using DevX API. 1969 * 1970 * @param[in] ctx 1971 * Context returned from mlx5 open_device() glue function. 1972 * @param [in] attr 1973 * Pointer to VIRTQ attributes structure. 1974 * 1975 * @return 1976 * The DevX object created, NULL otherwise and rte_errno is set. 1977 */ 1978 struct mlx5_devx_obj * 1979 mlx5_devx_cmd_create_virtq(void *ctx, 1980 struct mlx5_devx_virtq_attr *attr) 1981 { 1982 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1983 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1984 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1985 sizeof(*virtq_obj), 1986 0, SOCKET_ID_ANY); 1987 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1988 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1989 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1990 1991 if (!virtq_obj) { 1992 DRV_LOG(ERR, "Failed to allocate virtq data."); 1993 rte_errno = ENOMEM; 1994 return NULL; 1995 } 1996 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1997 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1998 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1999 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2000 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2001 attr->hw_available_index); 2002 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 2003 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2004 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2005 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2006 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2007 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2008 attr->virtio_version_1_0); 2009 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2010 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2011 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2012 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2013 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 2014 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2015 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 2016 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2017 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 2018 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 2019 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 2020 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 2021 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 2022 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 2023 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 2024 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 2025 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 2026 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 2027 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 2028 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 2029 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 2030 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 2031 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 2032 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2033 sizeof(out)); 2034 if (!virtq_obj->obj) { 2035 DEVX_DRV_LOG(ERR, out, "create VIRTQ", NULL, 0); 2036 mlx5_free(virtq_obj); 2037 return NULL; 2038 } 2039 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2040 return virtq_obj; 2041 } 2042 2043 /** 2044 * Modify VIRTQ using DevX API. 2045 * 2046 * @param[in] virtq_obj 2047 * Pointer to virtq object structure. 2048 * @param [in] attr 2049 * Pointer to modify virtq attributes structure. 2050 * 2051 * @return 2052 * 0 on success, a negative errno value otherwise and rte_errno is set. 2053 */ 2054 int 2055 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 2056 struct mlx5_devx_virtq_attr *attr) 2057 { 2058 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2059 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2060 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2061 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2062 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2063 int ret; 2064 2065 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2066 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 2067 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2068 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2069 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2070 MLX5_SET64(virtio_net_q, virtq, modify_field_select, 2071 attr->mod_fields_bitmap); 2072 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2073 if (!attr->mod_fields_bitmap) { 2074 DRV_LOG(ERR, "Failed to modify VIRTQ for no type set."); 2075 rte_errno = EINVAL; 2076 return -rte_errno; 2077 } 2078 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE) 2079 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 2080 if (attr->mod_fields_bitmap & 2081 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) { 2082 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 2083 attr->dirty_bitmap_mkey); 2084 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 2085 attr->dirty_bitmap_addr); 2086 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 2087 attr->dirty_bitmap_size); 2088 } 2089 if (attr->mod_fields_bitmap & 2090 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE) 2091 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 2092 attr->dirty_bitmap_dump_enable); 2093 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) { 2094 MLX5_SET(virtio_q, virtctx, queue_period_mode, 2095 attr->hw_latency_mode); 2096 MLX5_SET(virtio_q, virtctx, queue_period_us, 2097 attr->hw_max_latency_us); 2098 MLX5_SET(virtio_q, virtctx, queue_max_count, 2099 attr->hw_max_pending_comp); 2100 } 2101 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) { 2102 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2103 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2104 MLX5_SET64(virtio_q, virtctx, available_addr, 2105 attr->available_addr); 2106 } 2107 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX) 2108 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2109 attr->hw_available_index); 2110 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX) 2111 MLX5_SET16(virtio_net_q, virtq, hw_used_index, 2112 attr->hw_used_index); 2113 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE) 2114 MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type); 2115 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0) 2116 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2117 attr->virtio_version_1_0); 2118 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY) 2119 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2120 if (attr->mod_fields_bitmap & 2121 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) { 2122 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2123 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2124 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2125 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2126 } 2127 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) { 2128 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2129 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2130 } 2131 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 2132 out, sizeof(out)); 2133 if (ret) { 2134 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2135 rte_errno = errno; 2136 return -rte_errno; 2137 } 2138 return ret; 2139 } 2140 2141 /** 2142 * Query VIRTQ using DevX API. 2143 * 2144 * @param[in] virtq_obj 2145 * Pointer to virtq object structure. 2146 * @param [in/out] attr 2147 * Pointer to virtq attributes structure. 2148 * 2149 * @return 2150 * 0 on success, a negative errno value otherwise and rte_errno is set. 2151 */ 2152 int 2153 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 2154 struct mlx5_devx_virtq_attr *attr) 2155 { 2156 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2157 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 2158 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 2159 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 2160 int ret; 2161 2162 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2163 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2164 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2165 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2166 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2167 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2168 out, sizeof(out)); 2169 if (ret) { 2170 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2171 rte_errno = errno; 2172 return -errno; 2173 } 2174 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2175 hw_available_index); 2176 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2177 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2178 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2179 virtio_q_context.error_type); 2180 return ret; 2181 } 2182 2183 /** 2184 * Create QP using DevX API. 2185 * 2186 * @param[in] ctx 2187 * Context returned from mlx5 open_device() glue function. 2188 * @param [in] attr 2189 * Pointer to QP attributes structure. 2190 * 2191 * @return 2192 * The DevX object created, NULL otherwise and rte_errno is set. 2193 */ 2194 struct mlx5_devx_obj * 2195 mlx5_devx_cmd_create_qp(void *ctx, 2196 struct mlx5_devx_qp_attr *attr) 2197 { 2198 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2199 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2200 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2201 sizeof(*qp_obj), 2202 0, SOCKET_ID_ANY); 2203 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2204 2205 if (!qp_obj) { 2206 DRV_LOG(ERR, "Failed to allocate QP data."); 2207 rte_errno = ENOMEM; 2208 return NULL; 2209 } 2210 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2211 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2212 MLX5_SET(qpc, qpc, pd, attr->pd); 2213 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2214 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2215 if (attr->uar_index) { 2216 if (attr->mmo) { 2217 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2218 in, qpc_extension_and_pas_list); 2219 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2220 qpc_ext_and_pas_list, qpc_data_extension); 2221 2222 MLX5_SET(create_qp_in, in, qpc_ext, 1); 2223 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2224 } 2225 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2226 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2227 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2228 MLX5_SET(qpc, qpc, log_page_size, 2229 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2230 if (attr->num_of_send_wqbbs) { 2231 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs)); 2232 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2233 MLX5_SET(qpc, qpc, log_sq_size, 2234 rte_log2_u32(attr->num_of_send_wqbbs)); 2235 } else { 2236 MLX5_SET(qpc, qpc, no_sq, 1); 2237 } 2238 if (attr->num_of_receive_wqes) { 2239 MLX5_ASSERT(RTE_IS_POWER_OF_2( 2240 attr->num_of_receive_wqes)); 2241 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2242 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2243 MLX5_LOG_RQ_STRIDE_SHIFT); 2244 MLX5_SET(qpc, qpc, log_rq_size, 2245 rte_log2_u32(attr->num_of_receive_wqes)); 2246 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2247 } else { 2248 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2249 } 2250 if (attr->dbr_umem_valid) { 2251 MLX5_SET(qpc, qpc, dbr_umem_valid, 2252 attr->dbr_umem_valid); 2253 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2254 } 2255 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2256 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2257 attr->wq_umem_offset); 2258 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2259 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2260 } else { 2261 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2262 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2263 MLX5_SET(qpc, qpc, no_sq, 1); 2264 } 2265 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2266 sizeof(out)); 2267 if (!qp_obj->obj) { 2268 DEVX_DRV_LOG(ERR, out, "create QP", NULL, 0); 2269 mlx5_free(qp_obj); 2270 return NULL; 2271 } 2272 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2273 return qp_obj; 2274 } 2275 2276 /** 2277 * Modify QP using DevX API. 2278 * Currently supports only force loop-back QP. 2279 * 2280 * @param[in] qp 2281 * Pointer to QP object structure. 2282 * @param [in] qp_st_mod_op 2283 * The QP state modification operation. 2284 * @param [in] remote_qp_id 2285 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2286 * 2287 * @return 2288 * 0 on success, a negative errno value otherwise and rte_errno is set. 2289 */ 2290 int 2291 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2292 uint32_t remote_qp_id) 2293 { 2294 union { 2295 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2296 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2297 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2298 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)]; 2299 } in; 2300 union { 2301 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2302 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2303 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2304 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)]; 2305 } out; 2306 void *qpc; 2307 int ret; 2308 unsigned int inlen; 2309 unsigned int outlen; 2310 2311 memset(&in, 0, sizeof(in)); 2312 memset(&out, 0, sizeof(out)); 2313 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2314 switch (qp_st_mod_op) { 2315 case MLX5_CMD_OP_RST2INIT_QP: 2316 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2317 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2318 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2319 MLX5_SET(qpc, qpc, rre, 1); 2320 MLX5_SET(qpc, qpc, rwe, 1); 2321 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2322 inlen = sizeof(in.rst2init); 2323 outlen = sizeof(out.rst2init); 2324 break; 2325 case MLX5_CMD_OP_INIT2RTR_QP: 2326 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2327 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2328 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2329 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2330 MLX5_SET(qpc, qpc, mtu, 1); 2331 MLX5_SET(qpc, qpc, log_msg_max, 30); 2332 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2333 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2334 inlen = sizeof(in.init2rtr); 2335 outlen = sizeof(out.init2rtr); 2336 break; 2337 case MLX5_CMD_OP_RTR2RTS_QP: 2338 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2339 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2340 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16); 2341 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2342 MLX5_SET(qpc, qpc, retry_count, 7); 2343 MLX5_SET(qpc, qpc, rnr_retry, 7); 2344 inlen = sizeof(in.rtr2rts); 2345 outlen = sizeof(out.rtr2rts); 2346 break; 2347 case MLX5_CMD_OP_QP_2RST: 2348 MLX5_SET(2rst_qp_in, &in, qpn, qp->id); 2349 inlen = sizeof(in.qp2rst); 2350 outlen = sizeof(out.qp2rst); 2351 break; 2352 default: 2353 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2354 qp_st_mod_op); 2355 rte_errno = EINVAL; 2356 return -rte_errno; 2357 } 2358 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2359 if (ret) { 2360 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2361 rte_errno = errno; 2362 return -rte_errno; 2363 } 2364 return ret; 2365 } 2366 2367 struct mlx5_devx_obj * 2368 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2369 { 2370 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2371 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2372 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2373 sizeof(*couners_obj), 0, 2374 SOCKET_ID_ANY); 2375 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2376 2377 if (!couners_obj) { 2378 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2379 rte_errno = ENOMEM; 2380 return NULL; 2381 } 2382 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2383 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2384 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2385 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2386 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2387 sizeof(out)); 2388 if (!couners_obj->obj) { 2389 DEVX_DRV_LOG(ERR, out, "create virtio queue counters Obj", NULL, 2390 0); 2391 mlx5_free(couners_obj); 2392 return NULL; 2393 } 2394 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2395 return couners_obj; 2396 } 2397 2398 int 2399 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2400 struct mlx5_devx_virtio_q_couners_attr *attr) 2401 { 2402 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2403 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2404 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2405 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2406 virtio_q_counters); 2407 int ret; 2408 2409 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2410 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2411 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2412 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2413 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2414 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2415 sizeof(out)); 2416 if (ret) { 2417 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2418 rte_errno = errno; 2419 return -errno; 2420 } 2421 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2422 received_desc); 2423 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2424 completed_desc); 2425 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2426 error_cqes); 2427 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2428 bad_desc_errors); 2429 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2430 exceed_max_chain); 2431 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2432 invalid_buffer); 2433 return ret; 2434 } 2435 2436 /** 2437 * Create general object of type FLOW_HIT_ASO using DevX API. 2438 * 2439 * @param[in] ctx 2440 * Context returned from mlx5 open_device() glue function. 2441 * @param [in] pd 2442 * PD value to associate the FLOW_HIT_ASO object with. 2443 * 2444 * @return 2445 * The DevX object created, NULL otherwise and rte_errno is set. 2446 */ 2447 struct mlx5_devx_obj * 2448 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2449 { 2450 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2451 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2452 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2453 void *ptr = NULL; 2454 2455 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2456 0, SOCKET_ID_ANY); 2457 if (!flow_hit_aso_obj) { 2458 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2459 rte_errno = ENOMEM; 2460 return NULL; 2461 } 2462 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2463 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2464 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2465 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2466 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2467 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2468 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2469 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2470 out, sizeof(out)); 2471 if (!flow_hit_aso_obj->obj) { 2472 DEVX_DRV_LOG(ERR, out, "create FLOW_HIT_ASO", NULL, 0); 2473 mlx5_free(flow_hit_aso_obj); 2474 return NULL; 2475 } 2476 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2477 return flow_hit_aso_obj; 2478 } 2479 2480 /* 2481 * Create PD using DevX API. 2482 * 2483 * @param[in] ctx 2484 * Context returned from mlx5 open_device() glue function. 2485 * 2486 * @return 2487 * The DevX object created, NULL otherwise and rte_errno is set. 2488 */ 2489 struct mlx5_devx_obj * 2490 mlx5_devx_cmd_alloc_pd(void *ctx) 2491 { 2492 struct mlx5_devx_obj *ppd = 2493 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2494 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2495 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2496 2497 if (!ppd) { 2498 DRV_LOG(ERR, "Failed to allocate PD data."); 2499 rte_errno = ENOMEM; 2500 return NULL; 2501 } 2502 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2503 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2504 out, sizeof(out)); 2505 if (!ppd->obj) { 2506 mlx5_free(ppd); 2507 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2508 rte_errno = errno; 2509 return NULL; 2510 } 2511 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2512 return ppd; 2513 } 2514 2515 /** 2516 * Create general object of type FLOW_METER_ASO using DevX API. 2517 * 2518 * @param[in] ctx 2519 * Context returned from mlx5 open_device() glue function. 2520 * @param [in] pd 2521 * PD value to associate the FLOW_METER_ASO object with. 2522 * @param [in] log_obj_size 2523 * log_obj_size define to allocate number of 2 * meters 2524 * in one FLOW_METER_ASO object. 2525 * 2526 * @return 2527 * The DevX object created, NULL otherwise and rte_errno is set. 2528 */ 2529 struct mlx5_devx_obj * 2530 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2531 uint32_t log_obj_size) 2532 { 2533 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2534 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2535 struct mlx5_devx_obj *flow_meter_aso_obj; 2536 void *ptr; 2537 2538 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2539 sizeof(*flow_meter_aso_obj), 2540 0, SOCKET_ID_ANY); 2541 if (!flow_meter_aso_obj) { 2542 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2543 rte_errno = ENOMEM; 2544 return NULL; 2545 } 2546 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2547 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2548 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2549 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2550 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2551 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2552 log_obj_size); 2553 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2554 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2555 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2556 ctx, in, sizeof(in), 2557 out, sizeof(out)); 2558 if (!flow_meter_aso_obj->obj) { 2559 DEVX_DRV_LOG(ERR, out, "create FLOW_METTER_ASO", NULL, 0); 2560 mlx5_free(flow_meter_aso_obj); 2561 return NULL; 2562 } 2563 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2564 out, obj_id); 2565 return flow_meter_aso_obj; 2566 } 2567 2568 /* 2569 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2570 * 2571 * @param[in] ctx 2572 * Context returned from mlx5 open_device() glue function. 2573 * @param [in] pd 2574 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2575 * @param [in] log_obj_size 2576 * log_obj_size to allocate its power of 2 * objects 2577 * in one CONN_TRACK_OFFLOAD bulk allocation. 2578 * 2579 * @return 2580 * The DevX object created, NULL otherwise and rte_errno is set. 2581 */ 2582 struct mlx5_devx_obj * 2583 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2584 uint32_t log_obj_size) 2585 { 2586 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2587 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2588 struct mlx5_devx_obj *ct_aso_obj; 2589 void *ptr; 2590 2591 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2592 0, SOCKET_ID_ANY); 2593 if (!ct_aso_obj) { 2594 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2595 rte_errno = ENOMEM; 2596 return NULL; 2597 } 2598 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2599 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2600 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2601 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2602 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2603 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2604 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2605 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2606 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2607 out, sizeof(out)); 2608 if (!ct_aso_obj->obj) { 2609 DEVX_DRV_LOG(ERR, out, "create CONN_TRACK_OFFLOAD", NULL, 0); 2610 mlx5_free(ct_aso_obj); 2611 return NULL; 2612 } 2613 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2614 return ct_aso_obj; 2615 } 2616 2617 /** 2618 * Create general object of type GENEVE TLV option using DevX API. 2619 * 2620 * @param[in] ctx 2621 * Context returned from mlx5 open_device() glue function. 2622 * @param [in] class 2623 * TLV option variable value of class 2624 * @param [in] type 2625 * TLV option variable value of type 2626 * @param [in] len 2627 * TLV option variable value of len 2628 * 2629 * @return 2630 * The DevX object created, NULL otherwise and rte_errno is set. 2631 */ 2632 struct mlx5_devx_obj * 2633 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2634 uint16_t class, uint8_t type, uint8_t len) 2635 { 2636 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2637 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2638 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2639 sizeof(*geneve_tlv_opt_obj), 2640 0, SOCKET_ID_ANY); 2641 2642 if (!geneve_tlv_opt_obj) { 2643 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2644 rte_errno = ENOMEM; 2645 return NULL; 2646 } 2647 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2648 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2649 geneve_tlv_opt); 2650 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2651 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2652 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2653 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2654 MLX5_SET(geneve_tlv_option, opt, option_class, 2655 rte_be_to_cpu_16(class)); 2656 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2657 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2658 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2659 sizeof(in), out, sizeof(out)); 2660 if (!geneve_tlv_opt_obj->obj) { 2661 DEVX_DRV_LOG(ERR, out, "create GENEVE TLV", NULL, 0); 2662 mlx5_free(geneve_tlv_opt_obj); 2663 return NULL; 2664 } 2665 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2666 return geneve_tlv_opt_obj; 2667 } 2668 2669 int 2670 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2671 { 2672 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2673 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2674 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2675 int rc; 2676 void *rq_ctx; 2677 2678 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2679 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2680 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2681 if (rc) { 2682 rte_errno = errno; 2683 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2684 "rc = %d, errno = %d.", rc, errno); 2685 return -rc; 2686 }; 2687 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2688 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2689 return 0; 2690 #else 2691 (void)wq; 2692 (void)counter_set_id; 2693 return -ENOTSUP; 2694 #endif 2695 } 2696 2697 /* 2698 * Allocate queue counters via devx interface. 2699 * 2700 * @param[in] ctx 2701 * Context returned from mlx5 open_device() glue function. 2702 * 2703 * @return 2704 * Pointer to counter object on success, a NULL value otherwise and 2705 * rte_errno is set. 2706 */ 2707 struct mlx5_devx_obj * 2708 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2709 { 2710 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2711 SOCKET_ID_ANY); 2712 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2713 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2714 2715 if (!dcs) { 2716 rte_errno = ENOMEM; 2717 return NULL; 2718 } 2719 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2720 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2721 sizeof(out)); 2722 if (!dcs->obj) { 2723 DEVX_DRV_LOG(DEBUG, out, "create q counter set", NULL, 0); 2724 mlx5_free(dcs); 2725 return NULL; 2726 } 2727 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2728 return dcs; 2729 } 2730 2731 /** 2732 * Query queue counters values. 2733 * 2734 * @param[in] dcs 2735 * devx object of the queue counter set. 2736 * @param[in] clear 2737 * Whether hardware should clear the counters after the query or not. 2738 * @param[out] out_of_buffers 2739 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2740 * 2741 * @return 2742 * 0 on success, a negative value otherwise. 2743 */ 2744 int 2745 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2746 uint32_t *out_of_buffers) 2747 { 2748 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2749 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2750 int rc; 2751 2752 MLX5_SET(query_q_counter_in, in, opcode, 2753 MLX5_CMD_OP_QUERY_Q_COUNTER); 2754 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2755 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2756 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2757 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2758 sizeof(out)); 2759 if (rc) { 2760 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2761 rte_errno = rc; 2762 return -rc; 2763 } 2764 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2765 return 0; 2766 } 2767 2768 /** 2769 * Create general object of type DEK using DevX API. 2770 * 2771 * @param[in] ctx 2772 * Context returned from mlx5 open_device() glue function. 2773 * @param [in] attr 2774 * Pointer to DEK attributes structure. 2775 * 2776 * @return 2777 * The DevX object created, NULL otherwise and rte_errno is set. 2778 */ 2779 struct mlx5_devx_obj * 2780 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2781 { 2782 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2783 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2784 struct mlx5_devx_obj *dek_obj = NULL; 2785 void *ptr = NULL, *key_addr = NULL; 2786 2787 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2788 0, SOCKET_ID_ANY); 2789 if (dek_obj == NULL) { 2790 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2791 rte_errno = ENOMEM; 2792 return NULL; 2793 } 2794 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2795 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2796 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2797 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2798 MLX5_GENERAL_OBJ_TYPE_DEK); 2799 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2800 MLX5_SET(dek, ptr, key_size, attr->key_size); 2801 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2802 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2803 MLX5_SET(dek, ptr, pd, attr->pd); 2804 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2805 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2806 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2807 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2808 out, sizeof(out)); 2809 if (dek_obj->obj == NULL) { 2810 DEVX_DRV_LOG(ERR, out, "create DEK", NULL, 0); 2811 mlx5_free(dek_obj); 2812 return NULL; 2813 } 2814 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2815 return dek_obj; 2816 } 2817 2818 /** 2819 * Create general object of type IMPORT_KEK using DevX API. 2820 * 2821 * @param[in] ctx 2822 * Context returned from mlx5 open_device() glue function. 2823 * @param [in] attr 2824 * Pointer to IMPORT_KEK attributes structure. 2825 * 2826 * @return 2827 * The DevX object created, NULL otherwise and rte_errno is set. 2828 */ 2829 struct mlx5_devx_obj * 2830 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 2831 struct mlx5_devx_import_kek_attr *attr) 2832 { 2833 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 2834 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2835 struct mlx5_devx_obj *import_kek_obj = NULL; 2836 void *ptr = NULL, *key_addr = NULL; 2837 2838 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 2839 0, SOCKET_ID_ANY); 2840 if (import_kek_obj == NULL) { 2841 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 2842 rte_errno = ENOMEM; 2843 return NULL; 2844 } 2845 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 2846 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2847 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2848 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2849 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 2850 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 2851 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 2852 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 2853 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2854 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2855 out, sizeof(out)); 2856 if (import_kek_obj->obj == NULL) { 2857 DEVX_DRV_LOG(ERR, out, "create IMPORT_KEK", NULL, 0); 2858 mlx5_free(import_kek_obj); 2859 return NULL; 2860 } 2861 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2862 return import_kek_obj; 2863 } 2864 2865 /** 2866 * Create general object of type CREDENTIAL using DevX API. 2867 * 2868 * @param[in] ctx 2869 * Context returned from mlx5 open_device() glue function. 2870 * @param [in] attr 2871 * Pointer to CREDENTIAL attributes structure. 2872 * 2873 * @return 2874 * The DevX object created, NULL otherwise and rte_errno is set. 2875 */ 2876 struct mlx5_devx_obj * 2877 mlx5_devx_cmd_create_credential_obj(void *ctx, 2878 struct mlx5_devx_credential_attr *attr) 2879 { 2880 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 2881 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2882 struct mlx5_devx_obj *credential_obj = NULL; 2883 void *ptr = NULL, *credential_addr = NULL; 2884 2885 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 2886 0, SOCKET_ID_ANY); 2887 if (credential_obj == NULL) { 2888 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 2889 rte_errno = ENOMEM; 2890 return NULL; 2891 } 2892 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 2893 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2894 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2895 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2896 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 2897 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 2898 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 2899 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 2900 memcpy(credential_addr, (void *)(attr->credential), 2901 MLX5_CRYPTO_CREDENTIAL_SIZE); 2902 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2903 out, sizeof(out)); 2904 if (credential_obj->obj == NULL) { 2905 DEVX_DRV_LOG(ERR, out, "create CREDENTIAL", NULL, 0); 2906 mlx5_free(credential_obj); 2907 return NULL; 2908 } 2909 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2910 return credential_obj; 2911 } 2912 2913 /** 2914 * Create general object of type CRYPTO_LOGIN using DevX API. 2915 * 2916 * @param[in] ctx 2917 * Context returned from mlx5 open_device() glue function. 2918 * @param [in] attr 2919 * Pointer to CRYPTO_LOGIN attributes structure. 2920 * 2921 * @return 2922 * The DevX object created, NULL otherwise and rte_errno is set. 2923 */ 2924 struct mlx5_devx_obj * 2925 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 2926 struct mlx5_devx_crypto_login_attr *attr) 2927 { 2928 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 2929 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2930 struct mlx5_devx_obj *crypto_login_obj = NULL; 2931 void *ptr = NULL, *credential_addr = NULL; 2932 2933 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 2934 0, SOCKET_ID_ANY); 2935 if (crypto_login_obj == NULL) { 2936 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 2937 rte_errno = ENOMEM; 2938 return NULL; 2939 } 2940 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 2941 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2942 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2943 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2944 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 2945 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 2946 MLX5_SET(crypto_login, ptr, credential_pointer, 2947 attr->credential_pointer); 2948 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 2949 attr->session_import_kek_ptr); 2950 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 2951 memcpy(credential_addr, (void *)(attr->credential), 2952 MLX5_CRYPTO_CREDENTIAL_SIZE); 2953 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2954 out, sizeof(out)); 2955 if (crypto_login_obj->obj == NULL) { 2956 DEVX_DRV_LOG(ERR, out, "create CRYPTO_LOGIN", NULL, 0); 2957 mlx5_free(crypto_login_obj); 2958 return NULL; 2959 } 2960 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2961 return crypto_login_obj; 2962 } 2963 2964 /** 2965 * Query LAG context. 2966 * 2967 * @param[in] ctx 2968 * Pointer to ibv_context, returned from mlx5dv_open_device. 2969 * @param[out] lag_ctx 2970 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 2971 * 2972 * @return 2973 * 0 on success, a negative value otherwise. 2974 */ 2975 int 2976 mlx5_devx_cmd_query_lag(void *ctx, 2977 struct mlx5_devx_lag_context *lag_ctx) 2978 { 2979 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 2980 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 2981 void *lctx; 2982 int rc; 2983 2984 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 2985 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 2986 if (rc) 2987 goto error; 2988 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 2989 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 2990 fdb_selection_mode); 2991 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 2992 port_select_mode); 2993 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 2994 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 2995 tx_remap_affinity_2); 2996 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 2997 tx_remap_affinity_1); 2998 return 0; 2999 error: 3000 rc = (rc > 0) ? -rc : rc; 3001 return rc; 3002 } 3003