1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /* FW writes status value to the OUT buffer at offset 00H */ 17 #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status) 18 /* FW writes syndrome value to the OUT buffer at offset 04H */ 19 #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome) 20 21 #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1)) 22 23 #define DEVX_DRV_LOG(level, out, reason, param, value) \ 24 do { \ 25 /* \ 26 * Some (old) GCC compilers like 7.5.0 and aarch64 GCC 7.1-2017.08 \ 27 * do not expand correctly when the macro invoked when the `param` \ 28 * is `NULL`. \ 29 * Use `local_param` to avoid direct `NULL` expansion. \ 30 */ \ 31 const char *local_param = (const char *)param; \ 32 \ 33 rte_errno = errno; \ 34 if (!local_param) { \ 35 DRV_LOG(level, \ 36 "DevX %s failed errno=%d status=%#x syndrome=%#x", \ 37 (reason), errno, MLX5_FW_STATUS((out)), \ 38 MLX5_FW_SYNDROME((out))); \ 39 } else { \ 40 DRV_LOG(level, \ 41 "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x",\ 42 (reason), local_param, (value), errno, \ 43 MLX5_FW_STATUS((out)), MLX5_FW_SYNDROME((out))); \ 44 } \ 45 } while (0) 46 47 static void * 48 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, 49 int *err, uint32_t flags) 50 { 51 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); 52 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); 53 int rc; 54 55 memset(in, 0, size_in); 56 memset(out, 0, size_out); 57 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 58 MLX5_SET(query_hca_cap_in, in, op_mod, flags); 59 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); 60 if (rc || MLX5_FW_STATUS(out)) { 61 DEVX_DRV_LOG(ERR, out, "HCA capabilities", "func", flags >> 1); 62 if (err) 63 *err = MLX5_DEVX_ERR_RC(rc); 64 return NULL; 65 } 66 if (err) 67 *err = 0; 68 return MLX5_ADDR_OF(query_hca_cap_out, out, capability); 69 } 70 71 /** 72 * Perform read access to the registers. Reads data from register 73 * and writes ones to the specified buffer. 74 * 75 * @param[in] ctx 76 * Context returned from mlx5 open_device() glue function. 77 * @param[in] reg_id 78 * Register identifier according to the PRM. 79 * @param[in] arg 80 * Register access auxiliary parameter according to the PRM. 81 * @param[out] data 82 * Pointer to the buffer to store read data. 83 * @param[in] dw_cnt 84 * Buffer size in double words. 85 * 86 * @return 87 * 0 on success, a negative value otherwise. 88 */ 89 int 90 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 91 uint32_t *data, uint32_t dw_cnt) 92 { 93 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 94 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 95 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 96 int rc; 97 98 MLX5_ASSERT(data && dw_cnt); 99 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 100 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 101 DRV_LOG(ERR, "Not enough buffer for register read data"); 102 return -1; 103 } 104 MLX5_SET(access_register_in, in, opcode, 105 MLX5_CMD_OP_ACCESS_REGISTER_USER); 106 MLX5_SET(access_register_in, in, op_mod, 107 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 108 MLX5_SET(access_register_in, in, register_id, reg_id); 109 MLX5_SET(access_register_in, in, argument, arg); 110 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 111 MLX5_ST_SZ_BYTES(access_register_out) + 112 sizeof(uint32_t) * dw_cnt); 113 if (rc || MLX5_FW_STATUS(out)) { 114 DEVX_DRV_LOG(DEBUG, out, "read access", "NIC register", reg_id); 115 return MLX5_DEVX_ERR_RC(rc); 116 } 117 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 118 dw_cnt * sizeof(uint32_t)); 119 return 0; 120 } 121 122 /** 123 * Perform write access to the registers. 124 * 125 * @param[in] ctx 126 * Context returned from mlx5 open_device() glue function. 127 * @param[in] reg_id 128 * Register identifier according to the PRM. 129 * @param[in] arg 130 * Register access auxiliary parameter according to the PRM. 131 * @param[out] data 132 * Pointer to the buffer containing data to write. 133 * @param[in] dw_cnt 134 * Buffer size in double words (32bit units). 135 * 136 * @return 137 * 0 on success, a negative value otherwise. 138 */ 139 int 140 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 141 uint32_t *data, uint32_t dw_cnt) 142 { 143 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 144 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 145 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 146 int rc; 147 void *ptr; 148 149 MLX5_ASSERT(data && dw_cnt); 150 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 151 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 152 DRV_LOG(ERR, "Data to write exceeds max size"); 153 return -1; 154 } 155 MLX5_SET(access_register_in, in, opcode, 156 MLX5_CMD_OP_ACCESS_REGISTER_USER); 157 MLX5_SET(access_register_in, in, op_mod, 158 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 159 MLX5_SET(access_register_in, in, register_id, reg_id); 160 MLX5_SET(access_register_in, in, argument, arg); 161 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 162 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 163 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 164 if (rc || MLX5_FW_STATUS(out)) { 165 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 166 return MLX5_DEVX_ERR_RC(rc); 167 } 168 rc = mlx5_glue->devx_general_cmd(ctx, in, 169 MLX5_ST_SZ_BYTES(access_register_in) + 170 dw_cnt * sizeof(uint32_t), 171 out, sizeof(out)); 172 if (rc || MLX5_FW_STATUS(out)) { 173 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 174 return MLX5_DEVX_ERR_RC(rc); 175 } 176 return 0; 177 } 178 179 struct mlx5_devx_obj * 180 mlx5_devx_cmd_flow_counter_alloc_general(void *ctx, 181 struct mlx5_devx_counter_attr *attr) 182 { 183 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 184 0, SOCKET_ID_ANY); 185 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 186 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 187 188 if (!dcs) { 189 rte_errno = ENOMEM; 190 return NULL; 191 } 192 MLX5_SET(alloc_flow_counter_in, in, opcode, 193 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 194 if (attr->bulk_log_max_alloc) 195 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk_log_size, 196 attr->flow_counter_bulk_log_size); 197 else 198 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, 199 attr->bulk_n_128); 200 if (attr->pd_valid) 201 MLX5_SET(alloc_flow_counter_in, in, pd, attr->pd); 202 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 203 sizeof(in), out, sizeof(out)); 204 if (!dcs->obj) { 205 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 206 rte_errno = errno; 207 mlx5_free(dcs); 208 return NULL; 209 } 210 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 211 return dcs; 212 } 213 214 /** 215 * Allocate flow counters via devx interface. 216 * 217 * @param[in] ctx 218 * Context returned from mlx5 open_device() glue function. 219 * @param dcs 220 * Pointer to counters properties structure to be filled by the routine. 221 * @param bulk_n_128 222 * Bulk counter numbers in 128 counters units. 223 * 224 * @return 225 * Pointer to counter object on success, a negative value otherwise and 226 * rte_errno is set. 227 */ 228 struct mlx5_devx_obj * 229 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 230 { 231 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 232 0, SOCKET_ID_ANY); 233 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 234 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 235 236 if (!dcs) { 237 rte_errno = ENOMEM; 238 return NULL; 239 } 240 MLX5_SET(alloc_flow_counter_in, in, opcode, 241 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 242 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 243 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 244 sizeof(in), out, sizeof(out)); 245 if (!dcs->obj) { 246 DEVX_DRV_LOG(ERR, out, "allocate counters", NULL, 0); 247 mlx5_free(dcs); 248 return NULL; 249 } 250 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 251 return dcs; 252 } 253 254 /** 255 * Query flow counters values. 256 * 257 * @param[in] dcs 258 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 259 * @param[in] clear 260 * Whether hardware should clear the counters after the query or not. 261 * @param[in] n_counters 262 * 0 in case of 1 counter to read, otherwise the counter number to read. 263 * @param pkts 264 * The number of packets that matched the flow. 265 * @param bytes 266 * The number of bytes that matched the flow. 267 * @param mkey 268 * The mkey key for batch query. 269 * @param addr 270 * The address in the mkey range for batch query. 271 * @param cmd_comp 272 * The completion object for asynchronous batch query. 273 * @param async_id 274 * The ID to be returned in the asynchronous batch query response. 275 * 276 * @return 277 * 0 on success, a negative value otherwise. 278 */ 279 int 280 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 281 int clear, uint32_t n_counters, 282 uint64_t *pkts, uint64_t *bytes, 283 uint32_t mkey, void *addr, 284 void *cmd_comp, 285 uint64_t async_id) 286 { 287 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 288 MLX5_ST_SZ_BYTES(traffic_counter); 289 uint32_t out[out_len]; 290 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 291 void *stats; 292 int rc; 293 294 MLX5_SET(query_flow_counter_in, in, opcode, 295 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 296 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 297 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 298 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 299 300 if (n_counters) { 301 MLX5_SET(query_flow_counter_in, in, num_of_counters, 302 n_counters); 303 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 304 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 305 MLX5_SET64(query_flow_counter_in, in, address, 306 (uint64_t)(uintptr_t)addr); 307 } 308 if (!cmd_comp) 309 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 310 out_len); 311 else 312 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 313 out_len, async_id, 314 cmd_comp); 315 if (rc) { 316 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 317 rte_errno = rc; 318 return -rc; 319 } 320 if (!n_counters) { 321 stats = MLX5_ADDR_OF(query_flow_counter_out, 322 out, flow_statistics); 323 *pkts = MLX5_GET64(traffic_counter, stats, packets); 324 *bytes = MLX5_GET64(traffic_counter, stats, octets); 325 } 326 return 0; 327 } 328 329 /** 330 * Create a new mkey. 331 * 332 * @param[in] ctx 333 * Context returned from mlx5 open_device() glue function. 334 * @param[in] attr 335 * Attributes of the requested mkey. 336 * 337 * @return 338 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 339 * is set. 340 */ 341 struct mlx5_devx_obj * 342 mlx5_devx_cmd_mkey_create(void *ctx, 343 struct mlx5_devx_mkey_attr *attr) 344 { 345 struct mlx5_klm *klm_array = attr->klm_array; 346 int klm_num = attr->klm_num; 347 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 348 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 349 uint32_t in[in_size_dw]; 350 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 351 void *mkc; 352 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 353 0, SOCKET_ID_ANY); 354 size_t pgsize; 355 uint32_t translation_size; 356 357 if (!mkey) { 358 rte_errno = ENOMEM; 359 return NULL; 360 } 361 memset(in, 0, in_size_dw * 4); 362 pgsize = rte_mem_page_size(); 363 if (pgsize == (size_t)-1) { 364 mlx5_free(mkey); 365 DRV_LOG(ERR, "Failed to get page size"); 366 rte_errno = ENOMEM; 367 return NULL; 368 } 369 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 370 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 371 if (klm_num > 0) { 372 int i; 373 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 374 klm_pas_mtt); 375 translation_size = RTE_ALIGN(klm_num, 4); 376 for (i = 0; i < klm_num; i++) { 377 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 378 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 379 MLX5_SET64(klm, klm, address, klm_array[i].address); 380 klm += MLX5_ST_SZ_BYTES(klm); 381 } 382 for (; i < (int)translation_size; i++) { 383 MLX5_SET(klm, klm, mkey, 0x0); 384 MLX5_SET64(klm, klm, address, 0x0); 385 klm += MLX5_ST_SZ_BYTES(klm); 386 } 387 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 388 MLX5_MKC_ACCESS_MODE_KLM_FBS : 389 MLX5_MKC_ACCESS_MODE_KLM); 390 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 391 } else { 392 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 393 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 394 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 395 } 396 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 397 translation_size); 398 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 399 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 400 MLX5_SET(mkc, mkc, lw, 0x1); 401 MLX5_SET(mkc, mkc, lr, 0x1); 402 if (attr->set_remote_rw) { 403 MLX5_SET(mkc, mkc, rw, 0x1); 404 MLX5_SET(mkc, mkc, rr, 0x1); 405 } 406 MLX5_SET(mkc, mkc, qpn, 0xffffff); 407 MLX5_SET(mkc, mkc, pd, attr->pd); 408 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 409 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 410 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 411 MLX5_SET(mkc, mkc, relaxed_ordering_write, 412 attr->relaxed_ordering_write); 413 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 414 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 415 MLX5_SET64(mkc, mkc, len, attr->size); 416 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 417 if (attr->crypto_en) { 418 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 419 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 420 } 421 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 422 sizeof(out)); 423 if (!mkey->obj) { 424 DEVX_DRV_LOG(ERR, out, klm_num ? "create indirect mkey" 425 : "create direct key", NULL, 0); 426 mlx5_free(mkey); 427 return NULL; 428 } 429 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 430 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 431 return mkey; 432 } 433 434 /** 435 * Get status of devx command response. 436 * Mainly used for asynchronous commands. 437 * 438 * @param[in] out 439 * The out response buffer. 440 * 441 * @return 442 * 0 on success, non-zero value otherwise. 443 */ 444 int 445 mlx5_devx_get_out_command_status(void *out) 446 { 447 int status; 448 449 if (!out) 450 return -EINVAL; 451 status = MLX5_GET(query_flow_counter_out, out, status); 452 if (status) { 453 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 454 455 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 456 syndrome); 457 } 458 return status; 459 } 460 461 /** 462 * Destroy any object allocated by a Devx API. 463 * 464 * @param[in] obj 465 * Pointer to a general object. 466 * 467 * @return 468 * 0 on success, a negative value otherwise. 469 */ 470 int 471 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 472 { 473 int ret; 474 475 if (!obj) 476 return 0; 477 ret = mlx5_glue->devx_obj_destroy(obj->obj); 478 mlx5_free(obj); 479 return ret; 480 } 481 482 /** 483 * Query NIC vport context. 484 * Fills minimal inline attribute. 485 * 486 * @param[in] ctx 487 * ibv contexts returned from mlx5dv_open_device. 488 * @param[in] vport 489 * vport index 490 * @param[out] attr 491 * Attributes device values. 492 * 493 * @return 494 * 0 on success, a negative value otherwise. 495 */ 496 static int 497 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 498 unsigned int vport, 499 struct mlx5_hca_attr *attr) 500 { 501 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 502 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 503 void *vctx; 504 int rc; 505 506 /* Query NIC vport context to determine inline mode. */ 507 MLX5_SET(query_nic_vport_context_in, in, opcode, 508 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 509 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 510 if (vport) 511 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 512 rc = mlx5_glue->devx_general_cmd(ctx, 513 in, sizeof(in), 514 out, sizeof(out)); 515 if (rc || MLX5_FW_STATUS(out)) { 516 DEVX_DRV_LOG(ERR, out, "query NIC vport context", NULL, 0); 517 return MLX5_DEVX_ERR_RC(rc); 518 } 519 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 520 nic_vport_context); 521 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 522 min_wqe_inline_mode); 523 return 0; 524 } 525 526 /** 527 * Query NIC vDPA attributes. 528 * 529 * @param[in] ctx 530 * Context returned from mlx5 open_device() glue function. 531 * @param[out] vdpa_attr 532 * vDPA Attributes structure to fill. 533 */ 534 static void 535 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 536 struct mlx5_hca_vdpa_attr *vdpa_attr) 537 { 538 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 539 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 540 void *hcattr; 541 542 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, 543 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 544 MLX5_HCA_CAP_OPMOD_GET_CUR); 545 if (!hcattr) { 546 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities"); 547 vdpa_attr->valid = 0; 548 } else { 549 vdpa_attr->valid = 1; 550 vdpa_attr->desc_tunnel_offload_type = 551 MLX5_GET(virtio_emulation_cap, hcattr, 552 desc_tunnel_offload_type); 553 vdpa_attr->eth_frame_offload_type = 554 MLX5_GET(virtio_emulation_cap, hcattr, 555 eth_frame_offload_type); 556 vdpa_attr->virtio_version_1_0 = 557 MLX5_GET(virtio_emulation_cap, hcattr, 558 virtio_version_1_0); 559 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 560 tso_ipv4); 561 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 562 tso_ipv6); 563 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 564 tx_csum); 565 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 566 rx_csum); 567 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 568 event_mode); 569 vdpa_attr->virtio_queue_type = 570 MLX5_GET(virtio_emulation_cap, hcattr, 571 virtio_queue_type); 572 vdpa_attr->log_doorbell_stride = 573 MLX5_GET(virtio_emulation_cap, hcattr, 574 log_doorbell_stride); 575 vdpa_attr->vnet_modify_ext = 576 MLX5_GET(virtio_emulation_cap, hcattr, 577 vnet_modify_ext); 578 vdpa_attr->virtio_net_q_addr_modify = 579 MLX5_GET(virtio_emulation_cap, hcattr, 580 virtio_net_q_addr_modify); 581 vdpa_attr->virtio_q_index_modify = 582 MLX5_GET(virtio_emulation_cap, hcattr, 583 virtio_q_index_modify); 584 vdpa_attr->log_doorbell_bar_size = 585 MLX5_GET(virtio_emulation_cap, hcattr, 586 log_doorbell_bar_size); 587 vdpa_attr->doorbell_bar_offset = 588 MLX5_GET64(virtio_emulation_cap, hcattr, 589 doorbell_bar_offset); 590 vdpa_attr->max_num_virtio_queues = 591 MLX5_GET(virtio_emulation_cap, hcattr, 592 max_num_virtio_queues); 593 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 594 umem_1_buffer_param_a); 595 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 596 umem_1_buffer_param_b); 597 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 598 umem_2_buffer_param_a); 599 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 600 umem_2_buffer_param_b); 601 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 602 umem_3_buffer_param_a); 603 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 604 umem_3_buffer_param_b); 605 } 606 } 607 608 /** 609 * Query match sample handle parameters. 610 * 611 * This command allows translating a field sample handle returned by either 612 * PARSE_GRAPH_FLOW_MATCH_SAMPLE or by GENEVE TLV OPTION object into values 613 * used for header modification or header matching/hashing. 614 * 615 * @param[in] ctx 616 * Context used to create either GENEVE TLV option or FLEX PARSE GRAPH object. 617 * @param[in] sample_field_id 618 * Field sample handle returned by either PARSE_GRAPH_FLOW_MATCH_SAMPLE 619 * or by GENEVE TLV OPTION object. 620 * @param[out] attr 621 * Pointer to match sample info attributes structure. 622 * 623 * @return 624 * 0 on success, a negative errno otherwise and rte_errno is set. 625 */ 626 int 627 mlx5_devx_cmd_match_sample_info_query(void *ctx, uint32_t sample_field_id, 628 struct mlx5_devx_match_sample_info_query_attr *attr) 629 { 630 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 631 uint32_t out[MLX5_ST_SZ_DW(query_match_sample_info_out)] = {0}; 632 uint32_t in[MLX5_ST_SZ_DW(query_match_sample_info_in)] = {0}; 633 int rc; 634 635 MLX5_SET(query_match_sample_info_in, in, opcode, 636 MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO); 637 MLX5_SET(query_match_sample_info_in, in, op_mod, 0); 638 MLX5_SET(query_match_sample_info_in, in, sample_field_id, 639 sample_field_id); 640 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 641 if (rc) { 642 DRV_LOG(ERR, "Failed to query match sample info using DevX: %s", 643 strerror(rc)); 644 rte_errno = rc; 645 return -rc; 646 } 647 attr->modify_field_id = MLX5_GET(query_match_sample_info_out, out, 648 modify_field_id); 649 attr->sample_dw_data = MLX5_GET(query_match_sample_info_out, out, 650 field_format_select_dw); 651 attr->sample_dw_ok_bit = MLX5_GET(query_match_sample_info_out, out, 652 ok_bit_format_select_dw); 653 attr->sample_dw_ok_bit_offset = MLX5_GET(query_match_sample_info_out, 654 out, ok_bit_offset); 655 return 0; 656 #else 657 (void)ctx; 658 (void)sample_field_id; 659 (void)attr; 660 return -ENOTSUP; 661 #endif 662 } 663 664 int 665 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 666 uint32_t *ids, 667 uint32_t num, uint8_t *anchor) 668 { 669 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 670 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 671 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 672 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 673 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 674 int ret; 675 uint32_t idx = 0; 676 uint32_t i; 677 678 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 679 rte_errno = EINVAL; 680 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 681 return -rte_errno; 682 } 683 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 684 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 685 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 686 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 687 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 688 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 689 out, sizeof(out)); 690 if (ret) { 691 rte_errno = ret; 692 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 693 (void *)flex_obj); 694 return -rte_errno; 695 } 696 if (anchor) 697 *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id); 698 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx < num; i++) { 699 void *s_off = (void *)((char *)sample + i * 700 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 701 uint32_t en; 702 703 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 704 flow_match_sample_en); 705 if (!en) 706 continue; 707 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 708 flow_match_sample_field_id); 709 } 710 if (num != idx) { 711 rte_errno = EINVAL; 712 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 713 return -rte_errno; 714 } 715 return ret; 716 } 717 718 struct mlx5_devx_obj * 719 mlx5_devx_cmd_create_flex_parser(void *ctx, 720 struct mlx5_devx_graph_node_attr *data) 721 { 722 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 723 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 724 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 725 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 726 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 727 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 728 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 729 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 730 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 731 uint32_t i; 732 733 if (!parse_flex_obj) { 734 DRV_LOG(ERR, "Failed to allocate flex parser data."); 735 rte_errno = ENOMEM; 736 return NULL; 737 } 738 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 739 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 740 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 741 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 742 MLX5_SET(parse_graph_flex, flex, header_length_mode, 743 data->header_length_mode); 744 MLX5_SET64(parse_graph_flex, flex, modify_field_select, 745 data->modify_field_select); 746 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 747 data->header_length_base_value); 748 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 749 data->header_length_field_offset); 750 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 751 data->header_length_field_shift); 752 MLX5_SET(parse_graph_flex, flex, next_header_field_offset, 753 data->next_header_field_offset); 754 MLX5_SET(parse_graph_flex, flex, next_header_field_size, 755 data->next_header_field_size); 756 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 757 data->header_length_field_mask); 758 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 759 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 760 void *s_off = (void *)((char *)sample + i * 761 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 762 763 if (!s->flow_match_sample_en) 764 continue; 765 MLX5_SET(parse_graph_flow_match_sample, s_off, 766 flow_match_sample_en, !!s->flow_match_sample_en); 767 MLX5_SET(parse_graph_flow_match_sample, s_off, 768 flow_match_sample_field_offset, 769 s->flow_match_sample_field_offset); 770 MLX5_SET(parse_graph_flow_match_sample, s_off, 771 flow_match_sample_offset_mode, 772 s->flow_match_sample_offset_mode); 773 MLX5_SET(parse_graph_flow_match_sample, s_off, 774 flow_match_sample_field_offset_mask, 775 s->flow_match_sample_field_offset_mask); 776 MLX5_SET(parse_graph_flow_match_sample, s_off, 777 flow_match_sample_field_offset_shift, 778 s->flow_match_sample_field_offset_shift); 779 MLX5_SET(parse_graph_flow_match_sample, s_off, 780 flow_match_sample_field_base_offset, 781 s->flow_match_sample_field_base_offset); 782 MLX5_SET(parse_graph_flow_match_sample, s_off, 783 flow_match_sample_tunnel_mode, 784 s->flow_match_sample_tunnel_mode); 785 } 786 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 787 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 788 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 789 void *in_off = (void *)((char *)in_arc + i * 790 MLX5_ST_SZ_BYTES(parse_graph_arc)); 791 void *out_off = (void *)((char *)out_arc + i * 792 MLX5_ST_SZ_BYTES(parse_graph_arc)); 793 794 if (ia->arc_parse_graph_node != 0) { 795 MLX5_SET(parse_graph_arc, in_off, 796 compare_condition_value, 797 ia->compare_condition_value); 798 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 799 ia->start_inner_tunnel); 800 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 801 ia->arc_parse_graph_node); 802 MLX5_SET(parse_graph_arc, in_off, 803 parse_graph_node_handle, 804 ia->parse_graph_node_handle); 805 } 806 if (oa->arc_parse_graph_node != 0) { 807 MLX5_SET(parse_graph_arc, out_off, 808 compare_condition_value, 809 oa->compare_condition_value); 810 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 811 oa->start_inner_tunnel); 812 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 813 oa->arc_parse_graph_node); 814 MLX5_SET(parse_graph_arc, out_off, 815 parse_graph_node_handle, 816 oa->parse_graph_node_handle); 817 } 818 } 819 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 820 out, sizeof(out)); 821 if (!parse_flex_obj->obj) { 822 DEVX_DRV_LOG(ERR, out, "create FLEX PARSE GRAPH", NULL, 0); 823 mlx5_free(parse_flex_obj); 824 return NULL; 825 } 826 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 827 return parse_flex_obj; 828 } 829 830 static int 831 mlx5_devx_cmd_query_hca_parse_graph_node_cap 832 (void *ctx, struct mlx5_hca_flex_attr *attr) 833 { 834 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 835 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 836 void *hcattr; 837 int rc; 838 839 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 840 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | 841 MLX5_HCA_CAP_OPMOD_GET_CUR); 842 if (!hcattr) 843 return rc; 844 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); 845 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); 846 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, 847 header_length_mode); 848 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, 849 sample_offset_mode); 850 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, 851 max_num_arc_in); 852 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, 853 max_num_arc_out); 854 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, 855 max_num_sample); 856 attr->parse_graph_anchor = MLX5_GET(parse_graph_node_cap, hcattr, parse_graph_anchor); 857 attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr, 858 sample_tunnel_inner2); 859 attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr, 860 zero_size_supported); 861 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, 862 sample_id_in_out); 863 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, 864 max_base_header_length); 865 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, 866 max_sample_base_offset); 867 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, 868 max_next_header_offset); 869 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, 870 header_length_mask_width); 871 /* Get the max supported samples from HCA CAP 2 */ 872 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 873 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 874 MLX5_HCA_CAP_OPMOD_GET_CUR); 875 if (!hcattr) 876 return rc; 877 attr->max_num_prog_sample = 878 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); 879 return 0; 880 } 881 882 static int 883 mlx5_devx_query_pkt_integrity_match(void *hcattr) 884 { 885 return MLX5_GET(flow_table_nic_cap, hcattr, 886 ft_field_support_2_nic_receive.inner_l3_ok) && 887 MLX5_GET(flow_table_nic_cap, hcattr, 888 ft_field_support_2_nic_receive.inner_l4_ok) && 889 MLX5_GET(flow_table_nic_cap, hcattr, 890 ft_field_support_2_nic_receive.outer_l3_ok) && 891 MLX5_GET(flow_table_nic_cap, hcattr, 892 ft_field_support_2_nic_receive.outer_l4_ok) && 893 MLX5_GET(flow_table_nic_cap, hcattr, 894 ft_field_support_2_nic_receive 895 .inner_ipv4_checksum_ok) && 896 MLX5_GET(flow_table_nic_cap, hcattr, 897 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 898 MLX5_GET(flow_table_nic_cap, hcattr, 899 ft_field_support_2_nic_receive 900 .outer_ipv4_checksum_ok) && 901 MLX5_GET(flow_table_nic_cap, hcattr, 902 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 903 } 904 905 /** 906 * Query HCA attributes. 907 * Using those attributes we can check on run time if the device 908 * is having the required capabilities. 909 * 910 * @param[in] ctx 911 * Context returned from mlx5 open_device() glue function. 912 * @param[out] attr 913 * Attributes device values. 914 * 915 * @return 916 * 0 on success, a negative value otherwise. 917 */ 918 int 919 mlx5_devx_cmd_query_hca_attr(void *ctx, 920 struct mlx5_hca_attr *attr) 921 { 922 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 923 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 924 bool hca_cap_2_sup; 925 uint64_t general_obj_types_supported = 0; 926 void *hcattr; 927 int rc, i; 928 929 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 930 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 931 MLX5_HCA_CAP_OPMOD_GET_CUR); 932 if (!hcattr) 933 return rc; 934 hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2); 935 attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq); 936 attr->flow_counter_bulk_alloc_bitmap = 937 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 938 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 939 flow_counters_dump); 940 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp); 941 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp); 942 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 943 log_max_rqt_size); 944 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 945 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 946 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 947 log_max_hairpin_queues); 948 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 949 log_max_hairpin_wq_data_sz); 950 attr->log_max_hairpin_num_packets = MLX5_GET 951 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 952 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 953 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 954 relaxed_ordering_write); 955 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 956 relaxed_ordering_read); 957 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 958 access_register_user); 959 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 960 eth_net_offloads); 961 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 962 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 963 flex_parser_protocols); 964 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 965 max_geneve_tlv_options); 966 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 967 max_geneve_tlv_option_data_len); 968 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 969 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 970 general_obj_types) & 971 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 972 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 973 general_obj_types) & 974 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 975 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 976 general_obj_types) & 977 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 978 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 979 general_obj_types) & 980 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 981 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 982 wqe_index_ignore_cap); 983 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 984 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 985 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 986 log_max_static_sq_wq); 987 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 988 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 989 device_frequency_khz); 990 attr->scatter_fcs_w_decap_disable = 991 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 992 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 993 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 994 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 995 attr->steering_format_version = 996 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 997 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 998 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 999 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 1000 regexp_num_of_engines); 1001 /* Read the general_obj_types bitmap and extract the relevant bits. */ 1002 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 1003 general_obj_types); 1004 attr->vdpa.valid = !!(general_obj_types_supported & 1005 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 1006 attr->vdpa.queue_counters_valid = 1007 !!(general_obj_types_supported & 1008 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 1009 attr->parse_graph_flex_node = 1010 !!(general_obj_types_supported & 1011 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 1012 attr->flow_hit_aso = !!(general_obj_types_supported & 1013 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 1014 attr->geneve_tlv_opt = !!(general_obj_types_supported & 1015 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 1016 attr->dek = !!(general_obj_types_supported & 1017 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 1018 attr->import_kek = !!(general_obj_types_supported & 1019 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 1020 attr->credential = !!(general_obj_types_supported & 1021 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 1022 attr->crypto_login = !!(general_obj_types_supported & 1023 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 1024 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 1025 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 1026 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 1027 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 1028 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 1029 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 1030 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 1031 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 1032 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 1033 attr->reg_c_preserve = 1034 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 1035 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 1036 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 1037 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 1038 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 1039 compress_mmo_sq); 1040 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 1041 decompress_mmo_sq); 1042 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 1043 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 1044 compress_mmo_qp); 1045 attr->decomp_deflate_v1_en = MLX5_GET(cmd_hca_cap, hcattr, 1046 decompress_deflate_v1); 1047 attr->decomp_deflate_v2_en = MLX5_GET(cmd_hca_cap, hcattr, 1048 decompress_deflate_v2); 1049 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 1050 compress_min_block_size); 1051 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 1052 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 1053 log_compress_mmo_size); 1054 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 1055 log_decompress_mmo_size); 1056 attr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr, 1057 decompress_lz4_data_only_v2); 1058 attr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, 1059 decompress_lz4_no_checksum_v2); 1060 attr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, 1061 decompress_lz4_checksum_v2); 1062 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 1063 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 1064 mini_cqe_resp_flow_tag); 1065 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 1066 mini_cqe_resp_l3_l4_tag); 1067 attr->enhanced_cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, 1068 enhanced_cqe_compression); 1069 attr->umr_indirect_mkey_disabled = 1070 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 1071 attr->umr_modify_entity_size_disabled = 1072 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 1073 attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time); 1074 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 1075 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 1076 general_obj_types) & 1077 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 1078 attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); 1079 attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr, 1080 max_flow_counter_15_0); 1081 attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr, 1082 max_flow_counter_31_16); 1083 attr->alloc_flow_counter_pd = MLX5_GET(cmd_hca_cap, hcattr, 1084 alloc_flow_counter_pd); 1085 attr->flow_counter_access_aso = MLX5_GET(cmd_hca_cap, hcattr, 1086 flow_counter_access_aso); 1087 attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr, 1088 flow_access_aso_opc_mod); 1089 /* 1090 * Flex item support needs max_num_prog_sample_field 1091 * from the Capabilities 2 table for PARSE_GRAPH_NODE 1092 */ 1093 if (attr->parse_graph_flex_node) { 1094 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap 1095 (ctx, &attr->flex); 1096 if (rc) 1097 return -1; 1098 attr->flex.query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr, 1099 query_match_sample_info); 1100 } 1101 if (attr->crypto) { 1102 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) || 1103 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_multi_block_be_tweak) || 1104 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_single_block_le_tweak); 1105 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1106 MLX5_GET_HCA_CAP_OP_MOD_CRYPTO | 1107 MLX5_HCA_CAP_OPMOD_GET_CUR); 1108 if (!hcattr) 1109 return -1; 1110 attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps, 1111 hcattr, wrapped_import_method) 1112 & 1 << 2); 1113 } 1114 if (hca_cap_2_sup) { 1115 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1116 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 1117 MLX5_HCA_CAP_OPMOD_GET_CUR); 1118 if (!hcattr) { 1119 DRV_LOG(DEBUG, 1120 "Failed to query DevX HCA capabilities 2."); 1121 return rc; 1122 } 1123 attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, 1124 log_min_stride_wqe_sz); 1125 attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr, 1126 hairpin_sq_wqe_bb_size); 1127 attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr, 1128 hairpin_sq_wq_in_host_mem); 1129 attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr, 1130 hairpin_data_buffer_locked); 1131 attr->flow_counter_bulk_log_max_alloc = MLX5_GET(cmd_hca_cap_2, 1132 hcattr, flow_counter_bulk_log_max_alloc); 1133 attr->flow_counter_bulk_log_granularity = 1134 MLX5_GET(cmd_hca_cap_2, hcattr, 1135 flow_counter_bulk_log_granularity); 1136 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1137 cross_vhca_object_to_object_supported); 1138 attr->cross_vhca = 1139 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR) && 1140 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT) && 1141 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT) && 1142 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC); 1143 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1144 allowed_object_for_other_vhca_access); 1145 attr->cross_vhca = attr->cross_vhca && 1146 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR) && 1147 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_FT) && 1148 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC); 1149 } 1150 if (attr->log_min_stride_wqe_sz == 0) 1151 attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 1152 if (attr->qos.sup) { 1153 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1154 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 1155 MLX5_HCA_CAP_OPMOD_GET_CUR); 1156 if (!hcattr) { 1157 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); 1158 return rc; 1159 } 1160 attr->qos.flow_meter_old = 1161 MLX5_GET(qos_cap, hcattr, flow_meter_old); 1162 attr->qos.log_max_flow_meter = 1163 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 1164 attr->qos.flow_meter_reg_c_ids = 1165 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 1166 attr->qos.flow_meter = 1167 MLX5_GET(qos_cap, hcattr, flow_meter); 1168 attr->qos.packet_pacing = 1169 MLX5_GET(qos_cap, hcattr, packet_pacing); 1170 attr->qos.wqe_rate_pp = 1171 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 1172 if (attr->qos.flow_meter_aso_sup) { 1173 attr->qos.log_meter_aso_granularity = 1174 MLX5_GET(qos_cap, hcattr, 1175 log_meter_aso_granularity); 1176 attr->qos.log_meter_aso_max_alloc = 1177 MLX5_GET(qos_cap, hcattr, 1178 log_meter_aso_max_alloc); 1179 attr->qos.log_max_num_meter_aso = 1180 MLX5_GET(qos_cap, hcattr, 1181 log_max_num_meter_aso); 1182 } 1183 } 1184 if (attr->vdpa.valid) 1185 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 1186 if (!attr->eth_net_offloads) 1187 return 0; 1188 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 1189 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1190 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 1191 MLX5_HCA_CAP_OPMOD_GET_CUR); 1192 if (!hcattr) { 1193 attr->log_max_ft_sampler_num = 0; 1194 return rc; 1195 } 1196 attr->log_max_ft_sampler_num = MLX5_GET 1197 (flow_table_nic_cap, hcattr, 1198 flow_table_properties_nic_receive.log_max_ft_sampler_num); 1199 attr->flow.tunnel_header_0_1 = MLX5_GET 1200 (flow_table_nic_cap, hcattr, 1201 ft_field_support_2_nic_receive.tunnel_header_0_1); 1202 attr->flow.tunnel_header_2_3 = MLX5_GET 1203 (flow_table_nic_cap, hcattr, 1204 ft_field_support_2_nic_receive.tunnel_header_2_3); 1205 attr->modify_outer_ip_ecn = MLX5_GET 1206 (flow_table_nic_cap, hcattr, 1207 ft_header_modify_nic_receive.outer_ip_ecn); 1208 attr->set_reg_c = 0xff; 1209 if (attr->nic_flow_table) { 1210 #define GET_RX_REG_X_BITS \ 1211 MLX5_GET(flow_table_nic_cap, hcattr, \ 1212 ft_header_modify_nic_receive.metadata_reg_c_x) 1213 #define GET_TX_REG_X_BITS \ 1214 MLX5_GET(flow_table_nic_cap, hcattr, \ 1215 ft_header_modify_nic_transmit.metadata_reg_c_x) 1216 1217 uint32_t tx_reg, rx_reg; 1218 1219 tx_reg = GET_TX_REG_X_BITS; 1220 rx_reg = GET_RX_REG_X_BITS; 1221 attr->set_reg_c &= (rx_reg & tx_reg); 1222 1223 #undef GET_RX_REG_X_BITS 1224 #undef GET_TX_REG_X_BITS 1225 } 1226 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 1227 attr->inner_ipv4_ihl = MLX5_GET 1228 (flow_table_nic_cap, hcattr, 1229 ft_field_support_2_nic_receive.inner_ipv4_ihl); 1230 attr->outer_ipv4_ihl = MLX5_GET 1231 (flow_table_nic_cap, hcattr, 1232 ft_field_support_2_nic_receive.outer_ipv4_ihl); 1233 attr->lag_rx_port_affinity = MLX5_GET 1234 (flow_table_nic_cap, hcattr, 1235 ft_field_support_2_nic_receive.lag_rx_port_affinity); 1236 /* Query HCA offloads for Ethernet protocol. */ 1237 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1238 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 1239 MLX5_HCA_CAP_OPMOD_GET_CUR); 1240 if (!hcattr) { 1241 attr->eth_net_offloads = 0; 1242 return rc; 1243 } 1244 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 1245 hcattr, wqe_vlan_insert); 1246 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 1247 hcattr, csum_cap); 1248 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 1249 hcattr, vlan_cap); 1250 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1251 lro_cap); 1252 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1253 hcattr, max_lso_cap); 1254 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1255 hcattr, scatter_fcs); 1256 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1257 hcattr, tunnel_lro_gre); 1258 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1259 hcattr, tunnel_lro_vxlan); 1260 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1261 hcattr, swp); 1262 attr->tunnel_stateless_gre = 1263 MLX5_GET(per_protocol_networking_offload_caps, 1264 hcattr, tunnel_stateless_gre); 1265 attr->tunnel_stateless_vxlan = 1266 MLX5_GET(per_protocol_networking_offload_caps, 1267 hcattr, tunnel_stateless_vxlan); 1268 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1269 hcattr, swp_csum); 1270 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1271 hcattr, swp_lso); 1272 attr->lro_max_msg_sz_mode = MLX5_GET 1273 (per_protocol_networking_offload_caps, 1274 hcattr, lro_max_msg_sz_mode); 1275 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1276 attr->lro_timer_supported_periods[i] = 1277 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1278 lro_timer_supported_periods[i]); 1279 } 1280 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1281 hcattr, lro_min_mss_size); 1282 attr->tunnel_stateless_geneve_rx = 1283 MLX5_GET(per_protocol_networking_offload_caps, 1284 hcattr, tunnel_stateless_geneve_rx); 1285 attr->geneve_max_opt_len = 1286 MLX5_GET(per_protocol_networking_offload_caps, 1287 hcattr, max_geneve_opt_len); 1288 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1289 hcattr, wqe_inline_mode); 1290 attr->tunnel_stateless_gtp = MLX5_GET 1291 (per_protocol_networking_offload_caps, 1292 hcattr, tunnel_stateless_gtp); 1293 attr->rss_ind_tbl_cap = MLX5_GET 1294 (per_protocol_networking_offload_caps, 1295 hcattr, rss_ind_tbl_cap); 1296 /* Query HCA attribute for ROCE. */ 1297 if (attr->roce) { 1298 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1299 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1300 MLX5_HCA_CAP_OPMOD_GET_CUR); 1301 if (!hcattr) { 1302 DRV_LOG(DEBUG, 1303 "Failed to query devx HCA ROCE capabilities"); 1304 return rc; 1305 } 1306 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1307 } 1308 if (attr->eth_virt && 1309 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1310 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1311 if (rc) { 1312 attr->eth_virt = 0; 1313 goto error; 1314 } 1315 } 1316 if (attr->eswitch_manager) { 1317 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1318 MLX5_SET_HCA_CAP_OP_MOD_ESW | 1319 MLX5_HCA_CAP_OPMOD_GET_CUR); 1320 if (!hcattr) 1321 return rc; 1322 attr->esw_mgr_vport_id_valid = 1323 MLX5_GET(esw_cap, hcattr, 1324 esw_manager_vport_number_valid); 1325 attr->esw_mgr_vport_id = 1326 MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); 1327 } 1328 if (attr->eswitch_manager) { 1329 uint32_t esw_reg; 1330 1331 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1332 MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE | 1333 MLX5_HCA_CAP_OPMOD_GET_CUR); 1334 if (!hcattr) 1335 return rc; 1336 esw_reg = MLX5_GET(flow_table_esw_cap, hcattr, 1337 ft_header_modify_esw_fdb.metadata_reg_c_x); 1338 attr->set_reg_c &= esw_reg; 1339 } 1340 return 0; 1341 error: 1342 rc = (rc > 0) ? -rc : rc; 1343 return rc; 1344 } 1345 1346 /** 1347 * Query TIS transport domain from QP verbs object using DevX API. 1348 * 1349 * @param[in] qp 1350 * Pointer to verbs QP returned by ibv_create_qp . 1351 * @param[in] tis_num 1352 * TIS number of TIS to query. 1353 * @param[out] tis_td 1354 * Pointer to TIS transport domain variable, to be set by the routine. 1355 * 1356 * @return 1357 * 0 on success, a negative value otherwise. 1358 */ 1359 int 1360 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1361 uint32_t *tis_td) 1362 { 1363 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1364 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1365 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1366 int rc; 1367 void *tis_ctx; 1368 1369 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1370 MLX5_SET(query_tis_in, in, tisn, tis_num); 1371 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1372 if (rc) { 1373 DRV_LOG(ERR, "Failed to query QP using DevX"); 1374 return -rc; 1375 }; 1376 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1377 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1378 return 0; 1379 #else 1380 (void)qp; 1381 (void)tis_num; 1382 (void)tis_td; 1383 return -ENOTSUP; 1384 #endif 1385 } 1386 1387 /** 1388 * Fill WQ data for DevX API command. 1389 * Utility function for use when creating DevX objects containing a WQ. 1390 * 1391 * @param[in] wq_ctx 1392 * Pointer to WQ context to fill with data. 1393 * @param [in] wq_attr 1394 * Pointer to WQ attributes structure to fill in WQ context. 1395 */ 1396 static void 1397 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1398 { 1399 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1400 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1401 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1402 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1403 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1404 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1405 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1406 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1407 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1408 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1409 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1410 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1411 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1412 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1413 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1414 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1415 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1416 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1417 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1418 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1419 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1420 wq_attr->log_hairpin_num_packets); 1421 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1422 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1423 wq_attr->single_wqe_log_num_of_strides); 1424 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1425 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1426 wq_attr->single_stride_log_num_of_bytes); 1427 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1428 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1429 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1430 } 1431 1432 /** 1433 * Create RQ using DevX API. 1434 * 1435 * @param[in] ctx 1436 * Context returned from mlx5 open_device() glue function. 1437 * @param [in] rq_attr 1438 * Pointer to create RQ attributes structure. 1439 * @param [in] socket 1440 * CPU socket ID for allocations. 1441 * 1442 * @return 1443 * The DevX object created, NULL otherwise and rte_errno is set. 1444 */ 1445 struct mlx5_devx_obj * 1446 mlx5_devx_cmd_create_rq(void *ctx, 1447 struct mlx5_devx_create_rq_attr *rq_attr, 1448 int socket) 1449 { 1450 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1451 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1452 void *rq_ctx, *wq_ctx; 1453 struct mlx5_devx_wq_attr *wq_attr; 1454 struct mlx5_devx_obj *rq = NULL; 1455 1456 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1457 if (!rq) { 1458 DRV_LOG(ERR, "Failed to allocate RQ data"); 1459 rte_errno = ENOMEM; 1460 return NULL; 1461 } 1462 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1463 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1464 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1465 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1466 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1467 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1468 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1469 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1470 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1471 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1472 MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type); 1473 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1474 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1475 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1476 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1477 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1478 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1479 wq_attr = &rq_attr->wq_attr; 1480 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1481 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1482 out, sizeof(out)); 1483 if (!rq->obj) { 1484 DEVX_DRV_LOG(ERR, out, "create RQ", NULL, 0); 1485 mlx5_free(rq); 1486 return NULL; 1487 } 1488 rq->id = MLX5_GET(create_rq_out, out, rqn); 1489 return rq; 1490 } 1491 1492 /** 1493 * Modify RQ using DevX API. 1494 * 1495 * @param[in] rq 1496 * Pointer to RQ object structure. 1497 * @param [in] rq_attr 1498 * Pointer to modify RQ attributes structure. 1499 * 1500 * @return 1501 * 0 on success, a negative errno value otherwise and rte_errno is set. 1502 */ 1503 int 1504 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1505 struct mlx5_devx_modify_rq_attr *rq_attr) 1506 { 1507 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1508 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1509 void *rq_ctx, *wq_ctx; 1510 int ret; 1511 1512 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1513 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1514 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1515 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1516 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1517 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1518 if (rq_attr->modify_bitmask & 1519 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1520 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1521 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1522 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1523 if (rq_attr->modify_bitmask & 1524 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1525 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1526 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1527 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1528 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1529 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1530 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1531 } 1532 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1533 out, sizeof(out)); 1534 if (ret) { 1535 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1536 rte_errno = errno; 1537 return -errno; 1538 } 1539 return ret; 1540 } 1541 1542 /** 1543 * Create RMP using DevX API. 1544 * 1545 * @param[in] ctx 1546 * Context returned from mlx5 open_device() glue function. 1547 * @param [in] rmp_attr 1548 * Pointer to create RMP attributes structure. 1549 * @param [in] socket 1550 * CPU socket ID for allocations. 1551 * 1552 * @return 1553 * The DevX object created, NULL otherwise and rte_errno is set. 1554 */ 1555 struct mlx5_devx_obj * 1556 mlx5_devx_cmd_create_rmp(void *ctx, 1557 struct mlx5_devx_create_rmp_attr *rmp_attr, 1558 int socket) 1559 { 1560 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0}; 1561 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0}; 1562 void *rmp_ctx, *wq_ctx; 1563 struct mlx5_devx_wq_attr *wq_attr; 1564 struct mlx5_devx_obj *rmp = NULL; 1565 1566 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket); 1567 if (!rmp) { 1568 DRV_LOG(ERR, "Failed to allocate RMP data"); 1569 rte_errno = ENOMEM; 1570 return NULL; 1571 } 1572 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP); 1573 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx); 1574 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state); 1575 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe, 1576 rmp_attr->basic_cyclic_rcv_wqe); 1577 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq); 1578 wq_attr = &rmp_attr->wq_attr; 1579 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1580 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1581 sizeof(out)); 1582 if (!rmp->obj) { 1583 DEVX_DRV_LOG(ERR, out, "create RMP", NULL, 0); 1584 mlx5_free(rmp); 1585 return NULL; 1586 } 1587 rmp->id = MLX5_GET(create_rmp_out, out, rmpn); 1588 return rmp; 1589 } 1590 1591 /* 1592 * Create TIR using DevX API. 1593 * 1594 * @param[in] ctx 1595 * Context returned from mlx5 open_device() glue function. 1596 * @param [in] tir_attr 1597 * Pointer to TIR attributes structure. 1598 * 1599 * @return 1600 * The DevX object created, NULL otherwise and rte_errno is set. 1601 */ 1602 struct mlx5_devx_obj * 1603 mlx5_devx_cmd_create_tir(void *ctx, 1604 struct mlx5_devx_tir_attr *tir_attr) 1605 { 1606 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1607 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1608 void *tir_ctx, *outer, *inner, *rss_key; 1609 struct mlx5_devx_obj *tir = NULL; 1610 1611 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1612 if (!tir) { 1613 DRV_LOG(ERR, "Failed to allocate TIR data"); 1614 rte_errno = ENOMEM; 1615 return NULL; 1616 } 1617 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1618 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1619 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1620 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1621 tir_attr->lro_timeout_period_usecs); 1622 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1623 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1624 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1625 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1626 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1627 tir_attr->tunneled_offload_en); 1628 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1629 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1630 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1631 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1632 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1633 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1634 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1635 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1636 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1637 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1638 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1639 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1640 tir_attr->rx_hash_field_selector_outer.selected_fields); 1641 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1642 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1643 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1644 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1645 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1646 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1647 tir_attr->rx_hash_field_selector_inner.selected_fields); 1648 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1649 out, sizeof(out)); 1650 if (!tir->obj) { 1651 DEVX_DRV_LOG(ERR, out, "create TIR", NULL, 0); 1652 mlx5_free(tir); 1653 return NULL; 1654 } 1655 tir->id = MLX5_GET(create_tir_out, out, tirn); 1656 return tir; 1657 } 1658 1659 /** 1660 * Modify TIR using DevX API. 1661 * 1662 * @param[in] tir 1663 * Pointer to TIR DevX object structure. 1664 * @param [in] modify_tir_attr 1665 * Pointer to TIR modification attributes structure. 1666 * 1667 * @return 1668 * 0 on success, a negative errno value otherwise and rte_errno is set. 1669 */ 1670 int 1671 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1672 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1673 { 1674 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1675 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1676 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1677 void *tir_ctx; 1678 int ret; 1679 1680 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1681 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1682 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1683 modify_tir_attr->modify_bitmask); 1684 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1685 if (modify_tir_attr->modify_bitmask & 1686 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1687 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1688 tir_attr->lro_timeout_period_usecs); 1689 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1690 tir_attr->lro_enable_mask); 1691 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1692 tir_attr->lro_max_msg_sz); 1693 } 1694 if (modify_tir_attr->modify_bitmask & 1695 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1696 MLX5_SET(tirc, tir_ctx, indirect_table, 1697 tir_attr->indirect_table); 1698 if (modify_tir_attr->modify_bitmask & 1699 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1700 int i; 1701 void *outer, *inner; 1702 1703 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1704 tir_attr->rx_hash_symmetric); 1705 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1706 for (i = 0; i < 10; i++) { 1707 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1708 tir_attr->rx_hash_toeplitz_key[i]); 1709 } 1710 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1711 rx_hash_field_selector_outer); 1712 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1713 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1714 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1715 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1716 MLX5_SET 1717 (rx_hash_field_select, outer, selected_fields, 1718 tir_attr->rx_hash_field_selector_outer.selected_fields); 1719 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1720 rx_hash_field_selector_inner); 1721 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1722 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1723 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1724 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1725 MLX5_SET 1726 (rx_hash_field_select, inner, selected_fields, 1727 tir_attr->rx_hash_field_selector_inner.selected_fields); 1728 } 1729 if (modify_tir_attr->modify_bitmask & 1730 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1731 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1732 } 1733 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1734 out, sizeof(out)); 1735 if (ret) { 1736 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1737 rte_errno = errno; 1738 return -errno; 1739 } 1740 return ret; 1741 } 1742 1743 /** 1744 * Create RQT using DevX API. 1745 * 1746 * @param[in] ctx 1747 * Context returned from mlx5 open_device() glue function. 1748 * @param [in] rqt_attr 1749 * Pointer to RQT attributes structure. 1750 * 1751 * @return 1752 * The DevX object created, NULL otherwise and rte_errno is set. 1753 */ 1754 struct mlx5_devx_obj * 1755 mlx5_devx_cmd_create_rqt(void *ctx, 1756 struct mlx5_devx_rqt_attr *rqt_attr) 1757 { 1758 uint32_t *in = NULL; 1759 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1760 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1761 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1762 void *rqt_ctx; 1763 struct mlx5_devx_obj *rqt = NULL; 1764 int i; 1765 1766 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1767 if (!in) { 1768 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1769 rte_errno = ENOMEM; 1770 return NULL; 1771 } 1772 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1773 if (!rqt) { 1774 DRV_LOG(ERR, "Failed to allocate RQT data"); 1775 rte_errno = ENOMEM; 1776 mlx5_free(in); 1777 return NULL; 1778 } 1779 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1780 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1781 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1782 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1783 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1784 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1785 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1786 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1787 mlx5_free(in); 1788 if (!rqt->obj) { 1789 DEVX_DRV_LOG(ERR, out, "create RQT", NULL, 0); 1790 mlx5_free(rqt); 1791 return NULL; 1792 } 1793 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1794 return rqt; 1795 } 1796 1797 /** 1798 * Modify RQT using DevX API. 1799 * 1800 * @param[in] rqt 1801 * Pointer to RQT DevX object structure. 1802 * @param [in] rqt_attr 1803 * Pointer to RQT attributes structure. 1804 * 1805 * @return 1806 * 0 on success, a negative errno value otherwise and rte_errno is set. 1807 */ 1808 int 1809 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1810 struct mlx5_devx_rqt_attr *rqt_attr) 1811 { 1812 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1813 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1814 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1815 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1816 void *rqt_ctx; 1817 int i; 1818 int ret; 1819 1820 if (!in) { 1821 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1822 rte_errno = ENOMEM; 1823 return -ENOMEM; 1824 } 1825 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1826 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1827 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1828 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1829 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1830 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1831 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1832 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1833 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1834 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1835 mlx5_free(in); 1836 if (ret) { 1837 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1838 rte_errno = errno; 1839 return -rte_errno; 1840 } 1841 return ret; 1842 } 1843 1844 /** 1845 * Create SQ using DevX API. 1846 * 1847 * @param[in] ctx 1848 * Context returned from mlx5 open_device() glue function. 1849 * @param [in] sq_attr 1850 * Pointer to SQ attributes structure. 1851 * @param [in] socket 1852 * CPU socket ID for allocations. 1853 * 1854 * @return 1855 * The DevX object created, NULL otherwise and rte_errno is set. 1856 **/ 1857 struct mlx5_devx_obj * 1858 mlx5_devx_cmd_create_sq(void *ctx, 1859 struct mlx5_devx_create_sq_attr *sq_attr) 1860 { 1861 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1862 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1863 void *sq_ctx; 1864 void *wq_ctx; 1865 struct mlx5_devx_wq_attr *wq_attr; 1866 struct mlx5_devx_obj *sq = NULL; 1867 1868 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1869 if (!sq) { 1870 DRV_LOG(ERR, "Failed to allocate SQ data"); 1871 rte_errno = ENOMEM; 1872 return NULL; 1873 } 1874 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1875 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1876 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1877 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1878 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1879 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1880 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1881 sq_attr->allow_multi_pkt_send_wqe); 1882 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1883 sq_attr->min_wqe_inline_mode); 1884 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1885 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1886 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1887 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1888 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1889 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1890 MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type); 1891 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1892 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1893 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1894 sq_attr->packet_pacing_rate_limit_index); 1895 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1896 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1897 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1898 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1899 wq_attr = &sq_attr->wq_attr; 1900 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1901 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1902 out, sizeof(out)); 1903 if (!sq->obj) { 1904 DEVX_DRV_LOG(ERR, out, "create SQ", NULL, 0); 1905 mlx5_free(sq); 1906 return NULL; 1907 } 1908 sq->id = MLX5_GET(create_sq_out, out, sqn); 1909 return sq; 1910 } 1911 1912 /** 1913 * Modify SQ using DevX API. 1914 * 1915 * @param[in] sq 1916 * Pointer to SQ object structure. 1917 * @param [in] sq_attr 1918 * Pointer to SQ attributes structure. 1919 * 1920 * @return 1921 * 0 on success, a negative errno value otherwise and rte_errno is set. 1922 */ 1923 int 1924 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1925 struct mlx5_devx_modify_sq_attr *sq_attr) 1926 { 1927 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1928 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1929 void *sq_ctx; 1930 int ret; 1931 1932 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1933 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1934 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1935 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1936 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1937 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1938 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1939 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1940 out, sizeof(out)); 1941 if (ret) { 1942 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1943 rte_errno = errno; 1944 return -rte_errno; 1945 } 1946 return ret; 1947 } 1948 1949 /** 1950 * Create TIS using DevX API. 1951 * 1952 * @param[in] ctx 1953 * Context returned from mlx5 open_device() glue function. 1954 * @param [in] tis_attr 1955 * Pointer to TIS attributes structure. 1956 * 1957 * @return 1958 * The DevX object created, NULL otherwise and rte_errno is set. 1959 */ 1960 struct mlx5_devx_obj * 1961 mlx5_devx_cmd_create_tis(void *ctx, 1962 struct mlx5_devx_tis_attr *tis_attr) 1963 { 1964 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1965 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1966 struct mlx5_devx_obj *tis = NULL; 1967 void *tis_ctx; 1968 1969 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1970 if (!tis) { 1971 DRV_LOG(ERR, "Failed to allocate TIS object"); 1972 rte_errno = ENOMEM; 1973 return NULL; 1974 } 1975 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1976 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1977 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1978 tis_attr->strict_lag_tx_port_affinity); 1979 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1980 tis_attr->lag_tx_port_affinity); 1981 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1982 MLX5_SET(tisc, tis_ctx, transport_domain, 1983 tis_attr->transport_domain); 1984 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1985 out, sizeof(out)); 1986 if (!tis->obj) { 1987 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 1988 mlx5_free(tis); 1989 return NULL; 1990 } 1991 tis->id = MLX5_GET(create_tis_out, out, tisn); 1992 return tis; 1993 } 1994 1995 /** 1996 * Create transport domain using DevX API. 1997 * 1998 * @param[in] ctx 1999 * Context returned from mlx5 open_device() glue function. 2000 * @return 2001 * The DevX object created, NULL otherwise and rte_errno is set. 2002 */ 2003 struct mlx5_devx_obj * 2004 mlx5_devx_cmd_create_td(void *ctx) 2005 { 2006 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 2007 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 2008 struct mlx5_devx_obj *td = NULL; 2009 2010 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 2011 if (!td) { 2012 DRV_LOG(ERR, "Failed to allocate TD object"); 2013 rte_errno = ENOMEM; 2014 return NULL; 2015 } 2016 MLX5_SET(alloc_transport_domain_in, in, opcode, 2017 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 2018 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2019 out, sizeof(out)); 2020 if (!td->obj) { 2021 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 2022 mlx5_free(td); 2023 return NULL; 2024 } 2025 td->id = MLX5_GET(alloc_transport_domain_out, out, 2026 transport_domain); 2027 return td; 2028 } 2029 2030 /** 2031 * Dump all flows to file. 2032 * 2033 * @param[in] fdb_domain 2034 * FDB domain. 2035 * @param[in] rx_domain 2036 * RX domain. 2037 * @param[in] tx_domain 2038 * TX domain. 2039 * @param[out] file 2040 * Pointer to file stream. 2041 * 2042 * @return 2043 * 0 on success, a negative value otherwise. 2044 */ 2045 int 2046 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 2047 void *rx_domain __rte_unused, 2048 void *tx_domain __rte_unused, FILE *file __rte_unused) 2049 { 2050 int ret = 0; 2051 2052 #ifdef HAVE_MLX5_DR_FLOW_DUMP 2053 if (fdb_domain) { 2054 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 2055 if (ret) 2056 return ret; 2057 } 2058 MLX5_ASSERT(rx_domain); 2059 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 2060 if (ret) 2061 return ret; 2062 MLX5_ASSERT(tx_domain); 2063 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 2064 #else 2065 ret = ENOTSUP; 2066 #endif 2067 return -ret; 2068 } 2069 2070 int 2071 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 2072 FILE *file __rte_unused) 2073 { 2074 int ret = 0; 2075 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 2076 if (rule_info) 2077 ret = mlx5_glue->dr_dump_rule(file, rule_info); 2078 #else 2079 ret = ENOTSUP; 2080 #endif 2081 return -ret; 2082 } 2083 2084 /* 2085 * Create CQ using DevX API. 2086 * 2087 * @param[in] ctx 2088 * Context returned from mlx5 open_device() glue function. 2089 * @param [in] attr 2090 * Pointer to CQ attributes structure. 2091 * 2092 * @return 2093 * The DevX object created, NULL otherwise and rte_errno is set. 2094 */ 2095 struct mlx5_devx_obj * 2096 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 2097 { 2098 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 2099 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 2100 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2101 sizeof(*cq_obj), 2102 0, SOCKET_ID_ANY); 2103 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 2104 2105 if (!cq_obj) { 2106 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 2107 rte_errno = ENOMEM; 2108 return NULL; 2109 } 2110 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 2111 if (attr->db_umem_valid) { 2112 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 2113 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 2114 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 2115 } else { 2116 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 2117 } 2118 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 2119 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 2120 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 2121 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 2122 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 2123 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2124 MLX5_SET(cqc, cqctx, log_page_size, 2125 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2126 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 2127 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 2128 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 2129 MLX5_SET(cqc, cqctx, cqe_comp_layout, !!attr->cqe_comp_layout); 2130 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 2131 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 2132 attr->mini_cqe_res_format_ext); 2133 if (attr->q_umem_valid) { 2134 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 2135 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 2136 MLX5_SET64(create_cq_in, in, cq_umem_offset, 2137 attr->q_umem_offset); 2138 } 2139 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2140 sizeof(out)); 2141 if (!cq_obj->obj) { 2142 DEVX_DRV_LOG(ERR, out, "create CQ", NULL, 0); 2143 mlx5_free(cq_obj); 2144 return NULL; 2145 } 2146 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 2147 return cq_obj; 2148 } 2149 2150 /** 2151 * Create VIRTQ using DevX API. 2152 * 2153 * @param[in] ctx 2154 * Context returned from mlx5 open_device() glue function. 2155 * @param [in] attr 2156 * Pointer to VIRTQ attributes structure. 2157 * 2158 * @return 2159 * The DevX object created, NULL otherwise and rte_errno is set. 2160 */ 2161 struct mlx5_devx_obj * 2162 mlx5_devx_cmd_create_virtq(void *ctx, 2163 struct mlx5_devx_virtq_attr *attr) 2164 { 2165 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2166 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2167 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2168 sizeof(*virtq_obj), 2169 0, SOCKET_ID_ANY); 2170 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2171 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2172 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2173 2174 if (!virtq_obj) { 2175 DRV_LOG(ERR, "Failed to allocate virtq data."); 2176 rte_errno = ENOMEM; 2177 return NULL; 2178 } 2179 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2180 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2181 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2182 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2183 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2184 attr->hw_available_index); 2185 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 2186 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2187 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2188 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2189 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2190 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2191 attr->virtio_version_1_0); 2192 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2193 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2194 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2195 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2196 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 2197 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2198 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 2199 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2200 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 2201 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 2202 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 2203 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 2204 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 2205 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 2206 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 2207 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 2208 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 2209 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 2210 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 2211 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 2212 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 2213 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 2214 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 2215 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2216 sizeof(out)); 2217 if (!virtq_obj->obj) { 2218 DEVX_DRV_LOG(ERR, out, "create VIRTQ", NULL, 0); 2219 mlx5_free(virtq_obj); 2220 return NULL; 2221 } 2222 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2223 return virtq_obj; 2224 } 2225 2226 /** 2227 * Modify VIRTQ using DevX API. 2228 * 2229 * @param[in] virtq_obj 2230 * Pointer to virtq object structure. 2231 * @param [in] attr 2232 * Pointer to modify virtq attributes structure. 2233 * 2234 * @return 2235 * 0 on success, a negative errno value otherwise and rte_errno is set. 2236 */ 2237 int 2238 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 2239 struct mlx5_devx_virtq_attr *attr) 2240 { 2241 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2242 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2243 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2244 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2245 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2246 int ret; 2247 2248 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2249 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 2250 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2251 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2252 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2253 MLX5_SET64(virtio_net_q, virtq, modify_field_select, 2254 attr->mod_fields_bitmap); 2255 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2256 if (!attr->mod_fields_bitmap) { 2257 DRV_LOG(ERR, "Failed to modify VIRTQ for no type set."); 2258 rte_errno = EINVAL; 2259 return -rte_errno; 2260 } 2261 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE) 2262 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 2263 if (attr->mod_fields_bitmap & 2264 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) { 2265 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 2266 attr->dirty_bitmap_mkey); 2267 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 2268 attr->dirty_bitmap_addr); 2269 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 2270 attr->dirty_bitmap_size); 2271 } 2272 if (attr->mod_fields_bitmap & 2273 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE) 2274 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 2275 attr->dirty_bitmap_dump_enable); 2276 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) { 2277 MLX5_SET(virtio_q, virtctx, queue_period_mode, 2278 attr->hw_latency_mode); 2279 MLX5_SET(virtio_q, virtctx, queue_period_us, 2280 attr->hw_max_latency_us); 2281 MLX5_SET(virtio_q, virtctx, queue_max_count, 2282 attr->hw_max_pending_comp); 2283 } 2284 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) { 2285 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2286 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2287 MLX5_SET64(virtio_q, virtctx, available_addr, 2288 attr->available_addr); 2289 } 2290 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX) 2291 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2292 attr->hw_available_index); 2293 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX) 2294 MLX5_SET16(virtio_net_q, virtq, hw_used_index, 2295 attr->hw_used_index); 2296 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE) 2297 MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type); 2298 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0) 2299 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2300 attr->virtio_version_1_0); 2301 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY) 2302 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2303 if (attr->mod_fields_bitmap & 2304 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) { 2305 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2306 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2307 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2308 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2309 } 2310 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) { 2311 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2312 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2313 } 2314 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 2315 out, sizeof(out)); 2316 if (ret) { 2317 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2318 rte_errno = errno; 2319 return -rte_errno; 2320 } 2321 return ret; 2322 } 2323 2324 /** 2325 * Query VIRTQ using DevX API. 2326 * 2327 * @param[in] virtq_obj 2328 * Pointer to virtq object structure. 2329 * @param [in/out] attr 2330 * Pointer to virtq attributes structure. 2331 * 2332 * @return 2333 * 0 on success, a negative errno value otherwise and rte_errno is set. 2334 */ 2335 int 2336 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 2337 struct mlx5_devx_virtq_attr *attr) 2338 { 2339 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2340 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 2341 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 2342 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 2343 int ret; 2344 2345 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2346 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2347 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2348 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2349 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2350 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2351 out, sizeof(out)); 2352 if (ret) { 2353 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2354 rte_errno = errno; 2355 return -errno; 2356 } 2357 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2358 hw_available_index); 2359 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2360 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2361 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2362 virtio_q_context.error_type); 2363 return ret; 2364 } 2365 2366 /** 2367 * Create QP using DevX API. 2368 * 2369 * @param[in] ctx 2370 * Context returned from mlx5 open_device() glue function. 2371 * @param [in] attr 2372 * Pointer to QP attributes structure. 2373 * 2374 * @return 2375 * The DevX object created, NULL otherwise and rte_errno is set. 2376 */ 2377 struct mlx5_devx_obj * 2378 mlx5_devx_cmd_create_qp(void *ctx, 2379 struct mlx5_devx_qp_attr *attr) 2380 { 2381 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2382 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2383 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2384 sizeof(*qp_obj), 2385 0, SOCKET_ID_ANY); 2386 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2387 2388 if (!qp_obj) { 2389 DRV_LOG(ERR, "Failed to allocate QP data."); 2390 rte_errno = ENOMEM; 2391 return NULL; 2392 } 2393 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2394 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2395 MLX5_SET(qpc, qpc, pd, attr->pd); 2396 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2397 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2398 if (attr->uar_index) { 2399 if (attr->mmo) { 2400 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2401 in, qpc_extension_and_pas_list); 2402 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2403 qpc_ext_and_pas_list, qpc_data_extension); 2404 2405 MLX5_SET(create_qp_in, in, qpc_ext, 1); 2406 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2407 } 2408 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2409 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2410 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2411 MLX5_SET(qpc, qpc, log_page_size, 2412 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2413 if (attr->num_of_send_wqbbs) { 2414 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs)); 2415 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2416 MLX5_SET(qpc, qpc, log_sq_size, 2417 rte_log2_u32(attr->num_of_send_wqbbs)); 2418 } else { 2419 MLX5_SET(qpc, qpc, no_sq, 1); 2420 } 2421 if (attr->num_of_receive_wqes) { 2422 MLX5_ASSERT(RTE_IS_POWER_OF_2( 2423 attr->num_of_receive_wqes)); 2424 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2425 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2426 MLX5_LOG_RQ_STRIDE_SHIFT); 2427 MLX5_SET(qpc, qpc, log_rq_size, 2428 rte_log2_u32(attr->num_of_receive_wqes)); 2429 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2430 } else { 2431 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2432 } 2433 if (attr->dbr_umem_valid) { 2434 MLX5_SET(qpc, qpc, dbr_umem_valid, 2435 attr->dbr_umem_valid); 2436 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2437 } 2438 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2439 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2440 attr->wq_umem_offset); 2441 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2442 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2443 } else { 2444 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2445 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2446 MLX5_SET(qpc, qpc, no_sq, 1); 2447 } 2448 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2449 sizeof(out)); 2450 if (!qp_obj->obj) { 2451 DEVX_DRV_LOG(ERR, out, "create QP", NULL, 0); 2452 mlx5_free(qp_obj); 2453 return NULL; 2454 } 2455 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2456 return qp_obj; 2457 } 2458 2459 /** 2460 * Modify QP using DevX API. 2461 * Currently supports only force loop-back QP. 2462 * 2463 * @param[in] qp 2464 * Pointer to QP object structure. 2465 * @param [in] qp_st_mod_op 2466 * The QP state modification operation. 2467 * @param [in] remote_qp_id 2468 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2469 * 2470 * @return 2471 * 0 on success, a negative errno value otherwise and rte_errno is set. 2472 */ 2473 int 2474 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2475 uint32_t remote_qp_id) 2476 { 2477 union { 2478 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2479 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2480 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2481 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)]; 2482 } in; 2483 union { 2484 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2485 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2486 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2487 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)]; 2488 } out; 2489 void *qpc; 2490 int ret; 2491 unsigned int inlen; 2492 unsigned int outlen; 2493 2494 memset(&in, 0, sizeof(in)); 2495 memset(&out, 0, sizeof(out)); 2496 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2497 switch (qp_st_mod_op) { 2498 case MLX5_CMD_OP_RST2INIT_QP: 2499 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2500 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2501 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2502 MLX5_SET(qpc, qpc, rre, 1); 2503 MLX5_SET(qpc, qpc, rwe, 1); 2504 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2505 inlen = sizeof(in.rst2init); 2506 outlen = sizeof(out.rst2init); 2507 break; 2508 case MLX5_CMD_OP_INIT2RTR_QP: 2509 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2510 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2511 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2512 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2513 MLX5_SET(qpc, qpc, mtu, 1); 2514 MLX5_SET(qpc, qpc, log_msg_max, 30); 2515 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2516 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2517 inlen = sizeof(in.init2rtr); 2518 outlen = sizeof(out.init2rtr); 2519 break; 2520 case MLX5_CMD_OP_RTR2RTS_QP: 2521 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2522 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2523 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16); 2524 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2525 MLX5_SET(qpc, qpc, retry_count, 7); 2526 MLX5_SET(qpc, qpc, rnr_retry, 7); 2527 inlen = sizeof(in.rtr2rts); 2528 outlen = sizeof(out.rtr2rts); 2529 break; 2530 case MLX5_CMD_OP_QP_2RST: 2531 MLX5_SET(2rst_qp_in, &in, qpn, qp->id); 2532 inlen = sizeof(in.qp2rst); 2533 outlen = sizeof(out.qp2rst); 2534 break; 2535 default: 2536 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2537 qp_st_mod_op); 2538 rte_errno = EINVAL; 2539 return -rte_errno; 2540 } 2541 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2542 if (ret) { 2543 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2544 rte_errno = errno; 2545 return -rte_errno; 2546 } 2547 return ret; 2548 } 2549 2550 struct mlx5_devx_obj * 2551 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2552 { 2553 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2554 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2555 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2556 sizeof(*couners_obj), 0, 2557 SOCKET_ID_ANY); 2558 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2559 2560 if (!couners_obj) { 2561 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2562 rte_errno = ENOMEM; 2563 return NULL; 2564 } 2565 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2566 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2567 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2568 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2569 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2570 sizeof(out)); 2571 if (!couners_obj->obj) { 2572 DEVX_DRV_LOG(ERR, out, "create virtio queue counters Obj", NULL, 2573 0); 2574 mlx5_free(couners_obj); 2575 return NULL; 2576 } 2577 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2578 return couners_obj; 2579 } 2580 2581 int 2582 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2583 struct mlx5_devx_virtio_q_couners_attr *attr) 2584 { 2585 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2586 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2587 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2588 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2589 virtio_q_counters); 2590 int ret; 2591 2592 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2593 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2594 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2595 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2596 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2597 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2598 sizeof(out)); 2599 if (ret) { 2600 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2601 rte_errno = errno; 2602 return -errno; 2603 } 2604 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2605 received_desc); 2606 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2607 completed_desc); 2608 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2609 error_cqes); 2610 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2611 bad_desc_errors); 2612 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2613 exceed_max_chain); 2614 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2615 invalid_buffer); 2616 return ret; 2617 } 2618 2619 /** 2620 * Create general object of type FLOW_HIT_ASO using DevX API. 2621 * 2622 * @param[in] ctx 2623 * Context returned from mlx5 open_device() glue function. 2624 * @param [in] pd 2625 * PD value to associate the FLOW_HIT_ASO object with. 2626 * 2627 * @return 2628 * The DevX object created, NULL otherwise and rte_errno is set. 2629 */ 2630 struct mlx5_devx_obj * 2631 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2632 { 2633 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2634 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2635 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2636 void *ptr = NULL; 2637 2638 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2639 0, SOCKET_ID_ANY); 2640 if (!flow_hit_aso_obj) { 2641 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2642 rte_errno = ENOMEM; 2643 return NULL; 2644 } 2645 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2646 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2647 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2648 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2649 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2650 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2651 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2652 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2653 out, sizeof(out)); 2654 if (!flow_hit_aso_obj->obj) { 2655 DEVX_DRV_LOG(ERR, out, "create FLOW_HIT_ASO", NULL, 0); 2656 mlx5_free(flow_hit_aso_obj); 2657 return NULL; 2658 } 2659 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2660 return flow_hit_aso_obj; 2661 } 2662 2663 /* 2664 * Create PD using DevX API. 2665 * 2666 * @param[in] ctx 2667 * Context returned from mlx5 open_device() glue function. 2668 * 2669 * @return 2670 * The DevX object created, NULL otherwise and rte_errno is set. 2671 */ 2672 struct mlx5_devx_obj * 2673 mlx5_devx_cmd_alloc_pd(void *ctx) 2674 { 2675 struct mlx5_devx_obj *ppd = 2676 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2677 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2678 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2679 2680 if (!ppd) { 2681 DRV_LOG(ERR, "Failed to allocate PD data."); 2682 rte_errno = ENOMEM; 2683 return NULL; 2684 } 2685 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2686 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2687 out, sizeof(out)); 2688 if (!ppd->obj) { 2689 mlx5_free(ppd); 2690 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2691 rte_errno = errno; 2692 return NULL; 2693 } 2694 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2695 return ppd; 2696 } 2697 2698 /** 2699 * Create general object of type FLOW_METER_ASO using DevX API. 2700 * 2701 * @param[in] ctx 2702 * Context returned from mlx5 open_device() glue function. 2703 * @param [in] pd 2704 * PD value to associate the FLOW_METER_ASO object with. 2705 * @param [in] log_obj_size 2706 * log_obj_size define to allocate number of 2 * meters 2707 * in one FLOW_METER_ASO object. 2708 * 2709 * @return 2710 * The DevX object created, NULL otherwise and rte_errno is set. 2711 */ 2712 struct mlx5_devx_obj * 2713 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2714 uint32_t log_obj_size) 2715 { 2716 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2717 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2718 struct mlx5_devx_obj *flow_meter_aso_obj; 2719 void *ptr; 2720 2721 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2722 sizeof(*flow_meter_aso_obj), 2723 0, SOCKET_ID_ANY); 2724 if (!flow_meter_aso_obj) { 2725 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2726 rte_errno = ENOMEM; 2727 return NULL; 2728 } 2729 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2730 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2731 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2732 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2733 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2734 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2735 log_obj_size); 2736 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2737 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2738 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2739 ctx, in, sizeof(in), 2740 out, sizeof(out)); 2741 if (!flow_meter_aso_obj->obj) { 2742 DEVX_DRV_LOG(ERR, out, "create FLOW_METTER_ASO", NULL, 0); 2743 mlx5_free(flow_meter_aso_obj); 2744 return NULL; 2745 } 2746 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2747 out, obj_id); 2748 return flow_meter_aso_obj; 2749 } 2750 2751 /* 2752 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2753 * 2754 * @param[in] ctx 2755 * Context returned from mlx5 open_device() glue function. 2756 * @param [in] pd 2757 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2758 * @param [in] log_obj_size 2759 * log_obj_size to allocate its power of 2 * objects 2760 * in one CONN_TRACK_OFFLOAD bulk allocation. 2761 * 2762 * @return 2763 * The DevX object created, NULL otherwise and rte_errno is set. 2764 */ 2765 struct mlx5_devx_obj * 2766 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2767 uint32_t log_obj_size) 2768 { 2769 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2770 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2771 struct mlx5_devx_obj *ct_aso_obj; 2772 void *ptr; 2773 2774 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2775 0, SOCKET_ID_ANY); 2776 if (!ct_aso_obj) { 2777 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2778 rte_errno = ENOMEM; 2779 return NULL; 2780 } 2781 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2782 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2783 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2784 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2785 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2786 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2787 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2788 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2789 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2790 out, sizeof(out)); 2791 if (!ct_aso_obj->obj) { 2792 DEVX_DRV_LOG(ERR, out, "create CONN_TRACK_OFFLOAD", NULL, 0); 2793 mlx5_free(ct_aso_obj); 2794 return NULL; 2795 } 2796 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2797 return ct_aso_obj; 2798 } 2799 2800 /** 2801 * Create general object of type GENEVE TLV option using DevX API. 2802 * 2803 * @param[in] ctx 2804 * Context returned from mlx5 open_device() glue function. 2805 * @param [in] class 2806 * TLV option variable value of class 2807 * @param [in] type 2808 * TLV option variable value of type 2809 * @param [in] len 2810 * TLV option variable value of len 2811 * 2812 * @return 2813 * The DevX object created, NULL otherwise and rte_errno is set. 2814 */ 2815 struct mlx5_devx_obj * 2816 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2817 uint16_t class, uint8_t type, uint8_t len) 2818 { 2819 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2820 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2821 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2822 sizeof(*geneve_tlv_opt_obj), 2823 0, SOCKET_ID_ANY); 2824 2825 if (!geneve_tlv_opt_obj) { 2826 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2827 rte_errno = ENOMEM; 2828 return NULL; 2829 } 2830 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2831 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2832 geneve_tlv_opt); 2833 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2834 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2835 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2836 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2837 MLX5_SET(geneve_tlv_option, opt, option_class, 2838 rte_be_to_cpu_16(class)); 2839 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2840 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2841 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2842 sizeof(in), out, sizeof(out)); 2843 if (!geneve_tlv_opt_obj->obj) { 2844 DEVX_DRV_LOG(ERR, out, "create GENEVE TLV", NULL, 0); 2845 mlx5_free(geneve_tlv_opt_obj); 2846 return NULL; 2847 } 2848 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2849 return geneve_tlv_opt_obj; 2850 } 2851 2852 int 2853 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2854 { 2855 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2856 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2857 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2858 int rc; 2859 void *rq_ctx; 2860 2861 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2862 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2863 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2864 if (rc) { 2865 rte_errno = errno; 2866 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2867 "rc = %d, errno = %d.", rc, errno); 2868 return -rc; 2869 }; 2870 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2871 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2872 return 0; 2873 #else 2874 (void)wq; 2875 (void)counter_set_id; 2876 return -ENOTSUP; 2877 #endif 2878 } 2879 2880 /* 2881 * Allocate queue counters via devx interface. 2882 * 2883 * @param[in] ctx 2884 * Context returned from mlx5 open_device() glue function. 2885 * 2886 * @return 2887 * Pointer to counter object on success, a NULL value otherwise and 2888 * rte_errno is set. 2889 */ 2890 struct mlx5_devx_obj * 2891 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2892 { 2893 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2894 SOCKET_ID_ANY); 2895 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2896 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2897 2898 if (!dcs) { 2899 rte_errno = ENOMEM; 2900 return NULL; 2901 } 2902 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2903 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2904 sizeof(out)); 2905 if (!dcs->obj) { 2906 DEVX_DRV_LOG(DEBUG, out, "create q counter set", NULL, 0); 2907 mlx5_free(dcs); 2908 return NULL; 2909 } 2910 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2911 return dcs; 2912 } 2913 2914 /** 2915 * Query queue counters values. 2916 * 2917 * @param[in] dcs 2918 * devx object of the queue counter set. 2919 * @param[in] clear 2920 * Whether hardware should clear the counters after the query or not. 2921 * @param[out] out_of_buffers 2922 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2923 * 2924 * @return 2925 * 0 on success, a negative value otherwise. 2926 */ 2927 int 2928 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2929 uint32_t *out_of_buffers) 2930 { 2931 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2932 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2933 int rc; 2934 2935 MLX5_SET(query_q_counter_in, in, opcode, 2936 MLX5_CMD_OP_QUERY_Q_COUNTER); 2937 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2938 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2939 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2940 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2941 sizeof(out)); 2942 if (rc) { 2943 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2944 rte_errno = rc; 2945 return -rc; 2946 } 2947 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2948 return 0; 2949 } 2950 2951 /** 2952 * Create general object of type DEK using DevX API. 2953 * 2954 * @param[in] ctx 2955 * Context returned from mlx5 open_device() glue function. 2956 * @param [in] attr 2957 * Pointer to DEK attributes structure. 2958 * 2959 * @return 2960 * The DevX object created, NULL otherwise and rte_errno is set. 2961 */ 2962 struct mlx5_devx_obj * 2963 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2964 { 2965 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2966 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2967 struct mlx5_devx_obj *dek_obj = NULL; 2968 void *ptr = NULL, *key_addr = NULL; 2969 2970 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2971 0, SOCKET_ID_ANY); 2972 if (dek_obj == NULL) { 2973 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2974 rte_errno = ENOMEM; 2975 return NULL; 2976 } 2977 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2978 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2979 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2980 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2981 MLX5_GENERAL_OBJ_TYPE_DEK); 2982 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2983 MLX5_SET(dek, ptr, key_size, attr->key_size); 2984 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2985 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2986 MLX5_SET(dek, ptr, pd, attr->pd); 2987 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2988 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2989 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2990 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2991 out, sizeof(out)); 2992 if (dek_obj->obj == NULL) { 2993 DEVX_DRV_LOG(ERR, out, "create DEK", NULL, 0); 2994 mlx5_free(dek_obj); 2995 return NULL; 2996 } 2997 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2998 return dek_obj; 2999 } 3000 3001 /** 3002 * Create general object of type IMPORT_KEK using DevX API. 3003 * 3004 * @param[in] ctx 3005 * Context returned from mlx5 open_device() glue function. 3006 * @param [in] attr 3007 * Pointer to IMPORT_KEK attributes structure. 3008 * 3009 * @return 3010 * The DevX object created, NULL otherwise and rte_errno is set. 3011 */ 3012 struct mlx5_devx_obj * 3013 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 3014 struct mlx5_devx_import_kek_attr *attr) 3015 { 3016 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 3017 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3018 struct mlx5_devx_obj *import_kek_obj = NULL; 3019 void *ptr = NULL, *key_addr = NULL; 3020 3021 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 3022 0, SOCKET_ID_ANY); 3023 if (import_kek_obj == NULL) { 3024 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 3025 rte_errno = ENOMEM; 3026 return NULL; 3027 } 3028 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 3029 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3030 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3031 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3032 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 3033 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 3034 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 3035 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 3036 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 3037 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3038 out, sizeof(out)); 3039 if (import_kek_obj->obj == NULL) { 3040 DEVX_DRV_LOG(ERR, out, "create IMPORT_KEK", NULL, 0); 3041 mlx5_free(import_kek_obj); 3042 return NULL; 3043 } 3044 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3045 return import_kek_obj; 3046 } 3047 3048 /** 3049 * Create general object of type CREDENTIAL using DevX API. 3050 * 3051 * @param[in] ctx 3052 * Context returned from mlx5 open_device() glue function. 3053 * @param [in] attr 3054 * Pointer to CREDENTIAL attributes structure. 3055 * 3056 * @return 3057 * The DevX object created, NULL otherwise and rte_errno is set. 3058 */ 3059 struct mlx5_devx_obj * 3060 mlx5_devx_cmd_create_credential_obj(void *ctx, 3061 struct mlx5_devx_credential_attr *attr) 3062 { 3063 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 3064 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3065 struct mlx5_devx_obj *credential_obj = NULL; 3066 void *ptr = NULL, *credential_addr = NULL; 3067 3068 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 3069 0, SOCKET_ID_ANY); 3070 if (credential_obj == NULL) { 3071 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 3072 rte_errno = ENOMEM; 3073 return NULL; 3074 } 3075 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 3076 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3077 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3078 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3079 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 3080 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 3081 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 3082 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 3083 memcpy(credential_addr, (void *)(attr->credential), 3084 MLX5_CRYPTO_CREDENTIAL_SIZE); 3085 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3086 out, sizeof(out)); 3087 if (credential_obj->obj == NULL) { 3088 DEVX_DRV_LOG(ERR, out, "create CREDENTIAL", NULL, 0); 3089 mlx5_free(credential_obj); 3090 return NULL; 3091 } 3092 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3093 return credential_obj; 3094 } 3095 3096 /** 3097 * Create general object of type CRYPTO_LOGIN using DevX API. 3098 * 3099 * @param[in] ctx 3100 * Context returned from mlx5 open_device() glue function. 3101 * @param [in] attr 3102 * Pointer to CRYPTO_LOGIN attributes structure. 3103 * 3104 * @return 3105 * The DevX object created, NULL otherwise and rte_errno is set. 3106 */ 3107 struct mlx5_devx_obj * 3108 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 3109 struct mlx5_devx_crypto_login_attr *attr) 3110 { 3111 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 3112 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3113 struct mlx5_devx_obj *crypto_login_obj = NULL; 3114 void *ptr = NULL, *credential_addr = NULL; 3115 3116 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 3117 0, SOCKET_ID_ANY); 3118 if (crypto_login_obj == NULL) { 3119 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 3120 rte_errno = ENOMEM; 3121 return NULL; 3122 } 3123 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 3124 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3125 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3126 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3127 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 3128 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 3129 MLX5_SET(crypto_login, ptr, credential_pointer, 3130 attr->credential_pointer); 3131 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 3132 attr->session_import_kek_ptr); 3133 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 3134 memcpy(credential_addr, (void *)(attr->credential), 3135 MLX5_CRYPTO_CREDENTIAL_SIZE); 3136 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3137 out, sizeof(out)); 3138 if (crypto_login_obj->obj == NULL) { 3139 DEVX_DRV_LOG(ERR, out, "create CRYPTO_LOGIN", NULL, 0); 3140 mlx5_free(crypto_login_obj); 3141 return NULL; 3142 } 3143 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3144 return crypto_login_obj; 3145 } 3146 3147 /** 3148 * Query LAG context. 3149 * 3150 * @param[in] ctx 3151 * Pointer to ibv_context, returned from mlx5dv_open_device. 3152 * @param[out] lag_ctx 3153 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 3154 * 3155 * @return 3156 * 0 on success, a negative value otherwise. 3157 */ 3158 int 3159 mlx5_devx_cmd_query_lag(void *ctx, 3160 struct mlx5_devx_lag_context *lag_ctx) 3161 { 3162 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 3163 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 3164 void *lctx; 3165 int rc; 3166 3167 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 3168 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 3169 if (rc) 3170 goto error; 3171 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 3172 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 3173 fdb_selection_mode); 3174 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 3175 port_select_mode); 3176 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 3177 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 3178 tx_remap_affinity_2); 3179 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 3180 tx_remap_affinity_1); 3181 return 0; 3182 error: 3183 rc = (rc > 0) ? -rc : rc; 3184 return rc; 3185 } 3186