1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /* FW writes status value to the OUT buffer at offset 00H */ 17 #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status) 18 /* FW writes syndrome value to the OUT buffer at offset 04H */ 19 #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome) 20 21 #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1)) 22 23 #define DEVX_DRV_LOG(level, out, reason, param, value) \ 24 do { \ 25 /* \ 26 * Some (old) GCC compilers like 7.5.0 and aarch64 GCC 7.1-2017.08 \ 27 * do not expand correctly when the macro invoked when the `param` \ 28 * is `NULL`. \ 29 * Use `local_param` to avoid direct `NULL` expansion. \ 30 */ \ 31 const char *local_param = (const char *)param; \ 32 \ 33 rte_errno = errno; \ 34 if (!local_param) { \ 35 DRV_LOG(level, \ 36 "DevX %s failed errno=%d status=%#x syndrome=%#x", \ 37 (reason), errno, MLX5_FW_STATUS((out)), \ 38 MLX5_FW_SYNDROME((out))); \ 39 } else { \ 40 DRV_LOG(level, \ 41 "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x",\ 42 (reason), local_param, (value), errno, \ 43 MLX5_FW_STATUS((out)), MLX5_FW_SYNDROME((out))); \ 44 } \ 45 } while (0) 46 47 static void * 48 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, 49 int *err, uint32_t flags) 50 { 51 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); 52 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); 53 int rc; 54 55 memset(in, 0, size_in); 56 memset(out, 0, size_out); 57 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 58 MLX5_SET(query_hca_cap_in, in, op_mod, flags); 59 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); 60 if (rc || MLX5_FW_STATUS(out)) { 61 DEVX_DRV_LOG(ERR, out, "HCA capabilities", "func", flags >> 1); 62 if (err) 63 *err = MLX5_DEVX_ERR_RC(rc); 64 return NULL; 65 } 66 if (err) 67 *err = 0; 68 return MLX5_ADDR_OF(query_hca_cap_out, out, capability); 69 } 70 71 /** 72 * Perform read access to the registers. Reads data from register 73 * and writes ones to the specified buffer. 74 * 75 * @param[in] ctx 76 * Context returned from mlx5 open_device() glue function. 77 * @param[in] reg_id 78 * Register identifier according to the PRM. 79 * @param[in] arg 80 * Register access auxiliary parameter according to the PRM. 81 * @param[out] data 82 * Pointer to the buffer to store read data. 83 * @param[in] dw_cnt 84 * Buffer size in double words. 85 * 86 * @return 87 * 0 on success, a negative value otherwise. 88 */ 89 int 90 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 91 uint32_t *data, uint32_t dw_cnt) 92 { 93 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 94 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 95 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 96 int rc; 97 98 MLX5_ASSERT(data && dw_cnt); 99 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 100 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 101 DRV_LOG(ERR, "Not enough buffer for register read data"); 102 return -1; 103 } 104 MLX5_SET(access_register_in, in, opcode, 105 MLX5_CMD_OP_ACCESS_REGISTER_USER); 106 MLX5_SET(access_register_in, in, op_mod, 107 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 108 MLX5_SET(access_register_in, in, register_id, reg_id); 109 MLX5_SET(access_register_in, in, argument, arg); 110 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 111 MLX5_ST_SZ_BYTES(access_register_out) + 112 sizeof(uint32_t) * dw_cnt); 113 if (rc || MLX5_FW_STATUS(out)) { 114 DEVX_DRV_LOG(DEBUG, out, "read access", "NIC register", reg_id); 115 return MLX5_DEVX_ERR_RC(rc); 116 } 117 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 118 dw_cnt * sizeof(uint32_t)); 119 return 0; 120 } 121 122 /** 123 * Perform write access to the registers. 124 * 125 * @param[in] ctx 126 * Context returned from mlx5 open_device() glue function. 127 * @param[in] reg_id 128 * Register identifier according to the PRM. 129 * @param[in] arg 130 * Register access auxiliary parameter according to the PRM. 131 * @param[out] data 132 * Pointer to the buffer containing data to write. 133 * @param[in] dw_cnt 134 * Buffer size in double words (32bit units). 135 * 136 * @return 137 * 0 on success, a negative value otherwise. 138 */ 139 int 140 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 141 uint32_t *data, uint32_t dw_cnt) 142 { 143 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 144 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 145 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 146 int rc; 147 void *ptr; 148 149 MLX5_ASSERT(data && dw_cnt); 150 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 151 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 152 DRV_LOG(ERR, "Data to write exceeds max size"); 153 return -1; 154 } 155 MLX5_SET(access_register_in, in, opcode, 156 MLX5_CMD_OP_ACCESS_REGISTER_USER); 157 MLX5_SET(access_register_in, in, op_mod, 158 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 159 MLX5_SET(access_register_in, in, register_id, reg_id); 160 MLX5_SET(access_register_in, in, argument, arg); 161 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 162 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 163 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 164 if (rc || MLX5_FW_STATUS(out)) { 165 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 166 return MLX5_DEVX_ERR_RC(rc); 167 } 168 rc = mlx5_glue->devx_general_cmd(ctx, in, 169 MLX5_ST_SZ_BYTES(access_register_in) + 170 dw_cnt * sizeof(uint32_t), 171 out, sizeof(out)); 172 if (rc || MLX5_FW_STATUS(out)) { 173 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 174 return MLX5_DEVX_ERR_RC(rc); 175 } 176 return 0; 177 } 178 179 struct mlx5_devx_obj * 180 mlx5_devx_cmd_flow_counter_alloc_general(void *ctx, 181 struct mlx5_devx_counter_attr *attr) 182 { 183 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 184 0, SOCKET_ID_ANY); 185 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 186 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 187 188 if (!dcs) { 189 rte_errno = ENOMEM; 190 return NULL; 191 } 192 MLX5_SET(alloc_flow_counter_in, in, opcode, 193 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 194 if (attr->bulk_log_max_alloc) 195 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk_log_size, 196 attr->flow_counter_bulk_log_size); 197 else 198 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, 199 attr->bulk_n_128); 200 if (attr->pd_valid) 201 MLX5_SET(alloc_flow_counter_in, in, pd, attr->pd); 202 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 203 sizeof(in), out, sizeof(out)); 204 if (!dcs->obj) { 205 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 206 rte_errno = errno; 207 mlx5_free(dcs); 208 return NULL; 209 } 210 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 211 return dcs; 212 } 213 214 /** 215 * Allocate flow counters via devx interface. 216 * 217 * @param[in] ctx 218 * Context returned from mlx5 open_device() glue function. 219 * @param dcs 220 * Pointer to counters properties structure to be filled by the routine. 221 * @param bulk_n_128 222 * Bulk counter numbers in 128 counters units. 223 * 224 * @return 225 * Pointer to counter object on success, a negative value otherwise and 226 * rte_errno is set. 227 */ 228 struct mlx5_devx_obj * 229 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 230 { 231 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 232 0, SOCKET_ID_ANY); 233 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 234 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 235 236 if (!dcs) { 237 rte_errno = ENOMEM; 238 return NULL; 239 } 240 MLX5_SET(alloc_flow_counter_in, in, opcode, 241 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 242 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 243 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 244 sizeof(in), out, sizeof(out)); 245 if (!dcs->obj) { 246 DEVX_DRV_LOG(ERR, out, "allocate counters", NULL, 0); 247 mlx5_free(dcs); 248 return NULL; 249 } 250 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 251 return dcs; 252 } 253 254 /** 255 * Query flow counters values. 256 * 257 * @param[in] dcs 258 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 259 * @param[in] clear 260 * Whether hardware should clear the counters after the query or not. 261 * @param[in] n_counters 262 * 0 in case of 1 counter to read, otherwise the counter number to read. 263 * @param pkts 264 * The number of packets that matched the flow. 265 * @param bytes 266 * The number of bytes that matched the flow. 267 * @param mkey 268 * The mkey key for batch query. 269 * @param addr 270 * The address in the mkey range for batch query. 271 * @param cmd_comp 272 * The completion object for asynchronous batch query. 273 * @param async_id 274 * The ID to be returned in the asynchronous batch query response. 275 * 276 * @return 277 * 0 on success, a negative value otherwise. 278 */ 279 int 280 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 281 int clear, uint32_t n_counters, 282 uint64_t *pkts, uint64_t *bytes, 283 uint32_t mkey, void *addr, 284 void *cmd_comp, 285 uint64_t async_id) 286 { 287 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 288 MLX5_ST_SZ_BYTES(traffic_counter); 289 uint32_t out[out_len]; 290 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 291 void *stats; 292 int rc; 293 294 MLX5_SET(query_flow_counter_in, in, opcode, 295 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 296 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 297 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 298 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 299 300 if (n_counters) { 301 MLX5_SET(query_flow_counter_in, in, num_of_counters, 302 n_counters); 303 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 304 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 305 MLX5_SET64(query_flow_counter_in, in, address, 306 (uint64_t)(uintptr_t)addr); 307 } 308 if (!cmd_comp) 309 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 310 out_len); 311 else 312 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 313 out_len, async_id, 314 cmd_comp); 315 if (rc) { 316 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 317 rte_errno = rc; 318 return -rc; 319 } 320 if (!n_counters) { 321 stats = MLX5_ADDR_OF(query_flow_counter_out, 322 out, flow_statistics); 323 *pkts = MLX5_GET64(traffic_counter, stats, packets); 324 *bytes = MLX5_GET64(traffic_counter, stats, octets); 325 } 326 return 0; 327 } 328 329 /** 330 * Create a new mkey. 331 * 332 * @param[in] ctx 333 * Context returned from mlx5 open_device() glue function. 334 * @param[in] attr 335 * Attributes of the requested mkey. 336 * 337 * @return 338 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 339 * is set. 340 */ 341 struct mlx5_devx_obj * 342 mlx5_devx_cmd_mkey_create(void *ctx, 343 struct mlx5_devx_mkey_attr *attr) 344 { 345 struct mlx5_klm *klm_array = attr->klm_array; 346 int klm_num = attr->klm_num; 347 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 348 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 349 uint32_t in[in_size_dw]; 350 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 351 void *mkc; 352 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 353 0, SOCKET_ID_ANY); 354 size_t pgsize; 355 uint32_t translation_size; 356 357 if (!mkey) { 358 rte_errno = ENOMEM; 359 return NULL; 360 } 361 memset(in, 0, in_size_dw * 4); 362 pgsize = rte_mem_page_size(); 363 if (pgsize == (size_t)-1) { 364 mlx5_free(mkey); 365 DRV_LOG(ERR, "Failed to get page size"); 366 rte_errno = ENOMEM; 367 return NULL; 368 } 369 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 370 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 371 if (klm_num > 0) { 372 int i; 373 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 374 klm_pas_mtt); 375 translation_size = RTE_ALIGN(klm_num, 4); 376 for (i = 0; i < klm_num; i++) { 377 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 378 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 379 MLX5_SET64(klm, klm, address, klm_array[i].address); 380 klm += MLX5_ST_SZ_BYTES(klm); 381 } 382 for (; i < (int)translation_size; i++) { 383 MLX5_SET(klm, klm, mkey, 0x0); 384 MLX5_SET64(klm, klm, address, 0x0); 385 klm += MLX5_ST_SZ_BYTES(klm); 386 } 387 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 388 MLX5_MKC_ACCESS_MODE_KLM_FBS : 389 MLX5_MKC_ACCESS_MODE_KLM); 390 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 391 } else { 392 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 393 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 394 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 395 } 396 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 397 translation_size); 398 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 399 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 400 MLX5_SET(mkc, mkc, lw, 0x1); 401 MLX5_SET(mkc, mkc, lr, 0x1); 402 if (attr->set_remote_rw) { 403 MLX5_SET(mkc, mkc, rw, 0x1); 404 MLX5_SET(mkc, mkc, rr, 0x1); 405 } 406 MLX5_SET(mkc, mkc, qpn, 0xffffff); 407 MLX5_SET(mkc, mkc, pd, attr->pd); 408 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 409 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 410 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 411 MLX5_SET(mkc, mkc, relaxed_ordering_write, 412 attr->relaxed_ordering_write); 413 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 414 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 415 MLX5_SET64(mkc, mkc, len, attr->size); 416 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 417 if (attr->crypto_en) { 418 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 419 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 420 } 421 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 422 sizeof(out)); 423 if (!mkey->obj) { 424 DEVX_DRV_LOG(ERR, out, klm_num ? "create indirect mkey" 425 : "create direct key", NULL, 0); 426 mlx5_free(mkey); 427 return NULL; 428 } 429 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 430 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 431 return mkey; 432 } 433 434 /** 435 * Get status of devx command response. 436 * Mainly used for asynchronous commands. 437 * 438 * @param[in] out 439 * The out response buffer. 440 * 441 * @return 442 * 0 on success, non-zero value otherwise. 443 */ 444 int 445 mlx5_devx_get_out_command_status(void *out) 446 { 447 int status; 448 449 if (!out) 450 return -EINVAL; 451 status = MLX5_GET(query_flow_counter_out, out, status); 452 if (status) { 453 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 454 455 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 456 syndrome); 457 } 458 return status; 459 } 460 461 /** 462 * Destroy any object allocated by a Devx API. 463 * 464 * @param[in] obj 465 * Pointer to a general object. 466 * 467 * @return 468 * 0 on success, a negative value otherwise. 469 */ 470 int 471 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 472 { 473 int ret; 474 475 if (!obj) 476 return 0; 477 ret = mlx5_glue->devx_obj_destroy(obj->obj); 478 mlx5_free(obj); 479 return ret; 480 } 481 482 /** 483 * Query NIC vport context. 484 * Fills minimal inline attribute. 485 * 486 * @param[in] ctx 487 * ibv contexts returned from mlx5dv_open_device. 488 * @param[in] vport 489 * vport index 490 * @param[out] attr 491 * Attributes device values. 492 * 493 * @return 494 * 0 on success, a negative value otherwise. 495 */ 496 static int 497 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 498 unsigned int vport, 499 struct mlx5_hca_attr *attr) 500 { 501 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 502 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 503 void *vctx; 504 int rc; 505 506 /* Query NIC vport context to determine inline mode. */ 507 MLX5_SET(query_nic_vport_context_in, in, opcode, 508 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 509 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 510 if (vport) 511 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 512 rc = mlx5_glue->devx_general_cmd(ctx, 513 in, sizeof(in), 514 out, sizeof(out)); 515 if (rc || MLX5_FW_STATUS(out)) { 516 DEVX_DRV_LOG(ERR, out, "query NIC vport context", NULL, 0); 517 return MLX5_DEVX_ERR_RC(rc); 518 } 519 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 520 nic_vport_context); 521 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 522 min_wqe_inline_mode); 523 return 0; 524 } 525 526 /** 527 * Query NIC vDPA attributes. 528 * 529 * @param[in] ctx 530 * Context returned from mlx5 open_device() glue function. 531 * @param[out] vdpa_attr 532 * vDPA Attributes structure to fill. 533 */ 534 static void 535 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 536 struct mlx5_hca_vdpa_attr *vdpa_attr) 537 { 538 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 539 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 540 void *hcattr; 541 542 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, 543 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 544 MLX5_HCA_CAP_OPMOD_GET_CUR); 545 if (!hcattr) { 546 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities"); 547 vdpa_attr->valid = 0; 548 } else { 549 vdpa_attr->valid = 1; 550 vdpa_attr->desc_tunnel_offload_type = 551 MLX5_GET(virtio_emulation_cap, hcattr, 552 desc_tunnel_offload_type); 553 vdpa_attr->eth_frame_offload_type = 554 MLX5_GET(virtio_emulation_cap, hcattr, 555 eth_frame_offload_type); 556 vdpa_attr->virtio_version_1_0 = 557 MLX5_GET(virtio_emulation_cap, hcattr, 558 virtio_version_1_0); 559 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 560 tso_ipv4); 561 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 562 tso_ipv6); 563 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 564 tx_csum); 565 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 566 rx_csum); 567 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 568 event_mode); 569 vdpa_attr->virtio_queue_type = 570 MLX5_GET(virtio_emulation_cap, hcattr, 571 virtio_queue_type); 572 vdpa_attr->log_doorbell_stride = 573 MLX5_GET(virtio_emulation_cap, hcattr, 574 log_doorbell_stride); 575 vdpa_attr->vnet_modify_ext = 576 MLX5_GET(virtio_emulation_cap, hcattr, 577 vnet_modify_ext); 578 vdpa_attr->virtio_net_q_addr_modify = 579 MLX5_GET(virtio_emulation_cap, hcattr, 580 virtio_net_q_addr_modify); 581 vdpa_attr->virtio_q_index_modify = 582 MLX5_GET(virtio_emulation_cap, hcattr, 583 virtio_q_index_modify); 584 vdpa_attr->log_doorbell_bar_size = 585 MLX5_GET(virtio_emulation_cap, hcattr, 586 log_doorbell_bar_size); 587 vdpa_attr->doorbell_bar_offset = 588 MLX5_GET64(virtio_emulation_cap, hcattr, 589 doorbell_bar_offset); 590 vdpa_attr->max_num_virtio_queues = 591 MLX5_GET(virtio_emulation_cap, hcattr, 592 max_num_virtio_queues); 593 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 594 umem_1_buffer_param_a); 595 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 596 umem_1_buffer_param_b); 597 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 598 umem_2_buffer_param_a); 599 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 600 umem_2_buffer_param_b); 601 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 602 umem_3_buffer_param_a); 603 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 604 umem_3_buffer_param_b); 605 } 606 } 607 608 int 609 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 610 struct mlx5_ext_sample_id *ids, 611 uint32_t num, uint8_t *anchor) 612 { 613 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 614 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 615 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 616 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 617 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 618 int ret; 619 uint32_t idx = 0; 620 uint32_t i; 621 622 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 623 rte_errno = EINVAL; 624 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 625 return -rte_errno; 626 } 627 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 628 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 629 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 630 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 631 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 632 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 633 out, sizeof(out)); 634 if (ret) { 635 rte_errno = ret; 636 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 637 (void *)flex_obj); 638 return -rte_errno; 639 } 640 if (anchor) 641 *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id); 642 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx <= num; i++) { 643 void *s_off = (void *)((char *)sample + i * 644 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 645 uint32_t en; 646 647 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 648 flow_match_sample_en); 649 if (!en) 650 continue; 651 ids[idx++].id = MLX5_GET(parse_graph_flow_match_sample, s_off, 652 flow_match_sample_field_id); 653 } 654 if (num != idx) { 655 rte_errno = EINVAL; 656 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 657 return -rte_errno; 658 } 659 return ret; 660 } 661 662 struct mlx5_devx_obj * 663 mlx5_devx_cmd_create_flex_parser(void *ctx, 664 struct mlx5_devx_graph_node_attr *data) 665 { 666 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 667 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 668 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 669 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 670 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 671 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 672 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 673 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 674 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 675 uint32_t i; 676 677 if (!parse_flex_obj) { 678 DRV_LOG(ERR, "Failed to allocate flex parser data."); 679 rte_errno = ENOMEM; 680 return NULL; 681 } 682 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 683 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 684 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 685 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 686 MLX5_SET(parse_graph_flex, flex, header_length_mode, 687 data->header_length_mode); 688 MLX5_SET64(parse_graph_flex, flex, modify_field_select, 689 data->modify_field_select); 690 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 691 data->header_length_base_value); 692 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 693 data->header_length_field_offset); 694 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 695 data->header_length_field_shift); 696 MLX5_SET(parse_graph_flex, flex, next_header_field_offset, 697 data->next_header_field_offset); 698 MLX5_SET(parse_graph_flex, flex, next_header_field_size, 699 data->next_header_field_size); 700 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 701 data->header_length_field_mask); 702 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 703 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 704 void *s_off = (void *)((char *)sample + i * 705 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 706 707 if (!s->flow_match_sample_en) 708 continue; 709 MLX5_SET(parse_graph_flow_match_sample, s_off, 710 flow_match_sample_en, !!s->flow_match_sample_en); 711 MLX5_SET(parse_graph_flow_match_sample, s_off, 712 flow_match_sample_field_offset, 713 s->flow_match_sample_field_offset); 714 MLX5_SET(parse_graph_flow_match_sample, s_off, 715 flow_match_sample_offset_mode, 716 s->flow_match_sample_offset_mode); 717 MLX5_SET(parse_graph_flow_match_sample, s_off, 718 flow_match_sample_field_offset_mask, 719 s->flow_match_sample_field_offset_mask); 720 MLX5_SET(parse_graph_flow_match_sample, s_off, 721 flow_match_sample_field_offset_shift, 722 s->flow_match_sample_field_offset_shift); 723 MLX5_SET(parse_graph_flow_match_sample, s_off, 724 flow_match_sample_field_base_offset, 725 s->flow_match_sample_field_base_offset); 726 MLX5_SET(parse_graph_flow_match_sample, s_off, 727 flow_match_sample_tunnel_mode, 728 s->flow_match_sample_tunnel_mode); 729 } 730 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 731 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 732 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 733 void *in_off = (void *)((char *)in_arc + i * 734 MLX5_ST_SZ_BYTES(parse_graph_arc)); 735 void *out_off = (void *)((char *)out_arc + i * 736 MLX5_ST_SZ_BYTES(parse_graph_arc)); 737 738 if (ia->arc_parse_graph_node != 0) { 739 MLX5_SET(parse_graph_arc, in_off, 740 compare_condition_value, 741 ia->compare_condition_value); 742 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 743 ia->start_inner_tunnel); 744 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 745 ia->arc_parse_graph_node); 746 MLX5_SET(parse_graph_arc, in_off, 747 parse_graph_node_handle, 748 ia->parse_graph_node_handle); 749 } 750 if (oa->arc_parse_graph_node != 0) { 751 MLX5_SET(parse_graph_arc, out_off, 752 compare_condition_value, 753 oa->compare_condition_value); 754 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 755 oa->start_inner_tunnel); 756 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 757 oa->arc_parse_graph_node); 758 MLX5_SET(parse_graph_arc, out_off, 759 parse_graph_node_handle, 760 oa->parse_graph_node_handle); 761 } 762 } 763 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 764 out, sizeof(out)); 765 if (!parse_flex_obj->obj) { 766 DEVX_DRV_LOG(ERR, out, "create FLEX PARSE GRAPH", NULL, 0); 767 mlx5_free(parse_flex_obj); 768 return NULL; 769 } 770 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 771 return parse_flex_obj; 772 } 773 774 static int 775 mlx5_devx_cmd_query_hca_parse_graph_node_cap 776 (void *ctx, struct mlx5_hca_flex_attr *attr) 777 { 778 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 779 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 780 void *hcattr; 781 int rc; 782 783 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 784 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | 785 MLX5_HCA_CAP_OPMOD_GET_CUR); 786 if (!hcattr) 787 return rc; 788 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); 789 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); 790 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, 791 header_length_mode); 792 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, 793 sample_offset_mode); 794 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, 795 max_num_arc_in); 796 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, 797 max_num_arc_out); 798 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, 799 max_num_sample); 800 attr->anchor_en = MLX5_GET(parse_graph_node_cap, hcattr, anchor_en); 801 attr->ext_sample_id = MLX5_GET(parse_graph_node_cap, hcattr, ext_sample_id); 802 attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr, 803 sample_tunnel_inner2); 804 attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr, 805 zero_size_supported); 806 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, 807 sample_id_in_out); 808 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, 809 max_base_header_length); 810 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, 811 max_sample_base_offset); 812 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, 813 max_next_header_offset); 814 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, 815 header_length_mask_width); 816 /* Get the max supported samples from HCA CAP 2 */ 817 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 818 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 819 MLX5_HCA_CAP_OPMOD_GET_CUR); 820 if (!hcattr) 821 return rc; 822 attr->max_num_prog_sample = 823 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); 824 return 0; 825 } 826 827 static int 828 mlx5_devx_query_pkt_integrity_match(void *hcattr) 829 { 830 return MLX5_GET(flow_table_nic_cap, hcattr, 831 ft_field_support_2_nic_receive.inner_l3_ok) && 832 MLX5_GET(flow_table_nic_cap, hcattr, 833 ft_field_support_2_nic_receive.inner_l4_ok) && 834 MLX5_GET(flow_table_nic_cap, hcattr, 835 ft_field_support_2_nic_receive.outer_l3_ok) && 836 MLX5_GET(flow_table_nic_cap, hcattr, 837 ft_field_support_2_nic_receive.outer_l4_ok) && 838 MLX5_GET(flow_table_nic_cap, hcattr, 839 ft_field_support_2_nic_receive 840 .inner_ipv4_checksum_ok) && 841 MLX5_GET(flow_table_nic_cap, hcattr, 842 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 843 MLX5_GET(flow_table_nic_cap, hcattr, 844 ft_field_support_2_nic_receive 845 .outer_ipv4_checksum_ok) && 846 MLX5_GET(flow_table_nic_cap, hcattr, 847 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 848 } 849 850 /** 851 * Query HCA attributes. 852 * Using those attributes we can check on run time if the device 853 * is having the required capabilities. 854 * 855 * @param[in] ctx 856 * Context returned from mlx5 open_device() glue function. 857 * @param[out] attr 858 * Attributes device values. 859 * 860 * @return 861 * 0 on success, a negative value otherwise. 862 */ 863 int 864 mlx5_devx_cmd_query_hca_attr(void *ctx, 865 struct mlx5_hca_attr *attr) 866 { 867 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 868 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 869 bool hca_cap_2_sup; 870 uint64_t general_obj_types_supported = 0; 871 void *hcattr; 872 int rc, i; 873 874 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 875 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 876 MLX5_HCA_CAP_OPMOD_GET_CUR); 877 if (!hcattr) 878 return rc; 879 hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2); 880 attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq); 881 attr->flow_counter_bulk_alloc_bitmap = 882 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 883 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 884 flow_counters_dump); 885 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp); 886 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp); 887 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 888 log_max_rqt_size); 889 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 890 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 891 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 892 log_max_hairpin_queues); 893 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 894 log_max_hairpin_wq_data_sz); 895 attr->log_max_hairpin_num_packets = MLX5_GET 896 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 897 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 898 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 899 relaxed_ordering_write); 900 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 901 relaxed_ordering_read); 902 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 903 access_register_user); 904 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 905 eth_net_offloads); 906 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 907 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 908 flex_parser_protocols); 909 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 910 max_geneve_tlv_options); 911 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 912 max_geneve_tlv_option_data_len); 913 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 914 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 915 general_obj_types) & 916 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 917 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 918 general_obj_types) & 919 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 920 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 921 general_obj_types) & 922 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 923 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 924 general_obj_types) & 925 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 926 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 927 wqe_index_ignore_cap); 928 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 929 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 930 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 931 log_max_static_sq_wq); 932 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 933 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 934 device_frequency_khz); 935 attr->scatter_fcs_w_decap_disable = 936 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 937 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 938 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 939 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 940 attr->steering_format_version = 941 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 942 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 943 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 944 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 945 regexp_num_of_engines); 946 /* Read the general_obj_types bitmap and extract the relevant bits. */ 947 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 948 general_obj_types); 949 attr->vdpa.valid = !!(general_obj_types_supported & 950 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 951 attr->vdpa.queue_counters_valid = 952 !!(general_obj_types_supported & 953 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 954 attr->parse_graph_flex_node = 955 !!(general_obj_types_supported & 956 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 957 attr->flow_hit_aso = !!(general_obj_types_supported & 958 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 959 attr->geneve_tlv_opt = !!(general_obj_types_supported & 960 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 961 attr->dek = !!(general_obj_types_supported & 962 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 963 attr->import_kek = !!(general_obj_types_supported & 964 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 965 attr->credential = !!(general_obj_types_supported & 966 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 967 attr->crypto_login = !!(general_obj_types_supported & 968 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 969 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 970 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 971 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 972 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 973 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 974 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 975 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 976 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 977 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 978 attr->reg_c_preserve = 979 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 980 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 981 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 982 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 983 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 984 compress_mmo_sq); 985 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 986 decompress_mmo_sq); 987 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 988 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 989 compress_mmo_qp); 990 attr->decomp_deflate_v1_en = MLX5_GET(cmd_hca_cap, hcattr, 991 decompress_deflate_v1); 992 attr->decomp_deflate_v2_en = MLX5_GET(cmd_hca_cap, hcattr, 993 decompress_deflate_v2); 994 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 995 compress_min_block_size); 996 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 997 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 998 log_compress_mmo_size); 999 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 1000 log_decompress_mmo_size); 1001 attr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr, 1002 decompress_lz4_data_only_v2); 1003 attr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, 1004 decompress_lz4_no_checksum_v2); 1005 attr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, 1006 decompress_lz4_checksum_v2); 1007 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 1008 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 1009 mini_cqe_resp_flow_tag); 1010 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 1011 mini_cqe_resp_l3_l4_tag); 1012 attr->enhanced_cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, 1013 enhanced_cqe_compression); 1014 attr->umr_indirect_mkey_disabled = 1015 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 1016 attr->umr_modify_entity_size_disabled = 1017 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 1018 attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time); 1019 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 1020 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 1021 general_obj_types) & 1022 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 1023 attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); 1024 attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr, 1025 max_flow_counter_15_0); 1026 attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr, 1027 max_flow_counter_31_16); 1028 attr->alloc_flow_counter_pd = MLX5_GET(cmd_hca_cap, hcattr, 1029 alloc_flow_counter_pd); 1030 attr->flow_counter_access_aso = MLX5_GET(cmd_hca_cap, hcattr, 1031 flow_counter_access_aso); 1032 attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr, 1033 flow_access_aso_opc_mod); 1034 if (attr->crypto) { 1035 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) || 1036 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_multi_block_be_tweak) || 1037 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_single_block_le_tweak); 1038 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1039 MLX5_GET_HCA_CAP_OP_MOD_CRYPTO | 1040 MLX5_HCA_CAP_OPMOD_GET_CUR); 1041 if (!hcattr) 1042 return -1; 1043 attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps, 1044 hcattr, wrapped_import_method) 1045 & 1 << 2); 1046 } 1047 if (hca_cap_2_sup) { 1048 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1049 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 1050 MLX5_HCA_CAP_OPMOD_GET_CUR); 1051 if (!hcattr) { 1052 DRV_LOG(DEBUG, 1053 "Failed to query DevX HCA capabilities 2."); 1054 return rc; 1055 } 1056 attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, 1057 log_min_stride_wqe_sz); 1058 attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr, 1059 hairpin_sq_wqe_bb_size); 1060 attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr, 1061 hairpin_sq_wq_in_host_mem); 1062 attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr, 1063 hairpin_data_buffer_locked); 1064 attr->flow_counter_bulk_log_max_alloc = MLX5_GET(cmd_hca_cap_2, 1065 hcattr, flow_counter_bulk_log_max_alloc); 1066 attr->flow_counter_bulk_log_granularity = 1067 MLX5_GET(cmd_hca_cap_2, hcattr, 1068 flow_counter_bulk_log_granularity); 1069 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1070 cross_vhca_object_to_object_supported); 1071 attr->cross_vhca = 1072 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR) && 1073 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT) && 1074 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT) && 1075 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC); 1076 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1077 allowed_object_for_other_vhca_access); 1078 attr->cross_vhca = attr->cross_vhca && 1079 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR) && 1080 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_FT) && 1081 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC); 1082 } 1083 if (attr->log_min_stride_wqe_sz == 0) 1084 attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 1085 if (attr->qos.sup) { 1086 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1087 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 1088 MLX5_HCA_CAP_OPMOD_GET_CUR); 1089 if (!hcattr) { 1090 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); 1091 return rc; 1092 } 1093 attr->qos.flow_meter_old = 1094 MLX5_GET(qos_cap, hcattr, flow_meter_old); 1095 attr->qos.log_max_flow_meter = 1096 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 1097 attr->qos.flow_meter_reg_c_ids = 1098 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 1099 attr->qos.flow_meter = 1100 MLX5_GET(qos_cap, hcattr, flow_meter); 1101 attr->qos.packet_pacing = 1102 MLX5_GET(qos_cap, hcattr, packet_pacing); 1103 attr->qos.wqe_rate_pp = 1104 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 1105 if (attr->qos.flow_meter_aso_sup) { 1106 attr->qos.log_meter_aso_granularity = 1107 MLX5_GET(qos_cap, hcattr, 1108 log_meter_aso_granularity); 1109 attr->qos.log_meter_aso_max_alloc = 1110 MLX5_GET(qos_cap, hcattr, 1111 log_meter_aso_max_alloc); 1112 attr->qos.log_max_num_meter_aso = 1113 MLX5_GET(qos_cap, hcattr, 1114 log_max_num_meter_aso); 1115 } 1116 } 1117 /* 1118 * Flex item support needs max_num_prog_sample_field 1119 * from the Capabilities 2 table for PARSE_GRAPH_NODE 1120 */ 1121 if (attr->parse_graph_flex_node) { 1122 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap 1123 (ctx, &attr->flex); 1124 if (rc) 1125 return -1; 1126 } 1127 if (attr->vdpa.valid) 1128 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 1129 if (!attr->eth_net_offloads) 1130 return 0; 1131 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 1132 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1133 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 1134 MLX5_HCA_CAP_OPMOD_GET_CUR); 1135 if (!hcattr) { 1136 attr->log_max_ft_sampler_num = 0; 1137 return rc; 1138 } 1139 attr->log_max_ft_sampler_num = MLX5_GET 1140 (flow_table_nic_cap, hcattr, 1141 flow_table_properties_nic_receive.log_max_ft_sampler_num); 1142 attr->flow.tunnel_header_0_1 = MLX5_GET 1143 (flow_table_nic_cap, hcattr, 1144 ft_field_support_2_nic_receive.tunnel_header_0_1); 1145 attr->flow.tunnel_header_2_3 = MLX5_GET 1146 (flow_table_nic_cap, hcattr, 1147 ft_field_support_2_nic_receive.tunnel_header_2_3); 1148 attr->modify_outer_ip_ecn = MLX5_GET 1149 (flow_table_nic_cap, hcattr, 1150 ft_header_modify_nic_receive.outer_ip_ecn); 1151 attr->set_reg_c = 0xff; 1152 if (attr->nic_flow_table) { 1153 #define GET_RX_REG_X_BITS \ 1154 MLX5_GET(flow_table_nic_cap, hcattr, \ 1155 ft_header_modify_nic_receive.metadata_reg_c_x) 1156 #define GET_TX_REG_X_BITS \ 1157 MLX5_GET(flow_table_nic_cap, hcattr, \ 1158 ft_header_modify_nic_transmit.metadata_reg_c_x) 1159 1160 uint32_t tx_reg, rx_reg; 1161 1162 tx_reg = GET_TX_REG_X_BITS; 1163 rx_reg = GET_RX_REG_X_BITS; 1164 attr->set_reg_c &= (rx_reg & tx_reg); 1165 1166 #undef GET_RX_REG_X_BITS 1167 #undef GET_TX_REG_X_BITS 1168 } 1169 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 1170 attr->inner_ipv4_ihl = MLX5_GET 1171 (flow_table_nic_cap, hcattr, 1172 ft_field_support_2_nic_receive.inner_ipv4_ihl); 1173 attr->outer_ipv4_ihl = MLX5_GET 1174 (flow_table_nic_cap, hcattr, 1175 ft_field_support_2_nic_receive.outer_ipv4_ihl); 1176 attr->lag_rx_port_affinity = MLX5_GET 1177 (flow_table_nic_cap, hcattr, 1178 ft_field_support_2_nic_receive.lag_rx_port_affinity); 1179 /* Query HCA offloads for Ethernet protocol. */ 1180 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1181 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 1182 MLX5_HCA_CAP_OPMOD_GET_CUR); 1183 if (!hcattr) { 1184 attr->eth_net_offloads = 0; 1185 return rc; 1186 } 1187 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 1188 hcattr, wqe_vlan_insert); 1189 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 1190 hcattr, csum_cap); 1191 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 1192 hcattr, vlan_cap); 1193 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1194 lro_cap); 1195 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1196 hcattr, max_lso_cap); 1197 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1198 hcattr, scatter_fcs); 1199 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1200 hcattr, tunnel_lro_gre); 1201 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1202 hcattr, tunnel_lro_vxlan); 1203 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1204 hcattr, swp); 1205 attr->tunnel_stateless_gre = 1206 MLX5_GET(per_protocol_networking_offload_caps, 1207 hcattr, tunnel_stateless_gre); 1208 attr->tunnel_stateless_vxlan = 1209 MLX5_GET(per_protocol_networking_offload_caps, 1210 hcattr, tunnel_stateless_vxlan); 1211 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1212 hcattr, swp_csum); 1213 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1214 hcattr, swp_lso); 1215 attr->lro_max_msg_sz_mode = MLX5_GET 1216 (per_protocol_networking_offload_caps, 1217 hcattr, lro_max_msg_sz_mode); 1218 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1219 attr->lro_timer_supported_periods[i] = 1220 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1221 lro_timer_supported_periods[i]); 1222 } 1223 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1224 hcattr, lro_min_mss_size); 1225 attr->tunnel_stateless_geneve_rx = 1226 MLX5_GET(per_protocol_networking_offload_caps, 1227 hcattr, tunnel_stateless_geneve_rx); 1228 attr->geneve_max_opt_len = 1229 MLX5_GET(per_protocol_networking_offload_caps, 1230 hcattr, max_geneve_opt_len); 1231 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1232 hcattr, wqe_inline_mode); 1233 attr->tunnel_stateless_gtp = MLX5_GET 1234 (per_protocol_networking_offload_caps, 1235 hcattr, tunnel_stateless_gtp); 1236 attr->rss_ind_tbl_cap = MLX5_GET 1237 (per_protocol_networking_offload_caps, 1238 hcattr, rss_ind_tbl_cap); 1239 /* Query HCA attribute for ROCE. */ 1240 if (attr->roce) { 1241 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1242 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1243 MLX5_HCA_CAP_OPMOD_GET_CUR); 1244 if (!hcattr) { 1245 DRV_LOG(DEBUG, 1246 "Failed to query devx HCA ROCE capabilities"); 1247 return rc; 1248 } 1249 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1250 } 1251 if (attr->eth_virt && 1252 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1253 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1254 if (rc) { 1255 attr->eth_virt = 0; 1256 goto error; 1257 } 1258 } 1259 if (attr->eswitch_manager) { 1260 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1261 MLX5_SET_HCA_CAP_OP_MOD_ESW | 1262 MLX5_HCA_CAP_OPMOD_GET_CUR); 1263 if (!hcattr) 1264 return rc; 1265 attr->esw_mgr_vport_id_valid = 1266 MLX5_GET(esw_cap, hcattr, 1267 esw_manager_vport_number_valid); 1268 attr->esw_mgr_vport_id = 1269 MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); 1270 } 1271 if (attr->eswitch_manager) { 1272 uint32_t esw_reg; 1273 1274 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1275 MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE | 1276 MLX5_HCA_CAP_OPMOD_GET_CUR); 1277 if (!hcattr) 1278 return rc; 1279 esw_reg = MLX5_GET(flow_table_esw_cap, hcattr, 1280 ft_header_modify_esw_fdb.metadata_reg_c_x); 1281 attr->set_reg_c &= esw_reg; 1282 } 1283 return 0; 1284 error: 1285 rc = (rc > 0) ? -rc : rc; 1286 return rc; 1287 } 1288 1289 /** 1290 * Query TIS transport domain from QP verbs object using DevX API. 1291 * 1292 * @param[in] qp 1293 * Pointer to verbs QP returned by ibv_create_qp . 1294 * @param[in] tis_num 1295 * TIS number of TIS to query. 1296 * @param[out] tis_td 1297 * Pointer to TIS transport domain variable, to be set by the routine. 1298 * 1299 * @return 1300 * 0 on success, a negative value otherwise. 1301 */ 1302 int 1303 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1304 uint32_t *tis_td) 1305 { 1306 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1307 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1308 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1309 int rc; 1310 void *tis_ctx; 1311 1312 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1313 MLX5_SET(query_tis_in, in, tisn, tis_num); 1314 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1315 if (rc) { 1316 DRV_LOG(ERR, "Failed to query QP using DevX"); 1317 return -rc; 1318 }; 1319 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1320 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1321 return 0; 1322 #else 1323 (void)qp; 1324 (void)tis_num; 1325 (void)tis_td; 1326 return -ENOTSUP; 1327 #endif 1328 } 1329 1330 /** 1331 * Fill WQ data for DevX API command. 1332 * Utility function for use when creating DevX objects containing a WQ. 1333 * 1334 * @param[in] wq_ctx 1335 * Pointer to WQ context to fill with data. 1336 * @param [in] wq_attr 1337 * Pointer to WQ attributes structure to fill in WQ context. 1338 */ 1339 static void 1340 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1341 { 1342 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1343 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1344 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1345 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1346 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1347 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1348 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1349 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1350 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1351 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1352 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1353 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1354 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1355 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1356 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1357 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1358 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1359 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1360 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1361 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1362 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1363 wq_attr->log_hairpin_num_packets); 1364 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1365 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1366 wq_attr->single_wqe_log_num_of_strides); 1367 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1368 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1369 wq_attr->single_stride_log_num_of_bytes); 1370 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1371 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1372 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1373 } 1374 1375 /** 1376 * Create RQ using DevX API. 1377 * 1378 * @param[in] ctx 1379 * Context returned from mlx5 open_device() glue function. 1380 * @param [in] rq_attr 1381 * Pointer to create RQ attributes structure. 1382 * @param [in] socket 1383 * CPU socket ID for allocations. 1384 * 1385 * @return 1386 * The DevX object created, NULL otherwise and rte_errno is set. 1387 */ 1388 struct mlx5_devx_obj * 1389 mlx5_devx_cmd_create_rq(void *ctx, 1390 struct mlx5_devx_create_rq_attr *rq_attr, 1391 int socket) 1392 { 1393 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1394 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1395 void *rq_ctx, *wq_ctx; 1396 struct mlx5_devx_wq_attr *wq_attr; 1397 struct mlx5_devx_obj *rq = NULL; 1398 1399 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1400 if (!rq) { 1401 DRV_LOG(ERR, "Failed to allocate RQ data"); 1402 rte_errno = ENOMEM; 1403 return NULL; 1404 } 1405 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1406 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1407 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1408 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1409 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1410 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1411 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1412 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1413 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1414 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1415 MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type); 1416 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1417 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1418 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1419 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1420 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1421 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1422 wq_attr = &rq_attr->wq_attr; 1423 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1424 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1425 out, sizeof(out)); 1426 if (!rq->obj) { 1427 DEVX_DRV_LOG(ERR, out, "create RQ", NULL, 0); 1428 mlx5_free(rq); 1429 return NULL; 1430 } 1431 rq->id = MLX5_GET(create_rq_out, out, rqn); 1432 return rq; 1433 } 1434 1435 /** 1436 * Modify RQ using DevX API. 1437 * 1438 * @param[in] rq 1439 * Pointer to RQ object structure. 1440 * @param [in] rq_attr 1441 * Pointer to modify RQ attributes structure. 1442 * 1443 * @return 1444 * 0 on success, a negative errno value otherwise and rte_errno is set. 1445 */ 1446 int 1447 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1448 struct mlx5_devx_modify_rq_attr *rq_attr) 1449 { 1450 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1451 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1452 void *rq_ctx, *wq_ctx; 1453 int ret; 1454 1455 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1456 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1457 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1458 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1459 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1460 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1461 if (rq_attr->modify_bitmask & 1462 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1463 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1464 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1465 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1466 if (rq_attr->modify_bitmask & 1467 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1468 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1469 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1470 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1471 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1472 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1473 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1474 } 1475 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1476 out, sizeof(out)); 1477 if (ret) { 1478 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1479 rte_errno = errno; 1480 return -errno; 1481 } 1482 return ret; 1483 } 1484 1485 /** 1486 * Create RMP using DevX API. 1487 * 1488 * @param[in] ctx 1489 * Context returned from mlx5 open_device() glue function. 1490 * @param [in] rmp_attr 1491 * Pointer to create RMP attributes structure. 1492 * @param [in] socket 1493 * CPU socket ID for allocations. 1494 * 1495 * @return 1496 * The DevX object created, NULL otherwise and rte_errno is set. 1497 */ 1498 struct mlx5_devx_obj * 1499 mlx5_devx_cmd_create_rmp(void *ctx, 1500 struct mlx5_devx_create_rmp_attr *rmp_attr, 1501 int socket) 1502 { 1503 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0}; 1504 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0}; 1505 void *rmp_ctx, *wq_ctx; 1506 struct mlx5_devx_wq_attr *wq_attr; 1507 struct mlx5_devx_obj *rmp = NULL; 1508 1509 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket); 1510 if (!rmp) { 1511 DRV_LOG(ERR, "Failed to allocate RMP data"); 1512 rte_errno = ENOMEM; 1513 return NULL; 1514 } 1515 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP); 1516 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx); 1517 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state); 1518 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe, 1519 rmp_attr->basic_cyclic_rcv_wqe); 1520 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq); 1521 wq_attr = &rmp_attr->wq_attr; 1522 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1523 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1524 sizeof(out)); 1525 if (!rmp->obj) { 1526 DEVX_DRV_LOG(ERR, out, "create RMP", NULL, 0); 1527 mlx5_free(rmp); 1528 return NULL; 1529 } 1530 rmp->id = MLX5_GET(create_rmp_out, out, rmpn); 1531 return rmp; 1532 } 1533 1534 /* 1535 * Create TIR using DevX API. 1536 * 1537 * @param[in] ctx 1538 * Context returned from mlx5 open_device() glue function. 1539 * @param [in] tir_attr 1540 * Pointer to TIR attributes structure. 1541 * 1542 * @return 1543 * The DevX object created, NULL otherwise and rte_errno is set. 1544 */ 1545 struct mlx5_devx_obj * 1546 mlx5_devx_cmd_create_tir(void *ctx, 1547 struct mlx5_devx_tir_attr *tir_attr) 1548 { 1549 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1550 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1551 void *tir_ctx, *outer, *inner, *rss_key; 1552 struct mlx5_devx_obj *tir = NULL; 1553 1554 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1555 if (!tir) { 1556 DRV_LOG(ERR, "Failed to allocate TIR data"); 1557 rte_errno = ENOMEM; 1558 return NULL; 1559 } 1560 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1561 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1562 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1563 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1564 tir_attr->lro_timeout_period_usecs); 1565 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1566 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1567 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1568 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1569 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1570 tir_attr->tunneled_offload_en); 1571 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1572 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1573 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1574 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1575 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1576 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1577 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1578 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1579 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1580 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1581 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1582 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1583 tir_attr->rx_hash_field_selector_outer.selected_fields); 1584 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1585 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1586 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1587 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1588 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1589 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1590 tir_attr->rx_hash_field_selector_inner.selected_fields); 1591 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1592 out, sizeof(out)); 1593 if (!tir->obj) { 1594 DEVX_DRV_LOG(ERR, out, "create TIR", NULL, 0); 1595 mlx5_free(tir); 1596 return NULL; 1597 } 1598 tir->id = MLX5_GET(create_tir_out, out, tirn); 1599 return tir; 1600 } 1601 1602 /** 1603 * Modify TIR using DevX API. 1604 * 1605 * @param[in] tir 1606 * Pointer to TIR DevX object structure. 1607 * @param [in] modify_tir_attr 1608 * Pointer to TIR modification attributes structure. 1609 * 1610 * @return 1611 * 0 on success, a negative errno value otherwise and rte_errno is set. 1612 */ 1613 int 1614 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1615 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1616 { 1617 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1618 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1619 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1620 void *tir_ctx; 1621 int ret; 1622 1623 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1624 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1625 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1626 modify_tir_attr->modify_bitmask); 1627 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1628 if (modify_tir_attr->modify_bitmask & 1629 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1630 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1631 tir_attr->lro_timeout_period_usecs); 1632 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1633 tir_attr->lro_enable_mask); 1634 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1635 tir_attr->lro_max_msg_sz); 1636 } 1637 if (modify_tir_attr->modify_bitmask & 1638 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1639 MLX5_SET(tirc, tir_ctx, indirect_table, 1640 tir_attr->indirect_table); 1641 if (modify_tir_attr->modify_bitmask & 1642 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1643 int i; 1644 void *outer, *inner; 1645 1646 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1647 tir_attr->rx_hash_symmetric); 1648 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1649 for (i = 0; i < 10; i++) { 1650 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1651 tir_attr->rx_hash_toeplitz_key[i]); 1652 } 1653 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1654 rx_hash_field_selector_outer); 1655 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1656 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1657 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1658 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1659 MLX5_SET 1660 (rx_hash_field_select, outer, selected_fields, 1661 tir_attr->rx_hash_field_selector_outer.selected_fields); 1662 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1663 rx_hash_field_selector_inner); 1664 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1665 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1666 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1667 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1668 MLX5_SET 1669 (rx_hash_field_select, inner, selected_fields, 1670 tir_attr->rx_hash_field_selector_inner.selected_fields); 1671 } 1672 if (modify_tir_attr->modify_bitmask & 1673 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1674 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1675 } 1676 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1677 out, sizeof(out)); 1678 if (ret) { 1679 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1680 rte_errno = errno; 1681 return -errno; 1682 } 1683 return ret; 1684 } 1685 1686 /** 1687 * Create RQT using DevX API. 1688 * 1689 * @param[in] ctx 1690 * Context returned from mlx5 open_device() glue function. 1691 * @param [in] rqt_attr 1692 * Pointer to RQT attributes structure. 1693 * 1694 * @return 1695 * The DevX object created, NULL otherwise and rte_errno is set. 1696 */ 1697 struct mlx5_devx_obj * 1698 mlx5_devx_cmd_create_rqt(void *ctx, 1699 struct mlx5_devx_rqt_attr *rqt_attr) 1700 { 1701 uint32_t *in = NULL; 1702 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1703 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1704 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1705 void *rqt_ctx; 1706 struct mlx5_devx_obj *rqt = NULL; 1707 int i; 1708 1709 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1710 if (!in) { 1711 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1712 rte_errno = ENOMEM; 1713 return NULL; 1714 } 1715 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1716 if (!rqt) { 1717 DRV_LOG(ERR, "Failed to allocate RQT data"); 1718 rte_errno = ENOMEM; 1719 mlx5_free(in); 1720 return NULL; 1721 } 1722 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1723 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1724 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1725 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1726 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1727 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1728 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1729 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1730 mlx5_free(in); 1731 if (!rqt->obj) { 1732 DEVX_DRV_LOG(ERR, out, "create RQT", NULL, 0); 1733 mlx5_free(rqt); 1734 return NULL; 1735 } 1736 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1737 return rqt; 1738 } 1739 1740 /** 1741 * Modify RQT using DevX API. 1742 * 1743 * @param[in] rqt 1744 * Pointer to RQT DevX object structure. 1745 * @param [in] rqt_attr 1746 * Pointer to RQT attributes structure. 1747 * 1748 * @return 1749 * 0 on success, a negative errno value otherwise and rte_errno is set. 1750 */ 1751 int 1752 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1753 struct mlx5_devx_rqt_attr *rqt_attr) 1754 { 1755 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1756 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1757 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1758 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1759 void *rqt_ctx; 1760 int i; 1761 int ret; 1762 1763 if (!in) { 1764 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1765 rte_errno = ENOMEM; 1766 return -ENOMEM; 1767 } 1768 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1769 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1770 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1771 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1772 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1773 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1774 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1775 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1776 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1777 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1778 mlx5_free(in); 1779 if (ret) { 1780 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1781 rte_errno = errno; 1782 return -rte_errno; 1783 } 1784 return ret; 1785 } 1786 1787 /** 1788 * Create SQ using DevX API. 1789 * 1790 * @param[in] ctx 1791 * Context returned from mlx5 open_device() glue function. 1792 * @param [in] sq_attr 1793 * Pointer to SQ attributes structure. 1794 * @param [in] socket 1795 * CPU socket ID for allocations. 1796 * 1797 * @return 1798 * The DevX object created, NULL otherwise and rte_errno is set. 1799 **/ 1800 struct mlx5_devx_obj * 1801 mlx5_devx_cmd_create_sq(void *ctx, 1802 struct mlx5_devx_create_sq_attr *sq_attr) 1803 { 1804 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1805 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1806 void *sq_ctx; 1807 void *wq_ctx; 1808 struct mlx5_devx_wq_attr *wq_attr; 1809 struct mlx5_devx_obj *sq = NULL; 1810 1811 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1812 if (!sq) { 1813 DRV_LOG(ERR, "Failed to allocate SQ data"); 1814 rte_errno = ENOMEM; 1815 return NULL; 1816 } 1817 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1818 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1819 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1820 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1821 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1822 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1823 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1824 sq_attr->allow_multi_pkt_send_wqe); 1825 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1826 sq_attr->min_wqe_inline_mode); 1827 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1828 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1829 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1830 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1831 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1832 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1833 MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type); 1834 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1835 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1836 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1837 sq_attr->packet_pacing_rate_limit_index); 1838 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1839 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1840 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1841 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1842 wq_attr = &sq_attr->wq_attr; 1843 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1844 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1845 out, sizeof(out)); 1846 if (!sq->obj) { 1847 DEVX_DRV_LOG(ERR, out, "create SQ", NULL, 0); 1848 mlx5_free(sq); 1849 return NULL; 1850 } 1851 sq->id = MLX5_GET(create_sq_out, out, sqn); 1852 return sq; 1853 } 1854 1855 /** 1856 * Modify SQ using DevX API. 1857 * 1858 * @param[in] sq 1859 * Pointer to SQ object structure. 1860 * @param [in] sq_attr 1861 * Pointer to SQ attributes structure. 1862 * 1863 * @return 1864 * 0 on success, a negative errno value otherwise and rte_errno is set. 1865 */ 1866 int 1867 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1868 struct mlx5_devx_modify_sq_attr *sq_attr) 1869 { 1870 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1871 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1872 void *sq_ctx; 1873 int ret; 1874 1875 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1876 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1877 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1878 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1879 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1880 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1881 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1882 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1883 out, sizeof(out)); 1884 if (ret) { 1885 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1886 rte_errno = errno; 1887 return -rte_errno; 1888 } 1889 return ret; 1890 } 1891 1892 /** 1893 * Create TIS using DevX API. 1894 * 1895 * @param[in] ctx 1896 * Context returned from mlx5 open_device() glue function. 1897 * @param [in] tis_attr 1898 * Pointer to TIS attributes structure. 1899 * 1900 * @return 1901 * The DevX object created, NULL otherwise and rte_errno is set. 1902 */ 1903 struct mlx5_devx_obj * 1904 mlx5_devx_cmd_create_tis(void *ctx, 1905 struct mlx5_devx_tis_attr *tis_attr) 1906 { 1907 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1908 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1909 struct mlx5_devx_obj *tis = NULL; 1910 void *tis_ctx; 1911 1912 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1913 if (!tis) { 1914 DRV_LOG(ERR, "Failed to allocate TIS object"); 1915 rte_errno = ENOMEM; 1916 return NULL; 1917 } 1918 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1919 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1920 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1921 tis_attr->strict_lag_tx_port_affinity); 1922 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1923 tis_attr->lag_tx_port_affinity); 1924 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1925 MLX5_SET(tisc, tis_ctx, transport_domain, 1926 tis_attr->transport_domain); 1927 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1928 out, sizeof(out)); 1929 if (!tis->obj) { 1930 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 1931 mlx5_free(tis); 1932 return NULL; 1933 } 1934 tis->id = MLX5_GET(create_tis_out, out, tisn); 1935 return tis; 1936 } 1937 1938 /** 1939 * Create transport domain using DevX API. 1940 * 1941 * @param[in] ctx 1942 * Context returned from mlx5 open_device() glue function. 1943 * @return 1944 * The DevX object created, NULL otherwise and rte_errno is set. 1945 */ 1946 struct mlx5_devx_obj * 1947 mlx5_devx_cmd_create_td(void *ctx) 1948 { 1949 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1950 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1951 struct mlx5_devx_obj *td = NULL; 1952 1953 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1954 if (!td) { 1955 DRV_LOG(ERR, "Failed to allocate TD object"); 1956 rte_errno = ENOMEM; 1957 return NULL; 1958 } 1959 MLX5_SET(alloc_transport_domain_in, in, opcode, 1960 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1961 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1962 out, sizeof(out)); 1963 if (!td->obj) { 1964 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 1965 mlx5_free(td); 1966 return NULL; 1967 } 1968 td->id = MLX5_GET(alloc_transport_domain_out, out, 1969 transport_domain); 1970 return td; 1971 } 1972 1973 /** 1974 * Dump all flows to file. 1975 * 1976 * @param[in] fdb_domain 1977 * FDB domain. 1978 * @param[in] rx_domain 1979 * RX domain. 1980 * @param[in] tx_domain 1981 * TX domain. 1982 * @param[out] file 1983 * Pointer to file stream. 1984 * 1985 * @return 1986 * 0 on success, a negative value otherwise. 1987 */ 1988 int 1989 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1990 void *rx_domain __rte_unused, 1991 void *tx_domain __rte_unused, FILE *file __rte_unused) 1992 { 1993 int ret = 0; 1994 1995 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1996 if (fdb_domain) { 1997 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1998 if (ret) 1999 return ret; 2000 } 2001 MLX5_ASSERT(rx_domain); 2002 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 2003 if (ret) 2004 return ret; 2005 MLX5_ASSERT(tx_domain); 2006 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 2007 #else 2008 ret = ENOTSUP; 2009 #endif 2010 return -ret; 2011 } 2012 2013 int 2014 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 2015 FILE *file __rte_unused) 2016 { 2017 int ret = 0; 2018 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 2019 if (rule_info) 2020 ret = mlx5_glue->dr_dump_rule(file, rule_info); 2021 #else 2022 ret = ENOTSUP; 2023 #endif 2024 return -ret; 2025 } 2026 2027 /* 2028 * Create CQ using DevX API. 2029 * 2030 * @param[in] ctx 2031 * Context returned from mlx5 open_device() glue function. 2032 * @param [in] attr 2033 * Pointer to CQ attributes structure. 2034 * 2035 * @return 2036 * The DevX object created, NULL otherwise and rte_errno is set. 2037 */ 2038 struct mlx5_devx_obj * 2039 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 2040 { 2041 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 2042 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 2043 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2044 sizeof(*cq_obj), 2045 0, SOCKET_ID_ANY); 2046 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 2047 2048 if (!cq_obj) { 2049 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 2050 rte_errno = ENOMEM; 2051 return NULL; 2052 } 2053 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 2054 if (attr->db_umem_valid) { 2055 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 2056 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 2057 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 2058 } else { 2059 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 2060 } 2061 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 2062 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 2063 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 2064 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 2065 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 2066 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2067 MLX5_SET(cqc, cqctx, log_page_size, 2068 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2069 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 2070 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 2071 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 2072 MLX5_SET(cqc, cqctx, cqe_comp_layout, !!attr->cqe_comp_layout); 2073 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 2074 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 2075 attr->mini_cqe_res_format_ext); 2076 if (attr->q_umem_valid) { 2077 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 2078 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 2079 MLX5_SET64(create_cq_in, in, cq_umem_offset, 2080 attr->q_umem_offset); 2081 } 2082 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2083 sizeof(out)); 2084 if (!cq_obj->obj) { 2085 DEVX_DRV_LOG(ERR, out, "create CQ", NULL, 0); 2086 mlx5_free(cq_obj); 2087 return NULL; 2088 } 2089 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 2090 return cq_obj; 2091 } 2092 2093 /** 2094 * Create VIRTQ using DevX API. 2095 * 2096 * @param[in] ctx 2097 * Context returned from mlx5 open_device() glue function. 2098 * @param [in] attr 2099 * Pointer to VIRTQ attributes structure. 2100 * 2101 * @return 2102 * The DevX object created, NULL otherwise and rte_errno is set. 2103 */ 2104 struct mlx5_devx_obj * 2105 mlx5_devx_cmd_create_virtq(void *ctx, 2106 struct mlx5_devx_virtq_attr *attr) 2107 { 2108 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2109 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2110 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2111 sizeof(*virtq_obj), 2112 0, SOCKET_ID_ANY); 2113 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2114 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2115 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2116 2117 if (!virtq_obj) { 2118 DRV_LOG(ERR, "Failed to allocate virtq data."); 2119 rte_errno = ENOMEM; 2120 return NULL; 2121 } 2122 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2123 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2124 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2125 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2126 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2127 attr->hw_available_index); 2128 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 2129 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2130 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2131 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2132 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2133 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2134 attr->virtio_version_1_0); 2135 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2136 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2137 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2138 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2139 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 2140 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2141 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 2142 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2143 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 2144 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 2145 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 2146 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 2147 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 2148 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 2149 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 2150 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 2151 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 2152 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 2153 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 2154 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 2155 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 2156 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 2157 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 2158 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2159 sizeof(out)); 2160 if (!virtq_obj->obj) { 2161 DEVX_DRV_LOG(ERR, out, "create VIRTQ", NULL, 0); 2162 mlx5_free(virtq_obj); 2163 return NULL; 2164 } 2165 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2166 return virtq_obj; 2167 } 2168 2169 /** 2170 * Modify VIRTQ using DevX API. 2171 * 2172 * @param[in] virtq_obj 2173 * Pointer to virtq object structure. 2174 * @param [in] attr 2175 * Pointer to modify virtq attributes structure. 2176 * 2177 * @return 2178 * 0 on success, a negative errno value otherwise and rte_errno is set. 2179 */ 2180 int 2181 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 2182 struct mlx5_devx_virtq_attr *attr) 2183 { 2184 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2185 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2186 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2187 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2188 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2189 int ret; 2190 2191 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2192 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 2193 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2194 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2195 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2196 MLX5_SET64(virtio_net_q, virtq, modify_field_select, 2197 attr->mod_fields_bitmap); 2198 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2199 if (!attr->mod_fields_bitmap) { 2200 DRV_LOG(ERR, "Failed to modify VIRTQ for no type set."); 2201 rte_errno = EINVAL; 2202 return -rte_errno; 2203 } 2204 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE) 2205 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 2206 if (attr->mod_fields_bitmap & 2207 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) { 2208 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 2209 attr->dirty_bitmap_mkey); 2210 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 2211 attr->dirty_bitmap_addr); 2212 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 2213 attr->dirty_bitmap_size); 2214 } 2215 if (attr->mod_fields_bitmap & 2216 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE) 2217 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 2218 attr->dirty_bitmap_dump_enable); 2219 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) { 2220 MLX5_SET(virtio_q, virtctx, queue_period_mode, 2221 attr->hw_latency_mode); 2222 MLX5_SET(virtio_q, virtctx, queue_period_us, 2223 attr->hw_max_latency_us); 2224 MLX5_SET(virtio_q, virtctx, queue_max_count, 2225 attr->hw_max_pending_comp); 2226 } 2227 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) { 2228 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2229 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2230 MLX5_SET64(virtio_q, virtctx, available_addr, 2231 attr->available_addr); 2232 } 2233 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX) 2234 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2235 attr->hw_available_index); 2236 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX) 2237 MLX5_SET16(virtio_net_q, virtq, hw_used_index, 2238 attr->hw_used_index); 2239 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE) 2240 MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type); 2241 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0) 2242 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2243 attr->virtio_version_1_0); 2244 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY) 2245 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2246 if (attr->mod_fields_bitmap & 2247 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) { 2248 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2249 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2250 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2251 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2252 } 2253 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) { 2254 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2255 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2256 } 2257 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 2258 out, sizeof(out)); 2259 if (ret) { 2260 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2261 rte_errno = errno; 2262 return -rte_errno; 2263 } 2264 return ret; 2265 } 2266 2267 /** 2268 * Query VIRTQ using DevX API. 2269 * 2270 * @param[in] virtq_obj 2271 * Pointer to virtq object structure. 2272 * @param [in/out] attr 2273 * Pointer to virtq attributes structure. 2274 * 2275 * @return 2276 * 0 on success, a negative errno value otherwise and rte_errno is set. 2277 */ 2278 int 2279 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 2280 struct mlx5_devx_virtq_attr *attr) 2281 { 2282 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2283 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 2284 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 2285 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 2286 int ret; 2287 2288 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2289 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2290 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2291 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2292 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2293 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2294 out, sizeof(out)); 2295 if (ret) { 2296 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2297 rte_errno = errno; 2298 return -errno; 2299 } 2300 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2301 hw_available_index); 2302 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2303 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2304 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2305 virtio_q_context.error_type); 2306 return ret; 2307 } 2308 2309 /** 2310 * Create QP using DevX API. 2311 * 2312 * @param[in] ctx 2313 * Context returned from mlx5 open_device() glue function. 2314 * @param [in] attr 2315 * Pointer to QP attributes structure. 2316 * 2317 * @return 2318 * The DevX object created, NULL otherwise and rte_errno is set. 2319 */ 2320 struct mlx5_devx_obj * 2321 mlx5_devx_cmd_create_qp(void *ctx, 2322 struct mlx5_devx_qp_attr *attr) 2323 { 2324 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2325 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2326 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2327 sizeof(*qp_obj), 2328 0, SOCKET_ID_ANY); 2329 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2330 2331 if (!qp_obj) { 2332 DRV_LOG(ERR, "Failed to allocate QP data."); 2333 rte_errno = ENOMEM; 2334 return NULL; 2335 } 2336 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2337 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2338 MLX5_SET(qpc, qpc, pd, attr->pd); 2339 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2340 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2341 if (attr->uar_index) { 2342 if (attr->mmo) { 2343 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2344 in, qpc_extension_and_pas_list); 2345 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2346 qpc_ext_and_pas_list, qpc_data_extension); 2347 2348 MLX5_SET(create_qp_in, in, qpc_ext, 1); 2349 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2350 } 2351 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2352 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2353 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2354 MLX5_SET(qpc, qpc, log_page_size, 2355 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2356 if (attr->num_of_send_wqbbs) { 2357 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs)); 2358 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2359 MLX5_SET(qpc, qpc, log_sq_size, 2360 rte_log2_u32(attr->num_of_send_wqbbs)); 2361 } else { 2362 MLX5_SET(qpc, qpc, no_sq, 1); 2363 } 2364 if (attr->num_of_receive_wqes) { 2365 MLX5_ASSERT(RTE_IS_POWER_OF_2( 2366 attr->num_of_receive_wqes)); 2367 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2368 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2369 MLX5_LOG_RQ_STRIDE_SHIFT); 2370 MLX5_SET(qpc, qpc, log_rq_size, 2371 rte_log2_u32(attr->num_of_receive_wqes)); 2372 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2373 } else { 2374 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2375 } 2376 if (attr->dbr_umem_valid) { 2377 MLX5_SET(qpc, qpc, dbr_umem_valid, 2378 attr->dbr_umem_valid); 2379 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2380 } 2381 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2382 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2383 attr->wq_umem_offset); 2384 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2385 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2386 } else { 2387 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2388 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2389 MLX5_SET(qpc, qpc, no_sq, 1); 2390 } 2391 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2392 sizeof(out)); 2393 if (!qp_obj->obj) { 2394 DEVX_DRV_LOG(ERR, out, "create QP", NULL, 0); 2395 mlx5_free(qp_obj); 2396 return NULL; 2397 } 2398 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2399 return qp_obj; 2400 } 2401 2402 /** 2403 * Modify QP using DevX API. 2404 * Currently supports only force loop-back QP. 2405 * 2406 * @param[in] qp 2407 * Pointer to QP object structure. 2408 * @param [in] qp_st_mod_op 2409 * The QP state modification operation. 2410 * @param [in] remote_qp_id 2411 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2412 * 2413 * @return 2414 * 0 on success, a negative errno value otherwise and rte_errno is set. 2415 */ 2416 int 2417 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2418 uint32_t remote_qp_id) 2419 { 2420 union { 2421 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2422 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2423 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2424 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)]; 2425 } in; 2426 union { 2427 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2428 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2429 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2430 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)]; 2431 } out; 2432 void *qpc; 2433 int ret; 2434 unsigned int inlen; 2435 unsigned int outlen; 2436 2437 memset(&in, 0, sizeof(in)); 2438 memset(&out, 0, sizeof(out)); 2439 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2440 switch (qp_st_mod_op) { 2441 case MLX5_CMD_OP_RST2INIT_QP: 2442 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2443 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2444 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2445 MLX5_SET(qpc, qpc, rre, 1); 2446 MLX5_SET(qpc, qpc, rwe, 1); 2447 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2448 inlen = sizeof(in.rst2init); 2449 outlen = sizeof(out.rst2init); 2450 break; 2451 case MLX5_CMD_OP_INIT2RTR_QP: 2452 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2453 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2454 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2455 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2456 MLX5_SET(qpc, qpc, mtu, 1); 2457 MLX5_SET(qpc, qpc, log_msg_max, 30); 2458 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2459 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2460 inlen = sizeof(in.init2rtr); 2461 outlen = sizeof(out.init2rtr); 2462 break; 2463 case MLX5_CMD_OP_RTR2RTS_QP: 2464 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2465 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2466 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16); 2467 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2468 MLX5_SET(qpc, qpc, retry_count, 7); 2469 MLX5_SET(qpc, qpc, rnr_retry, 7); 2470 inlen = sizeof(in.rtr2rts); 2471 outlen = sizeof(out.rtr2rts); 2472 break; 2473 case MLX5_CMD_OP_QP_2RST: 2474 MLX5_SET(2rst_qp_in, &in, qpn, qp->id); 2475 inlen = sizeof(in.qp2rst); 2476 outlen = sizeof(out.qp2rst); 2477 break; 2478 default: 2479 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2480 qp_st_mod_op); 2481 rte_errno = EINVAL; 2482 return -rte_errno; 2483 } 2484 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2485 if (ret) { 2486 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2487 rte_errno = errno; 2488 return -rte_errno; 2489 } 2490 return ret; 2491 } 2492 2493 struct mlx5_devx_obj * 2494 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2495 { 2496 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2497 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2498 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2499 sizeof(*couners_obj), 0, 2500 SOCKET_ID_ANY); 2501 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2502 2503 if (!couners_obj) { 2504 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2505 rte_errno = ENOMEM; 2506 return NULL; 2507 } 2508 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2509 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2510 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2511 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2512 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2513 sizeof(out)); 2514 if (!couners_obj->obj) { 2515 DEVX_DRV_LOG(ERR, out, "create virtio queue counters Obj", NULL, 2516 0); 2517 mlx5_free(couners_obj); 2518 return NULL; 2519 } 2520 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2521 return couners_obj; 2522 } 2523 2524 int 2525 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2526 struct mlx5_devx_virtio_q_couners_attr *attr) 2527 { 2528 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2529 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2530 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2531 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2532 virtio_q_counters); 2533 int ret; 2534 2535 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2536 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2537 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2538 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2539 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2540 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2541 sizeof(out)); 2542 if (ret) { 2543 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2544 rte_errno = errno; 2545 return -errno; 2546 } 2547 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2548 received_desc); 2549 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2550 completed_desc); 2551 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2552 error_cqes); 2553 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2554 bad_desc_errors); 2555 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2556 exceed_max_chain); 2557 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2558 invalid_buffer); 2559 return ret; 2560 } 2561 2562 /** 2563 * Create general object of type FLOW_HIT_ASO using DevX API. 2564 * 2565 * @param[in] ctx 2566 * Context returned from mlx5 open_device() glue function. 2567 * @param [in] pd 2568 * PD value to associate the FLOW_HIT_ASO object with. 2569 * 2570 * @return 2571 * The DevX object created, NULL otherwise and rte_errno is set. 2572 */ 2573 struct mlx5_devx_obj * 2574 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2575 { 2576 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2577 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2578 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2579 void *ptr = NULL; 2580 2581 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2582 0, SOCKET_ID_ANY); 2583 if (!flow_hit_aso_obj) { 2584 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2585 rte_errno = ENOMEM; 2586 return NULL; 2587 } 2588 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2589 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2590 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2591 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2592 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2593 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2594 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2595 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2596 out, sizeof(out)); 2597 if (!flow_hit_aso_obj->obj) { 2598 DEVX_DRV_LOG(ERR, out, "create FLOW_HIT_ASO", NULL, 0); 2599 mlx5_free(flow_hit_aso_obj); 2600 return NULL; 2601 } 2602 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2603 return flow_hit_aso_obj; 2604 } 2605 2606 /* 2607 * Create PD using DevX API. 2608 * 2609 * @param[in] ctx 2610 * Context returned from mlx5 open_device() glue function. 2611 * 2612 * @return 2613 * The DevX object created, NULL otherwise and rte_errno is set. 2614 */ 2615 struct mlx5_devx_obj * 2616 mlx5_devx_cmd_alloc_pd(void *ctx) 2617 { 2618 struct mlx5_devx_obj *ppd = 2619 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2620 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2621 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2622 2623 if (!ppd) { 2624 DRV_LOG(ERR, "Failed to allocate PD data."); 2625 rte_errno = ENOMEM; 2626 return NULL; 2627 } 2628 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2629 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2630 out, sizeof(out)); 2631 if (!ppd->obj) { 2632 mlx5_free(ppd); 2633 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2634 rte_errno = errno; 2635 return NULL; 2636 } 2637 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2638 return ppd; 2639 } 2640 2641 /** 2642 * Create general object of type FLOW_METER_ASO using DevX API. 2643 * 2644 * @param[in] ctx 2645 * Context returned from mlx5 open_device() glue function. 2646 * @param [in] pd 2647 * PD value to associate the FLOW_METER_ASO object with. 2648 * @param [in] log_obj_size 2649 * log_obj_size define to allocate number of 2 * meters 2650 * in one FLOW_METER_ASO object. 2651 * 2652 * @return 2653 * The DevX object created, NULL otherwise and rte_errno is set. 2654 */ 2655 struct mlx5_devx_obj * 2656 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2657 uint32_t log_obj_size) 2658 { 2659 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2660 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2661 struct mlx5_devx_obj *flow_meter_aso_obj; 2662 void *ptr; 2663 2664 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2665 sizeof(*flow_meter_aso_obj), 2666 0, SOCKET_ID_ANY); 2667 if (!flow_meter_aso_obj) { 2668 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2669 rte_errno = ENOMEM; 2670 return NULL; 2671 } 2672 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2673 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2674 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2675 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2676 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2677 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2678 log_obj_size); 2679 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2680 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2681 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2682 ctx, in, sizeof(in), 2683 out, sizeof(out)); 2684 if (!flow_meter_aso_obj->obj) { 2685 DEVX_DRV_LOG(ERR, out, "create FLOW_METTER_ASO", NULL, 0); 2686 mlx5_free(flow_meter_aso_obj); 2687 return NULL; 2688 } 2689 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2690 out, obj_id); 2691 return flow_meter_aso_obj; 2692 } 2693 2694 /* 2695 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2696 * 2697 * @param[in] ctx 2698 * Context returned from mlx5 open_device() glue function. 2699 * @param [in] pd 2700 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2701 * @param [in] log_obj_size 2702 * log_obj_size to allocate its power of 2 * objects 2703 * in one CONN_TRACK_OFFLOAD bulk allocation. 2704 * 2705 * @return 2706 * The DevX object created, NULL otherwise and rte_errno is set. 2707 */ 2708 struct mlx5_devx_obj * 2709 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2710 uint32_t log_obj_size) 2711 { 2712 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2713 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2714 struct mlx5_devx_obj *ct_aso_obj; 2715 void *ptr; 2716 2717 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2718 0, SOCKET_ID_ANY); 2719 if (!ct_aso_obj) { 2720 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2721 rte_errno = ENOMEM; 2722 return NULL; 2723 } 2724 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2725 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2726 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2727 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2728 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2729 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2730 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2731 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2732 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2733 out, sizeof(out)); 2734 if (!ct_aso_obj->obj) { 2735 DEVX_DRV_LOG(ERR, out, "create CONN_TRACK_OFFLOAD", NULL, 0); 2736 mlx5_free(ct_aso_obj); 2737 return NULL; 2738 } 2739 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2740 return ct_aso_obj; 2741 } 2742 2743 /** 2744 * Create general object of type GENEVE TLV option using DevX API. 2745 * 2746 * @param[in] ctx 2747 * Context returned from mlx5 open_device() glue function. 2748 * @param [in] class 2749 * TLV option variable value of class 2750 * @param [in] type 2751 * TLV option variable value of type 2752 * @param [in] len 2753 * TLV option variable value of len 2754 * 2755 * @return 2756 * The DevX object created, NULL otherwise and rte_errno is set. 2757 */ 2758 struct mlx5_devx_obj * 2759 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2760 uint16_t class, uint8_t type, uint8_t len) 2761 { 2762 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2763 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2764 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2765 sizeof(*geneve_tlv_opt_obj), 2766 0, SOCKET_ID_ANY); 2767 2768 if (!geneve_tlv_opt_obj) { 2769 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2770 rte_errno = ENOMEM; 2771 return NULL; 2772 } 2773 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2774 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2775 geneve_tlv_opt); 2776 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2777 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2778 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2779 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2780 MLX5_SET(geneve_tlv_option, opt, option_class, 2781 rte_be_to_cpu_16(class)); 2782 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2783 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2784 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2785 sizeof(in), out, sizeof(out)); 2786 if (!geneve_tlv_opt_obj->obj) { 2787 DEVX_DRV_LOG(ERR, out, "create GENEVE TLV", NULL, 0); 2788 mlx5_free(geneve_tlv_opt_obj); 2789 return NULL; 2790 } 2791 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2792 return geneve_tlv_opt_obj; 2793 } 2794 2795 int 2796 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2797 { 2798 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2799 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2800 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2801 int rc; 2802 void *rq_ctx; 2803 2804 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2805 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2806 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2807 if (rc) { 2808 rte_errno = errno; 2809 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2810 "rc = %d, errno = %d.", rc, errno); 2811 return -rc; 2812 }; 2813 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2814 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2815 return 0; 2816 #else 2817 (void)wq; 2818 (void)counter_set_id; 2819 return -ENOTSUP; 2820 #endif 2821 } 2822 2823 /* 2824 * Allocate queue counters via devx interface. 2825 * 2826 * @param[in] ctx 2827 * Context returned from mlx5 open_device() glue function. 2828 * 2829 * @return 2830 * Pointer to counter object on success, a NULL value otherwise and 2831 * rte_errno is set. 2832 */ 2833 struct mlx5_devx_obj * 2834 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2835 { 2836 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2837 SOCKET_ID_ANY); 2838 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2839 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2840 2841 if (!dcs) { 2842 rte_errno = ENOMEM; 2843 return NULL; 2844 } 2845 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2846 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2847 sizeof(out)); 2848 if (!dcs->obj) { 2849 DEVX_DRV_LOG(DEBUG, out, "create q counter set", NULL, 0); 2850 mlx5_free(dcs); 2851 return NULL; 2852 } 2853 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2854 return dcs; 2855 } 2856 2857 /** 2858 * Query queue counters values. 2859 * 2860 * @param[in] dcs 2861 * devx object of the queue counter set. 2862 * @param[in] clear 2863 * Whether hardware should clear the counters after the query or not. 2864 * @param[out] out_of_buffers 2865 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2866 * 2867 * @return 2868 * 0 on success, a negative value otherwise. 2869 */ 2870 int 2871 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2872 uint32_t *out_of_buffers) 2873 { 2874 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2875 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2876 int rc; 2877 2878 MLX5_SET(query_q_counter_in, in, opcode, 2879 MLX5_CMD_OP_QUERY_Q_COUNTER); 2880 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2881 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2882 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2883 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2884 sizeof(out)); 2885 if (rc) { 2886 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2887 rte_errno = rc; 2888 return -rc; 2889 } 2890 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2891 return 0; 2892 } 2893 2894 /** 2895 * Create general object of type DEK using DevX API. 2896 * 2897 * @param[in] ctx 2898 * Context returned from mlx5 open_device() glue function. 2899 * @param [in] attr 2900 * Pointer to DEK attributes structure. 2901 * 2902 * @return 2903 * The DevX object created, NULL otherwise and rte_errno is set. 2904 */ 2905 struct mlx5_devx_obj * 2906 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2907 { 2908 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2909 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2910 struct mlx5_devx_obj *dek_obj = NULL; 2911 void *ptr = NULL, *key_addr = NULL; 2912 2913 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2914 0, SOCKET_ID_ANY); 2915 if (dek_obj == NULL) { 2916 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2917 rte_errno = ENOMEM; 2918 return NULL; 2919 } 2920 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2921 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2922 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2923 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2924 MLX5_GENERAL_OBJ_TYPE_DEK); 2925 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2926 MLX5_SET(dek, ptr, key_size, attr->key_size); 2927 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2928 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2929 MLX5_SET(dek, ptr, pd, attr->pd); 2930 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2931 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2932 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2933 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2934 out, sizeof(out)); 2935 if (dek_obj->obj == NULL) { 2936 DEVX_DRV_LOG(ERR, out, "create DEK", NULL, 0); 2937 mlx5_free(dek_obj); 2938 return NULL; 2939 } 2940 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2941 return dek_obj; 2942 } 2943 2944 /** 2945 * Create general object of type IMPORT_KEK using DevX API. 2946 * 2947 * @param[in] ctx 2948 * Context returned from mlx5 open_device() glue function. 2949 * @param [in] attr 2950 * Pointer to IMPORT_KEK attributes structure. 2951 * 2952 * @return 2953 * The DevX object created, NULL otherwise and rte_errno is set. 2954 */ 2955 struct mlx5_devx_obj * 2956 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 2957 struct mlx5_devx_import_kek_attr *attr) 2958 { 2959 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 2960 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2961 struct mlx5_devx_obj *import_kek_obj = NULL; 2962 void *ptr = NULL, *key_addr = NULL; 2963 2964 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 2965 0, SOCKET_ID_ANY); 2966 if (import_kek_obj == NULL) { 2967 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 2968 rte_errno = ENOMEM; 2969 return NULL; 2970 } 2971 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 2972 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2973 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2974 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2975 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 2976 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 2977 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 2978 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 2979 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2980 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2981 out, sizeof(out)); 2982 if (import_kek_obj->obj == NULL) { 2983 DEVX_DRV_LOG(ERR, out, "create IMPORT_KEK", NULL, 0); 2984 mlx5_free(import_kek_obj); 2985 return NULL; 2986 } 2987 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2988 return import_kek_obj; 2989 } 2990 2991 /** 2992 * Create general object of type CREDENTIAL using DevX API. 2993 * 2994 * @param[in] ctx 2995 * Context returned from mlx5 open_device() glue function. 2996 * @param [in] attr 2997 * Pointer to CREDENTIAL attributes structure. 2998 * 2999 * @return 3000 * The DevX object created, NULL otherwise and rte_errno is set. 3001 */ 3002 struct mlx5_devx_obj * 3003 mlx5_devx_cmd_create_credential_obj(void *ctx, 3004 struct mlx5_devx_credential_attr *attr) 3005 { 3006 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 3007 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3008 struct mlx5_devx_obj *credential_obj = NULL; 3009 void *ptr = NULL, *credential_addr = NULL; 3010 3011 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 3012 0, SOCKET_ID_ANY); 3013 if (credential_obj == NULL) { 3014 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 3015 rte_errno = ENOMEM; 3016 return NULL; 3017 } 3018 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 3019 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3020 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3021 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3022 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 3023 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 3024 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 3025 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 3026 memcpy(credential_addr, (void *)(attr->credential), 3027 MLX5_CRYPTO_CREDENTIAL_SIZE); 3028 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3029 out, sizeof(out)); 3030 if (credential_obj->obj == NULL) { 3031 DEVX_DRV_LOG(ERR, out, "create CREDENTIAL", NULL, 0); 3032 mlx5_free(credential_obj); 3033 return NULL; 3034 } 3035 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3036 return credential_obj; 3037 } 3038 3039 /** 3040 * Create general object of type CRYPTO_LOGIN using DevX API. 3041 * 3042 * @param[in] ctx 3043 * Context returned from mlx5 open_device() glue function. 3044 * @param [in] attr 3045 * Pointer to CRYPTO_LOGIN attributes structure. 3046 * 3047 * @return 3048 * The DevX object created, NULL otherwise and rte_errno is set. 3049 */ 3050 struct mlx5_devx_obj * 3051 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 3052 struct mlx5_devx_crypto_login_attr *attr) 3053 { 3054 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 3055 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3056 struct mlx5_devx_obj *crypto_login_obj = NULL; 3057 void *ptr = NULL, *credential_addr = NULL; 3058 3059 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 3060 0, SOCKET_ID_ANY); 3061 if (crypto_login_obj == NULL) { 3062 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 3063 rte_errno = ENOMEM; 3064 return NULL; 3065 } 3066 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 3067 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3068 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3069 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3070 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 3071 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 3072 MLX5_SET(crypto_login, ptr, credential_pointer, 3073 attr->credential_pointer); 3074 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 3075 attr->session_import_kek_ptr); 3076 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 3077 memcpy(credential_addr, (void *)(attr->credential), 3078 MLX5_CRYPTO_CREDENTIAL_SIZE); 3079 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3080 out, sizeof(out)); 3081 if (crypto_login_obj->obj == NULL) { 3082 DEVX_DRV_LOG(ERR, out, "create CRYPTO_LOGIN", NULL, 0); 3083 mlx5_free(crypto_login_obj); 3084 return NULL; 3085 } 3086 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3087 return crypto_login_obj; 3088 } 3089 3090 /** 3091 * Query LAG context. 3092 * 3093 * @param[in] ctx 3094 * Pointer to ibv_context, returned from mlx5dv_open_device. 3095 * @param[out] lag_ctx 3096 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 3097 * 3098 * @return 3099 * 0 on success, a negative value otherwise. 3100 */ 3101 int 3102 mlx5_devx_cmd_query_lag(void *ctx, 3103 struct mlx5_devx_lag_context *lag_ctx) 3104 { 3105 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 3106 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 3107 void *lctx; 3108 int rc; 3109 3110 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 3111 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 3112 if (rc) 3113 goto error; 3114 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 3115 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 3116 fdb_selection_mode); 3117 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 3118 port_select_mode); 3119 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 3120 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 3121 tx_remap_affinity_2); 3122 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 3123 tx_remap_affinity_1); 3124 return 0; 3125 error: 3126 rc = (rc > 0) ? -rc : rc; 3127 return rc; 3128 } 3129