1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /* FW writes status value to the OUT buffer at offset 00H */ 17 #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status) 18 /* FW writes syndrome value to the OUT buffer at offset 04H */ 19 #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome) 20 21 #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1)) 22 23 #define DEVX_DRV_LOG(level, out, reason, param, value) \ 24 do { \ 25 /* \ 26 * Some (old) GCC compilers like 7.5.0 and aarch64 GCC 7.1-2017.08 \ 27 * do not expand correctly when the macro invoked when the `param` \ 28 * is `NULL`. \ 29 * Use `local_param` to avoid direct `NULL` expansion. \ 30 */ \ 31 const char *local_param = (const char *)param; \ 32 \ 33 rte_errno = errno; \ 34 if (!local_param) { \ 35 DRV_LOG(level, \ 36 "DevX %s failed errno=%d status=%#x syndrome=%#x", \ 37 (reason), errno, MLX5_FW_STATUS((out)), \ 38 MLX5_FW_SYNDROME((out))); \ 39 } else { \ 40 DRV_LOG(level, \ 41 "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x",\ 42 (reason), local_param, (value), errno, \ 43 MLX5_FW_STATUS((out)), MLX5_FW_SYNDROME((out))); \ 44 } \ 45 } while (0) 46 47 static void * 48 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, 49 int *err, uint32_t flags) 50 { 51 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); 52 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); 53 int rc; 54 55 memset(in, 0, size_in); 56 memset(out, 0, size_out); 57 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 58 MLX5_SET(query_hca_cap_in, in, op_mod, flags); 59 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); 60 if (rc || MLX5_FW_STATUS(out)) { 61 DEVX_DRV_LOG(ERR, out, "HCA capabilities", "func", flags >> 1); 62 if (err) 63 *err = MLX5_DEVX_ERR_RC(rc); 64 return NULL; 65 } 66 if (err) 67 *err = 0; 68 return MLX5_ADDR_OF(query_hca_cap_out, out, capability); 69 } 70 71 /** 72 * Perform read access to the registers. Reads data from register 73 * and writes ones to the specified buffer. 74 * 75 * @param[in] ctx 76 * Context returned from mlx5 open_device() glue function. 77 * @param[in] reg_id 78 * Register identifier according to the PRM. 79 * @param[in] arg 80 * Register access auxiliary parameter according to the PRM. 81 * @param[out] data 82 * Pointer to the buffer to store read data. 83 * @param[in] dw_cnt 84 * Buffer size in double words. 85 * 86 * @return 87 * 0 on success, a negative value otherwise. 88 */ 89 int 90 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 91 uint32_t *data, uint32_t dw_cnt) 92 { 93 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 94 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 95 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 96 int rc; 97 98 MLX5_ASSERT(data && dw_cnt); 99 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 100 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 101 DRV_LOG(ERR, "Not enough buffer for register read data"); 102 return -1; 103 } 104 MLX5_SET(access_register_in, in, opcode, 105 MLX5_CMD_OP_ACCESS_REGISTER_USER); 106 MLX5_SET(access_register_in, in, op_mod, 107 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 108 MLX5_SET(access_register_in, in, register_id, reg_id); 109 MLX5_SET(access_register_in, in, argument, arg); 110 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 111 MLX5_ST_SZ_BYTES(access_register_out) + 112 sizeof(uint32_t) * dw_cnt); 113 if (rc || MLX5_FW_STATUS(out)) { 114 DEVX_DRV_LOG(DEBUG, out, "read access", "NIC register", reg_id); 115 return MLX5_DEVX_ERR_RC(rc); 116 } 117 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 118 dw_cnt * sizeof(uint32_t)); 119 return 0; 120 } 121 122 /** 123 * Perform write access to the registers. 124 * 125 * @param[in] ctx 126 * Context returned from mlx5 open_device() glue function. 127 * @param[in] reg_id 128 * Register identifier according to the PRM. 129 * @param[in] arg 130 * Register access auxiliary parameter according to the PRM. 131 * @param[out] data 132 * Pointer to the buffer containing data to write. 133 * @param[in] dw_cnt 134 * Buffer size in double words (32bit units). 135 * 136 * @return 137 * 0 on success, a negative value otherwise. 138 */ 139 int 140 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 141 uint32_t *data, uint32_t dw_cnt) 142 { 143 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 144 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 145 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 146 int rc; 147 void *ptr; 148 149 MLX5_ASSERT(data && dw_cnt); 150 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 151 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 152 DRV_LOG(ERR, "Data to write exceeds max size"); 153 return -1; 154 } 155 MLX5_SET(access_register_in, in, opcode, 156 MLX5_CMD_OP_ACCESS_REGISTER_USER); 157 MLX5_SET(access_register_in, in, op_mod, 158 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 159 MLX5_SET(access_register_in, in, register_id, reg_id); 160 MLX5_SET(access_register_in, in, argument, arg); 161 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 162 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 163 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 164 if (rc || MLX5_FW_STATUS(out)) { 165 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 166 return MLX5_DEVX_ERR_RC(rc); 167 } 168 rc = mlx5_glue->devx_general_cmd(ctx, in, 169 MLX5_ST_SZ_BYTES(access_register_in) + 170 dw_cnt * sizeof(uint32_t), 171 out, sizeof(out)); 172 if (rc || MLX5_FW_STATUS(out)) { 173 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 174 return MLX5_DEVX_ERR_RC(rc); 175 } 176 return 0; 177 } 178 179 struct mlx5_devx_obj * 180 mlx5_devx_cmd_flow_counter_alloc_general(void *ctx, 181 struct mlx5_devx_counter_attr *attr) 182 { 183 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 184 0, SOCKET_ID_ANY); 185 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 186 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 187 188 if (!dcs) { 189 rte_errno = ENOMEM; 190 return NULL; 191 } 192 MLX5_SET(alloc_flow_counter_in, in, opcode, 193 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 194 if (attr->bulk_log_max_alloc) 195 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk_log_size, 196 attr->flow_counter_bulk_log_size); 197 else 198 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, 199 attr->bulk_n_128); 200 if (attr->pd_valid) 201 MLX5_SET(alloc_flow_counter_in, in, pd, attr->pd); 202 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 203 sizeof(in), out, sizeof(out)); 204 if (!dcs->obj) { 205 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 206 rte_errno = errno; 207 mlx5_free(dcs); 208 return NULL; 209 } 210 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 211 return dcs; 212 } 213 214 /** 215 * Allocate flow counters via devx interface. 216 * 217 * @param[in] ctx 218 * Context returned from mlx5 open_device() glue function. 219 * @param dcs 220 * Pointer to counters properties structure to be filled by the routine. 221 * @param bulk_n_128 222 * Bulk counter numbers in 128 counters units. 223 * 224 * @return 225 * Pointer to counter object on success, a negative value otherwise and 226 * rte_errno is set. 227 */ 228 struct mlx5_devx_obj * 229 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 230 { 231 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 232 0, SOCKET_ID_ANY); 233 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 234 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 235 236 if (!dcs) { 237 rte_errno = ENOMEM; 238 return NULL; 239 } 240 MLX5_SET(alloc_flow_counter_in, in, opcode, 241 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 242 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 243 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 244 sizeof(in), out, sizeof(out)); 245 if (!dcs->obj) { 246 DEVX_DRV_LOG(ERR, out, "allocate counters", NULL, 0); 247 mlx5_free(dcs); 248 return NULL; 249 } 250 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 251 return dcs; 252 } 253 254 /** 255 * Query flow counters values. 256 * 257 * @param[in] dcs 258 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 259 * @param[in] clear 260 * Whether hardware should clear the counters after the query or not. 261 * @param[in] n_counters 262 * 0 in case of 1 counter to read, otherwise the counter number to read. 263 * @param pkts 264 * The number of packets that matched the flow. 265 * @param bytes 266 * The number of bytes that matched the flow. 267 * @param mkey 268 * The mkey key for batch query. 269 * @param addr 270 * The address in the mkey range for batch query. 271 * @param cmd_comp 272 * The completion object for asynchronous batch query. 273 * @param async_id 274 * The ID to be returned in the asynchronous batch query response. 275 * 276 * @return 277 * 0 on success, a negative value otherwise. 278 */ 279 int 280 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 281 int clear, uint32_t n_counters, 282 uint64_t *pkts, uint64_t *bytes, 283 uint32_t mkey, void *addr, 284 void *cmd_comp, 285 uint64_t async_id) 286 { 287 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 288 MLX5_ST_SZ_BYTES(traffic_counter); 289 uint32_t out[out_len]; 290 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 291 void *stats; 292 int rc; 293 294 MLX5_SET(query_flow_counter_in, in, opcode, 295 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 296 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 297 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 298 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 299 300 if (n_counters) { 301 MLX5_SET(query_flow_counter_in, in, num_of_counters, 302 n_counters); 303 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 304 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 305 MLX5_SET64(query_flow_counter_in, in, address, 306 (uint64_t)(uintptr_t)addr); 307 } 308 if (!cmd_comp) 309 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 310 out_len); 311 else 312 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 313 out_len, async_id, 314 cmd_comp); 315 if (rc) { 316 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 317 rte_errno = rc; 318 return -rc; 319 } 320 if (!n_counters) { 321 stats = MLX5_ADDR_OF(query_flow_counter_out, 322 out, flow_statistics); 323 *pkts = MLX5_GET64(traffic_counter, stats, packets); 324 *bytes = MLX5_GET64(traffic_counter, stats, octets); 325 } 326 return 0; 327 } 328 329 /** 330 * Create a new mkey. 331 * 332 * @param[in] ctx 333 * Context returned from mlx5 open_device() glue function. 334 * @param[in] attr 335 * Attributes of the requested mkey. 336 * 337 * @return 338 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 339 * is set. 340 */ 341 struct mlx5_devx_obj * 342 mlx5_devx_cmd_mkey_create(void *ctx, 343 struct mlx5_devx_mkey_attr *attr) 344 { 345 struct mlx5_klm *klm_array = attr->klm_array; 346 int klm_num = attr->klm_num; 347 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 348 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 349 uint32_t in[in_size_dw]; 350 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 351 void *mkc; 352 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 353 0, SOCKET_ID_ANY); 354 size_t pgsize; 355 uint32_t translation_size; 356 357 if (!mkey) { 358 rte_errno = ENOMEM; 359 return NULL; 360 } 361 memset(in, 0, in_size_dw * 4); 362 pgsize = rte_mem_page_size(); 363 if (pgsize == (size_t)-1) { 364 mlx5_free(mkey); 365 DRV_LOG(ERR, "Failed to get page size"); 366 rte_errno = ENOMEM; 367 return NULL; 368 } 369 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 370 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 371 if (klm_num > 0) { 372 int i; 373 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 374 klm_pas_mtt); 375 translation_size = RTE_ALIGN(klm_num, 4); 376 for (i = 0; i < klm_num; i++) { 377 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 378 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 379 MLX5_SET64(klm, klm, address, klm_array[i].address); 380 klm += MLX5_ST_SZ_BYTES(klm); 381 } 382 for (; i < (int)translation_size; i++) { 383 MLX5_SET(klm, klm, mkey, 0x0); 384 MLX5_SET64(klm, klm, address, 0x0); 385 klm += MLX5_ST_SZ_BYTES(klm); 386 } 387 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 388 MLX5_MKC_ACCESS_MODE_KLM_FBS : 389 MLX5_MKC_ACCESS_MODE_KLM); 390 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 391 } else { 392 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 393 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 394 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 395 } 396 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 397 translation_size); 398 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 399 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 400 MLX5_SET(mkc, mkc, lw, 0x1); 401 MLX5_SET(mkc, mkc, lr, 0x1); 402 if (attr->set_remote_rw) { 403 MLX5_SET(mkc, mkc, rw, 0x1); 404 MLX5_SET(mkc, mkc, rr, 0x1); 405 } 406 MLX5_SET(mkc, mkc, qpn, 0xffffff); 407 MLX5_SET(mkc, mkc, pd, attr->pd); 408 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 409 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 410 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 411 MLX5_SET(mkc, mkc, relaxed_ordering_write, 412 attr->relaxed_ordering_write); 413 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 414 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 415 MLX5_SET64(mkc, mkc, len, attr->size); 416 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 417 if (attr->crypto_en) { 418 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 419 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 420 } 421 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 422 sizeof(out)); 423 if (!mkey->obj) { 424 DEVX_DRV_LOG(ERR, out, klm_num ? "create indirect mkey" 425 : "create direct key", NULL, 0); 426 mlx5_free(mkey); 427 return NULL; 428 } 429 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 430 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 431 return mkey; 432 } 433 434 /** 435 * Get status of devx command response. 436 * Mainly used for asynchronous commands. 437 * 438 * @param[in] out 439 * The out response buffer. 440 * 441 * @return 442 * 0 on success, non-zero value otherwise. 443 */ 444 int 445 mlx5_devx_get_out_command_status(void *out) 446 { 447 int status; 448 449 if (!out) 450 return -EINVAL; 451 status = MLX5_GET(query_flow_counter_out, out, status); 452 if (status) { 453 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 454 455 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 456 syndrome); 457 } 458 return status; 459 } 460 461 /** 462 * Destroy any object allocated by a Devx API. 463 * 464 * @param[in] obj 465 * Pointer to a general object. 466 * 467 * @return 468 * 0 on success, a negative value otherwise. 469 */ 470 int 471 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 472 { 473 int ret; 474 475 if (!obj) 476 return 0; 477 ret = mlx5_glue->devx_obj_destroy(obj->obj); 478 mlx5_free(obj); 479 return ret; 480 } 481 482 /** 483 * Query NIC vport context. 484 * Fills minimal inline attribute. 485 * 486 * @param[in] ctx 487 * ibv contexts returned from mlx5dv_open_device. 488 * @param[in] vport 489 * vport index 490 * @param[out] attr 491 * Attributes device values. 492 * 493 * @return 494 * 0 on success, a negative value otherwise. 495 */ 496 static int 497 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 498 unsigned int vport, 499 struct mlx5_hca_attr *attr) 500 { 501 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 502 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 503 void *vctx; 504 int rc; 505 506 /* Query NIC vport context to determine inline mode. */ 507 MLX5_SET(query_nic_vport_context_in, in, opcode, 508 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 509 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 510 if (vport) 511 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 512 rc = mlx5_glue->devx_general_cmd(ctx, 513 in, sizeof(in), 514 out, sizeof(out)); 515 if (rc || MLX5_FW_STATUS(out)) { 516 DEVX_DRV_LOG(ERR, out, "query NIC vport context", NULL, 0); 517 return MLX5_DEVX_ERR_RC(rc); 518 } 519 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 520 nic_vport_context); 521 if (attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) 522 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 523 min_wqe_inline_mode); 524 attr->system_image_guid = MLX5_GET64(nic_vport_context, vctx, 525 system_image_guid); 526 return 0; 527 } 528 529 /** 530 * Query NIC vDPA attributes. 531 * 532 * @param[in] ctx 533 * Context returned from mlx5 open_device() glue function. 534 * @param[out] vdpa_attr 535 * vDPA Attributes structure to fill. 536 */ 537 static void 538 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 539 struct mlx5_hca_vdpa_attr *vdpa_attr) 540 { 541 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 542 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 543 void *hcattr; 544 545 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, 546 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 547 MLX5_HCA_CAP_OPMOD_GET_CUR); 548 if (!hcattr) { 549 DRV_LOG(DEBUG, "Failed to query devx VDPA capabilities"); 550 vdpa_attr->valid = 0; 551 } else { 552 vdpa_attr->valid = 1; 553 vdpa_attr->desc_tunnel_offload_type = 554 MLX5_GET(virtio_emulation_cap, hcattr, 555 desc_tunnel_offload_type); 556 vdpa_attr->eth_frame_offload_type = 557 MLX5_GET(virtio_emulation_cap, hcattr, 558 eth_frame_offload_type); 559 vdpa_attr->virtio_version_1_0 = 560 MLX5_GET(virtio_emulation_cap, hcattr, 561 virtio_version_1_0); 562 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 563 tso_ipv4); 564 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 565 tso_ipv6); 566 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 567 tx_csum); 568 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 569 rx_csum); 570 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 571 event_mode); 572 vdpa_attr->virtio_queue_type = 573 MLX5_GET(virtio_emulation_cap, hcattr, 574 virtio_queue_type); 575 vdpa_attr->log_doorbell_stride = 576 MLX5_GET(virtio_emulation_cap, hcattr, 577 log_doorbell_stride); 578 vdpa_attr->vnet_modify_ext = 579 MLX5_GET(virtio_emulation_cap, hcattr, 580 vnet_modify_ext); 581 vdpa_attr->virtio_net_q_addr_modify = 582 MLX5_GET(virtio_emulation_cap, hcattr, 583 virtio_net_q_addr_modify); 584 vdpa_attr->virtio_q_index_modify = 585 MLX5_GET(virtio_emulation_cap, hcattr, 586 virtio_q_index_modify); 587 vdpa_attr->log_doorbell_bar_size = 588 MLX5_GET(virtio_emulation_cap, hcattr, 589 log_doorbell_bar_size); 590 vdpa_attr->doorbell_bar_offset = 591 MLX5_GET64(virtio_emulation_cap, hcattr, 592 doorbell_bar_offset); 593 vdpa_attr->max_num_virtio_queues = 594 MLX5_GET(virtio_emulation_cap, hcattr, 595 max_num_virtio_queues); 596 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 597 umem_1_buffer_param_a); 598 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 599 umem_1_buffer_param_b); 600 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 601 umem_2_buffer_param_a); 602 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 603 umem_2_buffer_param_b); 604 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 605 umem_3_buffer_param_a); 606 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 607 umem_3_buffer_param_b); 608 } 609 } 610 611 /** 612 * Query match sample handle parameters. 613 * 614 * This command allows translating a field sample handle returned by either 615 * PARSE_GRAPH_FLOW_MATCH_SAMPLE or by GENEVE TLV OPTION object into values 616 * used for header modification or header matching/hashing. 617 * 618 * @param[in] ctx 619 * Context used to create either GENEVE TLV option or FLEX PARSE GRAPH object. 620 * @param[in] sample_field_id 621 * Field sample handle returned by either PARSE_GRAPH_FLOW_MATCH_SAMPLE 622 * or by GENEVE TLV OPTION object. 623 * @param[out] attr 624 * Pointer to match sample info attributes structure. 625 * 626 * @return 627 * 0 on success, a negative errno otherwise and rte_errno is set. 628 */ 629 int 630 mlx5_devx_cmd_match_sample_info_query(void *ctx, uint32_t sample_field_id, 631 struct mlx5_devx_match_sample_info_query_attr *attr) 632 { 633 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 634 uint32_t out[MLX5_ST_SZ_DW(query_match_sample_info_out)] = {0}; 635 uint32_t in[MLX5_ST_SZ_DW(query_match_sample_info_in)] = {0}; 636 int rc; 637 638 MLX5_SET(query_match_sample_info_in, in, opcode, 639 MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO); 640 MLX5_SET(query_match_sample_info_in, in, op_mod, 0); 641 MLX5_SET(query_match_sample_info_in, in, sample_field_id, 642 sample_field_id); 643 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 644 if (rc || MLX5_FW_STATUS(out)) { 645 DEVX_DRV_LOG(ERR, out, "query match sample info", 646 "sample_field_id", sample_field_id); 647 return MLX5_DEVX_ERR_RC(rc); 648 } 649 attr->modify_field_id = MLX5_GET(query_match_sample_info_out, out, 650 modify_field_id); 651 attr->sample_dw_data = MLX5_GET(query_match_sample_info_out, out, 652 field_format_select_dw); 653 attr->sample_dw_ok_bit = MLX5_GET(query_match_sample_info_out, out, 654 ok_bit_format_select_dw); 655 attr->sample_dw_ok_bit_offset = MLX5_GET(query_match_sample_info_out, 656 out, ok_bit_offset); 657 return 0; 658 #else 659 (void)ctx; 660 (void)sample_field_id; 661 (void)attr; 662 return -ENOTSUP; 663 #endif 664 } 665 666 int 667 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 668 uint32_t *ids, 669 uint32_t num, uint8_t *anchor) 670 { 671 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 672 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 673 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 674 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 675 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 676 int ret; 677 uint32_t idx = 0; 678 uint32_t i; 679 680 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 681 rte_errno = EINVAL; 682 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 683 return -rte_errno; 684 } 685 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 686 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 687 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 688 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 689 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 690 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 691 out, sizeof(out)); 692 if (ret) { 693 rte_errno = ret; 694 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 695 (void *)flex_obj); 696 return -rte_errno; 697 } 698 if (anchor) 699 *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id); 700 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx < num; i++) { 701 void *s_off = (void *)((char *)sample + i * 702 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 703 uint32_t en; 704 705 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 706 flow_match_sample_en); 707 if (!en) 708 continue; 709 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 710 flow_match_sample_field_id); 711 } 712 if (num != idx) { 713 rte_errno = EINVAL; 714 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 715 return -rte_errno; 716 } 717 return ret; 718 } 719 720 struct mlx5_devx_obj * 721 mlx5_devx_cmd_create_flex_parser(void *ctx, 722 struct mlx5_devx_graph_node_attr *data) 723 { 724 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 725 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 726 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 727 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 728 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 729 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 730 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 731 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 732 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 733 uint32_t i; 734 735 if (!parse_flex_obj) { 736 DRV_LOG(ERR, "Failed to allocate flex parser data."); 737 rte_errno = ENOMEM; 738 return NULL; 739 } 740 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 741 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 742 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 743 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 744 MLX5_SET(parse_graph_flex, flex, header_length_mode, 745 data->header_length_mode); 746 MLX5_SET64(parse_graph_flex, flex, modify_field_select, 747 data->modify_field_select); 748 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 749 data->header_length_base_value); 750 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 751 data->header_length_field_offset); 752 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 753 data->header_length_field_shift); 754 MLX5_SET(parse_graph_flex, flex, next_header_field_offset, 755 data->next_header_field_offset); 756 MLX5_SET(parse_graph_flex, flex, next_header_field_size, 757 data->next_header_field_size); 758 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 759 data->header_length_field_mask); 760 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 761 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 762 void *s_off = (void *)((char *)sample + i * 763 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 764 765 if (!s->flow_match_sample_en) 766 continue; 767 MLX5_SET(parse_graph_flow_match_sample, s_off, 768 flow_match_sample_en, !!s->flow_match_sample_en); 769 MLX5_SET(parse_graph_flow_match_sample, s_off, 770 flow_match_sample_field_offset, 771 s->flow_match_sample_field_offset); 772 MLX5_SET(parse_graph_flow_match_sample, s_off, 773 flow_match_sample_offset_mode, 774 s->flow_match_sample_offset_mode); 775 MLX5_SET(parse_graph_flow_match_sample, s_off, 776 flow_match_sample_field_offset_mask, 777 s->flow_match_sample_field_offset_mask); 778 MLX5_SET(parse_graph_flow_match_sample, s_off, 779 flow_match_sample_field_offset_shift, 780 s->flow_match_sample_field_offset_shift); 781 MLX5_SET(parse_graph_flow_match_sample, s_off, 782 flow_match_sample_field_base_offset, 783 s->flow_match_sample_field_base_offset); 784 MLX5_SET(parse_graph_flow_match_sample, s_off, 785 flow_match_sample_tunnel_mode, 786 s->flow_match_sample_tunnel_mode); 787 } 788 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 789 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 790 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 791 void *in_off = (void *)((char *)in_arc + i * 792 MLX5_ST_SZ_BYTES(parse_graph_arc)); 793 void *out_off = (void *)((char *)out_arc + i * 794 MLX5_ST_SZ_BYTES(parse_graph_arc)); 795 796 if (ia->arc_parse_graph_node != 0) { 797 MLX5_SET(parse_graph_arc, in_off, 798 compare_condition_value, 799 ia->compare_condition_value); 800 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 801 ia->start_inner_tunnel); 802 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 803 ia->arc_parse_graph_node); 804 MLX5_SET(parse_graph_arc, in_off, 805 parse_graph_node_handle, 806 ia->parse_graph_node_handle); 807 } 808 if (oa->arc_parse_graph_node != 0) { 809 MLX5_SET(parse_graph_arc, out_off, 810 compare_condition_value, 811 oa->compare_condition_value); 812 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 813 oa->start_inner_tunnel); 814 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 815 oa->arc_parse_graph_node); 816 MLX5_SET(parse_graph_arc, out_off, 817 parse_graph_node_handle, 818 oa->parse_graph_node_handle); 819 } 820 } 821 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 822 out, sizeof(out)); 823 if (!parse_flex_obj->obj) { 824 DEVX_DRV_LOG(ERR, out, "create FLEX PARSE GRAPH", NULL, 0); 825 mlx5_free(parse_flex_obj); 826 return NULL; 827 } 828 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 829 return parse_flex_obj; 830 } 831 832 static int 833 mlx5_devx_cmd_query_hca_parse_graph_node_cap 834 (void *ctx, struct mlx5_hca_flex_attr *attr) 835 { 836 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 837 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 838 void *hcattr; 839 int rc; 840 841 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 842 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | 843 MLX5_HCA_CAP_OPMOD_GET_CUR); 844 if (!hcattr) 845 return rc; 846 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); 847 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); 848 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, 849 header_length_mode); 850 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, 851 sample_offset_mode); 852 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, 853 max_num_arc_in); 854 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, 855 max_num_arc_out); 856 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, 857 max_num_sample); 858 attr->parse_graph_anchor = MLX5_GET(parse_graph_node_cap, hcattr, parse_graph_anchor); 859 attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr, 860 sample_tunnel_inner2); 861 attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr, 862 zero_size_supported); 863 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, 864 sample_id_in_out); 865 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, 866 max_base_header_length); 867 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, 868 max_sample_base_offset); 869 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, 870 max_next_header_offset); 871 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, 872 header_length_mask_width); 873 /* Get the max supported samples from HCA CAP 2 */ 874 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 875 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 876 MLX5_HCA_CAP_OPMOD_GET_CUR); 877 if (!hcattr) 878 return rc; 879 attr->max_num_prog_sample = 880 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); 881 return 0; 882 } 883 884 static int 885 mlx5_devx_query_pkt_integrity_match(void *hcattr) 886 { 887 return MLX5_GET(flow_table_nic_cap, hcattr, 888 ft_field_support_2_nic_receive.inner_l3_ok) && 889 MLX5_GET(flow_table_nic_cap, hcattr, 890 ft_field_support_2_nic_receive.inner_l4_ok) && 891 MLX5_GET(flow_table_nic_cap, hcattr, 892 ft_field_support_2_nic_receive.outer_l3_ok) && 893 MLX5_GET(flow_table_nic_cap, hcattr, 894 ft_field_support_2_nic_receive.outer_l4_ok) && 895 MLX5_GET(flow_table_nic_cap, hcattr, 896 ft_field_support_2_nic_receive 897 .inner_ipv4_checksum_ok) && 898 MLX5_GET(flow_table_nic_cap, hcattr, 899 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 900 MLX5_GET(flow_table_nic_cap, hcattr, 901 ft_field_support_2_nic_receive 902 .outer_ipv4_checksum_ok) && 903 MLX5_GET(flow_table_nic_cap, hcattr, 904 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 905 } 906 907 /** 908 * Query HCA attributes. 909 * Using those attributes we can check on run time if the device 910 * is having the required capabilities. 911 * 912 * @param[in] ctx 913 * Context returned from mlx5 open_device() glue function. 914 * @param[out] attr 915 * Attributes device values. 916 * 917 * @return 918 * 0 on success, a negative value otherwise. 919 */ 920 int 921 mlx5_devx_cmd_query_hca_attr(void *ctx, 922 struct mlx5_hca_attr *attr) 923 { 924 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 925 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 926 bool hca_cap_2_sup; 927 uint64_t general_obj_types_supported = 0; 928 void *hcattr; 929 int rc, i; 930 931 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 932 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 933 MLX5_HCA_CAP_OPMOD_GET_CUR); 934 if (!hcattr) 935 return rc; 936 hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2); 937 attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq); 938 attr->flow_counter_bulk_alloc_bitmap = 939 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 940 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 941 flow_counters_dump); 942 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp); 943 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp); 944 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 945 log_max_rqt_size); 946 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 947 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 948 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 949 log_max_hairpin_queues); 950 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 951 log_max_hairpin_wq_data_sz); 952 attr->log_max_hairpin_num_packets = MLX5_GET 953 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 954 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 955 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 956 relaxed_ordering_write); 957 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 958 relaxed_ordering_read); 959 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 960 access_register_user); 961 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 962 eth_net_offloads); 963 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 964 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 965 flex_parser_protocols); 966 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 967 max_geneve_tlv_options); 968 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 969 max_geneve_tlv_option_data_len); 970 attr->geneve_tlv_option_offset = MLX5_GET(cmd_hca_cap, hcattr, 971 geneve_tlv_option_offset); 972 attr->geneve_tlv_sample = MLX5_GET(cmd_hca_cap, hcattr, 973 geneve_tlv_sample); 974 attr->query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr, 975 query_match_sample_info); 976 attr->geneve_tlv_option_sample_id = MLX5_GET(cmd_hca_cap, hcattr, 977 flex_parser_id_geneve_opt_0); 978 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 979 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 980 wqe_index_ignore_cap); 981 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 982 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 983 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 984 log_max_static_sq_wq); 985 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 986 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 987 device_frequency_khz); 988 attr->scatter_fcs_w_decap_disable = 989 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 990 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 991 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 992 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 993 attr->steering_format_version = 994 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 995 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 996 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 997 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 998 regexp_num_of_engines); 999 /* Read the general_obj_types bitmap and extract the relevant bits. */ 1000 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 1001 general_obj_types); 1002 attr->qos.flow_meter_aso_sup = 1003 !!(general_obj_types_supported & 1004 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 1005 attr->vdpa.valid = !!(general_obj_types_supported & 1006 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 1007 attr->vdpa.queue_counters_valid = 1008 !!(general_obj_types_supported & 1009 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 1010 attr->parse_graph_flex_node = 1011 !!(general_obj_types_supported & 1012 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 1013 attr->flow_hit_aso = !!(general_obj_types_supported & 1014 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 1015 attr->geneve_tlv_opt = !!(general_obj_types_supported & 1016 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 1017 attr->dek = !!(general_obj_types_supported & 1018 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 1019 attr->import_kek = !!(general_obj_types_supported & 1020 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 1021 attr->credential = !!(general_obj_types_supported & 1022 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 1023 attr->crypto_login = !!(general_obj_types_supported & 1024 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 1025 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 1026 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 1027 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 1028 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 1029 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 1030 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 1031 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 1032 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 1033 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 1034 attr->reg_c_preserve = 1035 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 1036 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 1037 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 1038 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 1039 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 1040 compress_mmo_sq); 1041 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 1042 decompress_mmo_sq); 1043 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 1044 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 1045 compress_mmo_qp); 1046 attr->decomp_deflate_v1_en = MLX5_GET(cmd_hca_cap, hcattr, 1047 decompress_deflate_v1); 1048 attr->decomp_deflate_v2_en = MLX5_GET(cmd_hca_cap, hcattr, 1049 decompress_deflate_v2); 1050 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 1051 compress_min_block_size); 1052 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 1053 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 1054 log_compress_mmo_size); 1055 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 1056 log_decompress_mmo_size); 1057 attr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr, 1058 decompress_lz4_data_only_v2); 1059 attr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, 1060 decompress_lz4_no_checksum_v2); 1061 attr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, 1062 decompress_lz4_checksum_v2); 1063 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 1064 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 1065 mini_cqe_resp_flow_tag); 1066 attr->cqe_compression_128 = MLX5_GET(cmd_hca_cap, hcattr, 1067 cqe_compression_128); 1068 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 1069 mini_cqe_resp_l3_l4_tag); 1070 attr->enhanced_cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, 1071 enhanced_cqe_compression); 1072 attr->umr_indirect_mkey_disabled = 1073 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 1074 attr->umr_modify_entity_size_disabled = 1075 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 1076 attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time); 1077 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 1078 attr->ct_offload = !!(general_obj_types_supported & 1079 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 1080 attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); 1081 attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table); 1082 attr->striding_rq = MLX5_GET(cmd_hca_cap, hcattr, striding_rq); 1083 attr->ext_stride_num_range = 1084 MLX5_GET(cmd_hca_cap, hcattr, ext_stride_num_range); 1085 attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table); 1086 attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr, 1087 max_flow_counter_15_0); 1088 attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr, 1089 max_flow_counter_31_16); 1090 attr->alloc_flow_counter_pd = MLX5_GET(cmd_hca_cap, hcattr, 1091 alloc_flow_counter_pd); 1092 attr->flow_counter_access_aso = MLX5_GET(cmd_hca_cap, hcattr, 1093 flow_counter_access_aso); 1094 attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr, 1095 flow_access_aso_opc_mod); 1096 attr->wqe_based_flow_table_sup = MLX5_GET(cmd_hca_cap, hcattr, 1097 wqe_based_flow_table_update_cap); 1098 /* 1099 * Flex item support needs max_num_prog_sample_field 1100 * from the Capabilities 2 table for PARSE_GRAPH_NODE 1101 */ 1102 if (attr->parse_graph_flex_node) { 1103 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap 1104 (ctx, &attr->flex); 1105 if (rc) 1106 return -1; 1107 attr->flex.query_match_sample_info = 1108 attr->query_match_sample_info; 1109 } 1110 if (attr->crypto) { 1111 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) || 1112 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_multi_block_be_tweak) || 1113 MLX5_GET(cmd_hca_cap, hcattr, aes_xts_single_block_le_tweak); 1114 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1115 MLX5_GET_HCA_CAP_OP_MOD_CRYPTO | 1116 MLX5_HCA_CAP_OPMOD_GET_CUR); 1117 if (!hcattr) 1118 return -1; 1119 attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps, 1120 hcattr, wrapped_import_method) 1121 & 1 << 2); 1122 attr->crypto_mmo.crypto_mmo_qp = MLX5_GET(crypto_caps, hcattr, crypto_mmo_qp); 1123 attr->crypto_mmo.gcm_256_encrypt = 1124 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_encrypt); 1125 attr->crypto_mmo.gcm_128_encrypt = 1126 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_encrypt); 1127 attr->crypto_mmo.gcm_256_decrypt = 1128 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_decrypt); 1129 attr->crypto_mmo.gcm_128_decrypt = 1130 MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_decrypt); 1131 attr->crypto_mmo.gcm_auth_tag_128 = 1132 MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_128); 1133 attr->crypto_mmo.gcm_auth_tag_96 = 1134 MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_96); 1135 attr->crypto_mmo.log_crypto_mmo_max_size = 1136 MLX5_GET(crypto_caps, hcattr, log_crypto_mmo_max_size); 1137 } 1138 if (hca_cap_2_sup) { 1139 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1140 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 1141 MLX5_HCA_CAP_OPMOD_GET_CUR); 1142 if (!hcattr) { 1143 DRV_LOG(DEBUG, 1144 "Failed to query DevX HCA capabilities 2."); 1145 return rc; 1146 } 1147 attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, 1148 log_min_stride_wqe_sz); 1149 attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr, 1150 hairpin_sq_wqe_bb_size); 1151 attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr, 1152 hairpin_sq_wq_in_host_mem); 1153 attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr, 1154 hairpin_data_buffer_locked); 1155 attr->flow_counter_bulk_log_max_alloc = MLX5_GET(cmd_hca_cap_2, 1156 hcattr, flow_counter_bulk_log_max_alloc); 1157 attr->flow_counter_bulk_log_granularity = 1158 MLX5_GET(cmd_hca_cap_2, hcattr, 1159 flow_counter_bulk_log_granularity); 1160 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1161 cross_vhca_object_to_object_supported); 1162 attr->cross_vhca = 1163 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR) && 1164 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT) && 1165 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT) && 1166 (rc & MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC); 1167 rc = MLX5_GET(cmd_hca_cap_2, hcattr, 1168 allowed_object_for_other_vhca_access); 1169 attr->cross_vhca = attr->cross_vhca && 1170 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR) && 1171 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_FT) && 1172 (rc & MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC); 1173 if (attr->ct_offload) 1174 attr->log_max_conn_track_offload = MLX5_GET(cmd_hca_cap_2, hcattr, 1175 log_max_conn_track_offload); 1176 } 1177 if (attr->log_min_stride_wqe_sz == 0) 1178 attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 1179 if (attr->qos.sup) { 1180 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1181 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 1182 MLX5_HCA_CAP_OPMOD_GET_CUR); 1183 if (!hcattr) { 1184 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); 1185 return rc; 1186 } 1187 attr->qos.flow_meter_old = 1188 MLX5_GET(qos_cap, hcattr, flow_meter_old); 1189 attr->qos.log_max_flow_meter = 1190 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 1191 attr->qos.flow_meter_reg_c_ids = 1192 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 1193 attr->qos.flow_meter = 1194 MLX5_GET(qos_cap, hcattr, flow_meter); 1195 attr->qos.packet_pacing = 1196 MLX5_GET(qos_cap, hcattr, packet_pacing); 1197 attr->qos.wqe_rate_pp = 1198 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 1199 if (attr->qos.flow_meter_aso_sup) { 1200 attr->qos.log_meter_aso_granularity = 1201 MLX5_GET(qos_cap, hcattr, 1202 log_meter_aso_granularity); 1203 attr->qos.log_meter_aso_max_alloc = 1204 MLX5_GET(qos_cap, hcattr, 1205 log_meter_aso_max_alloc); 1206 attr->qos.log_max_num_meter_aso = 1207 MLX5_GET(qos_cap, hcattr, 1208 log_max_num_meter_aso); 1209 } 1210 } 1211 if (attr->vdpa.valid) 1212 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 1213 if (!attr->eth_net_offloads) 1214 return 0; 1215 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 1216 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1217 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 1218 MLX5_HCA_CAP_OPMOD_GET_CUR); 1219 if (!hcattr) { 1220 attr->log_max_ft_sampler_num = 0; 1221 return rc; 1222 } 1223 attr->log_max_ft_sampler_num = MLX5_GET 1224 (flow_table_nic_cap, hcattr, 1225 flow_table_properties_nic_receive.log_max_ft_sampler_num); 1226 attr->flow.tunnel_header_0_1 = MLX5_GET 1227 (flow_table_nic_cap, hcattr, 1228 ft_field_support_2_nic_receive.tunnel_header_0_1); 1229 attr->flow.tunnel_header_2_3 = MLX5_GET 1230 (flow_table_nic_cap, hcattr, 1231 ft_field_support_2_nic_receive.tunnel_header_2_3); 1232 attr->modify_outer_ip_ecn = MLX5_GET 1233 (flow_table_nic_cap, hcattr, 1234 ft_header_modify_nic_receive.outer_ip_ecn); 1235 attr->modify_outer_ipv6_traffic_class = MLX5_GET 1236 (flow_table_nic_cap, hcattr, 1237 ft_header_modify_nic_receive.outer_ipv6_traffic_class); 1238 attr->set_reg_c = 0xffff; 1239 if (attr->nic_flow_table) { 1240 #define GET_RX_REG_X_BITS \ 1241 MLX5_GET(flow_table_nic_cap, hcattr, \ 1242 ft_header_modify_nic_receive.metadata_reg_c_x) 1243 #define GET_TX_REG_X_BITS \ 1244 MLX5_GET(flow_table_nic_cap, hcattr, \ 1245 ft_header_modify_nic_transmit.metadata_reg_c_x) 1246 1247 uint32_t tx_reg, rx_reg, reg_c_8_15; 1248 1249 tx_reg = GET_TX_REG_X_BITS; 1250 reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr, 1251 ft_field_support_2_nic_transmit.metadata_reg_c_8_15); 1252 tx_reg |= ((0xff & reg_c_8_15) << 8); 1253 rx_reg = GET_RX_REG_X_BITS; 1254 reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr, 1255 ft_field_support_2_nic_receive.metadata_reg_c_8_15); 1256 rx_reg |= ((0xff & reg_c_8_15) << 8); 1257 attr->set_reg_c &= (rx_reg & tx_reg); 1258 1259 #undef GET_RX_REG_X_BITS 1260 #undef GET_TX_REG_X_BITS 1261 } 1262 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 1263 attr->inner_ipv4_ihl = MLX5_GET 1264 (flow_table_nic_cap, hcattr, 1265 ft_field_support_2_nic_receive.inner_ipv4_ihl); 1266 attr->outer_ipv4_ihl = MLX5_GET 1267 (flow_table_nic_cap, hcattr, 1268 ft_field_support_2_nic_receive.outer_ipv4_ihl); 1269 attr->lag_rx_port_affinity = MLX5_GET 1270 (flow_table_nic_cap, hcattr, 1271 ft_field_support_2_nic_receive.lag_rx_port_affinity); 1272 /* Query HCA offloads for Ethernet protocol. */ 1273 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1274 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 1275 MLX5_HCA_CAP_OPMOD_GET_CUR); 1276 if (!hcattr) { 1277 attr->eth_net_offloads = 0; 1278 return rc; 1279 } 1280 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 1281 hcattr, wqe_vlan_insert); 1282 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 1283 hcattr, csum_cap); 1284 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 1285 hcattr, vlan_cap); 1286 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1287 lro_cap); 1288 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1289 hcattr, max_lso_cap); 1290 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1291 hcattr, scatter_fcs); 1292 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1293 hcattr, tunnel_lro_gre); 1294 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1295 hcattr, tunnel_lro_vxlan); 1296 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1297 hcattr, swp); 1298 attr->tunnel_stateless_gre = 1299 MLX5_GET(per_protocol_networking_offload_caps, 1300 hcattr, tunnel_stateless_gre); 1301 attr->tunnel_stateless_vxlan = 1302 MLX5_GET(per_protocol_networking_offload_caps, 1303 hcattr, tunnel_stateless_vxlan); 1304 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1305 hcattr, swp_csum); 1306 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1307 hcattr, swp_lso); 1308 attr->lro_max_msg_sz_mode = MLX5_GET 1309 (per_protocol_networking_offload_caps, 1310 hcattr, lro_max_msg_sz_mode); 1311 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1312 attr->lro_timer_supported_periods[i] = 1313 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1314 lro_timer_supported_periods[i]); 1315 } 1316 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1317 hcattr, lro_min_mss_size); 1318 attr->tunnel_stateless_geneve_rx = 1319 MLX5_GET(per_protocol_networking_offload_caps, 1320 hcattr, tunnel_stateless_geneve_rx); 1321 attr->geneve_max_opt_len = 1322 MLX5_GET(per_protocol_networking_offload_caps, 1323 hcattr, max_geneve_opt_len); 1324 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1325 hcattr, wqe_inline_mode); 1326 attr->tunnel_stateless_gtp = MLX5_GET 1327 (per_protocol_networking_offload_caps, 1328 hcattr, tunnel_stateless_gtp); 1329 attr->tunnel_stateless_vxlan_gpe_nsh = MLX5_GET 1330 (per_protocol_networking_offload_caps, 1331 hcattr, tunnel_stateless_vxlan_gpe_nsh); 1332 attr->rss_ind_tbl_cap = MLX5_GET 1333 (per_protocol_networking_offload_caps, 1334 hcattr, rss_ind_tbl_cap); 1335 attr->multi_pkt_send_wqe = MLX5_GET 1336 (per_protocol_networking_offload_caps, 1337 hcattr, multi_pkt_send_wqe); 1338 attr->enhanced_multi_pkt_send_wqe = MLX5_GET 1339 (per_protocol_networking_offload_caps, 1340 hcattr, enhanced_multi_pkt_send_wqe); 1341 if (attr->wqe_based_flow_table_sup) { 1342 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1343 MLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE | 1344 MLX5_HCA_CAP_OPMOD_GET_CUR); 1345 if (!hcattr) { 1346 DRV_LOG(DEBUG, "Failed to query WQE Based Flow table capabilities"); 1347 return rc; 1348 } 1349 attr->max_header_modify_pattern_length = MLX5_GET(wqe_based_flow_table_cap, 1350 hcattr, 1351 max_header_modify_pattern_length); 1352 } 1353 /* Query HCA attribute for ROCE. */ 1354 if (attr->roce) { 1355 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1356 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1357 MLX5_HCA_CAP_OPMOD_GET_CUR); 1358 if (!hcattr) { 1359 DRV_LOG(DEBUG, 1360 "Failed to query devx HCA ROCE capabilities"); 1361 return rc; 1362 } 1363 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1364 } 1365 if (attr->eth_virt) { 1366 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1367 if (rc) { 1368 attr->eth_virt = 0; 1369 goto error; 1370 } 1371 } 1372 if (attr->eswitch_manager) { 1373 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1374 MLX5_SET_HCA_CAP_OP_MOD_ESW | 1375 MLX5_HCA_CAP_OPMOD_GET_CUR); 1376 if (!hcattr) 1377 return rc; 1378 attr->esw_mgr_vport_id_valid = 1379 MLX5_GET(esw_cap, hcattr, 1380 esw_manager_vport_number_valid); 1381 attr->esw_mgr_vport_id = 1382 MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); 1383 } 1384 if (attr->eswitch_manager) { 1385 uint32_t esw_reg, reg_c_8_15; 1386 1387 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1388 MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE | 1389 MLX5_HCA_CAP_OPMOD_GET_CUR); 1390 if (!hcattr) 1391 return rc; 1392 esw_reg = MLX5_GET(flow_table_esw_cap, hcattr, 1393 ft_header_modify_esw_fdb.metadata_reg_c_x); 1394 reg_c_8_15 = MLX5_GET(flow_table_esw_cap, hcattr, 1395 ft_field_support_2_esw_fdb.metadata_reg_c_8_15); 1396 attr->set_reg_c &= ((0xff & reg_c_8_15) << 8) | esw_reg; 1397 } 1398 return 0; 1399 error: 1400 rc = (rc > 0) ? -rc : rc; 1401 return rc; 1402 } 1403 1404 /** 1405 * Query TIS transport domain from QP verbs object using DevX API. 1406 * 1407 * @param[in] qp 1408 * Pointer to verbs QP returned by ibv_create_qp . 1409 * @param[in] tis_num 1410 * TIS number of TIS to query. 1411 * @param[out] tis_td 1412 * Pointer to TIS transport domain variable, to be set by the routine. 1413 * 1414 * @return 1415 * 0 on success, a negative value otherwise. 1416 */ 1417 int 1418 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1419 uint32_t *tis_td) 1420 { 1421 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1422 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1423 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1424 int rc; 1425 void *tis_ctx; 1426 1427 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1428 MLX5_SET(query_tis_in, in, tisn, tis_num); 1429 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1430 if (rc) { 1431 DRV_LOG(ERR, "Failed to query QP using DevX"); 1432 return -rc; 1433 }; 1434 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1435 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1436 return 0; 1437 #else 1438 (void)qp; 1439 (void)tis_num; 1440 (void)tis_td; 1441 return -ENOTSUP; 1442 #endif 1443 } 1444 1445 /** 1446 * Fill WQ data for DevX API command. 1447 * Utility function for use when creating DevX objects containing a WQ. 1448 * 1449 * @param[in] wq_ctx 1450 * Pointer to WQ context to fill with data. 1451 * @param [in] wq_attr 1452 * Pointer to WQ attributes structure to fill in WQ context. 1453 */ 1454 static void 1455 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1456 { 1457 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1458 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1459 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1460 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1461 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1462 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1463 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1464 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1465 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1466 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1467 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1468 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1469 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1470 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1471 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1472 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1473 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1474 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1475 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1476 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1477 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1478 wq_attr->log_hairpin_num_packets); 1479 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1480 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1481 wq_attr->single_wqe_log_num_of_strides); 1482 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1483 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1484 wq_attr->single_stride_log_num_of_bytes); 1485 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1486 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1487 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1488 } 1489 1490 /** 1491 * Create RQ using DevX API. 1492 * 1493 * @param[in] ctx 1494 * Context returned from mlx5 open_device() glue function. 1495 * @param [in] rq_attr 1496 * Pointer to create RQ attributes structure. 1497 * @param [in] socket 1498 * CPU socket ID for allocations. 1499 * 1500 * @return 1501 * The DevX object created, NULL otherwise and rte_errno is set. 1502 */ 1503 struct mlx5_devx_obj * 1504 mlx5_devx_cmd_create_rq(void *ctx, 1505 struct mlx5_devx_create_rq_attr *rq_attr, 1506 int socket) 1507 { 1508 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1509 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1510 void *rq_ctx, *wq_ctx; 1511 struct mlx5_devx_wq_attr *wq_attr; 1512 struct mlx5_devx_obj *rq = NULL; 1513 1514 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1515 if (!rq) { 1516 DRV_LOG(ERR, "Failed to allocate RQ data"); 1517 rte_errno = ENOMEM; 1518 return NULL; 1519 } 1520 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1521 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1522 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1523 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1524 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1525 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1526 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1527 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1528 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1529 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1530 MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type); 1531 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1532 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1533 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1534 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1535 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1536 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1537 wq_attr = &rq_attr->wq_attr; 1538 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1539 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1540 out, sizeof(out)); 1541 if (!rq->obj) { 1542 DEVX_DRV_LOG(ERR, out, "create RQ", NULL, 0); 1543 mlx5_free(rq); 1544 return NULL; 1545 } 1546 rq->id = MLX5_GET(create_rq_out, out, rqn); 1547 return rq; 1548 } 1549 1550 /** 1551 * Modify RQ using DevX API. 1552 * 1553 * @param[in] rq 1554 * Pointer to RQ object structure. 1555 * @param [in] rq_attr 1556 * Pointer to modify RQ attributes structure. 1557 * 1558 * @return 1559 * 0 on success, a negative errno value otherwise and rte_errno is set. 1560 */ 1561 int 1562 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1563 struct mlx5_devx_modify_rq_attr *rq_attr) 1564 { 1565 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1566 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1567 void *rq_ctx, *wq_ctx; 1568 int ret; 1569 1570 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1571 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1572 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1573 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1574 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1575 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1576 if (rq_attr->modify_bitmask & 1577 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1578 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1579 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1580 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1581 if (rq_attr->modify_bitmask & 1582 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1583 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1584 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1585 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1586 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1587 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1588 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1589 } 1590 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1591 out, sizeof(out)); 1592 if (ret) { 1593 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1594 rte_errno = errno; 1595 return -errno; 1596 } 1597 return ret; 1598 } 1599 1600 /* 1601 * Query RQ using DevX API. 1602 * 1603 * @param[in] rq_obj 1604 * RQ Devx Object 1605 * @param[out] out 1606 * RQ Query Output 1607 * @param[in] outlen 1608 * RQ Query Output Length 1609 * 1610 * @return 1611 * 0 if Query successful, else non-zero return value from devx_obj_query API 1612 */ 1613 int 1614 mlx5_devx_cmd_query_rq(struct mlx5_devx_obj *rq_obj, void *out, size_t outlen) 1615 { 1616 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 1617 int rc; 1618 1619 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 1620 MLX5_SET(query_rq_in, in, rqn, rq_obj->id); 1621 rc = mlx5_glue->devx_obj_query(rq_obj->obj, in, sizeof(in), out, outlen); 1622 if (rc || MLX5_FW_STATUS(out)) { 1623 DEVX_DRV_LOG(ERR, out, "RQ query", "rq_id", rq_obj->id); 1624 return MLX5_DEVX_ERR_RC(rc); 1625 } 1626 return 0; 1627 } 1628 1629 /** 1630 * Create RMP using DevX API. 1631 * 1632 * @param[in] ctx 1633 * Context returned from mlx5 open_device() glue function. 1634 * @param [in] rmp_attr 1635 * Pointer to create RMP attributes structure. 1636 * @param [in] socket 1637 * CPU socket ID for allocations. 1638 * 1639 * @return 1640 * The DevX object created, NULL otherwise and rte_errno is set. 1641 */ 1642 struct mlx5_devx_obj * 1643 mlx5_devx_cmd_create_rmp(void *ctx, 1644 struct mlx5_devx_create_rmp_attr *rmp_attr, 1645 int socket) 1646 { 1647 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0}; 1648 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0}; 1649 void *rmp_ctx, *wq_ctx; 1650 struct mlx5_devx_wq_attr *wq_attr; 1651 struct mlx5_devx_obj *rmp = NULL; 1652 1653 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket); 1654 if (!rmp) { 1655 DRV_LOG(ERR, "Failed to allocate RMP data"); 1656 rte_errno = ENOMEM; 1657 return NULL; 1658 } 1659 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP); 1660 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx); 1661 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state); 1662 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe, 1663 rmp_attr->basic_cyclic_rcv_wqe); 1664 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq); 1665 wq_attr = &rmp_attr->wq_attr; 1666 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1667 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1668 sizeof(out)); 1669 if (!rmp->obj) { 1670 DEVX_DRV_LOG(ERR, out, "create RMP", NULL, 0); 1671 mlx5_free(rmp); 1672 return NULL; 1673 } 1674 rmp->id = MLX5_GET(create_rmp_out, out, rmpn); 1675 return rmp; 1676 } 1677 1678 /* 1679 * Create TIR using DevX API. 1680 * 1681 * @param[in] ctx 1682 * Context returned from mlx5 open_device() glue function. 1683 * @param [in] tir_attr 1684 * Pointer to TIR attributes structure. 1685 * 1686 * @return 1687 * The DevX object created, NULL otherwise and rte_errno is set. 1688 */ 1689 struct mlx5_devx_obj * 1690 mlx5_devx_cmd_create_tir(void *ctx, 1691 struct mlx5_devx_tir_attr *tir_attr) 1692 { 1693 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1694 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1695 void *tir_ctx, *outer, *inner, *rss_key; 1696 struct mlx5_devx_obj *tir = NULL; 1697 1698 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1699 if (!tir) { 1700 DRV_LOG(ERR, "Failed to allocate TIR data"); 1701 rte_errno = ENOMEM; 1702 return NULL; 1703 } 1704 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1705 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1706 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1707 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1708 tir_attr->lro_timeout_period_usecs); 1709 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1710 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1711 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1712 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1713 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1714 tir_attr->tunneled_offload_en); 1715 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1716 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1717 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1718 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1719 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1720 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1721 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1722 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1723 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1724 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1725 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1726 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1727 tir_attr->rx_hash_field_selector_outer.selected_fields); 1728 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1729 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1730 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1731 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1732 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1733 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1734 tir_attr->rx_hash_field_selector_inner.selected_fields); 1735 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1736 out, sizeof(out)); 1737 if (!tir->obj) { 1738 DEVX_DRV_LOG(ERR, out, "create TIR", NULL, 0); 1739 mlx5_free(tir); 1740 return NULL; 1741 } 1742 tir->id = MLX5_GET(create_tir_out, out, tirn); 1743 return tir; 1744 } 1745 1746 /** 1747 * Modify TIR using DevX API. 1748 * 1749 * @param[in] tir 1750 * Pointer to TIR DevX object structure. 1751 * @param [in] modify_tir_attr 1752 * Pointer to TIR modification attributes structure. 1753 * 1754 * @return 1755 * 0 on success, a negative errno value otherwise and rte_errno is set. 1756 */ 1757 int 1758 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1759 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1760 { 1761 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1762 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1763 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1764 void *tir_ctx; 1765 int ret; 1766 1767 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1768 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1769 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1770 modify_tir_attr->modify_bitmask); 1771 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1772 if (modify_tir_attr->modify_bitmask & 1773 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1774 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1775 tir_attr->lro_timeout_period_usecs); 1776 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1777 tir_attr->lro_enable_mask); 1778 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1779 tir_attr->lro_max_msg_sz); 1780 } 1781 if (modify_tir_attr->modify_bitmask & 1782 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1783 MLX5_SET(tirc, tir_ctx, indirect_table, 1784 tir_attr->indirect_table); 1785 if (modify_tir_attr->modify_bitmask & 1786 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1787 int i; 1788 void *outer, *inner; 1789 1790 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1791 tir_attr->rx_hash_symmetric); 1792 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1793 for (i = 0; i < 10; i++) { 1794 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1795 tir_attr->rx_hash_toeplitz_key[i]); 1796 } 1797 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1798 rx_hash_field_selector_outer); 1799 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1800 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1801 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1802 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1803 MLX5_SET 1804 (rx_hash_field_select, outer, selected_fields, 1805 tir_attr->rx_hash_field_selector_outer.selected_fields); 1806 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1807 rx_hash_field_selector_inner); 1808 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1809 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1810 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1811 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1812 MLX5_SET 1813 (rx_hash_field_select, inner, selected_fields, 1814 tir_attr->rx_hash_field_selector_inner.selected_fields); 1815 } 1816 if (modify_tir_attr->modify_bitmask & 1817 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1818 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1819 } 1820 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1821 out, sizeof(out)); 1822 if (ret) { 1823 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1824 rte_errno = errno; 1825 return -errno; 1826 } 1827 return ret; 1828 } 1829 1830 /** 1831 * Create RQT using DevX API. 1832 * 1833 * @param[in] ctx 1834 * Context returned from mlx5 open_device() glue function. 1835 * @param [in] rqt_attr 1836 * Pointer to RQT attributes structure. 1837 * 1838 * @return 1839 * The DevX object created, NULL otherwise and rte_errno is set. 1840 */ 1841 struct mlx5_devx_obj * 1842 mlx5_devx_cmd_create_rqt(void *ctx, 1843 struct mlx5_devx_rqt_attr *rqt_attr) 1844 { 1845 uint32_t *in = NULL; 1846 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1847 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1848 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1849 void *rqt_ctx; 1850 struct mlx5_devx_obj *rqt = NULL; 1851 unsigned int i; 1852 1853 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1854 if (!in) { 1855 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1856 rte_errno = ENOMEM; 1857 return NULL; 1858 } 1859 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1860 if (!rqt) { 1861 DRV_LOG(ERR, "Failed to allocate RQT data"); 1862 rte_errno = ENOMEM; 1863 mlx5_free(in); 1864 return NULL; 1865 } 1866 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1867 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1868 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1869 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1870 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1871 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1872 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1873 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1874 mlx5_free(in); 1875 if (!rqt->obj) { 1876 DEVX_DRV_LOG(ERR, out, "create RQT", NULL, 0); 1877 mlx5_free(rqt); 1878 return NULL; 1879 } 1880 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1881 return rqt; 1882 } 1883 1884 /** 1885 * Modify RQT using DevX API. 1886 * 1887 * @param[in] rqt 1888 * Pointer to RQT DevX object structure. 1889 * @param [in] rqt_attr 1890 * Pointer to RQT attributes structure. 1891 * 1892 * @return 1893 * 0 on success, a negative errno value otherwise and rte_errno is set. 1894 */ 1895 int 1896 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1897 struct mlx5_devx_rqt_attr *rqt_attr) 1898 { 1899 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1900 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1901 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1902 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1903 void *rqt_ctx; 1904 unsigned int i; 1905 int ret; 1906 1907 if (!in) { 1908 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1909 rte_errno = ENOMEM; 1910 return -ENOMEM; 1911 } 1912 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1913 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1914 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1915 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1916 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1917 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1918 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1919 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1920 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1921 mlx5_free(in); 1922 if (ret) { 1923 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1924 rte_errno = errno; 1925 return -rte_errno; 1926 } 1927 return ret; 1928 } 1929 1930 /** 1931 * Create SQ using DevX API. 1932 * 1933 * @param[in] ctx 1934 * Context returned from mlx5 open_device() glue function. 1935 * @param [in] sq_attr 1936 * Pointer to SQ attributes structure. 1937 * @param [in] socket 1938 * CPU socket ID for allocations. 1939 * 1940 * @return 1941 * The DevX object created, NULL otherwise and rte_errno is set. 1942 **/ 1943 struct mlx5_devx_obj * 1944 mlx5_devx_cmd_create_sq(void *ctx, 1945 struct mlx5_devx_create_sq_attr *sq_attr) 1946 { 1947 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1948 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1949 void *sq_ctx; 1950 void *wq_ctx; 1951 struct mlx5_devx_wq_attr *wq_attr; 1952 struct mlx5_devx_obj *sq = NULL; 1953 1954 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1955 if (!sq) { 1956 DRV_LOG(ERR, "Failed to allocate SQ data"); 1957 rte_errno = ENOMEM; 1958 return NULL; 1959 } 1960 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1961 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1962 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1963 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1964 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1965 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1966 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1967 sq_attr->allow_multi_pkt_send_wqe); 1968 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1969 sq_attr->min_wqe_inline_mode); 1970 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1971 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1972 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1973 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1974 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1975 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1976 MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type); 1977 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1978 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1979 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1980 sq_attr->packet_pacing_rate_limit_index); 1981 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1982 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1983 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1984 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1985 wq_attr = &sq_attr->wq_attr; 1986 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1987 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1988 out, sizeof(out)); 1989 if (!sq->obj) { 1990 DEVX_DRV_LOG(ERR, out, "create SQ", NULL, 0); 1991 mlx5_free(sq); 1992 return NULL; 1993 } 1994 sq->id = MLX5_GET(create_sq_out, out, sqn); 1995 return sq; 1996 } 1997 1998 /** 1999 * Modify SQ using DevX API. 2000 * 2001 * @param[in] sq 2002 * Pointer to SQ object structure. 2003 * @param [in] sq_attr 2004 * Pointer to SQ attributes structure. 2005 * 2006 * @return 2007 * 0 on success, a negative errno value otherwise and rte_errno is set. 2008 */ 2009 int 2010 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 2011 struct mlx5_devx_modify_sq_attr *sq_attr) 2012 { 2013 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 2014 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 2015 void *sq_ctx; 2016 int ret; 2017 2018 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 2019 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 2020 MLX5_SET(modify_sq_in, in, sqn, sq->id); 2021 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2022 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 2023 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 2024 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 2025 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 2026 out, sizeof(out)); 2027 if (ret) { 2028 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 2029 rte_errno = errno; 2030 return -rte_errno; 2031 } 2032 return ret; 2033 } 2034 2035 /* 2036 * Query SQ using DevX API. 2037 * 2038 * @param[in] sq_obj 2039 * SQ Devx Object 2040 * @param[out] out 2041 * SQ Query Output 2042 * @param[in] outlen 2043 * SQ Query Output Length 2044 * 2045 * @return 2046 * 0 if Query successful, else non-zero return value from devx_obj_query API 2047 */ 2048 int 2049 mlx5_devx_cmd_query_sq(struct mlx5_devx_obj *sq_obj, void *out, size_t outlen) 2050 { 2051 uint32_t in[MLX5_ST_SZ_DW(query_sq_in)] = {0}; 2052 int rc; 2053 2054 MLX5_SET(query_sq_in, in, opcode, MLX5_CMD_OP_QUERY_SQ); 2055 MLX5_SET(query_sq_in, in, sqn, sq_obj->id); 2056 rc = mlx5_glue->devx_obj_query(sq_obj->obj, in, sizeof(in), out, outlen); 2057 if (rc || MLX5_FW_STATUS(out)) { 2058 DEVX_DRV_LOG(ERR, out, "SQ query", "sq_id", sq_obj->id); 2059 return MLX5_DEVX_ERR_RC(rc); 2060 } 2061 return 0; 2062 } 2063 2064 /** 2065 * Create TIS using DevX API. 2066 * 2067 * @param[in] ctx 2068 * Context returned from mlx5 open_device() glue function. 2069 * @param [in] tis_attr 2070 * Pointer to TIS attributes structure. 2071 * 2072 * @return 2073 * The DevX object created, NULL otherwise and rte_errno is set. 2074 */ 2075 struct mlx5_devx_obj * 2076 mlx5_devx_cmd_create_tis(void *ctx, 2077 struct mlx5_devx_tis_attr *tis_attr) 2078 { 2079 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 2080 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 2081 struct mlx5_devx_obj *tis = NULL; 2082 void *tis_ctx; 2083 2084 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 2085 if (!tis) { 2086 DRV_LOG(ERR, "Failed to allocate TIS object"); 2087 rte_errno = ENOMEM; 2088 return NULL; 2089 } 2090 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 2091 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 2092 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 2093 tis_attr->strict_lag_tx_port_affinity); 2094 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 2095 tis_attr->lag_tx_port_affinity); 2096 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 2097 MLX5_SET(tisc, tis_ctx, transport_domain, 2098 tis_attr->transport_domain); 2099 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2100 out, sizeof(out)); 2101 if (!tis->obj) { 2102 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 2103 mlx5_free(tis); 2104 return NULL; 2105 } 2106 tis->id = MLX5_GET(create_tis_out, out, tisn); 2107 return tis; 2108 } 2109 2110 /** 2111 * Create transport domain using DevX API. 2112 * 2113 * @param[in] ctx 2114 * Context returned from mlx5 open_device() glue function. 2115 * @return 2116 * The DevX object created, NULL otherwise and rte_errno is set. 2117 */ 2118 struct mlx5_devx_obj * 2119 mlx5_devx_cmd_create_td(void *ctx) 2120 { 2121 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 2122 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 2123 struct mlx5_devx_obj *td = NULL; 2124 2125 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 2126 if (!td) { 2127 DRV_LOG(ERR, "Failed to allocate TD object"); 2128 rte_errno = ENOMEM; 2129 return NULL; 2130 } 2131 MLX5_SET(alloc_transport_domain_in, in, opcode, 2132 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 2133 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2134 out, sizeof(out)); 2135 if (!td->obj) { 2136 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 2137 mlx5_free(td); 2138 return NULL; 2139 } 2140 td->id = MLX5_GET(alloc_transport_domain_out, out, 2141 transport_domain); 2142 return td; 2143 } 2144 2145 /** 2146 * Dump all flows to file. 2147 * 2148 * @param[in] fdb_domain 2149 * FDB domain. 2150 * @param[in] rx_domain 2151 * RX domain. 2152 * @param[in] tx_domain 2153 * TX domain. 2154 * @param[out] file 2155 * Pointer to file stream. 2156 * 2157 * @return 2158 * 0 on success, a negative value otherwise. 2159 */ 2160 int 2161 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 2162 void *rx_domain __rte_unused, 2163 void *tx_domain __rte_unused, FILE *file __rte_unused) 2164 { 2165 int ret = 0; 2166 2167 #ifdef HAVE_MLX5_DR_FLOW_DUMP 2168 if (fdb_domain) { 2169 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 2170 if (ret) 2171 return ret; 2172 } 2173 MLX5_ASSERT(rx_domain); 2174 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 2175 if (ret) 2176 return ret; 2177 MLX5_ASSERT(tx_domain); 2178 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 2179 #else 2180 ret = ENOTSUP; 2181 #endif 2182 return -ret; 2183 } 2184 2185 int 2186 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 2187 FILE *file __rte_unused) 2188 { 2189 int ret = 0; 2190 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 2191 if (rule_info) 2192 ret = mlx5_glue->dr_dump_rule(file, rule_info); 2193 #else 2194 ret = ENOTSUP; 2195 #endif 2196 return -ret; 2197 } 2198 2199 /* 2200 * Create CQ using DevX API. 2201 * 2202 * @param[in] ctx 2203 * Context returned from mlx5 open_device() glue function. 2204 * @param [in] attr 2205 * Pointer to CQ attributes structure. 2206 * 2207 * @return 2208 * The DevX object created, NULL otherwise and rte_errno is set. 2209 */ 2210 struct mlx5_devx_obj * 2211 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 2212 { 2213 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 2214 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 2215 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2216 sizeof(*cq_obj), 2217 0, SOCKET_ID_ANY); 2218 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 2219 2220 if (!cq_obj) { 2221 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 2222 rte_errno = ENOMEM; 2223 return NULL; 2224 } 2225 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 2226 if (attr->db_umem_valid) { 2227 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 2228 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 2229 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 2230 } else { 2231 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 2232 } 2233 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 2234 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 2235 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 2236 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 2237 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 2238 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2239 MLX5_SET(cqc, cqctx, log_page_size, 2240 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2241 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 2242 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 2243 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 2244 MLX5_SET(cqc, cqctx, cqe_comp_layout, !!attr->cqe_comp_layout); 2245 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 2246 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 2247 attr->mini_cqe_res_format_ext); 2248 if (attr->q_umem_valid) { 2249 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 2250 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 2251 MLX5_SET64(create_cq_in, in, cq_umem_offset, 2252 attr->q_umem_offset); 2253 } 2254 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2255 sizeof(out)); 2256 if (!cq_obj->obj) { 2257 DEVX_DRV_LOG(ERR, out, "create CQ", NULL, 0); 2258 mlx5_free(cq_obj); 2259 return NULL; 2260 } 2261 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 2262 return cq_obj; 2263 } 2264 2265 /* 2266 * Query CQ using DevX API. 2267 * 2268 * @param[in] cq_obj 2269 * CQ Devx Object 2270 * @param[out] out 2271 * CQ Query Output 2272 * @param[in] outlen 2273 * CQ Query Output Length 2274 * 2275 * @return 2276 * 0 if Query successful, else non-zero return value from devx_obj_query API 2277 */ 2278 int 2279 mlx5_devx_cmd_query_cq(struct mlx5_devx_obj *cq_obj, void *out, size_t outlen) 2280 { 2281 uint32_t in[MLX5_ST_SZ_DW(query_cq_in)] = {0}; 2282 int rc; 2283 2284 MLX5_SET(query_cq_in, in, opcode, MLX5_CMD_OP_QUERY_CQ); 2285 MLX5_SET(query_cq_in, in, cqn, cq_obj->id); 2286 rc = mlx5_glue->devx_obj_query(cq_obj->obj, in, sizeof(in), out, outlen); 2287 if (rc || MLX5_FW_STATUS(out)) { 2288 DEVX_DRV_LOG(ERR, out, "CQ query", "cq_id", cq_obj->id); 2289 return MLX5_DEVX_ERR_RC(rc); 2290 } 2291 return 0; 2292 } 2293 2294 /** 2295 * Create VIRTQ using DevX API. 2296 * 2297 * @param[in] ctx 2298 * Context returned from mlx5 open_device() glue function. 2299 * @param [in] attr 2300 * Pointer to VIRTQ attributes structure. 2301 * 2302 * @return 2303 * The DevX object created, NULL otherwise and rte_errno is set. 2304 */ 2305 struct mlx5_devx_obj * 2306 mlx5_devx_cmd_create_virtq(void *ctx, 2307 struct mlx5_devx_virtq_attr *attr) 2308 { 2309 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2310 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2311 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2312 sizeof(*virtq_obj), 2313 0, SOCKET_ID_ANY); 2314 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2315 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2316 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2317 2318 if (!virtq_obj) { 2319 DRV_LOG(ERR, "Failed to allocate virtq data."); 2320 rte_errno = ENOMEM; 2321 return NULL; 2322 } 2323 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2324 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2325 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2326 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2327 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2328 attr->hw_available_index); 2329 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 2330 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2331 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2332 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2333 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2334 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2335 attr->virtio_version_1_0); 2336 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2337 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2338 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2339 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2340 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 2341 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2342 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 2343 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2344 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 2345 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 2346 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 2347 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 2348 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 2349 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 2350 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 2351 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 2352 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 2353 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 2354 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 2355 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 2356 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 2357 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 2358 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 2359 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2360 sizeof(out)); 2361 if (!virtq_obj->obj) { 2362 DEVX_DRV_LOG(ERR, out, "create VIRTQ", NULL, 0); 2363 mlx5_free(virtq_obj); 2364 return NULL; 2365 } 2366 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2367 return virtq_obj; 2368 } 2369 2370 /** 2371 * Modify VIRTQ using DevX API. 2372 * 2373 * @param[in] virtq_obj 2374 * Pointer to virtq object structure. 2375 * @param [in] attr 2376 * Pointer to modify virtq attributes structure. 2377 * 2378 * @return 2379 * 0 on success, a negative errno value otherwise and rte_errno is set. 2380 */ 2381 int 2382 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 2383 struct mlx5_devx_virtq_attr *attr) 2384 { 2385 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2386 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2387 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2388 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2389 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2390 int ret; 2391 2392 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2393 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 2394 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2395 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2396 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2397 MLX5_SET64(virtio_net_q, virtq, modify_field_select, 2398 attr->mod_fields_bitmap); 2399 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2400 if (!attr->mod_fields_bitmap) { 2401 DRV_LOG(ERR, "Failed to modify VIRTQ for no type set."); 2402 rte_errno = EINVAL; 2403 return -rte_errno; 2404 } 2405 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE) 2406 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 2407 if (attr->mod_fields_bitmap & 2408 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) { 2409 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 2410 attr->dirty_bitmap_mkey); 2411 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 2412 attr->dirty_bitmap_addr); 2413 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 2414 attr->dirty_bitmap_size); 2415 } 2416 if (attr->mod_fields_bitmap & 2417 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE) 2418 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 2419 attr->dirty_bitmap_dump_enable); 2420 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) { 2421 MLX5_SET(virtio_q, virtctx, queue_period_mode, 2422 attr->hw_latency_mode); 2423 MLX5_SET(virtio_q, virtctx, queue_period_us, 2424 attr->hw_max_latency_us); 2425 MLX5_SET(virtio_q, virtctx, queue_max_count, 2426 attr->hw_max_pending_comp); 2427 } 2428 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) { 2429 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2430 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2431 MLX5_SET64(virtio_q, virtctx, available_addr, 2432 attr->available_addr); 2433 } 2434 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX) 2435 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2436 attr->hw_available_index); 2437 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX) 2438 MLX5_SET16(virtio_net_q, virtq, hw_used_index, 2439 attr->hw_used_index); 2440 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE) 2441 MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type); 2442 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0) 2443 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2444 attr->virtio_version_1_0); 2445 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY) 2446 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2447 if (attr->mod_fields_bitmap & 2448 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) { 2449 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2450 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2451 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2452 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2453 } 2454 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) { 2455 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2456 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2457 } 2458 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 2459 out, sizeof(out)); 2460 if (ret) { 2461 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2462 rte_errno = errno; 2463 return -rte_errno; 2464 } 2465 return ret; 2466 } 2467 2468 /** 2469 * Query VIRTQ using DevX API. 2470 * 2471 * @param[in] virtq_obj 2472 * Pointer to virtq object structure. 2473 * @param [in/out] attr 2474 * Pointer to virtq attributes structure. 2475 * 2476 * @return 2477 * 0 on success, a negative errno value otherwise and rte_errno is set. 2478 */ 2479 int 2480 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 2481 struct mlx5_devx_virtq_attr *attr) 2482 { 2483 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2484 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 2485 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 2486 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 2487 int ret; 2488 2489 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2490 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2491 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2492 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2493 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2494 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2495 out, sizeof(out)); 2496 if (ret) { 2497 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2498 rte_errno = errno; 2499 return -errno; 2500 } 2501 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2502 hw_available_index); 2503 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2504 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2505 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2506 virtio_q_context.error_type); 2507 return ret; 2508 } 2509 2510 /** 2511 * Create QP using DevX API. 2512 * 2513 * @param[in] ctx 2514 * Context returned from mlx5 open_device() glue function. 2515 * @param [in] attr 2516 * Pointer to QP attributes structure. 2517 * 2518 * @return 2519 * The DevX object created, NULL otherwise and rte_errno is set. 2520 */ 2521 struct mlx5_devx_obj * 2522 mlx5_devx_cmd_create_qp(void *ctx, 2523 struct mlx5_devx_qp_attr *attr) 2524 { 2525 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2526 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2527 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2528 sizeof(*qp_obj), 2529 0, SOCKET_ID_ANY); 2530 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2531 2532 if (!qp_obj) { 2533 DRV_LOG(ERR, "Failed to allocate QP data."); 2534 rte_errno = ENOMEM; 2535 return NULL; 2536 } 2537 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2538 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2539 MLX5_SET(qpc, qpc, pd, attr->pd); 2540 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2541 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2542 if (attr->uar_index) { 2543 if (attr->mmo) { 2544 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2545 in, qpc_extension_and_pas_list); 2546 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2547 qpc_ext_and_pas_list, qpc_data_extension); 2548 2549 MLX5_SET(create_qp_in, in, qpc_ext, 1); 2550 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2551 } 2552 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2553 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2554 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2555 MLX5_SET(qpc, qpc, log_page_size, 2556 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2557 if (attr->num_of_send_wqbbs) { 2558 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs)); 2559 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2560 MLX5_SET(qpc, qpc, log_sq_size, 2561 rte_log2_u32(attr->num_of_send_wqbbs)); 2562 } else { 2563 MLX5_SET(qpc, qpc, no_sq, 1); 2564 } 2565 if (attr->num_of_receive_wqes) { 2566 MLX5_ASSERT(RTE_IS_POWER_OF_2( 2567 attr->num_of_receive_wqes)); 2568 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2569 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2570 MLX5_LOG_RQ_STRIDE_SHIFT); 2571 MLX5_SET(qpc, qpc, log_rq_size, 2572 rte_log2_u32(attr->num_of_receive_wqes)); 2573 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2574 } else { 2575 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2576 } 2577 if (attr->dbr_umem_valid) { 2578 MLX5_SET(qpc, qpc, dbr_umem_valid, 2579 attr->dbr_umem_valid); 2580 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2581 } 2582 if (attr->cd_master) 2583 MLX5_SET(qpc, qpc, cd_master, attr->cd_master); 2584 if (attr->cd_slave_send) 2585 MLX5_SET(qpc, qpc, cd_slave_send, attr->cd_slave_send); 2586 if (attr->cd_slave_recv) 2587 MLX5_SET(qpc, qpc, cd_slave_receive, attr->cd_slave_recv); 2588 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2589 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2590 attr->wq_umem_offset); 2591 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2592 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2593 } else { 2594 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2595 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2596 MLX5_SET(qpc, qpc, no_sq, 1); 2597 } 2598 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2599 sizeof(out)); 2600 if (!qp_obj->obj) { 2601 DEVX_DRV_LOG(ERR, out, "create QP", NULL, 0); 2602 mlx5_free(qp_obj); 2603 return NULL; 2604 } 2605 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2606 return qp_obj; 2607 } 2608 2609 /** 2610 * Modify QP using DevX API. 2611 * Currently supports only force loop-back QP. 2612 * 2613 * @param[in] qp 2614 * Pointer to QP object structure. 2615 * @param [in] qp_st_mod_op 2616 * The QP state modification operation. 2617 * @param [in] remote_qp_id 2618 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2619 * 2620 * @return 2621 * 0 on success, a negative errno value otherwise and rte_errno is set. 2622 */ 2623 int 2624 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2625 uint32_t remote_qp_id) 2626 { 2627 union { 2628 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2629 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2630 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2631 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)]; 2632 } in; 2633 union { 2634 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2635 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2636 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2637 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)]; 2638 } out; 2639 void *qpc; 2640 int ret; 2641 unsigned int inlen; 2642 unsigned int outlen; 2643 2644 memset(&in, 0, sizeof(in)); 2645 memset(&out, 0, sizeof(out)); 2646 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2647 switch (qp_st_mod_op) { 2648 case MLX5_CMD_OP_RST2INIT_QP: 2649 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2650 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2651 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2652 MLX5_SET(qpc, qpc, rre, 1); 2653 MLX5_SET(qpc, qpc, rwe, 1); 2654 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2655 inlen = sizeof(in.rst2init); 2656 outlen = sizeof(out.rst2init); 2657 break; 2658 case MLX5_CMD_OP_INIT2RTR_QP: 2659 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2660 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2661 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2662 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2663 MLX5_SET(qpc, qpc, mtu, 1); 2664 MLX5_SET(qpc, qpc, log_msg_max, 30); 2665 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2666 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2667 inlen = sizeof(in.init2rtr); 2668 outlen = sizeof(out.init2rtr); 2669 break; 2670 case MLX5_CMD_OP_RTR2RTS_QP: 2671 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2672 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2673 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16); 2674 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2675 MLX5_SET(qpc, qpc, retry_count, 7); 2676 MLX5_SET(qpc, qpc, rnr_retry, 7); 2677 inlen = sizeof(in.rtr2rts); 2678 outlen = sizeof(out.rtr2rts); 2679 break; 2680 case MLX5_CMD_OP_QP_2RST: 2681 MLX5_SET(2rst_qp_in, &in, qpn, qp->id); 2682 inlen = sizeof(in.qp2rst); 2683 outlen = sizeof(out.qp2rst); 2684 break; 2685 default: 2686 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2687 qp_st_mod_op); 2688 rte_errno = EINVAL; 2689 return -rte_errno; 2690 } 2691 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2692 if (ret) { 2693 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2694 rte_errno = errno; 2695 return -rte_errno; 2696 } 2697 return ret; 2698 } 2699 2700 struct mlx5_devx_obj * 2701 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2702 { 2703 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2704 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2705 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2706 sizeof(*couners_obj), 0, 2707 SOCKET_ID_ANY); 2708 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2709 2710 if (!couners_obj) { 2711 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2712 rte_errno = ENOMEM; 2713 return NULL; 2714 } 2715 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2716 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2717 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2718 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2719 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2720 sizeof(out)); 2721 if (!couners_obj->obj) { 2722 DEVX_DRV_LOG(ERR, out, "create virtio queue counters Obj", NULL, 2723 0); 2724 mlx5_free(couners_obj); 2725 return NULL; 2726 } 2727 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2728 return couners_obj; 2729 } 2730 2731 int 2732 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2733 struct mlx5_devx_virtio_q_couners_attr *attr) 2734 { 2735 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2736 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2737 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2738 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2739 virtio_q_counters); 2740 int ret; 2741 2742 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2743 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2744 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2745 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2746 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2747 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2748 sizeof(out)); 2749 if (ret) { 2750 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2751 rte_errno = errno; 2752 return -errno; 2753 } 2754 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2755 received_desc); 2756 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2757 completed_desc); 2758 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2759 error_cqes); 2760 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2761 bad_desc_errors); 2762 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2763 exceed_max_chain); 2764 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2765 invalid_buffer); 2766 return ret; 2767 } 2768 2769 /** 2770 * Create general object of type FLOW_HIT_ASO using DevX API. 2771 * 2772 * @param[in] ctx 2773 * Context returned from mlx5 open_device() glue function. 2774 * @param [in] pd 2775 * PD value to associate the FLOW_HIT_ASO object with. 2776 * 2777 * @return 2778 * The DevX object created, NULL otherwise and rte_errno is set. 2779 */ 2780 struct mlx5_devx_obj * 2781 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2782 { 2783 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2784 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2785 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2786 void *ptr = NULL; 2787 2788 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2789 0, SOCKET_ID_ANY); 2790 if (!flow_hit_aso_obj) { 2791 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2792 rte_errno = ENOMEM; 2793 return NULL; 2794 } 2795 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2796 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2797 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2798 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2799 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2800 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2801 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2802 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2803 out, sizeof(out)); 2804 if (!flow_hit_aso_obj->obj) { 2805 DEVX_DRV_LOG(ERR, out, "create FLOW_HIT_ASO", NULL, 0); 2806 mlx5_free(flow_hit_aso_obj); 2807 return NULL; 2808 } 2809 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2810 return flow_hit_aso_obj; 2811 } 2812 2813 /* 2814 * Create PD using DevX API. 2815 * 2816 * @param[in] ctx 2817 * Context returned from mlx5 open_device() glue function. 2818 * 2819 * @return 2820 * The DevX object created, NULL otherwise and rte_errno is set. 2821 */ 2822 struct mlx5_devx_obj * 2823 mlx5_devx_cmd_alloc_pd(void *ctx) 2824 { 2825 struct mlx5_devx_obj *ppd = 2826 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2827 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2828 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2829 2830 if (!ppd) { 2831 DRV_LOG(ERR, "Failed to allocate PD data."); 2832 rte_errno = ENOMEM; 2833 return NULL; 2834 } 2835 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2836 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2837 out, sizeof(out)); 2838 if (!ppd->obj) { 2839 mlx5_free(ppd); 2840 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2841 rte_errno = errno; 2842 return NULL; 2843 } 2844 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2845 return ppd; 2846 } 2847 2848 /** 2849 * Create general object of type FLOW_METER_ASO using DevX API. 2850 * 2851 * @param[in] ctx 2852 * Context returned from mlx5 open_device() glue function. 2853 * @param [in] pd 2854 * PD value to associate the FLOW_METER_ASO object with. 2855 * @param [in] log_obj_size 2856 * log_obj_size define to allocate number of 2 * meters 2857 * in one FLOW_METER_ASO object. 2858 * 2859 * @return 2860 * The DevX object created, NULL otherwise and rte_errno is set. 2861 */ 2862 struct mlx5_devx_obj * 2863 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2864 uint32_t log_obj_size) 2865 { 2866 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2867 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2868 struct mlx5_devx_obj *flow_meter_aso_obj; 2869 void *ptr; 2870 2871 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2872 sizeof(*flow_meter_aso_obj), 2873 0, SOCKET_ID_ANY); 2874 if (!flow_meter_aso_obj) { 2875 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2876 rte_errno = ENOMEM; 2877 return NULL; 2878 } 2879 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2880 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2881 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2882 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2883 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2884 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2885 log_obj_size); 2886 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2887 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2888 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2889 ctx, in, sizeof(in), 2890 out, sizeof(out)); 2891 if (!flow_meter_aso_obj->obj) { 2892 DEVX_DRV_LOG(ERR, out, "create FLOW_METTER_ASO", NULL, 0); 2893 mlx5_free(flow_meter_aso_obj); 2894 return NULL; 2895 } 2896 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2897 out, obj_id); 2898 return flow_meter_aso_obj; 2899 } 2900 2901 /* 2902 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2903 * 2904 * @param[in] ctx 2905 * Context returned from mlx5 open_device() glue function. 2906 * @param [in] pd 2907 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2908 * @param [in] log_obj_size 2909 * log_obj_size to allocate its power of 2 * objects 2910 * in one CONN_TRACK_OFFLOAD bulk allocation. 2911 * 2912 * @return 2913 * The DevX object created, NULL otherwise and rte_errno is set. 2914 */ 2915 struct mlx5_devx_obj * 2916 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2917 uint32_t log_obj_size) 2918 { 2919 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2920 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2921 struct mlx5_devx_obj *ct_aso_obj; 2922 void *ptr; 2923 2924 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2925 0, SOCKET_ID_ANY); 2926 if (!ct_aso_obj) { 2927 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2928 rte_errno = ENOMEM; 2929 return NULL; 2930 } 2931 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2932 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2933 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2934 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2935 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2936 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2937 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2938 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2939 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2940 out, sizeof(out)); 2941 if (!ct_aso_obj->obj) { 2942 DEVX_DRV_LOG(ERR, out, "create CONN_TRACK_OFFLOAD", NULL, 0); 2943 mlx5_free(ct_aso_obj); 2944 return NULL; 2945 } 2946 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2947 return ct_aso_obj; 2948 } 2949 2950 /** 2951 * Create general object of type GENEVE TLV option using DevX API. 2952 * 2953 * @param[in] ctx 2954 * Context returned from mlx5 open_device() glue function. 2955 * @param[in] attr 2956 * Pointer to GENEVE TLV option attributes structure. 2957 * 2958 * @return 2959 * The DevX object created, NULL otherwise and rte_errno is set. 2960 */ 2961 struct mlx5_devx_obj * 2962 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2963 struct mlx5_devx_geneve_tlv_option_attr *attr) 2964 { 2965 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2966 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2967 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2968 sizeof(*geneve_tlv_opt_obj), 2969 0, SOCKET_ID_ANY); 2970 2971 if (!geneve_tlv_opt_obj) { 2972 DRV_LOG(ERR, "Failed to allocate GENEVE TLV option object."); 2973 rte_errno = ENOMEM; 2974 return NULL; 2975 } 2976 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2977 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2978 geneve_tlv_opt); 2979 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2980 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2981 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2982 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2983 MLX5_SET(geneve_tlv_option, opt, option_type, attr->option_type); 2984 MLX5_SET(geneve_tlv_option, opt, option_data_length, 2985 attr->option_data_len); 2986 if (attr->option_class_ignore) 2987 MLX5_SET(geneve_tlv_option, opt, option_class_ignore, 2988 attr->option_class_ignore); 2989 else 2990 MLX5_SET(geneve_tlv_option, opt, option_class, 2991 rte_be_to_cpu_16(attr->option_class)); 2992 if (attr->offset_valid) { 2993 MLX5_SET(geneve_tlv_option, opt, sample_offset_valid, 2994 attr->offset_valid); 2995 MLX5_SET(geneve_tlv_option, opt, sample_offset, 2996 attr->sample_offset); 2997 } 2998 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2999 sizeof(in), out, 3000 sizeof(out)); 3001 if (!geneve_tlv_opt_obj->obj) { 3002 DEVX_DRV_LOG(ERR, out, "create GENEVE TLV option", NULL, 0); 3003 mlx5_free(geneve_tlv_opt_obj); 3004 return NULL; 3005 } 3006 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3007 return geneve_tlv_opt_obj; 3008 } 3009 3010 /** 3011 * Query GENEVE TLV option using DevX API. 3012 * 3013 * @param[in] ctx 3014 * Context used to create GENEVE TLV option object. 3015 * @param[in] geneve_tlv_opt_obj 3016 * DevX object of the GENEVE TLV option. 3017 * @param[out] attr 3018 * Pointer to match sample info attributes structure. 3019 * 3020 * @return 3021 * 0 on success, a negative errno otherwise and rte_errno is set. 3022 */ 3023 int 3024 mlx5_devx_cmd_query_geneve_tlv_option(void *ctx, 3025 struct mlx5_devx_obj *geneve_tlv_opt_obj, 3026 struct mlx5_devx_match_sample_info_query_attr *attr) 3027 { 3028 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 3029 uint32_t out[MLX5_ST_SZ_DW(query_geneve_tlv_option_out)] = {0}; 3030 void *hdr = MLX5_ADDR_OF(query_geneve_tlv_option_out, in, hdr); 3031 void *opt = MLX5_ADDR_OF(query_geneve_tlv_option_out, out, 3032 geneve_tlv_opt); 3033 int ret; 3034 3035 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 3036 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 3037 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 3038 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 3039 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, geneve_tlv_opt_obj->id); 3040 /* Call first query to get sample handle. */ 3041 ret = mlx5_glue->devx_obj_query(geneve_tlv_opt_obj->obj, in, sizeof(in), 3042 out, sizeof(out)); 3043 if (ret) { 3044 DRV_LOG(ERR, "Failed to query GENEVE TLV option using DevX."); 3045 rte_errno = errno; 3046 return -errno; 3047 } 3048 /* Call second query to get sample information. */ 3049 if (MLX5_GET(geneve_tlv_option, opt, sample_id_valid)) { 3050 uint32_t sample_id = MLX5_GET(geneve_tlv_option, opt, 3051 geneve_sample_field_id); 3052 3053 return mlx5_devx_cmd_match_sample_info_query(ctx, sample_id, 3054 attr); 3055 } 3056 DRV_LOG(DEBUG, "GENEVE TLV option sample isn't valid."); 3057 return 0; 3058 } 3059 3060 int 3061 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 3062 { 3063 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 3064 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 3065 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 3066 int rc; 3067 void *rq_ctx; 3068 3069 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 3070 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 3071 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 3072 if (rc) { 3073 rte_errno = errno; 3074 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 3075 "rc = %d, errno = %d.", rc, errno); 3076 return -rc; 3077 }; 3078 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 3079 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 3080 return 0; 3081 #else 3082 (void)wq; 3083 (void)counter_set_id; 3084 return -ENOTSUP; 3085 #endif 3086 } 3087 3088 /* 3089 * Allocate queue counters via devx interface. 3090 * 3091 * @param[in] ctx 3092 * Context returned from mlx5 open_device() glue function. 3093 * 3094 * @return 3095 * Pointer to counter object on success, a NULL value otherwise and 3096 * rte_errno is set. 3097 */ 3098 struct mlx5_devx_obj * 3099 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 3100 { 3101 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 3102 SOCKET_ID_ANY); 3103 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 3104 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 3105 3106 if (!dcs) { 3107 rte_errno = ENOMEM; 3108 return NULL; 3109 } 3110 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 3111 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 3112 sizeof(out)); 3113 if (!dcs->obj) { 3114 DEVX_DRV_LOG(DEBUG, out, "create q counter set", NULL, 0); 3115 mlx5_free(dcs); 3116 return NULL; 3117 } 3118 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 3119 return dcs; 3120 } 3121 3122 /** 3123 * Query queue counters values. 3124 * 3125 * @param[in] dcs 3126 * devx object of the queue counter set. 3127 * @param[in] clear 3128 * Whether hardware should clear the counters after the query or not. 3129 * @param[out] out_of_buffers 3130 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 3131 * 3132 * @return 3133 * 0 on success, a negative value otherwise. 3134 */ 3135 int 3136 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 3137 uint32_t *out_of_buffers) 3138 { 3139 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 3140 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 3141 int rc; 3142 3143 MLX5_SET(query_q_counter_in, in, opcode, 3144 MLX5_CMD_OP_QUERY_Q_COUNTER); 3145 MLX5_SET(query_q_counter_in, in, op_mod, 0); 3146 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 3147 MLX5_SET(query_q_counter_in, in, clear, !!clear); 3148 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 3149 sizeof(out)); 3150 if (rc) { 3151 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 3152 rte_errno = rc; 3153 return -rc; 3154 } 3155 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 3156 return 0; 3157 } 3158 3159 /** 3160 * Create general object of type DEK using DevX API. 3161 * 3162 * @param[in] ctx 3163 * Context returned from mlx5 open_device() glue function. 3164 * @param [in] attr 3165 * Pointer to DEK attributes structure. 3166 * 3167 * @return 3168 * The DevX object created, NULL otherwise and rte_errno is set. 3169 */ 3170 struct mlx5_devx_obj * 3171 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 3172 { 3173 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 3174 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3175 struct mlx5_devx_obj *dek_obj = NULL; 3176 void *ptr = NULL, *key_addr = NULL; 3177 3178 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 3179 0, SOCKET_ID_ANY); 3180 if (dek_obj == NULL) { 3181 DRV_LOG(ERR, "Failed to allocate DEK object data"); 3182 rte_errno = ENOMEM; 3183 return NULL; 3184 } 3185 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 3186 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3187 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3188 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3189 MLX5_GENERAL_OBJ_TYPE_DEK); 3190 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 3191 MLX5_SET(dek, ptr, key_size, attr->key_size); 3192 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 3193 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 3194 MLX5_SET(dek, ptr, pd, attr->pd); 3195 MLX5_SET64(dek, ptr, opaque, attr->opaque); 3196 key_addr = MLX5_ADDR_OF(dek, ptr, key); 3197 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 3198 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3199 out, sizeof(out)); 3200 if (dek_obj->obj == NULL) { 3201 DEVX_DRV_LOG(ERR, out, "create DEK", NULL, 0); 3202 mlx5_free(dek_obj); 3203 return NULL; 3204 } 3205 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3206 return dek_obj; 3207 } 3208 3209 /** 3210 * Create general object of type IMPORT_KEK using DevX API. 3211 * 3212 * @param[in] ctx 3213 * Context returned from mlx5 open_device() glue function. 3214 * @param [in] attr 3215 * Pointer to IMPORT_KEK attributes structure. 3216 * 3217 * @return 3218 * The DevX object created, NULL otherwise and rte_errno is set. 3219 */ 3220 struct mlx5_devx_obj * 3221 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 3222 struct mlx5_devx_import_kek_attr *attr) 3223 { 3224 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 3225 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3226 struct mlx5_devx_obj *import_kek_obj = NULL; 3227 void *ptr = NULL, *key_addr = NULL; 3228 3229 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 3230 0, SOCKET_ID_ANY); 3231 if (import_kek_obj == NULL) { 3232 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 3233 rte_errno = ENOMEM; 3234 return NULL; 3235 } 3236 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 3237 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3238 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3239 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3240 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 3241 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 3242 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 3243 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 3244 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 3245 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3246 out, sizeof(out)); 3247 if (import_kek_obj->obj == NULL) { 3248 DEVX_DRV_LOG(ERR, out, "create IMPORT_KEK", NULL, 0); 3249 mlx5_free(import_kek_obj); 3250 return NULL; 3251 } 3252 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3253 return import_kek_obj; 3254 } 3255 3256 /** 3257 * Create general object of type CREDENTIAL using DevX API. 3258 * 3259 * @param[in] ctx 3260 * Context returned from mlx5 open_device() glue function. 3261 * @param [in] attr 3262 * Pointer to CREDENTIAL attributes structure. 3263 * 3264 * @return 3265 * The DevX object created, NULL otherwise and rte_errno is set. 3266 */ 3267 struct mlx5_devx_obj * 3268 mlx5_devx_cmd_create_credential_obj(void *ctx, 3269 struct mlx5_devx_credential_attr *attr) 3270 { 3271 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 3272 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3273 struct mlx5_devx_obj *credential_obj = NULL; 3274 void *ptr = NULL, *credential_addr = NULL; 3275 3276 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 3277 0, SOCKET_ID_ANY); 3278 if (credential_obj == NULL) { 3279 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 3280 rte_errno = ENOMEM; 3281 return NULL; 3282 } 3283 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 3284 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3285 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3286 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3287 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 3288 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 3289 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 3290 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 3291 memcpy(credential_addr, (void *)(attr->credential), 3292 MLX5_CRYPTO_CREDENTIAL_SIZE); 3293 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3294 out, sizeof(out)); 3295 if (credential_obj->obj == NULL) { 3296 DEVX_DRV_LOG(ERR, out, "create CREDENTIAL", NULL, 0); 3297 mlx5_free(credential_obj); 3298 return NULL; 3299 } 3300 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3301 return credential_obj; 3302 } 3303 3304 /** 3305 * Create general object of type CRYPTO_LOGIN using DevX API. 3306 * 3307 * @param[in] ctx 3308 * Context returned from mlx5 open_device() glue function. 3309 * @param [in] attr 3310 * Pointer to CRYPTO_LOGIN attributes structure. 3311 * 3312 * @return 3313 * The DevX object created, NULL otherwise and rte_errno is set. 3314 */ 3315 struct mlx5_devx_obj * 3316 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 3317 struct mlx5_devx_crypto_login_attr *attr) 3318 { 3319 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 3320 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3321 struct mlx5_devx_obj *crypto_login_obj = NULL; 3322 void *ptr = NULL, *credential_addr = NULL; 3323 3324 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 3325 0, SOCKET_ID_ANY); 3326 if (crypto_login_obj == NULL) { 3327 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 3328 rte_errno = ENOMEM; 3329 return NULL; 3330 } 3331 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 3332 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3333 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3334 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3335 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 3336 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 3337 MLX5_SET(crypto_login, ptr, credential_pointer, 3338 attr->credential_pointer); 3339 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 3340 attr->session_import_kek_ptr); 3341 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 3342 memcpy(credential_addr, (void *)(attr->credential), 3343 MLX5_CRYPTO_CREDENTIAL_SIZE); 3344 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3345 out, sizeof(out)); 3346 if (crypto_login_obj->obj == NULL) { 3347 DEVX_DRV_LOG(ERR, out, "create CRYPTO_LOGIN", NULL, 0); 3348 mlx5_free(crypto_login_obj); 3349 return NULL; 3350 } 3351 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3352 return crypto_login_obj; 3353 } 3354 3355 /** 3356 * Query LAG context. 3357 * 3358 * @param[in] ctx 3359 * Pointer to ibv_context, returned from mlx5dv_open_device. 3360 * @param[out] lag_ctx 3361 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 3362 * 3363 * @return 3364 * 0 on success, a negative value otherwise. 3365 */ 3366 int 3367 mlx5_devx_cmd_query_lag(void *ctx, 3368 struct mlx5_devx_lag_context *lag_ctx) 3369 { 3370 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 3371 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 3372 void *lctx; 3373 int rc; 3374 3375 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 3376 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 3377 if (rc) 3378 goto error; 3379 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 3380 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 3381 fdb_selection_mode); 3382 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 3383 port_select_mode); 3384 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 3385 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 3386 tx_remap_affinity_2); 3387 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 3388 tx_remap_affinity_1); 3389 return 0; 3390 error: 3391 rc = (rc > 0) ? -rc : rc; 3392 return rc; 3393 } 3394