1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /* FW writes status value to the OUT buffer at offset 00H */ 17 #define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status) 18 /* FW writes syndrome value to the OUT buffer at offset 04H */ 19 #define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome) 20 21 #define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1)) 22 23 #define DEVX_DRV_LOG(level, out, reason, param, value) \ 24 do { \ 25 /* \ 26 * Some (old) GCC compilers like 7.5.0 and aarch64 GCC 7.1-2017.08 \ 27 * do not expand correctly when the macro invoked when the `param` \ 28 * is `NULL`. \ 29 * Use `local_param` to avoid direct `NULL` expansion. \ 30 */ \ 31 const char *local_param = (const char *)param; \ 32 \ 33 rte_errno = errno; \ 34 if (!local_param) { \ 35 DRV_LOG(level, \ 36 "DevX %s failed errno=%d status=%#x syndrome=%#x", \ 37 (reason), errno, MLX5_FW_STATUS((out)), \ 38 MLX5_FW_SYNDROME((out))); \ 39 } else { \ 40 DRV_LOG(level, \ 41 "DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x",\ 42 (reason), local_param, (value), errno, \ 43 MLX5_FW_STATUS((out)), MLX5_FW_SYNDROME((out))); \ 44 } \ 45 } while (0) 46 47 static void * 48 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, 49 int *err, uint32_t flags) 50 { 51 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); 52 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); 53 int rc; 54 55 memset(in, 0, size_in); 56 memset(out, 0, size_out); 57 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 58 MLX5_SET(query_hca_cap_in, in, op_mod, flags); 59 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); 60 if (rc || MLX5_FW_STATUS(out)) { 61 DEVX_DRV_LOG(ERR, out, "HCA capabilities", "func", flags >> 1); 62 if (err) 63 *err = MLX5_DEVX_ERR_RC(rc); 64 return NULL; 65 } 66 if (err) 67 *err = 0; 68 return MLX5_ADDR_OF(query_hca_cap_out, out, capability); 69 } 70 71 /** 72 * Perform read access to the registers. Reads data from register 73 * and writes ones to the specified buffer. 74 * 75 * @param[in] ctx 76 * Context returned from mlx5 open_device() glue function. 77 * @param[in] reg_id 78 * Register identifier according to the PRM. 79 * @param[in] arg 80 * Register access auxiliary parameter according to the PRM. 81 * @param[out] data 82 * Pointer to the buffer to store read data. 83 * @param[in] dw_cnt 84 * Buffer size in double words. 85 * 86 * @return 87 * 0 on success, a negative value otherwise. 88 */ 89 int 90 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 91 uint32_t *data, uint32_t dw_cnt) 92 { 93 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 94 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 95 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 96 int rc; 97 98 MLX5_ASSERT(data && dw_cnt); 99 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 100 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 101 DRV_LOG(ERR, "Not enough buffer for register read data"); 102 return -1; 103 } 104 MLX5_SET(access_register_in, in, opcode, 105 MLX5_CMD_OP_ACCESS_REGISTER_USER); 106 MLX5_SET(access_register_in, in, op_mod, 107 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 108 MLX5_SET(access_register_in, in, register_id, reg_id); 109 MLX5_SET(access_register_in, in, argument, arg); 110 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 111 MLX5_ST_SZ_BYTES(access_register_out) + 112 sizeof(uint32_t) * dw_cnt); 113 if (rc || MLX5_FW_STATUS(out)) { 114 DEVX_DRV_LOG(DEBUG, out, "read access", "NIC register", reg_id); 115 return MLX5_DEVX_ERR_RC(rc); 116 } 117 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 118 dw_cnt * sizeof(uint32_t)); 119 return 0; 120 } 121 122 /** 123 * Perform write access to the registers. 124 * 125 * @param[in] ctx 126 * Context returned from mlx5 open_device() glue function. 127 * @param[in] reg_id 128 * Register identifier according to the PRM. 129 * @param[in] arg 130 * Register access auxiliary parameter according to the PRM. 131 * @param[out] data 132 * Pointer to the buffer containing data to write. 133 * @param[in] dw_cnt 134 * Buffer size in double words (32bit units). 135 * 136 * @return 137 * 0 on success, a negative value otherwise. 138 */ 139 int 140 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 141 uint32_t *data, uint32_t dw_cnt) 142 { 143 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 144 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 145 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 146 int rc; 147 void *ptr; 148 149 MLX5_ASSERT(data && dw_cnt); 150 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 151 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 152 DRV_LOG(ERR, "Data to write exceeds max size"); 153 return -1; 154 } 155 MLX5_SET(access_register_in, in, opcode, 156 MLX5_CMD_OP_ACCESS_REGISTER_USER); 157 MLX5_SET(access_register_in, in, op_mod, 158 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 159 MLX5_SET(access_register_in, in, register_id, reg_id); 160 MLX5_SET(access_register_in, in, argument, arg); 161 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 162 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 163 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 164 if (rc || MLX5_FW_STATUS(out)) { 165 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 166 return MLX5_DEVX_ERR_RC(rc); 167 } 168 rc = mlx5_glue->devx_general_cmd(ctx, in, 169 MLX5_ST_SZ_BYTES(access_register_in) + 170 dw_cnt * sizeof(uint32_t), 171 out, sizeof(out)); 172 if (rc || MLX5_FW_STATUS(out)) { 173 DEVX_DRV_LOG(ERR, out, "write access", "NIC register", reg_id); 174 return MLX5_DEVX_ERR_RC(rc); 175 } 176 return 0; 177 } 178 179 struct mlx5_devx_obj * 180 mlx5_devx_cmd_flow_counter_alloc_general(void *ctx, 181 struct mlx5_devx_counter_attr *attr) 182 { 183 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 184 0, SOCKET_ID_ANY); 185 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 186 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 187 188 if (!dcs) { 189 rte_errno = ENOMEM; 190 return NULL; 191 } 192 MLX5_SET(alloc_flow_counter_in, in, opcode, 193 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 194 if (attr->bulk_log_max_alloc) 195 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk_log_size, 196 attr->flow_counter_bulk_log_size); 197 else 198 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, 199 attr->bulk_n_128); 200 if (attr->pd_valid) 201 MLX5_SET(alloc_flow_counter_in, in, pd, attr->pd); 202 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 203 sizeof(in), out, sizeof(out)); 204 if (!dcs->obj) { 205 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 206 rte_errno = errno; 207 mlx5_free(dcs); 208 return NULL; 209 } 210 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 211 return dcs; 212 } 213 214 /** 215 * Allocate flow counters via devx interface. 216 * 217 * @param[in] ctx 218 * Context returned from mlx5 open_device() glue function. 219 * @param dcs 220 * Pointer to counters properties structure to be filled by the routine. 221 * @param bulk_n_128 222 * Bulk counter numbers in 128 counters units. 223 * 224 * @return 225 * Pointer to counter object on success, a negative value otherwise and 226 * rte_errno is set. 227 */ 228 struct mlx5_devx_obj * 229 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 230 { 231 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 232 0, SOCKET_ID_ANY); 233 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 234 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 235 236 if (!dcs) { 237 rte_errno = ENOMEM; 238 return NULL; 239 } 240 MLX5_SET(alloc_flow_counter_in, in, opcode, 241 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 242 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 243 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 244 sizeof(in), out, sizeof(out)); 245 if (!dcs->obj) { 246 DEVX_DRV_LOG(ERR, out, "allocate counters", NULL, 0); 247 mlx5_free(dcs); 248 return NULL; 249 } 250 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 251 return dcs; 252 } 253 254 /** 255 * Query flow counters values. 256 * 257 * @param[in] dcs 258 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 259 * @param[in] clear 260 * Whether hardware should clear the counters after the query or not. 261 * @param[in] n_counters 262 * 0 in case of 1 counter to read, otherwise the counter number to read. 263 * @param pkts 264 * The number of packets that matched the flow. 265 * @param bytes 266 * The number of bytes that matched the flow. 267 * @param mkey 268 * The mkey key for batch query. 269 * @param addr 270 * The address in the mkey range for batch query. 271 * @param cmd_comp 272 * The completion object for asynchronous batch query. 273 * @param async_id 274 * The ID to be returned in the asynchronous batch query response. 275 * 276 * @return 277 * 0 on success, a negative value otherwise. 278 */ 279 int 280 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 281 int clear, uint32_t n_counters, 282 uint64_t *pkts, uint64_t *bytes, 283 uint32_t mkey, void *addr, 284 void *cmd_comp, 285 uint64_t async_id) 286 { 287 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 288 MLX5_ST_SZ_BYTES(traffic_counter); 289 uint32_t out[out_len]; 290 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 291 void *stats; 292 int rc; 293 294 MLX5_SET(query_flow_counter_in, in, opcode, 295 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 296 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 297 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 298 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 299 300 if (n_counters) { 301 MLX5_SET(query_flow_counter_in, in, num_of_counters, 302 n_counters); 303 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 304 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 305 MLX5_SET64(query_flow_counter_in, in, address, 306 (uint64_t)(uintptr_t)addr); 307 } 308 if (!cmd_comp) 309 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 310 out_len); 311 else 312 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 313 out_len, async_id, 314 cmd_comp); 315 if (rc) { 316 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 317 rte_errno = rc; 318 return -rc; 319 } 320 if (!n_counters) { 321 stats = MLX5_ADDR_OF(query_flow_counter_out, 322 out, flow_statistics); 323 *pkts = MLX5_GET64(traffic_counter, stats, packets); 324 *bytes = MLX5_GET64(traffic_counter, stats, octets); 325 } 326 return 0; 327 } 328 329 /** 330 * Create a new mkey. 331 * 332 * @param[in] ctx 333 * Context returned from mlx5 open_device() glue function. 334 * @param[in] attr 335 * Attributes of the requested mkey. 336 * 337 * @return 338 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 339 * is set. 340 */ 341 struct mlx5_devx_obj * 342 mlx5_devx_cmd_mkey_create(void *ctx, 343 struct mlx5_devx_mkey_attr *attr) 344 { 345 struct mlx5_klm *klm_array = attr->klm_array; 346 int klm_num = attr->klm_num; 347 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 348 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 349 uint32_t in[in_size_dw]; 350 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 351 void *mkc; 352 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 353 0, SOCKET_ID_ANY); 354 size_t pgsize; 355 uint32_t translation_size; 356 357 if (!mkey) { 358 rte_errno = ENOMEM; 359 return NULL; 360 } 361 memset(in, 0, in_size_dw * 4); 362 pgsize = rte_mem_page_size(); 363 if (pgsize == (size_t)-1) { 364 mlx5_free(mkey); 365 DRV_LOG(ERR, "Failed to get page size"); 366 rte_errno = ENOMEM; 367 return NULL; 368 } 369 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 370 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 371 if (klm_num > 0) { 372 int i; 373 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 374 klm_pas_mtt); 375 translation_size = RTE_ALIGN(klm_num, 4); 376 for (i = 0; i < klm_num; i++) { 377 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 378 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 379 MLX5_SET64(klm, klm, address, klm_array[i].address); 380 klm += MLX5_ST_SZ_BYTES(klm); 381 } 382 for (; i < (int)translation_size; i++) { 383 MLX5_SET(klm, klm, mkey, 0x0); 384 MLX5_SET64(klm, klm, address, 0x0); 385 klm += MLX5_ST_SZ_BYTES(klm); 386 } 387 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 388 MLX5_MKC_ACCESS_MODE_KLM_FBS : 389 MLX5_MKC_ACCESS_MODE_KLM); 390 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 391 } else { 392 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 393 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 394 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 395 } 396 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 397 translation_size); 398 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 399 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 400 MLX5_SET(mkc, mkc, lw, 0x1); 401 MLX5_SET(mkc, mkc, lr, 0x1); 402 if (attr->set_remote_rw) { 403 MLX5_SET(mkc, mkc, rw, 0x1); 404 MLX5_SET(mkc, mkc, rr, 0x1); 405 } 406 MLX5_SET(mkc, mkc, qpn, 0xffffff); 407 MLX5_SET(mkc, mkc, pd, attr->pd); 408 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 409 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 410 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 411 MLX5_SET(mkc, mkc, relaxed_ordering_write, 412 attr->relaxed_ordering_write); 413 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 414 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 415 MLX5_SET64(mkc, mkc, len, attr->size); 416 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 417 if (attr->crypto_en) { 418 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 419 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 420 } 421 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 422 sizeof(out)); 423 if (!mkey->obj) { 424 DEVX_DRV_LOG(ERR, out, klm_num ? "create indirect mkey" 425 : "create direct key", NULL, 0); 426 mlx5_free(mkey); 427 return NULL; 428 } 429 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 430 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 431 return mkey; 432 } 433 434 /** 435 * Get status of devx command response. 436 * Mainly used for asynchronous commands. 437 * 438 * @param[in] out 439 * The out response buffer. 440 * 441 * @return 442 * 0 on success, non-zero value otherwise. 443 */ 444 int 445 mlx5_devx_get_out_command_status(void *out) 446 { 447 int status; 448 449 if (!out) 450 return -EINVAL; 451 status = MLX5_GET(query_flow_counter_out, out, status); 452 if (status) { 453 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 454 455 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 456 syndrome); 457 } 458 return status; 459 } 460 461 /** 462 * Destroy any object allocated by a Devx API. 463 * 464 * @param[in] obj 465 * Pointer to a general object. 466 * 467 * @return 468 * 0 on success, a negative value otherwise. 469 */ 470 int 471 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 472 { 473 int ret; 474 475 if (!obj) 476 return 0; 477 ret = mlx5_glue->devx_obj_destroy(obj->obj); 478 mlx5_free(obj); 479 return ret; 480 } 481 482 /** 483 * Query NIC vport context. 484 * Fills minimal inline attribute. 485 * 486 * @param[in] ctx 487 * ibv contexts returned from mlx5dv_open_device. 488 * @param[in] vport 489 * vport index 490 * @param[out] attr 491 * Attributes device values. 492 * 493 * @return 494 * 0 on success, a negative value otherwise. 495 */ 496 static int 497 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 498 unsigned int vport, 499 struct mlx5_hca_attr *attr) 500 { 501 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 502 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 503 void *vctx; 504 int rc; 505 506 /* Query NIC vport context to determine inline mode. */ 507 MLX5_SET(query_nic_vport_context_in, in, opcode, 508 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 509 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 510 if (vport) 511 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 512 rc = mlx5_glue->devx_general_cmd(ctx, 513 in, sizeof(in), 514 out, sizeof(out)); 515 if (rc || MLX5_FW_STATUS(out)) { 516 DEVX_DRV_LOG(ERR, out, "query NIC vport context", NULL, 0); 517 return MLX5_DEVX_ERR_RC(rc); 518 } 519 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 520 nic_vport_context); 521 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 522 min_wqe_inline_mode); 523 return 0; 524 } 525 526 /** 527 * Query NIC vDPA attributes. 528 * 529 * @param[in] ctx 530 * Context returned from mlx5 open_device() glue function. 531 * @param[out] vdpa_attr 532 * vDPA Attributes structure to fill. 533 */ 534 static void 535 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 536 struct mlx5_hca_vdpa_attr *vdpa_attr) 537 { 538 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 539 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 540 void *hcattr; 541 542 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, 543 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 544 MLX5_HCA_CAP_OPMOD_GET_CUR); 545 if (!hcattr) { 546 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities"); 547 vdpa_attr->valid = 0; 548 } else { 549 vdpa_attr->valid = 1; 550 vdpa_attr->desc_tunnel_offload_type = 551 MLX5_GET(virtio_emulation_cap, hcattr, 552 desc_tunnel_offload_type); 553 vdpa_attr->eth_frame_offload_type = 554 MLX5_GET(virtio_emulation_cap, hcattr, 555 eth_frame_offload_type); 556 vdpa_attr->virtio_version_1_0 = 557 MLX5_GET(virtio_emulation_cap, hcattr, 558 virtio_version_1_0); 559 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 560 tso_ipv4); 561 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 562 tso_ipv6); 563 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 564 tx_csum); 565 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 566 rx_csum); 567 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 568 event_mode); 569 vdpa_attr->virtio_queue_type = 570 MLX5_GET(virtio_emulation_cap, hcattr, 571 virtio_queue_type); 572 vdpa_attr->log_doorbell_stride = 573 MLX5_GET(virtio_emulation_cap, hcattr, 574 log_doorbell_stride); 575 vdpa_attr->vnet_modify_ext = 576 MLX5_GET(virtio_emulation_cap, hcattr, 577 vnet_modify_ext); 578 vdpa_attr->virtio_net_q_addr_modify = 579 MLX5_GET(virtio_emulation_cap, hcattr, 580 virtio_net_q_addr_modify); 581 vdpa_attr->virtio_q_index_modify = 582 MLX5_GET(virtio_emulation_cap, hcattr, 583 virtio_q_index_modify); 584 vdpa_attr->log_doorbell_bar_size = 585 MLX5_GET(virtio_emulation_cap, hcattr, 586 log_doorbell_bar_size); 587 vdpa_attr->doorbell_bar_offset = 588 MLX5_GET64(virtio_emulation_cap, hcattr, 589 doorbell_bar_offset); 590 vdpa_attr->max_num_virtio_queues = 591 MLX5_GET(virtio_emulation_cap, hcattr, 592 max_num_virtio_queues); 593 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 594 umem_1_buffer_param_a); 595 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 596 umem_1_buffer_param_b); 597 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 598 umem_2_buffer_param_a); 599 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 600 umem_2_buffer_param_b); 601 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 602 umem_3_buffer_param_a); 603 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 604 umem_3_buffer_param_b); 605 } 606 } 607 608 int 609 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 610 uint32_t ids[], uint32_t num) 611 { 612 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 613 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 614 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 615 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 616 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 617 int ret; 618 uint32_t idx = 0; 619 uint32_t i; 620 621 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 622 rte_errno = EINVAL; 623 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 624 return -rte_errno; 625 } 626 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 627 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 628 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 629 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 630 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 631 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 632 out, sizeof(out)); 633 if (ret) { 634 rte_errno = ret; 635 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 636 (void *)flex_obj); 637 return -rte_errno; 638 } 639 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 640 void *s_off = (void *)((char *)sample + i * 641 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 642 uint32_t en; 643 644 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 645 flow_match_sample_en); 646 if (!en) 647 continue; 648 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 649 flow_match_sample_field_id); 650 } 651 if (num != idx) { 652 rte_errno = EINVAL; 653 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 654 return -rte_errno; 655 } 656 return ret; 657 } 658 659 struct mlx5_devx_obj * 660 mlx5_devx_cmd_create_flex_parser(void *ctx, 661 struct mlx5_devx_graph_node_attr *data) 662 { 663 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 664 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 665 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 666 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 667 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 668 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 669 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 670 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 671 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 672 uint32_t i; 673 674 if (!parse_flex_obj) { 675 DRV_LOG(ERR, "Failed to allocate flex parser data."); 676 rte_errno = ENOMEM; 677 return NULL; 678 } 679 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 680 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 681 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 682 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 683 MLX5_SET(parse_graph_flex, flex, header_length_mode, 684 data->header_length_mode); 685 MLX5_SET64(parse_graph_flex, flex, modify_field_select, 686 data->modify_field_select); 687 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 688 data->header_length_base_value); 689 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 690 data->header_length_field_offset); 691 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 692 data->header_length_field_shift); 693 MLX5_SET(parse_graph_flex, flex, next_header_field_offset, 694 data->next_header_field_offset); 695 MLX5_SET(parse_graph_flex, flex, next_header_field_size, 696 data->next_header_field_size); 697 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 698 data->header_length_field_mask); 699 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 700 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 701 void *s_off = (void *)((char *)sample + i * 702 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 703 704 if (!s->flow_match_sample_en) 705 continue; 706 MLX5_SET(parse_graph_flow_match_sample, s_off, 707 flow_match_sample_en, !!s->flow_match_sample_en); 708 MLX5_SET(parse_graph_flow_match_sample, s_off, 709 flow_match_sample_field_offset, 710 s->flow_match_sample_field_offset); 711 MLX5_SET(parse_graph_flow_match_sample, s_off, 712 flow_match_sample_offset_mode, 713 s->flow_match_sample_offset_mode); 714 MLX5_SET(parse_graph_flow_match_sample, s_off, 715 flow_match_sample_field_offset_mask, 716 s->flow_match_sample_field_offset_mask); 717 MLX5_SET(parse_graph_flow_match_sample, s_off, 718 flow_match_sample_field_offset_shift, 719 s->flow_match_sample_field_offset_shift); 720 MLX5_SET(parse_graph_flow_match_sample, s_off, 721 flow_match_sample_field_base_offset, 722 s->flow_match_sample_field_base_offset); 723 MLX5_SET(parse_graph_flow_match_sample, s_off, 724 flow_match_sample_tunnel_mode, 725 s->flow_match_sample_tunnel_mode); 726 } 727 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 728 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 729 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 730 void *in_off = (void *)((char *)in_arc + i * 731 MLX5_ST_SZ_BYTES(parse_graph_arc)); 732 void *out_off = (void *)((char *)out_arc + i * 733 MLX5_ST_SZ_BYTES(parse_graph_arc)); 734 735 if (ia->arc_parse_graph_node != 0) { 736 MLX5_SET(parse_graph_arc, in_off, 737 compare_condition_value, 738 ia->compare_condition_value); 739 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 740 ia->start_inner_tunnel); 741 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 742 ia->arc_parse_graph_node); 743 MLX5_SET(parse_graph_arc, in_off, 744 parse_graph_node_handle, 745 ia->parse_graph_node_handle); 746 } 747 if (oa->arc_parse_graph_node != 0) { 748 MLX5_SET(parse_graph_arc, out_off, 749 compare_condition_value, 750 oa->compare_condition_value); 751 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 752 oa->start_inner_tunnel); 753 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 754 oa->arc_parse_graph_node); 755 MLX5_SET(parse_graph_arc, out_off, 756 parse_graph_node_handle, 757 oa->parse_graph_node_handle); 758 } 759 } 760 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 761 out, sizeof(out)); 762 if (!parse_flex_obj->obj) { 763 DEVX_DRV_LOG(ERR, out, "create FLEX PARSE GRAPH", NULL, 0); 764 mlx5_free(parse_flex_obj); 765 return NULL; 766 } 767 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 768 return parse_flex_obj; 769 } 770 771 static int 772 mlx5_devx_cmd_query_hca_parse_graph_node_cap 773 (void *ctx, struct mlx5_hca_flex_attr *attr) 774 { 775 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 776 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 777 void *hcattr; 778 int rc; 779 780 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 781 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | 782 MLX5_HCA_CAP_OPMOD_GET_CUR); 783 if (!hcattr) 784 return rc; 785 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); 786 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); 787 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, 788 header_length_mode); 789 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, 790 sample_offset_mode); 791 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, 792 max_num_arc_in); 793 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, 794 max_num_arc_out); 795 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, 796 max_num_sample); 797 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, 798 sample_id_in_out); 799 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, 800 max_base_header_length); 801 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, 802 max_sample_base_offset); 803 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, 804 max_next_header_offset); 805 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, 806 header_length_mask_width); 807 /* Get the max supported samples from HCA CAP 2 */ 808 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 809 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 810 MLX5_HCA_CAP_OPMOD_GET_CUR); 811 if (!hcattr) 812 return rc; 813 attr->max_num_prog_sample = 814 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); 815 return 0; 816 } 817 818 static int 819 mlx5_devx_query_pkt_integrity_match(void *hcattr) 820 { 821 return MLX5_GET(flow_table_nic_cap, hcattr, 822 ft_field_support_2_nic_receive.inner_l3_ok) && 823 MLX5_GET(flow_table_nic_cap, hcattr, 824 ft_field_support_2_nic_receive.inner_l4_ok) && 825 MLX5_GET(flow_table_nic_cap, hcattr, 826 ft_field_support_2_nic_receive.outer_l3_ok) && 827 MLX5_GET(flow_table_nic_cap, hcattr, 828 ft_field_support_2_nic_receive.outer_l4_ok) && 829 MLX5_GET(flow_table_nic_cap, hcattr, 830 ft_field_support_2_nic_receive 831 .inner_ipv4_checksum_ok) && 832 MLX5_GET(flow_table_nic_cap, hcattr, 833 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 834 MLX5_GET(flow_table_nic_cap, hcattr, 835 ft_field_support_2_nic_receive 836 .outer_ipv4_checksum_ok) && 837 MLX5_GET(flow_table_nic_cap, hcattr, 838 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 839 } 840 841 /** 842 * Query HCA attributes. 843 * Using those attributes we can check on run time if the device 844 * is having the required capabilities. 845 * 846 * @param[in] ctx 847 * Context returned from mlx5 open_device() glue function. 848 * @param[out] attr 849 * Attributes device values. 850 * 851 * @return 852 * 0 on success, a negative value otherwise. 853 */ 854 int 855 mlx5_devx_cmd_query_hca_attr(void *ctx, 856 struct mlx5_hca_attr *attr) 857 { 858 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 859 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 860 bool hca_cap_2_sup; 861 uint64_t general_obj_types_supported = 0; 862 void *hcattr; 863 int rc, i; 864 865 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 866 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 867 MLX5_HCA_CAP_OPMOD_GET_CUR); 868 if (!hcattr) 869 return rc; 870 hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2); 871 attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq); 872 attr->flow_counter_bulk_alloc_bitmap = 873 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 874 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 875 flow_counters_dump); 876 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp); 877 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp); 878 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 879 log_max_rqt_size); 880 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 881 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 882 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 883 log_max_hairpin_queues); 884 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 885 log_max_hairpin_wq_data_sz); 886 attr->log_max_hairpin_num_packets = MLX5_GET 887 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 888 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 889 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 890 relaxed_ordering_write); 891 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 892 relaxed_ordering_read); 893 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 894 access_register_user); 895 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 896 eth_net_offloads); 897 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 898 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 899 flex_parser_protocols); 900 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 901 max_geneve_tlv_options); 902 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 903 max_geneve_tlv_option_data_len); 904 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 905 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 906 general_obj_types) & 907 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 908 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 909 general_obj_types) & 910 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 911 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 912 general_obj_types) & 913 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 914 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 915 general_obj_types) & 916 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 917 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 918 wqe_index_ignore_cap); 919 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 920 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 921 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 922 log_max_static_sq_wq); 923 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 924 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 925 device_frequency_khz); 926 attr->scatter_fcs_w_decap_disable = 927 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 928 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 929 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 930 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 931 attr->steering_format_version = 932 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 933 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 934 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 935 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 936 regexp_num_of_engines); 937 /* Read the general_obj_types bitmap and extract the relevant bits. */ 938 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 939 general_obj_types); 940 attr->vdpa.valid = !!(general_obj_types_supported & 941 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 942 attr->vdpa.queue_counters_valid = 943 !!(general_obj_types_supported & 944 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 945 attr->parse_graph_flex_node = 946 !!(general_obj_types_supported & 947 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 948 attr->flow_hit_aso = !!(general_obj_types_supported & 949 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 950 attr->geneve_tlv_opt = !!(general_obj_types_supported & 951 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 952 attr->dek = !!(general_obj_types_supported & 953 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 954 attr->import_kek = !!(general_obj_types_supported & 955 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 956 attr->credential = !!(general_obj_types_supported & 957 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 958 attr->crypto_login = !!(general_obj_types_supported & 959 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 960 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 961 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 962 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 963 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 964 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 965 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 966 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 967 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 968 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 969 attr->reg_c_preserve = 970 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 971 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 972 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 973 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 974 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 975 compress_mmo_sq); 976 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 977 decompress_mmo_sq); 978 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 979 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 980 compress_mmo_qp); 981 attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 982 decompress_mmo_qp); 983 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 984 compress_min_block_size); 985 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 986 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 987 log_compress_mmo_size); 988 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 989 log_decompress_mmo_size); 990 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 991 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 992 mini_cqe_resp_flow_tag); 993 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 994 mini_cqe_resp_l3_l4_tag); 995 attr->umr_indirect_mkey_disabled = 996 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 997 attr->umr_modify_entity_size_disabled = 998 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 999 attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time); 1000 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 1001 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 1002 general_obj_types) & 1003 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 1004 attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); 1005 attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr, 1006 max_flow_counter_15_0); 1007 attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr, 1008 max_flow_counter_31_16); 1009 attr->alloc_flow_counter_pd = MLX5_GET(cmd_hca_cap, hcattr, 1010 alloc_flow_counter_pd); 1011 attr->flow_counter_access_aso = MLX5_GET(cmd_hca_cap, hcattr, 1012 flow_counter_access_aso); 1013 attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr, 1014 flow_access_aso_opc_mod); 1015 if (attr->crypto) { 1016 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts); 1017 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1018 MLX5_GET_HCA_CAP_OP_MOD_CRYPTO | 1019 MLX5_HCA_CAP_OPMOD_GET_CUR); 1020 if (!hcattr) 1021 return -1; 1022 attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps, 1023 hcattr, wrapped_import_method) 1024 & 1 << 2); 1025 } 1026 if (hca_cap_2_sup) { 1027 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1028 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 1029 MLX5_HCA_CAP_OPMOD_GET_CUR); 1030 if (!hcattr) { 1031 DRV_LOG(DEBUG, 1032 "Failed to query DevX HCA capabilities 2."); 1033 return rc; 1034 } 1035 attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, 1036 log_min_stride_wqe_sz); 1037 attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr, 1038 hairpin_sq_wqe_bb_size); 1039 attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr, 1040 hairpin_sq_wq_in_host_mem); 1041 attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr, 1042 hairpin_data_buffer_locked); 1043 attr->flow_counter_bulk_log_max_alloc = MLX5_GET(cmd_hca_cap_2, 1044 hcattr, flow_counter_bulk_log_max_alloc); 1045 attr->flow_counter_bulk_log_granularity = 1046 MLX5_GET(cmd_hca_cap_2, hcattr, 1047 flow_counter_bulk_log_granularity); 1048 } 1049 if (attr->log_min_stride_wqe_sz == 0) 1050 attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 1051 if (attr->qos.sup) { 1052 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1053 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 1054 MLX5_HCA_CAP_OPMOD_GET_CUR); 1055 if (!hcattr) { 1056 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); 1057 return rc; 1058 } 1059 attr->qos.flow_meter_old = 1060 MLX5_GET(qos_cap, hcattr, flow_meter_old); 1061 attr->qos.log_max_flow_meter = 1062 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 1063 attr->qos.flow_meter_reg_c_ids = 1064 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 1065 attr->qos.flow_meter = 1066 MLX5_GET(qos_cap, hcattr, flow_meter); 1067 attr->qos.packet_pacing = 1068 MLX5_GET(qos_cap, hcattr, packet_pacing); 1069 attr->qos.wqe_rate_pp = 1070 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 1071 if (attr->qos.flow_meter_aso_sup) { 1072 attr->qos.log_meter_aso_granularity = 1073 MLX5_GET(qos_cap, hcattr, 1074 log_meter_aso_granularity); 1075 attr->qos.log_meter_aso_max_alloc = 1076 MLX5_GET(qos_cap, hcattr, 1077 log_meter_aso_max_alloc); 1078 attr->qos.log_max_num_meter_aso = 1079 MLX5_GET(qos_cap, hcattr, 1080 log_max_num_meter_aso); 1081 } 1082 } 1083 /* 1084 * Flex item support needs max_num_prog_sample_field 1085 * from the Capabilities 2 table for PARSE_GRAPH_NODE 1086 */ 1087 if (attr->parse_graph_flex_node) { 1088 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap 1089 (ctx, &attr->flex); 1090 if (rc) 1091 return -1; 1092 } 1093 if (attr->vdpa.valid) 1094 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 1095 if (!attr->eth_net_offloads) 1096 return 0; 1097 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 1098 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1099 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 1100 MLX5_HCA_CAP_OPMOD_GET_CUR); 1101 if (!hcattr) { 1102 attr->log_max_ft_sampler_num = 0; 1103 return rc; 1104 } 1105 attr->log_max_ft_sampler_num = MLX5_GET 1106 (flow_table_nic_cap, hcattr, 1107 flow_table_properties_nic_receive.log_max_ft_sampler_num); 1108 attr->flow.tunnel_header_0_1 = MLX5_GET 1109 (flow_table_nic_cap, hcattr, 1110 ft_field_support_2_nic_receive.tunnel_header_0_1); 1111 attr->flow.tunnel_header_2_3 = MLX5_GET 1112 (flow_table_nic_cap, hcattr, 1113 ft_field_support_2_nic_receive.tunnel_header_2_3); 1114 attr->modify_outer_ip_ecn = MLX5_GET 1115 (flow_table_nic_cap, hcattr, 1116 ft_header_modify_nic_receive.outer_ip_ecn); 1117 attr->set_reg_c = 0xff; 1118 if (attr->nic_flow_table) { 1119 #define GET_RX_REG_X_BITS \ 1120 MLX5_GET(flow_table_nic_cap, hcattr, \ 1121 ft_header_modify_nic_receive.metadata_reg_c_x) 1122 #define GET_TX_REG_X_BITS \ 1123 MLX5_GET(flow_table_nic_cap, hcattr, \ 1124 ft_header_modify_nic_transmit.metadata_reg_c_x) 1125 1126 uint32_t tx_reg, rx_reg; 1127 1128 tx_reg = GET_TX_REG_X_BITS; 1129 rx_reg = GET_RX_REG_X_BITS; 1130 attr->set_reg_c &= (rx_reg & tx_reg); 1131 1132 #undef GET_RX_REG_X_BITS 1133 #undef GET_TX_REG_X_BITS 1134 } 1135 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 1136 attr->inner_ipv4_ihl = MLX5_GET 1137 (flow_table_nic_cap, hcattr, 1138 ft_field_support_2_nic_receive.inner_ipv4_ihl); 1139 attr->outer_ipv4_ihl = MLX5_GET 1140 (flow_table_nic_cap, hcattr, 1141 ft_field_support_2_nic_receive.outer_ipv4_ihl); 1142 /* Query HCA offloads for Ethernet protocol. */ 1143 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1144 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 1145 MLX5_HCA_CAP_OPMOD_GET_CUR); 1146 if (!hcattr) { 1147 attr->eth_net_offloads = 0; 1148 return rc; 1149 } 1150 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 1151 hcattr, wqe_vlan_insert); 1152 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 1153 hcattr, csum_cap); 1154 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 1155 hcattr, vlan_cap); 1156 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1157 lro_cap); 1158 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1159 hcattr, max_lso_cap); 1160 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1161 hcattr, scatter_fcs); 1162 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1163 hcattr, tunnel_lro_gre); 1164 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1165 hcattr, tunnel_lro_vxlan); 1166 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1167 hcattr, swp); 1168 attr->tunnel_stateless_gre = 1169 MLX5_GET(per_protocol_networking_offload_caps, 1170 hcattr, tunnel_stateless_gre); 1171 attr->tunnel_stateless_vxlan = 1172 MLX5_GET(per_protocol_networking_offload_caps, 1173 hcattr, tunnel_stateless_vxlan); 1174 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1175 hcattr, swp_csum); 1176 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1177 hcattr, swp_lso); 1178 attr->lro_max_msg_sz_mode = MLX5_GET 1179 (per_protocol_networking_offload_caps, 1180 hcattr, lro_max_msg_sz_mode); 1181 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1182 attr->lro_timer_supported_periods[i] = 1183 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1184 lro_timer_supported_periods[i]); 1185 } 1186 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1187 hcattr, lro_min_mss_size); 1188 attr->tunnel_stateless_geneve_rx = 1189 MLX5_GET(per_protocol_networking_offload_caps, 1190 hcattr, tunnel_stateless_geneve_rx); 1191 attr->geneve_max_opt_len = 1192 MLX5_GET(per_protocol_networking_offload_caps, 1193 hcattr, max_geneve_opt_len); 1194 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1195 hcattr, wqe_inline_mode); 1196 attr->tunnel_stateless_gtp = MLX5_GET 1197 (per_protocol_networking_offload_caps, 1198 hcattr, tunnel_stateless_gtp); 1199 attr->rss_ind_tbl_cap = MLX5_GET 1200 (per_protocol_networking_offload_caps, 1201 hcattr, rss_ind_tbl_cap); 1202 /* Query HCA attribute for ROCE. */ 1203 if (attr->roce) { 1204 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1205 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1206 MLX5_HCA_CAP_OPMOD_GET_CUR); 1207 if (!hcattr) { 1208 DRV_LOG(DEBUG, 1209 "Failed to query devx HCA ROCE capabilities"); 1210 return rc; 1211 } 1212 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1213 } 1214 if (attr->eth_virt && 1215 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1216 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1217 if (rc) { 1218 attr->eth_virt = 0; 1219 goto error; 1220 } 1221 } 1222 if (attr->eswitch_manager) { 1223 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1224 MLX5_SET_HCA_CAP_OP_MOD_ESW | 1225 MLX5_HCA_CAP_OPMOD_GET_CUR); 1226 if (!hcattr) 1227 return rc; 1228 attr->esw_mgr_vport_id_valid = 1229 MLX5_GET(esw_cap, hcattr, 1230 esw_manager_vport_number_valid); 1231 attr->esw_mgr_vport_id = 1232 MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); 1233 } 1234 if (attr->eswitch_manager) { 1235 uint32_t esw_reg; 1236 1237 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1238 MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE | 1239 MLX5_HCA_CAP_OPMOD_GET_CUR); 1240 if (!hcattr) 1241 return rc; 1242 esw_reg = MLX5_GET(flow_table_esw_cap, hcattr, 1243 ft_header_modify_esw_fdb.metadata_reg_c_x); 1244 attr->set_reg_c &= esw_reg; 1245 } 1246 return 0; 1247 error: 1248 rc = (rc > 0) ? -rc : rc; 1249 return rc; 1250 } 1251 1252 /** 1253 * Query TIS transport domain from QP verbs object using DevX API. 1254 * 1255 * @param[in] qp 1256 * Pointer to verbs QP returned by ibv_create_qp . 1257 * @param[in] tis_num 1258 * TIS number of TIS to query. 1259 * @param[out] tis_td 1260 * Pointer to TIS transport domain variable, to be set by the routine. 1261 * 1262 * @return 1263 * 0 on success, a negative value otherwise. 1264 */ 1265 int 1266 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1267 uint32_t *tis_td) 1268 { 1269 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1270 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1271 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1272 int rc; 1273 void *tis_ctx; 1274 1275 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1276 MLX5_SET(query_tis_in, in, tisn, tis_num); 1277 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1278 if (rc) { 1279 DRV_LOG(ERR, "Failed to query QP using DevX"); 1280 return -rc; 1281 }; 1282 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1283 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1284 return 0; 1285 #else 1286 (void)qp; 1287 (void)tis_num; 1288 (void)tis_td; 1289 return -ENOTSUP; 1290 #endif 1291 } 1292 1293 /** 1294 * Fill WQ data for DevX API command. 1295 * Utility function for use when creating DevX objects containing a WQ. 1296 * 1297 * @param[in] wq_ctx 1298 * Pointer to WQ context to fill with data. 1299 * @param [in] wq_attr 1300 * Pointer to WQ attributes structure to fill in WQ context. 1301 */ 1302 static void 1303 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1304 { 1305 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1306 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1307 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1308 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1309 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1310 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1311 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1312 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1313 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1314 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1315 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1316 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1317 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1318 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1319 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1320 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1321 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1322 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1323 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1324 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1325 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1326 wq_attr->log_hairpin_num_packets); 1327 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1328 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1329 wq_attr->single_wqe_log_num_of_strides); 1330 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1331 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1332 wq_attr->single_stride_log_num_of_bytes); 1333 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1334 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1335 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1336 } 1337 1338 /** 1339 * Create RQ using DevX API. 1340 * 1341 * @param[in] ctx 1342 * Context returned from mlx5 open_device() glue function. 1343 * @param [in] rq_attr 1344 * Pointer to create RQ attributes structure. 1345 * @param [in] socket 1346 * CPU socket ID for allocations. 1347 * 1348 * @return 1349 * The DevX object created, NULL otherwise and rte_errno is set. 1350 */ 1351 struct mlx5_devx_obj * 1352 mlx5_devx_cmd_create_rq(void *ctx, 1353 struct mlx5_devx_create_rq_attr *rq_attr, 1354 int socket) 1355 { 1356 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1357 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1358 void *rq_ctx, *wq_ctx; 1359 struct mlx5_devx_wq_attr *wq_attr; 1360 struct mlx5_devx_obj *rq = NULL; 1361 1362 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1363 if (!rq) { 1364 DRV_LOG(ERR, "Failed to allocate RQ data"); 1365 rte_errno = ENOMEM; 1366 return NULL; 1367 } 1368 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1369 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1370 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1371 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1372 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1373 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1374 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1375 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1376 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1377 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1378 MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type); 1379 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1380 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1381 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1382 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1383 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1384 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1385 wq_attr = &rq_attr->wq_attr; 1386 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1387 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1388 out, sizeof(out)); 1389 if (!rq->obj) { 1390 DEVX_DRV_LOG(ERR, out, "create RQ", NULL, 0); 1391 mlx5_free(rq); 1392 return NULL; 1393 } 1394 rq->id = MLX5_GET(create_rq_out, out, rqn); 1395 return rq; 1396 } 1397 1398 /** 1399 * Modify RQ using DevX API. 1400 * 1401 * @param[in] rq 1402 * Pointer to RQ object structure. 1403 * @param [in] rq_attr 1404 * Pointer to modify RQ attributes structure. 1405 * 1406 * @return 1407 * 0 on success, a negative errno value otherwise and rte_errno is set. 1408 */ 1409 int 1410 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1411 struct mlx5_devx_modify_rq_attr *rq_attr) 1412 { 1413 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1414 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1415 void *rq_ctx, *wq_ctx; 1416 int ret; 1417 1418 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1419 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1420 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1421 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1422 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1423 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1424 if (rq_attr->modify_bitmask & 1425 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1426 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1427 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1428 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1429 if (rq_attr->modify_bitmask & 1430 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1431 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1432 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1433 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1434 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1435 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1436 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1437 } 1438 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1439 out, sizeof(out)); 1440 if (ret) { 1441 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1442 rte_errno = errno; 1443 return -errno; 1444 } 1445 return ret; 1446 } 1447 1448 /** 1449 * Create RMP using DevX API. 1450 * 1451 * @param[in] ctx 1452 * Context returned from mlx5 open_device() glue function. 1453 * @param [in] rmp_attr 1454 * Pointer to create RMP attributes structure. 1455 * @param [in] socket 1456 * CPU socket ID for allocations. 1457 * 1458 * @return 1459 * The DevX object created, NULL otherwise and rte_errno is set. 1460 */ 1461 struct mlx5_devx_obj * 1462 mlx5_devx_cmd_create_rmp(void *ctx, 1463 struct mlx5_devx_create_rmp_attr *rmp_attr, 1464 int socket) 1465 { 1466 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0}; 1467 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0}; 1468 void *rmp_ctx, *wq_ctx; 1469 struct mlx5_devx_wq_attr *wq_attr; 1470 struct mlx5_devx_obj *rmp = NULL; 1471 1472 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket); 1473 if (!rmp) { 1474 DRV_LOG(ERR, "Failed to allocate RMP data"); 1475 rte_errno = ENOMEM; 1476 return NULL; 1477 } 1478 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP); 1479 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx); 1480 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state); 1481 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe, 1482 rmp_attr->basic_cyclic_rcv_wqe); 1483 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq); 1484 wq_attr = &rmp_attr->wq_attr; 1485 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1486 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1487 sizeof(out)); 1488 if (!rmp->obj) { 1489 DEVX_DRV_LOG(ERR, out, "create RMP", NULL, 0); 1490 mlx5_free(rmp); 1491 return NULL; 1492 } 1493 rmp->id = MLX5_GET(create_rmp_out, out, rmpn); 1494 return rmp; 1495 } 1496 1497 /* 1498 * Create TIR using DevX API. 1499 * 1500 * @param[in] ctx 1501 * Context returned from mlx5 open_device() glue function. 1502 * @param [in] tir_attr 1503 * Pointer to TIR attributes structure. 1504 * 1505 * @return 1506 * The DevX object created, NULL otherwise and rte_errno is set. 1507 */ 1508 struct mlx5_devx_obj * 1509 mlx5_devx_cmd_create_tir(void *ctx, 1510 struct mlx5_devx_tir_attr *tir_attr) 1511 { 1512 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1513 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1514 void *tir_ctx, *outer, *inner, *rss_key; 1515 struct mlx5_devx_obj *tir = NULL; 1516 1517 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1518 if (!tir) { 1519 DRV_LOG(ERR, "Failed to allocate TIR data"); 1520 rte_errno = ENOMEM; 1521 return NULL; 1522 } 1523 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1524 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1525 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1526 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1527 tir_attr->lro_timeout_period_usecs); 1528 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1529 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1530 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1531 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1532 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1533 tir_attr->tunneled_offload_en); 1534 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1535 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1536 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1537 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1538 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1539 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1540 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1541 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1542 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1543 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1544 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1545 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1546 tir_attr->rx_hash_field_selector_outer.selected_fields); 1547 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1548 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1549 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1550 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1551 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1552 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1553 tir_attr->rx_hash_field_selector_inner.selected_fields); 1554 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1555 out, sizeof(out)); 1556 if (!tir->obj) { 1557 DEVX_DRV_LOG(ERR, out, "create TIR", NULL, 0); 1558 mlx5_free(tir); 1559 return NULL; 1560 } 1561 tir->id = MLX5_GET(create_tir_out, out, tirn); 1562 return tir; 1563 } 1564 1565 /** 1566 * Modify TIR using DevX API. 1567 * 1568 * @param[in] tir 1569 * Pointer to TIR DevX object structure. 1570 * @param [in] modify_tir_attr 1571 * Pointer to TIR modification attributes structure. 1572 * 1573 * @return 1574 * 0 on success, a negative errno value otherwise and rte_errno is set. 1575 */ 1576 int 1577 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1578 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1579 { 1580 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1581 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1582 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1583 void *tir_ctx; 1584 int ret; 1585 1586 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1587 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1588 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1589 modify_tir_attr->modify_bitmask); 1590 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1591 if (modify_tir_attr->modify_bitmask & 1592 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1593 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1594 tir_attr->lro_timeout_period_usecs); 1595 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1596 tir_attr->lro_enable_mask); 1597 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1598 tir_attr->lro_max_msg_sz); 1599 } 1600 if (modify_tir_attr->modify_bitmask & 1601 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1602 MLX5_SET(tirc, tir_ctx, indirect_table, 1603 tir_attr->indirect_table); 1604 if (modify_tir_attr->modify_bitmask & 1605 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1606 int i; 1607 void *outer, *inner; 1608 1609 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1610 tir_attr->rx_hash_symmetric); 1611 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1612 for (i = 0; i < 10; i++) { 1613 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1614 tir_attr->rx_hash_toeplitz_key[i]); 1615 } 1616 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1617 rx_hash_field_selector_outer); 1618 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1619 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1620 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1621 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1622 MLX5_SET 1623 (rx_hash_field_select, outer, selected_fields, 1624 tir_attr->rx_hash_field_selector_outer.selected_fields); 1625 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1626 rx_hash_field_selector_inner); 1627 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1628 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1629 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1630 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1631 MLX5_SET 1632 (rx_hash_field_select, inner, selected_fields, 1633 tir_attr->rx_hash_field_selector_inner.selected_fields); 1634 } 1635 if (modify_tir_attr->modify_bitmask & 1636 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1637 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1638 } 1639 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1640 out, sizeof(out)); 1641 if (ret) { 1642 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1643 rte_errno = errno; 1644 return -errno; 1645 } 1646 return ret; 1647 } 1648 1649 /** 1650 * Create RQT using DevX API. 1651 * 1652 * @param[in] ctx 1653 * Context returned from mlx5 open_device() glue function. 1654 * @param [in] rqt_attr 1655 * Pointer to RQT attributes structure. 1656 * 1657 * @return 1658 * The DevX object created, NULL otherwise and rte_errno is set. 1659 */ 1660 struct mlx5_devx_obj * 1661 mlx5_devx_cmd_create_rqt(void *ctx, 1662 struct mlx5_devx_rqt_attr *rqt_attr) 1663 { 1664 uint32_t *in = NULL; 1665 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1666 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1667 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1668 void *rqt_ctx; 1669 struct mlx5_devx_obj *rqt = NULL; 1670 int i; 1671 1672 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1673 if (!in) { 1674 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1675 rte_errno = ENOMEM; 1676 return NULL; 1677 } 1678 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1679 if (!rqt) { 1680 DRV_LOG(ERR, "Failed to allocate RQT data"); 1681 rte_errno = ENOMEM; 1682 mlx5_free(in); 1683 return NULL; 1684 } 1685 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1686 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1687 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1688 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1689 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1690 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1691 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1692 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1693 mlx5_free(in); 1694 if (!rqt->obj) { 1695 DEVX_DRV_LOG(ERR, out, "create RQT", NULL, 0); 1696 mlx5_free(rqt); 1697 return NULL; 1698 } 1699 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1700 return rqt; 1701 } 1702 1703 /** 1704 * Modify RQT using DevX API. 1705 * 1706 * @param[in] rqt 1707 * Pointer to RQT DevX object structure. 1708 * @param [in] rqt_attr 1709 * Pointer to RQT attributes structure. 1710 * 1711 * @return 1712 * 0 on success, a negative errno value otherwise and rte_errno is set. 1713 */ 1714 int 1715 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1716 struct mlx5_devx_rqt_attr *rqt_attr) 1717 { 1718 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1719 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1720 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1721 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1722 void *rqt_ctx; 1723 int i; 1724 int ret; 1725 1726 if (!in) { 1727 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1728 rte_errno = ENOMEM; 1729 return -ENOMEM; 1730 } 1731 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1732 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1733 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1734 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1735 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1736 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1737 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1738 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1739 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1740 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1741 mlx5_free(in); 1742 if (ret) { 1743 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1744 rte_errno = errno; 1745 return -rte_errno; 1746 } 1747 return ret; 1748 } 1749 1750 /** 1751 * Create SQ using DevX API. 1752 * 1753 * @param[in] ctx 1754 * Context returned from mlx5 open_device() glue function. 1755 * @param [in] sq_attr 1756 * Pointer to SQ attributes structure. 1757 * @param [in] socket 1758 * CPU socket ID for allocations. 1759 * 1760 * @return 1761 * The DevX object created, NULL otherwise and rte_errno is set. 1762 **/ 1763 struct mlx5_devx_obj * 1764 mlx5_devx_cmd_create_sq(void *ctx, 1765 struct mlx5_devx_create_sq_attr *sq_attr) 1766 { 1767 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1768 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1769 void *sq_ctx; 1770 void *wq_ctx; 1771 struct mlx5_devx_wq_attr *wq_attr; 1772 struct mlx5_devx_obj *sq = NULL; 1773 1774 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1775 if (!sq) { 1776 DRV_LOG(ERR, "Failed to allocate SQ data"); 1777 rte_errno = ENOMEM; 1778 return NULL; 1779 } 1780 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1781 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1782 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1783 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1784 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1785 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1786 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1787 sq_attr->allow_multi_pkt_send_wqe); 1788 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1789 sq_attr->min_wqe_inline_mode); 1790 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1791 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1792 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1793 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1794 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1795 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1796 MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type); 1797 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1798 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1799 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1800 sq_attr->packet_pacing_rate_limit_index); 1801 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1802 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1803 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1804 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1805 wq_attr = &sq_attr->wq_attr; 1806 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1807 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1808 out, sizeof(out)); 1809 if (!sq->obj) { 1810 DEVX_DRV_LOG(ERR, out, "create SQ", NULL, 0); 1811 mlx5_free(sq); 1812 return NULL; 1813 } 1814 sq->id = MLX5_GET(create_sq_out, out, sqn); 1815 return sq; 1816 } 1817 1818 /** 1819 * Modify SQ using DevX API. 1820 * 1821 * @param[in] sq 1822 * Pointer to SQ object structure. 1823 * @param [in] sq_attr 1824 * Pointer to SQ attributes structure. 1825 * 1826 * @return 1827 * 0 on success, a negative errno value otherwise and rte_errno is set. 1828 */ 1829 int 1830 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1831 struct mlx5_devx_modify_sq_attr *sq_attr) 1832 { 1833 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1834 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1835 void *sq_ctx; 1836 int ret; 1837 1838 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1839 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1840 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1841 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1842 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1843 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1844 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1845 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1846 out, sizeof(out)); 1847 if (ret) { 1848 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1849 rte_errno = errno; 1850 return -rte_errno; 1851 } 1852 return ret; 1853 } 1854 1855 /** 1856 * Create TIS using DevX API. 1857 * 1858 * @param[in] ctx 1859 * Context returned from mlx5 open_device() glue function. 1860 * @param [in] tis_attr 1861 * Pointer to TIS attributes structure. 1862 * 1863 * @return 1864 * The DevX object created, NULL otherwise and rte_errno is set. 1865 */ 1866 struct mlx5_devx_obj * 1867 mlx5_devx_cmd_create_tis(void *ctx, 1868 struct mlx5_devx_tis_attr *tis_attr) 1869 { 1870 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1871 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1872 struct mlx5_devx_obj *tis = NULL; 1873 void *tis_ctx; 1874 1875 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1876 if (!tis) { 1877 DRV_LOG(ERR, "Failed to allocate TIS object"); 1878 rte_errno = ENOMEM; 1879 return NULL; 1880 } 1881 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1882 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1883 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1884 tis_attr->strict_lag_tx_port_affinity); 1885 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1886 tis_attr->lag_tx_port_affinity); 1887 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1888 MLX5_SET(tisc, tis_ctx, transport_domain, 1889 tis_attr->transport_domain); 1890 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1891 out, sizeof(out)); 1892 if (!tis->obj) { 1893 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 1894 mlx5_free(tis); 1895 return NULL; 1896 } 1897 tis->id = MLX5_GET(create_tis_out, out, tisn); 1898 return tis; 1899 } 1900 1901 /** 1902 * Create transport domain using DevX API. 1903 * 1904 * @param[in] ctx 1905 * Context returned from mlx5 open_device() glue function. 1906 * @return 1907 * The DevX object created, NULL otherwise and rte_errno is set. 1908 */ 1909 struct mlx5_devx_obj * 1910 mlx5_devx_cmd_create_td(void *ctx) 1911 { 1912 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1913 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1914 struct mlx5_devx_obj *td = NULL; 1915 1916 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1917 if (!td) { 1918 DRV_LOG(ERR, "Failed to allocate TD object"); 1919 rte_errno = ENOMEM; 1920 return NULL; 1921 } 1922 MLX5_SET(alloc_transport_domain_in, in, opcode, 1923 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1924 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1925 out, sizeof(out)); 1926 if (!td->obj) { 1927 DEVX_DRV_LOG(ERR, out, "create TIS", NULL, 0); 1928 mlx5_free(td); 1929 return NULL; 1930 } 1931 td->id = MLX5_GET(alloc_transport_domain_out, out, 1932 transport_domain); 1933 return td; 1934 } 1935 1936 /** 1937 * Dump all flows to file. 1938 * 1939 * @param[in] fdb_domain 1940 * FDB domain. 1941 * @param[in] rx_domain 1942 * RX domain. 1943 * @param[in] tx_domain 1944 * TX domain. 1945 * @param[out] file 1946 * Pointer to file stream. 1947 * 1948 * @return 1949 * 0 on success, a negative value otherwise. 1950 */ 1951 int 1952 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1953 void *rx_domain __rte_unused, 1954 void *tx_domain __rte_unused, FILE *file __rte_unused) 1955 { 1956 int ret = 0; 1957 1958 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1959 if (fdb_domain) { 1960 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1961 if (ret) 1962 return ret; 1963 } 1964 MLX5_ASSERT(rx_domain); 1965 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1966 if (ret) 1967 return ret; 1968 MLX5_ASSERT(tx_domain); 1969 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1970 #else 1971 ret = ENOTSUP; 1972 #endif 1973 return -ret; 1974 } 1975 1976 int 1977 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 1978 FILE *file __rte_unused) 1979 { 1980 int ret = 0; 1981 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 1982 if (rule_info) 1983 ret = mlx5_glue->dr_dump_rule(file, rule_info); 1984 #else 1985 ret = ENOTSUP; 1986 #endif 1987 return -ret; 1988 } 1989 1990 /* 1991 * Create CQ using DevX API. 1992 * 1993 * @param[in] ctx 1994 * Context returned from mlx5 open_device() glue function. 1995 * @param [in] attr 1996 * Pointer to CQ attributes structure. 1997 * 1998 * @return 1999 * The DevX object created, NULL otherwise and rte_errno is set. 2000 */ 2001 struct mlx5_devx_obj * 2002 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 2003 { 2004 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 2005 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 2006 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2007 sizeof(*cq_obj), 2008 0, SOCKET_ID_ANY); 2009 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 2010 2011 if (!cq_obj) { 2012 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 2013 rte_errno = ENOMEM; 2014 return NULL; 2015 } 2016 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 2017 if (attr->db_umem_valid) { 2018 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 2019 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 2020 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 2021 } else { 2022 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 2023 } 2024 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 2025 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 2026 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 2027 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 2028 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 2029 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2030 MLX5_SET(cqc, cqctx, log_page_size, 2031 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2032 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 2033 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 2034 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 2035 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 2036 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 2037 attr->mini_cqe_res_format_ext); 2038 if (attr->q_umem_valid) { 2039 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 2040 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 2041 MLX5_SET64(create_cq_in, in, cq_umem_offset, 2042 attr->q_umem_offset); 2043 } 2044 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2045 sizeof(out)); 2046 if (!cq_obj->obj) { 2047 DEVX_DRV_LOG(ERR, out, "create CQ", NULL, 0); 2048 mlx5_free(cq_obj); 2049 return NULL; 2050 } 2051 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 2052 return cq_obj; 2053 } 2054 2055 /** 2056 * Create VIRTQ using DevX API. 2057 * 2058 * @param[in] ctx 2059 * Context returned from mlx5 open_device() glue function. 2060 * @param [in] attr 2061 * Pointer to VIRTQ attributes structure. 2062 * 2063 * @return 2064 * The DevX object created, NULL otherwise and rte_errno is set. 2065 */ 2066 struct mlx5_devx_obj * 2067 mlx5_devx_cmd_create_virtq(void *ctx, 2068 struct mlx5_devx_virtq_attr *attr) 2069 { 2070 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2071 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2072 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 2073 sizeof(*virtq_obj), 2074 0, SOCKET_ID_ANY); 2075 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2076 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2077 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2078 2079 if (!virtq_obj) { 2080 DRV_LOG(ERR, "Failed to allocate virtq data."); 2081 rte_errno = ENOMEM; 2082 return NULL; 2083 } 2084 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2085 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2086 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2087 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2088 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2089 attr->hw_available_index); 2090 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 2091 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2092 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2093 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2094 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2095 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2096 attr->virtio_version_1_0); 2097 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2098 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2099 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2100 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2101 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 2102 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2103 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 2104 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2105 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 2106 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 2107 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 2108 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 2109 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 2110 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 2111 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 2112 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 2113 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 2114 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 2115 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 2116 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 2117 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 2118 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 2119 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 2120 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2121 sizeof(out)); 2122 if (!virtq_obj->obj) { 2123 DEVX_DRV_LOG(ERR, out, "create VIRTQ", NULL, 0); 2124 mlx5_free(virtq_obj); 2125 return NULL; 2126 } 2127 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2128 return virtq_obj; 2129 } 2130 2131 /** 2132 * Modify VIRTQ using DevX API. 2133 * 2134 * @param[in] virtq_obj 2135 * Pointer to virtq object structure. 2136 * @param [in] attr 2137 * Pointer to modify virtq attributes structure. 2138 * 2139 * @return 2140 * 0 on success, a negative errno value otherwise and rte_errno is set. 2141 */ 2142 int 2143 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 2144 struct mlx5_devx_virtq_attr *attr) 2145 { 2146 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2147 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2148 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2149 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2150 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2151 int ret; 2152 2153 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2154 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 2155 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2156 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2157 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2158 MLX5_SET64(virtio_net_q, virtq, modify_field_select, 2159 attr->mod_fields_bitmap); 2160 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2161 if (!attr->mod_fields_bitmap) { 2162 DRV_LOG(ERR, "Failed to modify VIRTQ for no type set."); 2163 rte_errno = EINVAL; 2164 return -rte_errno; 2165 } 2166 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE) 2167 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 2168 if (attr->mod_fields_bitmap & 2169 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) { 2170 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 2171 attr->dirty_bitmap_mkey); 2172 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 2173 attr->dirty_bitmap_addr); 2174 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 2175 attr->dirty_bitmap_size); 2176 } 2177 if (attr->mod_fields_bitmap & 2178 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE) 2179 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 2180 attr->dirty_bitmap_dump_enable); 2181 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) { 2182 MLX5_SET(virtio_q, virtctx, queue_period_mode, 2183 attr->hw_latency_mode); 2184 MLX5_SET(virtio_q, virtctx, queue_period_us, 2185 attr->hw_max_latency_us); 2186 MLX5_SET(virtio_q, virtctx, queue_max_count, 2187 attr->hw_max_pending_comp); 2188 } 2189 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) { 2190 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 2191 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 2192 MLX5_SET64(virtio_q, virtctx, available_addr, 2193 attr->available_addr); 2194 } 2195 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX) 2196 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 2197 attr->hw_available_index); 2198 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX) 2199 MLX5_SET16(virtio_net_q, virtq, hw_used_index, 2200 attr->hw_used_index); 2201 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE) 2202 MLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type); 2203 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0) 2204 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 2205 attr->virtio_version_1_0); 2206 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY) 2207 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 2208 if (attr->mod_fields_bitmap & 2209 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) { 2210 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 2211 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 2212 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 2213 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 2214 } 2215 if (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) { 2216 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 2217 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 2218 } 2219 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 2220 out, sizeof(out)); 2221 if (ret) { 2222 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2223 rte_errno = errno; 2224 return -rte_errno; 2225 } 2226 return ret; 2227 } 2228 2229 /** 2230 * Query VIRTQ using DevX API. 2231 * 2232 * @param[in] virtq_obj 2233 * Pointer to virtq object structure. 2234 * @param [in/out] attr 2235 * Pointer to virtq attributes structure. 2236 * 2237 * @return 2238 * 0 on success, a negative errno value otherwise and rte_errno is set. 2239 */ 2240 int 2241 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 2242 struct mlx5_devx_virtq_attr *attr) 2243 { 2244 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2245 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 2246 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 2247 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 2248 int ret; 2249 2250 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2251 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2252 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2253 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2254 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2255 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2256 out, sizeof(out)); 2257 if (ret) { 2258 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2259 rte_errno = errno; 2260 return -errno; 2261 } 2262 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2263 hw_available_index); 2264 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2265 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2266 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2267 virtio_q_context.error_type); 2268 return ret; 2269 } 2270 2271 /** 2272 * Create QP using DevX API. 2273 * 2274 * @param[in] ctx 2275 * Context returned from mlx5 open_device() glue function. 2276 * @param [in] attr 2277 * Pointer to QP attributes structure. 2278 * 2279 * @return 2280 * The DevX object created, NULL otherwise and rte_errno is set. 2281 */ 2282 struct mlx5_devx_obj * 2283 mlx5_devx_cmd_create_qp(void *ctx, 2284 struct mlx5_devx_qp_attr *attr) 2285 { 2286 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2287 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2288 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2289 sizeof(*qp_obj), 2290 0, SOCKET_ID_ANY); 2291 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2292 2293 if (!qp_obj) { 2294 DRV_LOG(ERR, "Failed to allocate QP data."); 2295 rte_errno = ENOMEM; 2296 return NULL; 2297 } 2298 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2299 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2300 MLX5_SET(qpc, qpc, pd, attr->pd); 2301 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2302 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2303 if (attr->uar_index) { 2304 if (attr->mmo) { 2305 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2306 in, qpc_extension_and_pas_list); 2307 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2308 qpc_ext_and_pas_list, qpc_data_extension); 2309 2310 MLX5_SET(create_qp_in, in, qpc_ext, 1); 2311 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2312 } 2313 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2314 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2315 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2316 MLX5_SET(qpc, qpc, log_page_size, 2317 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2318 if (attr->num_of_send_wqbbs) { 2319 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs)); 2320 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2321 MLX5_SET(qpc, qpc, log_sq_size, 2322 rte_log2_u32(attr->num_of_send_wqbbs)); 2323 } else { 2324 MLX5_SET(qpc, qpc, no_sq, 1); 2325 } 2326 if (attr->num_of_receive_wqes) { 2327 MLX5_ASSERT(RTE_IS_POWER_OF_2( 2328 attr->num_of_receive_wqes)); 2329 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2330 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2331 MLX5_LOG_RQ_STRIDE_SHIFT); 2332 MLX5_SET(qpc, qpc, log_rq_size, 2333 rte_log2_u32(attr->num_of_receive_wqes)); 2334 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2335 } else { 2336 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2337 } 2338 if (attr->dbr_umem_valid) { 2339 MLX5_SET(qpc, qpc, dbr_umem_valid, 2340 attr->dbr_umem_valid); 2341 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2342 } 2343 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2344 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2345 attr->wq_umem_offset); 2346 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2347 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2348 } else { 2349 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2350 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2351 MLX5_SET(qpc, qpc, no_sq, 1); 2352 } 2353 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2354 sizeof(out)); 2355 if (!qp_obj->obj) { 2356 DEVX_DRV_LOG(ERR, out, "create QP", NULL, 0); 2357 mlx5_free(qp_obj); 2358 return NULL; 2359 } 2360 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2361 return qp_obj; 2362 } 2363 2364 /** 2365 * Modify QP using DevX API. 2366 * Currently supports only force loop-back QP. 2367 * 2368 * @param[in] qp 2369 * Pointer to QP object structure. 2370 * @param [in] qp_st_mod_op 2371 * The QP state modification operation. 2372 * @param [in] remote_qp_id 2373 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2374 * 2375 * @return 2376 * 0 on success, a negative errno value otherwise and rte_errno is set. 2377 */ 2378 int 2379 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2380 uint32_t remote_qp_id) 2381 { 2382 union { 2383 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2384 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2385 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2386 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_in)]; 2387 } in; 2388 union { 2389 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2390 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2391 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2392 uint32_t qp2rst[MLX5_ST_SZ_DW(2rst_qp_out)]; 2393 } out; 2394 void *qpc; 2395 int ret; 2396 unsigned int inlen; 2397 unsigned int outlen; 2398 2399 memset(&in, 0, sizeof(in)); 2400 memset(&out, 0, sizeof(out)); 2401 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2402 switch (qp_st_mod_op) { 2403 case MLX5_CMD_OP_RST2INIT_QP: 2404 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2405 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2406 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2407 MLX5_SET(qpc, qpc, rre, 1); 2408 MLX5_SET(qpc, qpc, rwe, 1); 2409 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2410 inlen = sizeof(in.rst2init); 2411 outlen = sizeof(out.rst2init); 2412 break; 2413 case MLX5_CMD_OP_INIT2RTR_QP: 2414 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2415 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2416 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2417 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2418 MLX5_SET(qpc, qpc, mtu, 1); 2419 MLX5_SET(qpc, qpc, log_msg_max, 30); 2420 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2421 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2422 inlen = sizeof(in.init2rtr); 2423 outlen = sizeof(out.init2rtr); 2424 break; 2425 case MLX5_CMD_OP_RTR2RTS_QP: 2426 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2427 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2428 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16); 2429 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2430 MLX5_SET(qpc, qpc, retry_count, 7); 2431 MLX5_SET(qpc, qpc, rnr_retry, 7); 2432 inlen = sizeof(in.rtr2rts); 2433 outlen = sizeof(out.rtr2rts); 2434 break; 2435 case MLX5_CMD_OP_QP_2RST: 2436 MLX5_SET(2rst_qp_in, &in, qpn, qp->id); 2437 inlen = sizeof(in.qp2rst); 2438 outlen = sizeof(out.qp2rst); 2439 break; 2440 default: 2441 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2442 qp_st_mod_op); 2443 rte_errno = EINVAL; 2444 return -rte_errno; 2445 } 2446 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2447 if (ret) { 2448 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2449 rte_errno = errno; 2450 return -rte_errno; 2451 } 2452 return ret; 2453 } 2454 2455 struct mlx5_devx_obj * 2456 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2457 { 2458 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2459 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2460 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2461 sizeof(*couners_obj), 0, 2462 SOCKET_ID_ANY); 2463 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2464 2465 if (!couners_obj) { 2466 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2467 rte_errno = ENOMEM; 2468 return NULL; 2469 } 2470 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2471 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2472 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2473 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2474 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2475 sizeof(out)); 2476 if (!couners_obj->obj) { 2477 DEVX_DRV_LOG(ERR, out, "create virtio queue counters Obj", NULL, 2478 0); 2479 mlx5_free(couners_obj); 2480 return NULL; 2481 } 2482 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2483 return couners_obj; 2484 } 2485 2486 int 2487 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2488 struct mlx5_devx_virtio_q_couners_attr *attr) 2489 { 2490 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2491 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2492 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2493 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2494 virtio_q_counters); 2495 int ret; 2496 2497 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2498 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2499 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2500 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2501 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2502 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2503 sizeof(out)); 2504 if (ret) { 2505 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2506 rte_errno = errno; 2507 return -errno; 2508 } 2509 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2510 received_desc); 2511 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2512 completed_desc); 2513 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2514 error_cqes); 2515 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2516 bad_desc_errors); 2517 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2518 exceed_max_chain); 2519 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2520 invalid_buffer); 2521 return ret; 2522 } 2523 2524 /** 2525 * Create general object of type FLOW_HIT_ASO using DevX API. 2526 * 2527 * @param[in] ctx 2528 * Context returned from mlx5 open_device() glue function. 2529 * @param [in] pd 2530 * PD value to associate the FLOW_HIT_ASO object with. 2531 * 2532 * @return 2533 * The DevX object created, NULL otherwise and rte_errno is set. 2534 */ 2535 struct mlx5_devx_obj * 2536 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2537 { 2538 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2539 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2540 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2541 void *ptr = NULL; 2542 2543 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2544 0, SOCKET_ID_ANY); 2545 if (!flow_hit_aso_obj) { 2546 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2547 rte_errno = ENOMEM; 2548 return NULL; 2549 } 2550 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2551 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2552 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2553 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2554 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2555 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2556 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2557 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2558 out, sizeof(out)); 2559 if (!flow_hit_aso_obj->obj) { 2560 DEVX_DRV_LOG(ERR, out, "create FLOW_HIT_ASO", NULL, 0); 2561 mlx5_free(flow_hit_aso_obj); 2562 return NULL; 2563 } 2564 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2565 return flow_hit_aso_obj; 2566 } 2567 2568 /* 2569 * Create PD using DevX API. 2570 * 2571 * @param[in] ctx 2572 * Context returned from mlx5 open_device() glue function. 2573 * 2574 * @return 2575 * The DevX object created, NULL otherwise and rte_errno is set. 2576 */ 2577 struct mlx5_devx_obj * 2578 mlx5_devx_cmd_alloc_pd(void *ctx) 2579 { 2580 struct mlx5_devx_obj *ppd = 2581 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2582 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2583 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2584 2585 if (!ppd) { 2586 DRV_LOG(ERR, "Failed to allocate PD data."); 2587 rte_errno = ENOMEM; 2588 return NULL; 2589 } 2590 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2591 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2592 out, sizeof(out)); 2593 if (!ppd->obj) { 2594 mlx5_free(ppd); 2595 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2596 rte_errno = errno; 2597 return NULL; 2598 } 2599 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2600 return ppd; 2601 } 2602 2603 /** 2604 * Create general object of type FLOW_METER_ASO using DevX API. 2605 * 2606 * @param[in] ctx 2607 * Context returned from mlx5 open_device() glue function. 2608 * @param [in] pd 2609 * PD value to associate the FLOW_METER_ASO object with. 2610 * @param [in] log_obj_size 2611 * log_obj_size define to allocate number of 2 * meters 2612 * in one FLOW_METER_ASO object. 2613 * 2614 * @return 2615 * The DevX object created, NULL otherwise and rte_errno is set. 2616 */ 2617 struct mlx5_devx_obj * 2618 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2619 uint32_t log_obj_size) 2620 { 2621 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2622 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2623 struct mlx5_devx_obj *flow_meter_aso_obj; 2624 void *ptr; 2625 2626 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2627 sizeof(*flow_meter_aso_obj), 2628 0, SOCKET_ID_ANY); 2629 if (!flow_meter_aso_obj) { 2630 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2631 rte_errno = ENOMEM; 2632 return NULL; 2633 } 2634 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2635 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2636 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2637 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2638 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2639 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2640 log_obj_size); 2641 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2642 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2643 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2644 ctx, in, sizeof(in), 2645 out, sizeof(out)); 2646 if (!flow_meter_aso_obj->obj) { 2647 DEVX_DRV_LOG(ERR, out, "create FLOW_METTER_ASO", NULL, 0); 2648 mlx5_free(flow_meter_aso_obj); 2649 return NULL; 2650 } 2651 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2652 out, obj_id); 2653 return flow_meter_aso_obj; 2654 } 2655 2656 /* 2657 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2658 * 2659 * @param[in] ctx 2660 * Context returned from mlx5 open_device() glue function. 2661 * @param [in] pd 2662 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2663 * @param [in] log_obj_size 2664 * log_obj_size to allocate its power of 2 * objects 2665 * in one CONN_TRACK_OFFLOAD bulk allocation. 2666 * 2667 * @return 2668 * The DevX object created, NULL otherwise and rte_errno is set. 2669 */ 2670 struct mlx5_devx_obj * 2671 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2672 uint32_t log_obj_size) 2673 { 2674 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2675 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2676 struct mlx5_devx_obj *ct_aso_obj; 2677 void *ptr; 2678 2679 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2680 0, SOCKET_ID_ANY); 2681 if (!ct_aso_obj) { 2682 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2683 rte_errno = ENOMEM; 2684 return NULL; 2685 } 2686 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2687 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2688 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2689 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2690 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2691 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2692 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2693 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2694 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2695 out, sizeof(out)); 2696 if (!ct_aso_obj->obj) { 2697 DEVX_DRV_LOG(ERR, out, "create CONN_TRACK_OFFLOAD", NULL, 0); 2698 mlx5_free(ct_aso_obj); 2699 return NULL; 2700 } 2701 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2702 return ct_aso_obj; 2703 } 2704 2705 /** 2706 * Create general object of type GENEVE TLV option using DevX API. 2707 * 2708 * @param[in] ctx 2709 * Context returned from mlx5 open_device() glue function. 2710 * @param [in] class 2711 * TLV option variable value of class 2712 * @param [in] type 2713 * TLV option variable value of type 2714 * @param [in] len 2715 * TLV option variable value of len 2716 * 2717 * @return 2718 * The DevX object created, NULL otherwise and rte_errno is set. 2719 */ 2720 struct mlx5_devx_obj * 2721 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2722 uint16_t class, uint8_t type, uint8_t len) 2723 { 2724 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2725 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2726 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2727 sizeof(*geneve_tlv_opt_obj), 2728 0, SOCKET_ID_ANY); 2729 2730 if (!geneve_tlv_opt_obj) { 2731 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2732 rte_errno = ENOMEM; 2733 return NULL; 2734 } 2735 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2736 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2737 geneve_tlv_opt); 2738 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2739 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2740 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2741 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2742 MLX5_SET(geneve_tlv_option, opt, option_class, 2743 rte_be_to_cpu_16(class)); 2744 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2745 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2746 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2747 sizeof(in), out, sizeof(out)); 2748 if (!geneve_tlv_opt_obj->obj) { 2749 DEVX_DRV_LOG(ERR, out, "create GENEVE TLV", NULL, 0); 2750 mlx5_free(geneve_tlv_opt_obj); 2751 return NULL; 2752 } 2753 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2754 return geneve_tlv_opt_obj; 2755 } 2756 2757 int 2758 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2759 { 2760 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2761 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2762 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2763 int rc; 2764 void *rq_ctx; 2765 2766 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2767 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2768 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2769 if (rc) { 2770 rte_errno = errno; 2771 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2772 "rc = %d, errno = %d.", rc, errno); 2773 return -rc; 2774 }; 2775 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2776 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2777 return 0; 2778 #else 2779 (void)wq; 2780 (void)counter_set_id; 2781 return -ENOTSUP; 2782 #endif 2783 } 2784 2785 /* 2786 * Allocate queue counters via devx interface. 2787 * 2788 * @param[in] ctx 2789 * Context returned from mlx5 open_device() glue function. 2790 * 2791 * @return 2792 * Pointer to counter object on success, a NULL value otherwise and 2793 * rte_errno is set. 2794 */ 2795 struct mlx5_devx_obj * 2796 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2797 { 2798 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2799 SOCKET_ID_ANY); 2800 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2801 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2802 2803 if (!dcs) { 2804 rte_errno = ENOMEM; 2805 return NULL; 2806 } 2807 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2808 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2809 sizeof(out)); 2810 if (!dcs->obj) { 2811 DEVX_DRV_LOG(DEBUG, out, "create q counter set", NULL, 0); 2812 mlx5_free(dcs); 2813 return NULL; 2814 } 2815 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2816 return dcs; 2817 } 2818 2819 /** 2820 * Query queue counters values. 2821 * 2822 * @param[in] dcs 2823 * devx object of the queue counter set. 2824 * @param[in] clear 2825 * Whether hardware should clear the counters after the query or not. 2826 * @param[out] out_of_buffers 2827 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2828 * 2829 * @return 2830 * 0 on success, a negative value otherwise. 2831 */ 2832 int 2833 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2834 uint32_t *out_of_buffers) 2835 { 2836 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2837 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2838 int rc; 2839 2840 MLX5_SET(query_q_counter_in, in, opcode, 2841 MLX5_CMD_OP_QUERY_Q_COUNTER); 2842 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2843 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2844 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2845 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2846 sizeof(out)); 2847 if (rc) { 2848 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2849 rte_errno = rc; 2850 return -rc; 2851 } 2852 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2853 return 0; 2854 } 2855 2856 /** 2857 * Create general object of type DEK using DevX API. 2858 * 2859 * @param[in] ctx 2860 * Context returned from mlx5 open_device() glue function. 2861 * @param [in] attr 2862 * Pointer to DEK attributes structure. 2863 * 2864 * @return 2865 * The DevX object created, NULL otherwise and rte_errno is set. 2866 */ 2867 struct mlx5_devx_obj * 2868 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2869 { 2870 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2871 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2872 struct mlx5_devx_obj *dek_obj = NULL; 2873 void *ptr = NULL, *key_addr = NULL; 2874 2875 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2876 0, SOCKET_ID_ANY); 2877 if (dek_obj == NULL) { 2878 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2879 rte_errno = ENOMEM; 2880 return NULL; 2881 } 2882 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2883 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2884 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2885 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2886 MLX5_GENERAL_OBJ_TYPE_DEK); 2887 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2888 MLX5_SET(dek, ptr, key_size, attr->key_size); 2889 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2890 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2891 MLX5_SET(dek, ptr, pd, attr->pd); 2892 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2893 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2894 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2895 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2896 out, sizeof(out)); 2897 if (dek_obj->obj == NULL) { 2898 DEVX_DRV_LOG(ERR, out, "create DEK", NULL, 0); 2899 mlx5_free(dek_obj); 2900 return NULL; 2901 } 2902 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2903 return dek_obj; 2904 } 2905 2906 /** 2907 * Create general object of type IMPORT_KEK using DevX API. 2908 * 2909 * @param[in] ctx 2910 * Context returned from mlx5 open_device() glue function. 2911 * @param [in] attr 2912 * Pointer to IMPORT_KEK attributes structure. 2913 * 2914 * @return 2915 * The DevX object created, NULL otherwise and rte_errno is set. 2916 */ 2917 struct mlx5_devx_obj * 2918 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 2919 struct mlx5_devx_import_kek_attr *attr) 2920 { 2921 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 2922 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2923 struct mlx5_devx_obj *import_kek_obj = NULL; 2924 void *ptr = NULL, *key_addr = NULL; 2925 2926 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 2927 0, SOCKET_ID_ANY); 2928 if (import_kek_obj == NULL) { 2929 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 2930 rte_errno = ENOMEM; 2931 return NULL; 2932 } 2933 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 2934 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2935 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2936 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2937 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 2938 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 2939 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 2940 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 2941 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2942 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2943 out, sizeof(out)); 2944 if (import_kek_obj->obj == NULL) { 2945 DEVX_DRV_LOG(ERR, out, "create IMPORT_KEK", NULL, 0); 2946 mlx5_free(import_kek_obj); 2947 return NULL; 2948 } 2949 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2950 return import_kek_obj; 2951 } 2952 2953 /** 2954 * Create general object of type CREDENTIAL using DevX API. 2955 * 2956 * @param[in] ctx 2957 * Context returned from mlx5 open_device() glue function. 2958 * @param [in] attr 2959 * Pointer to CREDENTIAL attributes structure. 2960 * 2961 * @return 2962 * The DevX object created, NULL otherwise and rte_errno is set. 2963 */ 2964 struct mlx5_devx_obj * 2965 mlx5_devx_cmd_create_credential_obj(void *ctx, 2966 struct mlx5_devx_credential_attr *attr) 2967 { 2968 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 2969 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2970 struct mlx5_devx_obj *credential_obj = NULL; 2971 void *ptr = NULL, *credential_addr = NULL; 2972 2973 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 2974 0, SOCKET_ID_ANY); 2975 if (credential_obj == NULL) { 2976 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 2977 rte_errno = ENOMEM; 2978 return NULL; 2979 } 2980 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 2981 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2982 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2983 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2984 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 2985 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 2986 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 2987 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 2988 memcpy(credential_addr, (void *)(attr->credential), 2989 MLX5_CRYPTO_CREDENTIAL_SIZE); 2990 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2991 out, sizeof(out)); 2992 if (credential_obj->obj == NULL) { 2993 DEVX_DRV_LOG(ERR, out, "create CREDENTIAL", NULL, 0); 2994 mlx5_free(credential_obj); 2995 return NULL; 2996 } 2997 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2998 return credential_obj; 2999 } 3000 3001 /** 3002 * Create general object of type CRYPTO_LOGIN using DevX API. 3003 * 3004 * @param[in] ctx 3005 * Context returned from mlx5 open_device() glue function. 3006 * @param [in] attr 3007 * Pointer to CRYPTO_LOGIN attributes structure. 3008 * 3009 * @return 3010 * The DevX object created, NULL otherwise and rte_errno is set. 3011 */ 3012 struct mlx5_devx_obj * 3013 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 3014 struct mlx5_devx_crypto_login_attr *attr) 3015 { 3016 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 3017 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 3018 struct mlx5_devx_obj *crypto_login_obj = NULL; 3019 void *ptr = NULL, *credential_addr = NULL; 3020 3021 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 3022 0, SOCKET_ID_ANY); 3023 if (crypto_login_obj == NULL) { 3024 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 3025 rte_errno = ENOMEM; 3026 return NULL; 3027 } 3028 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 3029 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 3030 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 3031 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 3032 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 3033 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 3034 MLX5_SET(crypto_login, ptr, credential_pointer, 3035 attr->credential_pointer); 3036 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 3037 attr->session_import_kek_ptr); 3038 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 3039 memcpy(credential_addr, (void *)(attr->credential), 3040 MLX5_CRYPTO_CREDENTIAL_SIZE); 3041 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 3042 out, sizeof(out)); 3043 if (crypto_login_obj->obj == NULL) { 3044 DEVX_DRV_LOG(ERR, out, "create CRYPTO_LOGIN", NULL, 0); 3045 mlx5_free(crypto_login_obj); 3046 return NULL; 3047 } 3048 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 3049 return crypto_login_obj; 3050 } 3051 3052 /** 3053 * Query LAG context. 3054 * 3055 * @param[in] ctx 3056 * Pointer to ibv_context, returned from mlx5dv_open_device. 3057 * @param[out] lag_ctx 3058 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 3059 * 3060 * @return 3061 * 0 on success, a negative value otherwise. 3062 */ 3063 int 3064 mlx5_devx_cmd_query_lag(void *ctx, 3065 struct mlx5_devx_lag_context *lag_ctx) 3066 { 3067 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 3068 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 3069 void *lctx; 3070 int rc; 3071 3072 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 3073 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 3074 if (rc) 3075 goto error; 3076 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 3077 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 3078 fdb_selection_mode); 3079 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 3080 port_select_mode); 3081 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 3082 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 3083 tx_remap_affinity_2); 3084 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 3085 tx_remap_affinity_1); 3086 return 0; 3087 error: 3088 rc = (rc > 0) ? -rc : rc; 3089 return rc; 3090 } 3091