1 // SPDX-License-Identifier: BSD-3-Clause 2 /* Copyright 2018 Mellanox Technologies, Ltd */ 3 4 #include <unistd.h> 5 6 #include <rte_errno.h> 7 #include <rte_malloc.h> 8 #include <rte_eal_paging.h> 9 10 #include "mlx5_prm.h" 11 #include "mlx5_devx_cmds.h" 12 #include "mlx5_common_utils.h" 13 #include "mlx5_malloc.h" 14 15 16 /** 17 * Perform read access to the registers. Reads data from register 18 * and writes ones to the specified buffer. 19 * 20 * @param[in] ctx 21 * Context returned from mlx5 open_device() glue function. 22 * @param[in] reg_id 23 * Register identifier according to the PRM. 24 * @param[in] arg 25 * Register access auxiliary parameter according to the PRM. 26 * @param[out] data 27 * Pointer to the buffer to store read data. 28 * @param[in] dw_cnt 29 * Buffer size in double words. 30 * 31 * @return 32 * 0 on success, a negative value otherwise. 33 */ 34 int 35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 36 uint32_t *data, uint32_t dw_cnt) 37 { 38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 41 int status, rc; 42 43 MLX5_ASSERT(data && dw_cnt); 44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 46 DRV_LOG(ERR, "Not enough buffer for register read data"); 47 return -1; 48 } 49 MLX5_SET(access_register_in, in, opcode, 50 MLX5_CMD_OP_ACCESS_REGISTER_USER); 51 MLX5_SET(access_register_in, in, op_mod, 52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 53 MLX5_SET(access_register_in, in, register_id, reg_id); 54 MLX5_SET(access_register_in, in, argument, arg); 55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 56 MLX5_ST_SZ_DW(access_register_out) * 57 sizeof(uint32_t) + dw_cnt); 58 if (rc) 59 goto error; 60 status = MLX5_GET(access_register_out, out, status); 61 if (status) { 62 int syndrome = MLX5_GET(access_register_out, out, syndrome); 63 64 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, " 65 "status %x, syndrome = %x", 66 reg_id, status, syndrome); 67 return -1; 68 } 69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 70 dw_cnt * sizeof(uint32_t)); 71 return 0; 72 error: 73 rc = (rc > 0) ? -rc : rc; 74 return rc; 75 } 76 77 /** 78 * Allocate flow counters via devx interface. 79 * 80 * @param[in] ctx 81 * Context returned from mlx5 open_device() glue function. 82 * @param dcs 83 * Pointer to counters properties structure to be filled by the routine. 84 * @param bulk_n_128 85 * Bulk counter numbers in 128 counters units. 86 * 87 * @return 88 * Pointer to counter object on success, a negative value otherwise and 89 * rte_errno is set. 90 */ 91 struct mlx5_devx_obj * 92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 93 { 94 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 95 0, SOCKET_ID_ANY); 96 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 97 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 98 99 if (!dcs) { 100 rte_errno = ENOMEM; 101 return NULL; 102 } 103 MLX5_SET(alloc_flow_counter_in, in, opcode, 104 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 105 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 106 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 107 sizeof(in), out, sizeof(out)); 108 if (!dcs->obj) { 109 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 110 rte_errno = errno; 111 mlx5_free(dcs); 112 return NULL; 113 } 114 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 115 return dcs; 116 } 117 118 /** 119 * Query flow counters values. 120 * 121 * @param[in] dcs 122 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 123 * @param[in] clear 124 * Whether hardware should clear the counters after the query or not. 125 * @param[in] n_counters 126 * 0 in case of 1 counter to read, otherwise the counter number to read. 127 * @param pkts 128 * The number of packets that matched the flow. 129 * @param bytes 130 * The number of bytes that matched the flow. 131 * @param mkey 132 * The mkey key for batch query. 133 * @param addr 134 * The address in the mkey range for batch query. 135 * @param cmd_comp 136 * The completion object for asynchronous batch query. 137 * @param async_id 138 * The ID to be returned in the asynchronous batch query response. 139 * 140 * @return 141 * 0 on success, a negative value otherwise. 142 */ 143 int 144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 145 int clear, uint32_t n_counters, 146 uint64_t *pkts, uint64_t *bytes, 147 uint32_t mkey, void *addr, 148 void *cmd_comp, 149 uint64_t async_id) 150 { 151 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 152 MLX5_ST_SZ_BYTES(traffic_counter); 153 uint32_t out[out_len]; 154 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 155 void *stats; 156 int rc; 157 158 MLX5_SET(query_flow_counter_in, in, opcode, 159 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 160 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 161 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 162 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 163 164 if (n_counters) { 165 MLX5_SET(query_flow_counter_in, in, num_of_counters, 166 n_counters); 167 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 168 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 169 MLX5_SET64(query_flow_counter_in, in, address, 170 (uint64_t)(uintptr_t)addr); 171 } 172 if (!cmd_comp) 173 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 174 out_len); 175 else 176 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 177 out_len, async_id, 178 cmd_comp); 179 if (rc) { 180 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 181 rte_errno = rc; 182 return -rc; 183 } 184 if (!n_counters) { 185 stats = MLX5_ADDR_OF(query_flow_counter_out, 186 out, flow_statistics); 187 *pkts = MLX5_GET64(traffic_counter, stats, packets); 188 *bytes = MLX5_GET64(traffic_counter, stats, octets); 189 } 190 return 0; 191 } 192 193 /** 194 * Create a new mkey. 195 * 196 * @param[in] ctx 197 * Context returned from mlx5 open_device() glue function. 198 * @param[in] attr 199 * Attributes of the requested mkey. 200 * 201 * @return 202 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 203 * is set. 204 */ 205 struct mlx5_devx_obj * 206 mlx5_devx_cmd_mkey_create(void *ctx, 207 struct mlx5_devx_mkey_attr *attr) 208 { 209 struct mlx5_klm *klm_array = attr->klm_array; 210 int klm_num = attr->klm_num; 211 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 212 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 213 uint32_t in[in_size_dw]; 214 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 215 void *mkc; 216 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 217 0, SOCKET_ID_ANY); 218 size_t pgsize; 219 uint32_t translation_size; 220 221 if (!mkey) { 222 rte_errno = ENOMEM; 223 return NULL; 224 } 225 memset(in, 0, in_size_dw * 4); 226 pgsize = rte_mem_page_size(); 227 if (pgsize == (size_t)-1) { 228 mlx5_free(mkey); 229 DRV_LOG(ERR, "Failed to get page size"); 230 rte_errno = ENOMEM; 231 return NULL; 232 } 233 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 234 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 235 if (klm_num > 0) { 236 int i; 237 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 238 klm_pas_mtt); 239 translation_size = RTE_ALIGN(klm_num, 4); 240 for (i = 0; i < klm_num; i++) { 241 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 242 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 243 MLX5_SET64(klm, klm, address, klm_array[i].address); 244 klm += MLX5_ST_SZ_BYTES(klm); 245 } 246 for (; i < (int)translation_size; i++) { 247 MLX5_SET(klm, klm, mkey, 0x0); 248 MLX5_SET64(klm, klm, address, 0x0); 249 klm += MLX5_ST_SZ_BYTES(klm); 250 } 251 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 252 MLX5_MKC_ACCESS_MODE_KLM_FBS : 253 MLX5_MKC_ACCESS_MODE_KLM); 254 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 255 } else { 256 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 257 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 258 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 259 } 260 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 261 translation_size); 262 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 263 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 264 MLX5_SET(mkc, mkc, lw, 0x1); 265 MLX5_SET(mkc, mkc, lr, 0x1); 266 MLX5_SET(mkc, mkc, qpn, 0xffffff); 267 MLX5_SET(mkc, mkc, pd, attr->pd); 268 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 269 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 270 if (attr->relaxed_ordering == 1) { 271 MLX5_SET(mkc, mkc, relaxed_ordering_write, 0x1); 272 MLX5_SET(mkc, mkc, relaxed_ordering_read, 0x1); 273 } 274 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 275 MLX5_SET64(mkc, mkc, len, attr->size); 276 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 277 sizeof(out)); 278 if (!mkey->obj) { 279 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d\n", 280 klm_num ? "an in" : "a ", errno); 281 rte_errno = errno; 282 mlx5_free(mkey); 283 return NULL; 284 } 285 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 286 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 287 return mkey; 288 } 289 290 /** 291 * Get status of devx command response. 292 * Mainly used for asynchronous commands. 293 * 294 * @param[in] out 295 * The out response buffer. 296 * 297 * @return 298 * 0 on success, non-zero value otherwise. 299 */ 300 int 301 mlx5_devx_get_out_command_status(void *out) 302 { 303 int status; 304 305 if (!out) 306 return -EINVAL; 307 status = MLX5_GET(query_flow_counter_out, out, status); 308 if (status) { 309 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 310 311 DRV_LOG(ERR, "Bad devX status %x, syndrome = %x", status, 312 syndrome); 313 } 314 return status; 315 } 316 317 /** 318 * Destroy any object allocated by a Devx API. 319 * 320 * @param[in] obj 321 * Pointer to a general object. 322 * 323 * @return 324 * 0 on success, a negative value otherwise. 325 */ 326 int 327 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 328 { 329 int ret; 330 331 if (!obj) 332 return 0; 333 ret = mlx5_glue->devx_obj_destroy(obj->obj); 334 mlx5_free(obj); 335 return ret; 336 } 337 338 /** 339 * Query NIC vport context. 340 * Fills minimal inline attribute. 341 * 342 * @param[in] ctx 343 * ibv contexts returned from mlx5dv_open_device. 344 * @param[in] vport 345 * vport index 346 * @param[out] attr 347 * Attributes device values. 348 * 349 * @return 350 * 0 on success, a negative value otherwise. 351 */ 352 static int 353 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 354 unsigned int vport, 355 struct mlx5_hca_attr *attr) 356 { 357 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 358 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 359 void *vctx; 360 int status, syndrome, rc; 361 362 /* Query NIC vport context to determine inline mode. */ 363 MLX5_SET(query_nic_vport_context_in, in, opcode, 364 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 365 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 366 if (vport) 367 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 368 rc = mlx5_glue->devx_general_cmd(ctx, 369 in, sizeof(in), 370 out, sizeof(out)); 371 if (rc) 372 goto error; 373 status = MLX5_GET(query_nic_vport_context_out, out, status); 374 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 375 if (status) { 376 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 377 "status %x, syndrome = %x", 378 status, syndrome); 379 return -1; 380 } 381 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 382 nic_vport_context); 383 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 384 min_wqe_inline_mode); 385 return 0; 386 error: 387 rc = (rc > 0) ? -rc : rc; 388 return rc; 389 } 390 391 /** 392 * Query NIC vDPA attributes. 393 * 394 * @param[in] ctx 395 * Context returned from mlx5 open_device() glue function. 396 * @param[out] vdpa_attr 397 * vDPA Attributes structure to fill. 398 */ 399 static void 400 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 401 struct mlx5_hca_vdpa_attr *vdpa_attr) 402 { 403 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 404 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 405 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 406 int status, syndrome, rc; 407 408 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 409 MLX5_SET(query_hca_cap_in, in, op_mod, 410 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 411 MLX5_HCA_CAP_OPMOD_GET_CUR); 412 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 413 status = MLX5_GET(query_hca_cap_out, out, status); 414 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 415 if (rc || status) { 416 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities," 417 " status %x, syndrome = %x", status, syndrome); 418 vdpa_attr->valid = 0; 419 } else { 420 vdpa_attr->valid = 1; 421 vdpa_attr->desc_tunnel_offload_type = 422 MLX5_GET(virtio_emulation_cap, hcattr, 423 desc_tunnel_offload_type); 424 vdpa_attr->eth_frame_offload_type = 425 MLX5_GET(virtio_emulation_cap, hcattr, 426 eth_frame_offload_type); 427 vdpa_attr->virtio_version_1_0 = 428 MLX5_GET(virtio_emulation_cap, hcattr, 429 virtio_version_1_0); 430 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 431 tso_ipv4); 432 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 433 tso_ipv6); 434 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 435 tx_csum); 436 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 437 rx_csum); 438 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 439 event_mode); 440 vdpa_attr->virtio_queue_type = 441 MLX5_GET(virtio_emulation_cap, hcattr, 442 virtio_queue_type); 443 vdpa_attr->log_doorbell_stride = 444 MLX5_GET(virtio_emulation_cap, hcattr, 445 log_doorbell_stride); 446 vdpa_attr->log_doorbell_bar_size = 447 MLX5_GET(virtio_emulation_cap, hcattr, 448 log_doorbell_bar_size); 449 vdpa_attr->doorbell_bar_offset = 450 MLX5_GET64(virtio_emulation_cap, hcattr, 451 doorbell_bar_offset); 452 vdpa_attr->max_num_virtio_queues = 453 MLX5_GET(virtio_emulation_cap, hcattr, 454 max_num_virtio_queues); 455 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 456 umem_1_buffer_param_a); 457 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 458 umem_1_buffer_param_b); 459 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 460 umem_2_buffer_param_a); 461 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 462 umem_2_buffer_param_b); 463 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 464 umem_3_buffer_param_a); 465 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 466 umem_3_buffer_param_b); 467 } 468 } 469 470 int 471 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 472 uint32_t ids[], uint32_t num) 473 { 474 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 475 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 476 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 477 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 478 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 479 int ret; 480 uint32_t idx = 0; 481 uint32_t i; 482 483 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 484 rte_errno = EINVAL; 485 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 486 return -rte_errno; 487 } 488 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 489 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 490 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 491 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 492 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 493 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 494 out, sizeof(out)); 495 if (ret) { 496 rte_errno = ret; 497 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 498 (void *)flex_obj); 499 return -rte_errno; 500 } 501 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 502 void *s_off = (void *)((char *)sample + i * 503 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 504 uint32_t en; 505 506 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 507 flow_match_sample_en); 508 if (!en) 509 continue; 510 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 511 flow_match_sample_field_id); 512 } 513 if (num != idx) { 514 rte_errno = EINVAL; 515 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 516 return -rte_errno; 517 } 518 return ret; 519 } 520 521 522 struct mlx5_devx_obj * 523 mlx5_devx_cmd_create_flex_parser(void *ctx, 524 struct mlx5_devx_graph_node_attr *data) 525 { 526 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 527 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 528 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 529 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 530 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 531 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 532 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 533 struct mlx5_devx_obj *parse_flex_obj = NULL; 534 uint32_t i; 535 536 parse_flex_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, 537 SOCKET_ID_ANY); 538 if (!parse_flex_obj) { 539 DRV_LOG(ERR, "Failed to allocate flex parser data"); 540 rte_errno = ENOMEM; 541 mlx5_free(in); 542 return NULL; 543 } 544 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 545 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 546 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 547 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 548 MLX5_SET(parse_graph_flex, flex, header_length_mode, 549 data->header_length_mode); 550 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 551 data->header_length_base_value); 552 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 553 data->header_length_field_offset); 554 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 555 data->header_length_field_shift); 556 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 557 data->header_length_field_mask); 558 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 559 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 560 void *s_off = (void *)((char *)sample + i * 561 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 562 563 if (!s->flow_match_sample_en) 564 continue; 565 MLX5_SET(parse_graph_flow_match_sample, s_off, 566 flow_match_sample_en, !!s->flow_match_sample_en); 567 MLX5_SET(parse_graph_flow_match_sample, s_off, 568 flow_match_sample_field_offset, 569 s->flow_match_sample_field_offset); 570 MLX5_SET(parse_graph_flow_match_sample, s_off, 571 flow_match_sample_offset_mode, 572 s->flow_match_sample_offset_mode); 573 MLX5_SET(parse_graph_flow_match_sample, s_off, 574 flow_match_sample_field_offset_mask, 575 s->flow_match_sample_field_offset_mask); 576 MLX5_SET(parse_graph_flow_match_sample, s_off, 577 flow_match_sample_field_offset_shift, 578 s->flow_match_sample_field_offset_shift); 579 MLX5_SET(parse_graph_flow_match_sample, s_off, 580 flow_match_sample_field_base_offset, 581 s->flow_match_sample_field_base_offset); 582 MLX5_SET(parse_graph_flow_match_sample, s_off, 583 flow_match_sample_tunnel_mode, 584 s->flow_match_sample_tunnel_mode); 585 } 586 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 587 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 588 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 589 void *in_off = (void *)((char *)in_arc + i * 590 MLX5_ST_SZ_BYTES(parse_graph_arc)); 591 void *out_off = (void *)((char *)out_arc + i * 592 MLX5_ST_SZ_BYTES(parse_graph_arc)); 593 594 if (ia->arc_parse_graph_node != 0) { 595 MLX5_SET(parse_graph_arc, in_off, 596 compare_condition_value, 597 ia->compare_condition_value); 598 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 599 ia->start_inner_tunnel); 600 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 601 ia->arc_parse_graph_node); 602 MLX5_SET(parse_graph_arc, in_off, 603 parse_graph_node_handle, 604 ia->parse_graph_node_handle); 605 } 606 if (oa->arc_parse_graph_node != 0) { 607 MLX5_SET(parse_graph_arc, out_off, 608 compare_condition_value, 609 oa->compare_condition_value); 610 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 611 oa->start_inner_tunnel); 612 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 613 oa->arc_parse_graph_node); 614 MLX5_SET(parse_graph_arc, out_off, 615 parse_graph_node_handle, 616 oa->parse_graph_node_handle); 617 } 618 } 619 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 620 out, sizeof(out)); 621 if (!parse_flex_obj->obj) { 622 rte_errno = errno; 623 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 624 "by using DevX."); 625 mlx5_free(parse_flex_obj); 626 return NULL; 627 } 628 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 629 return parse_flex_obj; 630 } 631 632 /** 633 * Query HCA attributes. 634 * Using those attributes we can check on run time if the device 635 * is having the required capabilities. 636 * 637 * @param[in] ctx 638 * Context returned from mlx5 open_device() glue function. 639 * @param[out] attr 640 * Attributes device values. 641 * 642 * @return 643 * 0 on success, a negative value otherwise. 644 */ 645 int 646 mlx5_devx_cmd_query_hca_attr(void *ctx, 647 struct mlx5_hca_attr *attr) 648 { 649 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 650 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 651 void *hcattr; 652 int status, syndrome, rc, i; 653 654 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 655 MLX5_SET(query_hca_cap_in, in, op_mod, 656 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 657 MLX5_HCA_CAP_OPMOD_GET_CUR); 658 659 rc = mlx5_glue->devx_general_cmd(ctx, 660 in, sizeof(in), out, sizeof(out)); 661 if (rc) 662 goto error; 663 status = MLX5_GET(query_hca_cap_out, out, status); 664 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 665 if (status) { 666 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 667 "status %x, syndrome = %x", 668 status, syndrome); 669 return -1; 670 } 671 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 672 attr->flow_counter_bulk_alloc_bitmap = 673 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 674 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 675 flow_counters_dump); 676 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 677 log_max_rqt_size); 678 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 679 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 680 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 681 log_max_hairpin_queues); 682 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 683 log_max_hairpin_wq_data_sz); 684 attr->log_max_hairpin_num_packets = MLX5_GET 685 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 686 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 687 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 688 relaxed_ordering_write); 689 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 690 relaxed_ordering_read); 691 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 692 access_register_user); 693 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 694 eth_net_offloads); 695 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 696 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 697 flex_parser_protocols); 698 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 699 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 700 general_obj_types) & 701 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 702 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 703 general_obj_types) & 704 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 705 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 706 general_obj_types) & 707 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 708 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 709 wqe_index_ignore_cap); 710 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 711 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 712 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 713 log_max_static_sq_wq); 714 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 715 device_frequency_khz); 716 attr->scatter_fcs_w_decap_disable = 717 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 718 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp); 719 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 720 regexp_num_of_engines); 721 if (attr->qos.sup) { 722 MLX5_SET(query_hca_cap_in, in, op_mod, 723 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 724 MLX5_HCA_CAP_OPMOD_GET_CUR); 725 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 726 out, sizeof(out)); 727 if (rc) 728 goto error; 729 if (status) { 730 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities," 731 " status %x, syndrome = %x", 732 status, syndrome); 733 return -1; 734 } 735 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 736 attr->qos.srtcm_sup = 737 MLX5_GET(qos_cap, hcattr, flow_meter_srtcm); 738 attr->qos.log_max_flow_meter = 739 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 740 attr->qos.flow_meter_reg_c_ids = 741 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 742 attr->qos.flow_meter_reg_share = 743 MLX5_GET(qos_cap, hcattr, flow_meter_reg_share); 744 attr->qos.packet_pacing = 745 MLX5_GET(qos_cap, hcattr, packet_pacing); 746 attr->qos.wqe_rate_pp = 747 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 748 } 749 if (attr->vdpa.valid) 750 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 751 if (!attr->eth_net_offloads) 752 return 0; 753 754 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 755 memset(in, 0, sizeof(in)); 756 memset(out, 0, sizeof(out)); 757 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 758 MLX5_SET(query_hca_cap_in, in, op_mod, 759 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 760 MLX5_HCA_CAP_OPMOD_GET_CUR); 761 762 rc = mlx5_glue->devx_general_cmd(ctx, 763 in, sizeof(in), 764 out, sizeof(out)); 765 if (rc) 766 goto error; 767 status = MLX5_GET(query_hca_cap_out, out, status); 768 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 769 if (status) { 770 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 771 "status %x, syndrome = %x", 772 status, syndrome); 773 attr->log_max_ft_sampler_num = 0; 774 return -1; 775 } 776 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 777 attr->log_max_ft_sampler_num = 778 MLX5_GET(flow_table_nic_cap, 779 hcattr, flow_table_properties.log_max_ft_sampler_num); 780 781 /* Query HCA offloads for Ethernet protocol. */ 782 memset(in, 0, sizeof(in)); 783 memset(out, 0, sizeof(out)); 784 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 785 MLX5_SET(query_hca_cap_in, in, op_mod, 786 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 787 MLX5_HCA_CAP_OPMOD_GET_CUR); 788 789 rc = mlx5_glue->devx_general_cmd(ctx, 790 in, sizeof(in), 791 out, sizeof(out)); 792 if (rc) { 793 attr->eth_net_offloads = 0; 794 goto error; 795 } 796 status = MLX5_GET(query_hca_cap_out, out, status); 797 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 798 if (status) { 799 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 800 "status %x, syndrome = %x", 801 status, syndrome); 802 attr->eth_net_offloads = 0; 803 return -1; 804 } 805 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 806 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 807 hcattr, wqe_vlan_insert); 808 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 809 lro_cap); 810 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 811 hcattr, tunnel_lro_gre); 812 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 813 hcattr, tunnel_lro_vxlan); 814 attr->lro_max_msg_sz_mode = MLX5_GET 815 (per_protocol_networking_offload_caps, 816 hcattr, lro_max_msg_sz_mode); 817 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 818 attr->lro_timer_supported_periods[i] = 819 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 820 lro_timer_supported_periods[i]); 821 } 822 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 823 hcattr, lro_min_mss_size); 824 attr->tunnel_stateless_geneve_rx = 825 MLX5_GET(per_protocol_networking_offload_caps, 826 hcattr, tunnel_stateless_geneve_rx); 827 attr->geneve_max_opt_len = 828 MLX5_GET(per_protocol_networking_offload_caps, 829 hcattr, max_geneve_opt_len); 830 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 831 hcattr, wqe_inline_mode); 832 attr->tunnel_stateless_gtp = MLX5_GET 833 (per_protocol_networking_offload_caps, 834 hcattr, tunnel_stateless_gtp); 835 if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) 836 return 0; 837 if (attr->eth_virt) { 838 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 839 if (rc) { 840 attr->eth_virt = 0; 841 goto error; 842 } 843 } 844 return 0; 845 error: 846 rc = (rc > 0) ? -rc : rc; 847 return rc; 848 } 849 850 /** 851 * Query TIS transport domain from QP verbs object using DevX API. 852 * 853 * @param[in] qp 854 * Pointer to verbs QP returned by ibv_create_qp . 855 * @param[in] tis_num 856 * TIS number of TIS to query. 857 * @param[out] tis_td 858 * Pointer to TIS transport domain variable, to be set by the routine. 859 * 860 * @return 861 * 0 on success, a negative value otherwise. 862 */ 863 int 864 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 865 uint32_t *tis_td) 866 { 867 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 868 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 869 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 870 int rc; 871 void *tis_ctx; 872 873 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 874 MLX5_SET(query_tis_in, in, tisn, tis_num); 875 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 876 if (rc) { 877 DRV_LOG(ERR, "Failed to query QP using DevX"); 878 return -rc; 879 }; 880 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 881 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 882 return 0; 883 #else 884 (void)qp; 885 (void)tis_num; 886 (void)tis_td; 887 return -ENOTSUP; 888 #endif 889 } 890 891 /** 892 * Fill WQ data for DevX API command. 893 * Utility function for use when creating DevX objects containing a WQ. 894 * 895 * @param[in] wq_ctx 896 * Pointer to WQ context to fill with data. 897 * @param [in] wq_attr 898 * Pointer to WQ attributes structure to fill in WQ context. 899 */ 900 static void 901 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 902 { 903 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 904 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 905 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 906 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 907 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 908 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 909 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 910 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 911 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 912 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 913 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 914 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 915 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 916 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 917 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz); 918 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 919 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 920 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 921 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 922 wq_attr->log_hairpin_num_packets); 923 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 924 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 925 wq_attr->single_wqe_log_num_of_strides); 926 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 927 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 928 wq_attr->single_stride_log_num_of_bytes); 929 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 930 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 931 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 932 } 933 934 /** 935 * Create RQ using DevX API. 936 * 937 * @param[in] ctx 938 * Context returned from mlx5 open_device() glue function. 939 * @param [in] rq_attr 940 * Pointer to create RQ attributes structure. 941 * @param [in] socket 942 * CPU socket ID for allocations. 943 * 944 * @return 945 * The DevX object created, NULL otherwise and rte_errno is set. 946 */ 947 struct mlx5_devx_obj * 948 mlx5_devx_cmd_create_rq(void *ctx, 949 struct mlx5_devx_create_rq_attr *rq_attr, 950 int socket) 951 { 952 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 953 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 954 void *rq_ctx, *wq_ctx; 955 struct mlx5_devx_wq_attr *wq_attr; 956 struct mlx5_devx_obj *rq = NULL; 957 958 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 959 if (!rq) { 960 DRV_LOG(ERR, "Failed to allocate RQ data"); 961 rte_errno = ENOMEM; 962 return NULL; 963 } 964 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 965 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 966 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 967 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 968 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 969 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 970 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 971 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 972 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 973 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 974 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 975 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 976 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 977 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 978 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 979 wq_attr = &rq_attr->wq_attr; 980 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 981 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 982 out, sizeof(out)); 983 if (!rq->obj) { 984 DRV_LOG(ERR, "Failed to create RQ using DevX"); 985 rte_errno = errno; 986 mlx5_free(rq); 987 return NULL; 988 } 989 rq->id = MLX5_GET(create_rq_out, out, rqn); 990 return rq; 991 } 992 993 /** 994 * Modify RQ using DevX API. 995 * 996 * @param[in] rq 997 * Pointer to RQ object structure. 998 * @param [in] rq_attr 999 * Pointer to modify RQ attributes structure. 1000 * 1001 * @return 1002 * 0 on success, a negative errno value otherwise and rte_errno is set. 1003 */ 1004 int 1005 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1006 struct mlx5_devx_modify_rq_attr *rq_attr) 1007 { 1008 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1009 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1010 void *rq_ctx, *wq_ctx; 1011 int ret; 1012 1013 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1014 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1015 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1016 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1017 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1018 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1019 if (rq_attr->modify_bitmask & 1020 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1021 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1022 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1023 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1024 if (rq_attr->modify_bitmask & 1025 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1026 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1027 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1028 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1029 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1030 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1031 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1032 } 1033 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1034 out, sizeof(out)); 1035 if (ret) { 1036 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1037 rte_errno = errno; 1038 return -errno; 1039 } 1040 return ret; 1041 } 1042 1043 /** 1044 * Create TIR using DevX API. 1045 * 1046 * @param[in] ctx 1047 * Context returned from mlx5 open_device() glue function. 1048 * @param [in] tir_attr 1049 * Pointer to TIR attributes structure. 1050 * 1051 * @return 1052 * The DevX object created, NULL otherwise and rte_errno is set. 1053 */ 1054 struct mlx5_devx_obj * 1055 mlx5_devx_cmd_create_tir(void *ctx, 1056 struct mlx5_devx_tir_attr *tir_attr) 1057 { 1058 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1059 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1060 void *tir_ctx, *outer, *inner, *rss_key; 1061 struct mlx5_devx_obj *tir = NULL; 1062 1063 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1064 if (!tir) { 1065 DRV_LOG(ERR, "Failed to allocate TIR data"); 1066 rte_errno = ENOMEM; 1067 return NULL; 1068 } 1069 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1070 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1071 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1072 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1073 tir_attr->lro_timeout_period_usecs); 1074 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1075 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1076 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1077 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1078 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1079 tir_attr->tunneled_offload_en); 1080 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1081 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1082 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1083 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1084 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1085 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1086 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1087 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1088 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1089 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1090 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1091 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1092 tir_attr->rx_hash_field_selector_outer.selected_fields); 1093 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1094 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1095 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1096 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1097 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1098 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1099 tir_attr->rx_hash_field_selector_inner.selected_fields); 1100 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1101 out, sizeof(out)); 1102 if (!tir->obj) { 1103 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1104 rte_errno = errno; 1105 mlx5_free(tir); 1106 return NULL; 1107 } 1108 tir->id = MLX5_GET(create_tir_out, out, tirn); 1109 return tir; 1110 } 1111 1112 /** 1113 * Modify TIR using DevX API. 1114 * 1115 * @param[in] tir 1116 * Pointer to TIR DevX object structure. 1117 * @param [in] modify_tir_attr 1118 * Pointer to TIR modification attributes structure. 1119 * 1120 * @return 1121 * 0 on success, a negative errno value otherwise and rte_errno is set. 1122 */ 1123 int 1124 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1125 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1126 { 1127 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1128 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1129 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1130 void *tir_ctx; 1131 int ret; 1132 1133 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1134 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1135 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1136 modify_tir_attr->modify_bitmask); 1137 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1138 if (modify_tir_attr->modify_bitmask & 1139 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1140 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1141 tir_attr->lro_timeout_period_usecs); 1142 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1143 tir_attr->lro_enable_mask); 1144 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1145 tir_attr->lro_max_msg_sz); 1146 } 1147 if (modify_tir_attr->modify_bitmask & 1148 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1149 MLX5_SET(tirc, tir_ctx, indirect_table, 1150 tir_attr->indirect_table); 1151 if (modify_tir_attr->modify_bitmask & 1152 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1153 int i; 1154 void *outer, *inner; 1155 1156 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1157 tir_attr->rx_hash_symmetric); 1158 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1159 for (i = 0; i < 10; i++) { 1160 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1161 tir_attr->rx_hash_toeplitz_key[i]); 1162 } 1163 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1164 rx_hash_field_selector_outer); 1165 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1166 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1167 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1168 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1169 MLX5_SET 1170 (rx_hash_field_select, outer, selected_fields, 1171 tir_attr->rx_hash_field_selector_outer.selected_fields); 1172 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1173 rx_hash_field_selector_inner); 1174 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1175 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1176 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1177 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1178 MLX5_SET 1179 (rx_hash_field_select, inner, selected_fields, 1180 tir_attr->rx_hash_field_selector_inner.selected_fields); 1181 } 1182 if (modify_tir_attr->modify_bitmask & 1183 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1184 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1185 } 1186 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1187 out, sizeof(out)); 1188 if (ret) { 1189 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1190 rte_errno = errno; 1191 return -errno; 1192 } 1193 return ret; 1194 } 1195 1196 /** 1197 * Create RQT using DevX API. 1198 * 1199 * @param[in] ctx 1200 * Context returned from mlx5 open_device() glue function. 1201 * @param [in] rqt_attr 1202 * Pointer to RQT attributes structure. 1203 * 1204 * @return 1205 * The DevX object created, NULL otherwise and rte_errno is set. 1206 */ 1207 struct mlx5_devx_obj * 1208 mlx5_devx_cmd_create_rqt(void *ctx, 1209 struct mlx5_devx_rqt_attr *rqt_attr) 1210 { 1211 uint32_t *in = NULL; 1212 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1213 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1214 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1215 void *rqt_ctx; 1216 struct mlx5_devx_obj *rqt = NULL; 1217 int i; 1218 1219 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1220 if (!in) { 1221 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1222 rte_errno = ENOMEM; 1223 return NULL; 1224 } 1225 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1226 if (!rqt) { 1227 DRV_LOG(ERR, "Failed to allocate RQT data"); 1228 rte_errno = ENOMEM; 1229 mlx5_free(in); 1230 return NULL; 1231 } 1232 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1233 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1234 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1235 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1236 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1237 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1238 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1239 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1240 mlx5_free(in); 1241 if (!rqt->obj) { 1242 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1243 rte_errno = errno; 1244 mlx5_free(rqt); 1245 return NULL; 1246 } 1247 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1248 return rqt; 1249 } 1250 1251 /** 1252 * Modify RQT using DevX API. 1253 * 1254 * @param[in] rqt 1255 * Pointer to RQT DevX object structure. 1256 * @param [in] rqt_attr 1257 * Pointer to RQT attributes structure. 1258 * 1259 * @return 1260 * 0 on success, a negative errno value otherwise and rte_errno is set. 1261 */ 1262 int 1263 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1264 struct mlx5_devx_rqt_attr *rqt_attr) 1265 { 1266 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1267 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1268 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1269 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1270 void *rqt_ctx; 1271 int i; 1272 int ret; 1273 1274 if (!in) { 1275 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1276 rte_errno = ENOMEM; 1277 return -ENOMEM; 1278 } 1279 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1280 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1281 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1282 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1283 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1284 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1285 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1286 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1287 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1288 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1289 mlx5_free(in); 1290 if (ret) { 1291 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1292 rte_errno = errno; 1293 return -rte_errno; 1294 } 1295 return ret; 1296 } 1297 1298 /** 1299 * Create SQ using DevX API. 1300 * 1301 * @param[in] ctx 1302 * Context returned from mlx5 open_device() glue function. 1303 * @param [in] sq_attr 1304 * Pointer to SQ attributes structure. 1305 * @param [in] socket 1306 * CPU socket ID for allocations. 1307 * 1308 * @return 1309 * The DevX object created, NULL otherwise and rte_errno is set. 1310 **/ 1311 struct mlx5_devx_obj * 1312 mlx5_devx_cmd_create_sq(void *ctx, 1313 struct mlx5_devx_create_sq_attr *sq_attr) 1314 { 1315 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1316 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1317 void *sq_ctx; 1318 void *wq_ctx; 1319 struct mlx5_devx_wq_attr *wq_attr; 1320 struct mlx5_devx_obj *sq = NULL; 1321 1322 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1323 if (!sq) { 1324 DRV_LOG(ERR, "Failed to allocate SQ data"); 1325 rte_errno = ENOMEM; 1326 return NULL; 1327 } 1328 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1329 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1330 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1331 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1332 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1333 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1334 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1335 sq_attr->flush_in_error_en); 1336 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1337 sq_attr->min_wqe_inline_mode); 1338 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1339 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1340 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1341 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1342 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1343 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1344 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1345 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1346 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1347 sq_attr->packet_pacing_rate_limit_index); 1348 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1349 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1350 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1351 wq_attr = &sq_attr->wq_attr; 1352 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1353 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1354 out, sizeof(out)); 1355 if (!sq->obj) { 1356 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1357 rte_errno = errno; 1358 mlx5_free(sq); 1359 return NULL; 1360 } 1361 sq->id = MLX5_GET(create_sq_out, out, sqn); 1362 return sq; 1363 } 1364 1365 /** 1366 * Modify SQ using DevX API. 1367 * 1368 * @param[in] sq 1369 * Pointer to SQ object structure. 1370 * @param [in] sq_attr 1371 * Pointer to SQ attributes structure. 1372 * 1373 * @return 1374 * 0 on success, a negative errno value otherwise and rte_errno is set. 1375 */ 1376 int 1377 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1378 struct mlx5_devx_modify_sq_attr *sq_attr) 1379 { 1380 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1381 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1382 void *sq_ctx; 1383 int ret; 1384 1385 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1386 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1387 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1388 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1389 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1390 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1391 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1392 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1393 out, sizeof(out)); 1394 if (ret) { 1395 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1396 rte_errno = errno; 1397 return -rte_errno; 1398 } 1399 return ret; 1400 } 1401 1402 /** 1403 * Create TIS using DevX API. 1404 * 1405 * @param[in] ctx 1406 * Context returned from mlx5 open_device() glue function. 1407 * @param [in] tis_attr 1408 * Pointer to TIS attributes structure. 1409 * 1410 * @return 1411 * The DevX object created, NULL otherwise and rte_errno is set. 1412 */ 1413 struct mlx5_devx_obj * 1414 mlx5_devx_cmd_create_tis(void *ctx, 1415 struct mlx5_devx_tis_attr *tis_attr) 1416 { 1417 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1418 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1419 struct mlx5_devx_obj *tis = NULL; 1420 void *tis_ctx; 1421 1422 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1423 if (!tis) { 1424 DRV_LOG(ERR, "Failed to allocate TIS object"); 1425 rte_errno = ENOMEM; 1426 return NULL; 1427 } 1428 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1429 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1430 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1431 tis_attr->strict_lag_tx_port_affinity); 1432 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1433 tis_attr->strict_lag_tx_port_affinity); 1434 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1435 MLX5_SET(tisc, tis_ctx, transport_domain, 1436 tis_attr->transport_domain); 1437 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1438 out, sizeof(out)); 1439 if (!tis->obj) { 1440 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1441 rte_errno = errno; 1442 mlx5_free(tis); 1443 return NULL; 1444 } 1445 tis->id = MLX5_GET(create_tis_out, out, tisn); 1446 return tis; 1447 } 1448 1449 /** 1450 * Create transport domain using DevX API. 1451 * 1452 * @param[in] ctx 1453 * Context returned from mlx5 open_device() glue function. 1454 * @return 1455 * The DevX object created, NULL otherwise and rte_errno is set. 1456 */ 1457 struct mlx5_devx_obj * 1458 mlx5_devx_cmd_create_td(void *ctx) 1459 { 1460 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1461 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1462 struct mlx5_devx_obj *td = NULL; 1463 1464 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1465 if (!td) { 1466 DRV_LOG(ERR, "Failed to allocate TD object"); 1467 rte_errno = ENOMEM; 1468 return NULL; 1469 } 1470 MLX5_SET(alloc_transport_domain_in, in, opcode, 1471 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1472 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1473 out, sizeof(out)); 1474 if (!td->obj) { 1475 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1476 rte_errno = errno; 1477 mlx5_free(td); 1478 return NULL; 1479 } 1480 td->id = MLX5_GET(alloc_transport_domain_out, out, 1481 transport_domain); 1482 return td; 1483 } 1484 1485 /** 1486 * Dump all flows to file. 1487 * 1488 * @param[in] fdb_domain 1489 * FDB domain. 1490 * @param[in] rx_domain 1491 * RX domain. 1492 * @param[in] tx_domain 1493 * TX domain. 1494 * @param[out] file 1495 * Pointer to file stream. 1496 * 1497 * @return 1498 * 0 on success, a nagative value otherwise. 1499 */ 1500 int 1501 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1502 void *rx_domain __rte_unused, 1503 void *tx_domain __rte_unused, FILE *file __rte_unused) 1504 { 1505 int ret = 0; 1506 1507 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1508 if (fdb_domain) { 1509 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1510 if (ret) 1511 return ret; 1512 } 1513 MLX5_ASSERT(rx_domain); 1514 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1515 if (ret) 1516 return ret; 1517 MLX5_ASSERT(tx_domain); 1518 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1519 #else 1520 ret = ENOTSUP; 1521 #endif 1522 return -ret; 1523 } 1524 1525 /* 1526 * Create CQ using DevX API. 1527 * 1528 * @param[in] ctx 1529 * Context returned from mlx5 open_device() glue function. 1530 * @param [in] attr 1531 * Pointer to CQ attributes structure. 1532 * 1533 * @return 1534 * The DevX object created, NULL otherwise and rte_errno is set. 1535 */ 1536 struct mlx5_devx_obj * 1537 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1538 { 1539 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1540 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1541 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1542 sizeof(*cq_obj), 1543 0, SOCKET_ID_ANY); 1544 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1545 1546 if (!cq_obj) { 1547 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1548 rte_errno = ENOMEM; 1549 return NULL; 1550 } 1551 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1552 if (attr->db_umem_valid) { 1553 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1554 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1555 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1556 } else { 1557 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1558 } 1559 MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size); 1560 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1561 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1562 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1563 MLX5_SET(cqc, cqctx, log_page_size, attr->log_page_size - 1564 MLX5_ADAPTER_PAGE_SHIFT); 1565 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1566 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1567 MLX5_SET(cqc, cqctx, cqe_comp_en, attr->cqe_comp_en); 1568 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1569 MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size); 1570 if (attr->q_umem_valid) { 1571 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1572 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1573 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1574 attr->q_umem_offset); 1575 } 1576 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1577 sizeof(out)); 1578 if (!cq_obj->obj) { 1579 rte_errno = errno; 1580 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1581 mlx5_free(cq_obj); 1582 return NULL; 1583 } 1584 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1585 return cq_obj; 1586 } 1587 1588 /** 1589 * Create VIRTQ using DevX API. 1590 * 1591 * @param[in] ctx 1592 * Context returned from mlx5 open_device() glue function. 1593 * @param [in] attr 1594 * Pointer to VIRTQ attributes structure. 1595 * 1596 * @return 1597 * The DevX object created, NULL otherwise and rte_errno is set. 1598 */ 1599 struct mlx5_devx_obj * 1600 mlx5_devx_cmd_create_virtq(void *ctx, 1601 struct mlx5_devx_virtq_attr *attr) 1602 { 1603 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1604 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1605 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1606 sizeof(*virtq_obj), 1607 0, SOCKET_ID_ANY); 1608 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1609 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1610 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1611 1612 if (!virtq_obj) { 1613 DRV_LOG(ERR, "Failed to allocate virtq data."); 1614 rte_errno = ENOMEM; 1615 return NULL; 1616 } 1617 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1618 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1619 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1620 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1621 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1622 attr->hw_available_index); 1623 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1624 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1625 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1626 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1627 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1628 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1629 attr->virtio_version_1_0); 1630 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1631 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1632 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1633 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1634 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1635 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1636 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1637 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1638 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1639 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 1640 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 1641 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 1642 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 1643 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 1644 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 1645 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 1646 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 1647 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 1648 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 1649 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 1650 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1651 sizeof(out)); 1652 if (!virtq_obj->obj) { 1653 rte_errno = errno; 1654 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 1655 mlx5_free(virtq_obj); 1656 return NULL; 1657 } 1658 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1659 return virtq_obj; 1660 } 1661 1662 /** 1663 * Modify VIRTQ using DevX API. 1664 * 1665 * @param[in] virtq_obj 1666 * Pointer to virtq object structure. 1667 * @param [in] attr 1668 * Pointer to modify virtq attributes structure. 1669 * 1670 * @return 1671 * 0 on success, a negative errno value otherwise and rte_errno is set. 1672 */ 1673 int 1674 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 1675 struct mlx5_devx_virtq_attr *attr) 1676 { 1677 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1678 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1679 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1680 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1681 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1682 int ret; 1683 1684 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1685 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 1686 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1687 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1688 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1689 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 1690 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1691 switch (attr->type) { 1692 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 1693 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 1694 break; 1695 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 1696 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 1697 attr->dirty_bitmap_mkey); 1698 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 1699 attr->dirty_bitmap_addr); 1700 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 1701 attr->dirty_bitmap_size); 1702 break; 1703 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 1704 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 1705 attr->dirty_bitmap_dump_enable); 1706 break; 1707 default: 1708 rte_errno = EINVAL; 1709 return -rte_errno; 1710 } 1711 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 1712 out, sizeof(out)); 1713 if (ret) { 1714 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1715 rte_errno = errno; 1716 return -rte_errno; 1717 } 1718 return ret; 1719 } 1720 1721 /** 1722 * Query VIRTQ using DevX API. 1723 * 1724 * @param[in] virtq_obj 1725 * Pointer to virtq object structure. 1726 * @param [in/out] attr 1727 * Pointer to virtq attributes structure. 1728 * 1729 * @return 1730 * 0 on success, a negative errno value otherwise and rte_errno is set. 1731 */ 1732 int 1733 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 1734 struct mlx5_devx_virtq_attr *attr) 1735 { 1736 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1737 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 1738 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 1739 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 1740 int ret; 1741 1742 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1743 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1744 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1745 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1746 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1747 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 1748 out, sizeof(out)); 1749 if (ret) { 1750 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1751 rte_errno = errno; 1752 return -errno; 1753 } 1754 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 1755 hw_available_index); 1756 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 1757 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 1758 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 1759 virtio_q_context.error_type); 1760 return ret; 1761 } 1762 1763 /** 1764 * Create QP using DevX API. 1765 * 1766 * @param[in] ctx 1767 * Context returned from mlx5 open_device() glue function. 1768 * @param [in] attr 1769 * Pointer to QP attributes structure. 1770 * 1771 * @return 1772 * The DevX object created, NULL otherwise and rte_errno is set. 1773 */ 1774 struct mlx5_devx_obj * 1775 mlx5_devx_cmd_create_qp(void *ctx, 1776 struct mlx5_devx_qp_attr *attr) 1777 { 1778 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 1779 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 1780 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 1781 sizeof(*qp_obj), 1782 0, SOCKET_ID_ANY); 1783 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1784 1785 if (!qp_obj) { 1786 DRV_LOG(ERR, "Failed to allocate QP data."); 1787 rte_errno = ENOMEM; 1788 return NULL; 1789 } 1790 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 1791 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 1792 MLX5_SET(qpc, qpc, pd, attr->pd); 1793 if (attr->uar_index) { 1794 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1795 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 1796 MLX5_SET(qpc, qpc, log_page_size, attr->log_page_size - 1797 MLX5_ADAPTER_PAGE_SHIFT); 1798 if (attr->sq_size) { 1799 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); 1800 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 1801 MLX5_SET(qpc, qpc, log_sq_size, 1802 rte_log2_u32(attr->sq_size)); 1803 } else { 1804 MLX5_SET(qpc, qpc, no_sq, 1); 1805 } 1806 if (attr->rq_size) { 1807 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); 1808 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 1809 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 1810 MLX5_LOG_RQ_STRIDE_SHIFT); 1811 MLX5_SET(qpc, qpc, log_rq_size, 1812 rte_log2_u32(attr->rq_size)); 1813 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 1814 } else { 1815 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1816 } 1817 if (attr->dbr_umem_valid) { 1818 MLX5_SET(qpc, qpc, dbr_umem_valid, 1819 attr->dbr_umem_valid); 1820 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 1821 } 1822 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 1823 MLX5_SET64(create_qp_in, in, wq_umem_offset, 1824 attr->wq_umem_offset); 1825 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 1826 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 1827 } else { 1828 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 1829 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1830 MLX5_SET(qpc, qpc, no_sq, 1); 1831 } 1832 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1833 sizeof(out)); 1834 if (!qp_obj->obj) { 1835 rte_errno = errno; 1836 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 1837 mlx5_free(qp_obj); 1838 return NULL; 1839 } 1840 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 1841 return qp_obj; 1842 } 1843 1844 /** 1845 * Modify QP using DevX API. 1846 * Currently supports only force loop-back QP. 1847 * 1848 * @param[in] qp 1849 * Pointer to QP object structure. 1850 * @param [in] qp_st_mod_op 1851 * The QP state modification operation. 1852 * @param [in] remote_qp_id 1853 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 1854 * 1855 * @return 1856 * 0 on success, a negative errno value otherwise and rte_errno is set. 1857 */ 1858 int 1859 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 1860 uint32_t remote_qp_id) 1861 { 1862 union { 1863 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 1864 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 1865 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 1866 } in; 1867 union { 1868 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 1869 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 1870 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 1871 } out; 1872 void *qpc; 1873 int ret; 1874 unsigned int inlen; 1875 unsigned int outlen; 1876 1877 memset(&in, 0, sizeof(in)); 1878 memset(&out, 0, sizeof(out)); 1879 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 1880 switch (qp_st_mod_op) { 1881 case MLX5_CMD_OP_RST2INIT_QP: 1882 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 1883 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 1884 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1885 MLX5_SET(qpc, qpc, rre, 1); 1886 MLX5_SET(qpc, qpc, rwe, 1); 1887 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1888 inlen = sizeof(in.rst2init); 1889 outlen = sizeof(out.rst2init); 1890 break; 1891 case MLX5_CMD_OP_INIT2RTR_QP: 1892 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 1893 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 1894 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 1895 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1896 MLX5_SET(qpc, qpc, mtu, 1); 1897 MLX5_SET(qpc, qpc, log_msg_max, 30); 1898 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 1899 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 1900 inlen = sizeof(in.init2rtr); 1901 outlen = sizeof(out.init2rtr); 1902 break; 1903 case MLX5_CMD_OP_RTR2RTS_QP: 1904 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 1905 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 1906 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 1907 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 1908 MLX5_SET(qpc, qpc, retry_count, 7); 1909 MLX5_SET(qpc, qpc, rnr_retry, 7); 1910 inlen = sizeof(in.rtr2rts); 1911 outlen = sizeof(out.rtr2rts); 1912 break; 1913 default: 1914 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 1915 qp_st_mod_op); 1916 rte_errno = EINVAL; 1917 return -rte_errno; 1918 } 1919 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 1920 if (ret) { 1921 DRV_LOG(ERR, "Failed to modify QP using DevX."); 1922 rte_errno = errno; 1923 return -rte_errno; 1924 } 1925 return ret; 1926 } 1927 1928 struct mlx5_devx_obj * 1929 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 1930 { 1931 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 1932 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1933 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 1934 sizeof(*couners_obj), 0, 1935 SOCKET_ID_ANY); 1936 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 1937 1938 if (!couners_obj) { 1939 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 1940 rte_errno = ENOMEM; 1941 return NULL; 1942 } 1943 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1944 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1945 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1946 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 1947 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1948 sizeof(out)); 1949 if (!couners_obj->obj) { 1950 rte_errno = errno; 1951 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 1952 " DevX."); 1953 mlx5_free(couners_obj); 1954 return NULL; 1955 } 1956 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1957 return couners_obj; 1958 } 1959 1960 int 1961 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 1962 struct mlx5_devx_virtio_q_couners_attr *attr) 1963 { 1964 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1965 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 1966 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 1967 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 1968 virtio_q_counters); 1969 int ret; 1970 1971 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1972 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1973 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1974 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 1975 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 1976 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 1977 sizeof(out)); 1978 if (ret) { 1979 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 1980 rte_errno = errno; 1981 return -errno; 1982 } 1983 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 1984 received_desc); 1985 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 1986 completed_desc); 1987 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 1988 error_cqes); 1989 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 1990 bad_desc_errors); 1991 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 1992 exceed_max_chain); 1993 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 1994 invalid_buffer); 1995 return ret; 1996 } 1997