1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /** 17 * Perform read access to the registers. Reads data from register 18 * and writes ones to the specified buffer. 19 * 20 * @param[in] ctx 21 * Context returned from mlx5 open_device() glue function. 22 * @param[in] reg_id 23 * Register identifier according to the PRM. 24 * @param[in] arg 25 * Register access auxiliary parameter according to the PRM. 26 * @param[out] data 27 * Pointer to the buffer to store read data. 28 * @param[in] dw_cnt 29 * Buffer size in double words. 30 * 31 * @return 32 * 0 on success, a negative value otherwise. 33 */ 34 int 35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 36 uint32_t *data, uint32_t dw_cnt) 37 { 38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 41 int status, rc; 42 43 MLX5_ASSERT(data && dw_cnt); 44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 46 DRV_LOG(ERR, "Not enough buffer for register read data"); 47 return -1; 48 } 49 MLX5_SET(access_register_in, in, opcode, 50 MLX5_CMD_OP_ACCESS_REGISTER_USER); 51 MLX5_SET(access_register_in, in, op_mod, 52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 53 MLX5_SET(access_register_in, in, register_id, reg_id); 54 MLX5_SET(access_register_in, in, argument, arg); 55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 56 MLX5_ST_SZ_BYTES(access_register_out) + 57 sizeof(uint32_t) * dw_cnt); 58 if (rc) 59 goto error; 60 status = MLX5_GET(access_register_out, out, status); 61 if (status) { 62 int syndrome = MLX5_GET(access_register_out, out, syndrome); 63 64 DRV_LOG(DEBUG, "Failed to read access NIC register 0x%X, " 65 "status %x, syndrome = %x", 66 reg_id, status, syndrome); 67 return -1; 68 } 69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 70 dw_cnt * sizeof(uint32_t)); 71 return 0; 72 error: 73 rc = (rc > 0) ? -rc : rc; 74 return rc; 75 } 76 77 /** 78 * Perform write access to the registers. 79 * 80 * @param[in] ctx 81 * Context returned from mlx5 open_device() glue function. 82 * @param[in] reg_id 83 * Register identifier according to the PRM. 84 * @param[in] arg 85 * Register access auxiliary parameter according to the PRM. 86 * @param[out] data 87 * Pointer to the buffer containing data to write. 88 * @param[in] dw_cnt 89 * Buffer size in double words (32bit units). 90 * 91 * @return 92 * 0 on success, a negative value otherwise. 93 */ 94 int 95 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 96 uint32_t *data, uint32_t dw_cnt) 97 { 98 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 99 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 100 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 101 int status, rc; 102 void *ptr; 103 104 MLX5_ASSERT(data && dw_cnt); 105 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 106 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 107 DRV_LOG(ERR, "Data to write exceeds max size"); 108 return -1; 109 } 110 MLX5_SET(access_register_in, in, opcode, 111 MLX5_CMD_OP_ACCESS_REGISTER_USER); 112 MLX5_SET(access_register_in, in, op_mod, 113 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 114 MLX5_SET(access_register_in, in, register_id, reg_id); 115 MLX5_SET(access_register_in, in, argument, arg); 116 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 117 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 118 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 119 120 rc = mlx5_glue->devx_general_cmd(ctx, in, 121 MLX5_ST_SZ_BYTES(access_register_in) + 122 dw_cnt * sizeof(uint32_t), 123 out, sizeof(out)); 124 if (rc) 125 goto error; 126 status = MLX5_GET(access_register_out, out, status); 127 if (status) { 128 int syndrome = MLX5_GET(access_register_out, out, syndrome); 129 130 DRV_LOG(DEBUG, "Failed to write access NIC register 0x%X, " 131 "status %x, syndrome = %x", 132 reg_id, status, syndrome); 133 return -1; 134 } 135 return 0; 136 error: 137 rc = (rc > 0) ? -rc : rc; 138 return rc; 139 } 140 141 /** 142 * Allocate flow counters via devx interface. 143 * 144 * @param[in] ctx 145 * Context returned from mlx5 open_device() glue function. 146 * @param dcs 147 * Pointer to counters properties structure to be filled by the routine. 148 * @param bulk_n_128 149 * Bulk counter numbers in 128 counters units. 150 * 151 * @return 152 * Pointer to counter object on success, a negative value otherwise and 153 * rte_errno is set. 154 */ 155 struct mlx5_devx_obj * 156 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 157 { 158 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 159 0, SOCKET_ID_ANY); 160 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 161 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 162 163 if (!dcs) { 164 rte_errno = ENOMEM; 165 return NULL; 166 } 167 MLX5_SET(alloc_flow_counter_in, in, opcode, 168 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 169 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 170 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 171 sizeof(in), out, sizeof(out)); 172 if (!dcs->obj) { 173 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 174 rte_errno = errno; 175 mlx5_free(dcs); 176 return NULL; 177 } 178 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 179 return dcs; 180 } 181 182 /** 183 * Query flow counters values. 184 * 185 * @param[in] dcs 186 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 187 * @param[in] clear 188 * Whether hardware should clear the counters after the query or not. 189 * @param[in] n_counters 190 * 0 in case of 1 counter to read, otherwise the counter number to read. 191 * @param pkts 192 * The number of packets that matched the flow. 193 * @param bytes 194 * The number of bytes that matched the flow. 195 * @param mkey 196 * The mkey key for batch query. 197 * @param addr 198 * The address in the mkey range for batch query. 199 * @param cmd_comp 200 * The completion object for asynchronous batch query. 201 * @param async_id 202 * The ID to be returned in the asynchronous batch query response. 203 * 204 * @return 205 * 0 on success, a negative value otherwise. 206 */ 207 int 208 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 209 int clear, uint32_t n_counters, 210 uint64_t *pkts, uint64_t *bytes, 211 uint32_t mkey, void *addr, 212 void *cmd_comp, 213 uint64_t async_id) 214 { 215 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 216 MLX5_ST_SZ_BYTES(traffic_counter); 217 uint32_t out[out_len]; 218 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 219 void *stats; 220 int rc; 221 222 MLX5_SET(query_flow_counter_in, in, opcode, 223 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 224 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 225 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 226 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 227 228 if (n_counters) { 229 MLX5_SET(query_flow_counter_in, in, num_of_counters, 230 n_counters); 231 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 232 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 233 MLX5_SET64(query_flow_counter_in, in, address, 234 (uint64_t)(uintptr_t)addr); 235 } 236 if (!cmd_comp) 237 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 238 out_len); 239 else 240 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 241 out_len, async_id, 242 cmd_comp); 243 if (rc) { 244 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 245 rte_errno = rc; 246 return -rc; 247 } 248 if (!n_counters) { 249 stats = MLX5_ADDR_OF(query_flow_counter_out, 250 out, flow_statistics); 251 *pkts = MLX5_GET64(traffic_counter, stats, packets); 252 *bytes = MLX5_GET64(traffic_counter, stats, octets); 253 } 254 return 0; 255 } 256 257 /** 258 * Create a new mkey. 259 * 260 * @param[in] ctx 261 * Context returned from mlx5 open_device() glue function. 262 * @param[in] attr 263 * Attributes of the requested mkey. 264 * 265 * @return 266 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 267 * is set. 268 */ 269 struct mlx5_devx_obj * 270 mlx5_devx_cmd_mkey_create(void *ctx, 271 struct mlx5_devx_mkey_attr *attr) 272 { 273 struct mlx5_klm *klm_array = attr->klm_array; 274 int klm_num = attr->klm_num; 275 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 276 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 277 uint32_t in[in_size_dw]; 278 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 279 void *mkc; 280 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 281 0, SOCKET_ID_ANY); 282 size_t pgsize; 283 uint32_t translation_size; 284 285 if (!mkey) { 286 rte_errno = ENOMEM; 287 return NULL; 288 } 289 memset(in, 0, in_size_dw * 4); 290 pgsize = rte_mem_page_size(); 291 if (pgsize == (size_t)-1) { 292 mlx5_free(mkey); 293 DRV_LOG(ERR, "Failed to get page size"); 294 rte_errno = ENOMEM; 295 return NULL; 296 } 297 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 298 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 299 if (klm_num > 0) { 300 int i; 301 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 302 klm_pas_mtt); 303 translation_size = RTE_ALIGN(klm_num, 4); 304 for (i = 0; i < klm_num; i++) { 305 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 306 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 307 MLX5_SET64(klm, klm, address, klm_array[i].address); 308 klm += MLX5_ST_SZ_BYTES(klm); 309 } 310 for (; i < (int)translation_size; i++) { 311 MLX5_SET(klm, klm, mkey, 0x0); 312 MLX5_SET64(klm, klm, address, 0x0); 313 klm += MLX5_ST_SZ_BYTES(klm); 314 } 315 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 316 MLX5_MKC_ACCESS_MODE_KLM_FBS : 317 MLX5_MKC_ACCESS_MODE_KLM); 318 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 319 } else { 320 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 321 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 322 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 323 } 324 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 325 translation_size); 326 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 327 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 328 MLX5_SET(mkc, mkc, lw, 0x1); 329 MLX5_SET(mkc, mkc, lr, 0x1); 330 if (attr->set_remote_rw) { 331 MLX5_SET(mkc, mkc, rw, 0x1); 332 MLX5_SET(mkc, mkc, rr, 0x1); 333 } 334 MLX5_SET(mkc, mkc, qpn, 0xffffff); 335 MLX5_SET(mkc, mkc, pd, attr->pd); 336 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 337 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 338 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 339 MLX5_SET(mkc, mkc, relaxed_ordering_write, 340 attr->relaxed_ordering_write); 341 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 342 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 343 MLX5_SET64(mkc, mkc, len, attr->size); 344 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 345 if (attr->crypto_en) { 346 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 347 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 348 } 349 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 350 sizeof(out)); 351 if (!mkey->obj) { 352 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d", 353 klm_num ? "an in" : "a ", errno); 354 rte_errno = errno; 355 mlx5_free(mkey); 356 return NULL; 357 } 358 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 359 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 360 return mkey; 361 } 362 363 /** 364 * Get status of devx command response. 365 * Mainly used for asynchronous commands. 366 * 367 * @param[in] out 368 * The out response buffer. 369 * 370 * @return 371 * 0 on success, non-zero value otherwise. 372 */ 373 int 374 mlx5_devx_get_out_command_status(void *out) 375 { 376 int status; 377 378 if (!out) 379 return -EINVAL; 380 status = MLX5_GET(query_flow_counter_out, out, status); 381 if (status) { 382 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 383 384 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 385 syndrome); 386 } 387 return status; 388 } 389 390 /** 391 * Destroy any object allocated by a Devx API. 392 * 393 * @param[in] obj 394 * Pointer to a general object. 395 * 396 * @return 397 * 0 on success, a negative value otherwise. 398 */ 399 int 400 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 401 { 402 int ret; 403 404 if (!obj) 405 return 0; 406 ret = mlx5_glue->devx_obj_destroy(obj->obj); 407 mlx5_free(obj); 408 return ret; 409 } 410 411 /** 412 * Query NIC vport context. 413 * Fills minimal inline attribute. 414 * 415 * @param[in] ctx 416 * ibv contexts returned from mlx5dv_open_device. 417 * @param[in] vport 418 * vport index 419 * @param[out] attr 420 * Attributes device values. 421 * 422 * @return 423 * 0 on success, a negative value otherwise. 424 */ 425 static int 426 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 427 unsigned int vport, 428 struct mlx5_hca_attr *attr) 429 { 430 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 431 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 432 void *vctx; 433 int status, syndrome, rc; 434 435 /* Query NIC vport context to determine inline mode. */ 436 MLX5_SET(query_nic_vport_context_in, in, opcode, 437 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 438 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 439 if (vport) 440 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 441 rc = mlx5_glue->devx_general_cmd(ctx, 442 in, sizeof(in), 443 out, sizeof(out)); 444 if (rc) 445 goto error; 446 status = MLX5_GET(query_nic_vport_context_out, out, status); 447 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 448 if (status) { 449 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 450 "status %x, syndrome = %x", status, syndrome); 451 return -1; 452 } 453 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 454 nic_vport_context); 455 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 456 min_wqe_inline_mode); 457 return 0; 458 error: 459 rc = (rc > 0) ? -rc : rc; 460 return rc; 461 } 462 463 /** 464 * Query NIC vDPA attributes. 465 * 466 * @param[in] ctx 467 * Context returned from mlx5 open_device() glue function. 468 * @param[out] vdpa_attr 469 * vDPA Attributes structure to fill. 470 */ 471 static void 472 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 473 struct mlx5_hca_vdpa_attr *vdpa_attr) 474 { 475 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 476 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 477 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 478 int status, syndrome, rc; 479 480 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 481 MLX5_SET(query_hca_cap_in, in, op_mod, 482 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 483 MLX5_HCA_CAP_OPMOD_GET_CUR); 484 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 485 status = MLX5_GET(query_hca_cap_out, out, status); 486 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 487 if (rc || status) { 488 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities," 489 " status %x, syndrome = %x", status, syndrome); 490 vdpa_attr->valid = 0; 491 } else { 492 vdpa_attr->valid = 1; 493 vdpa_attr->desc_tunnel_offload_type = 494 MLX5_GET(virtio_emulation_cap, hcattr, 495 desc_tunnel_offload_type); 496 vdpa_attr->eth_frame_offload_type = 497 MLX5_GET(virtio_emulation_cap, hcattr, 498 eth_frame_offload_type); 499 vdpa_attr->virtio_version_1_0 = 500 MLX5_GET(virtio_emulation_cap, hcattr, 501 virtio_version_1_0); 502 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 503 tso_ipv4); 504 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 505 tso_ipv6); 506 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 507 tx_csum); 508 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 509 rx_csum); 510 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 511 event_mode); 512 vdpa_attr->virtio_queue_type = 513 MLX5_GET(virtio_emulation_cap, hcattr, 514 virtio_queue_type); 515 vdpa_attr->log_doorbell_stride = 516 MLX5_GET(virtio_emulation_cap, hcattr, 517 log_doorbell_stride); 518 vdpa_attr->log_doorbell_bar_size = 519 MLX5_GET(virtio_emulation_cap, hcattr, 520 log_doorbell_bar_size); 521 vdpa_attr->doorbell_bar_offset = 522 MLX5_GET64(virtio_emulation_cap, hcattr, 523 doorbell_bar_offset); 524 vdpa_attr->max_num_virtio_queues = 525 MLX5_GET(virtio_emulation_cap, hcattr, 526 max_num_virtio_queues); 527 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 528 umem_1_buffer_param_a); 529 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 530 umem_1_buffer_param_b); 531 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 532 umem_2_buffer_param_a); 533 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 534 umem_2_buffer_param_b); 535 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 536 umem_3_buffer_param_a); 537 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 538 umem_3_buffer_param_b); 539 } 540 } 541 542 int 543 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 544 uint32_t ids[], uint32_t num) 545 { 546 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 547 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 548 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 549 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 550 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 551 int ret; 552 uint32_t idx = 0; 553 uint32_t i; 554 555 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 556 rte_errno = EINVAL; 557 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 558 return -rte_errno; 559 } 560 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 561 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 562 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 563 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 564 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 565 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 566 out, sizeof(out)); 567 if (ret) { 568 rte_errno = ret; 569 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 570 (void *)flex_obj); 571 return -rte_errno; 572 } 573 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 574 void *s_off = (void *)((char *)sample + i * 575 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 576 uint32_t en; 577 578 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 579 flow_match_sample_en); 580 if (!en) 581 continue; 582 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 583 flow_match_sample_field_id); 584 } 585 if (num != idx) { 586 rte_errno = EINVAL; 587 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 588 return -rte_errno; 589 } 590 return ret; 591 } 592 593 594 struct mlx5_devx_obj * 595 mlx5_devx_cmd_create_flex_parser(void *ctx, 596 struct mlx5_devx_graph_node_attr *data) 597 { 598 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 599 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 600 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 601 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 602 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 603 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 604 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 605 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 606 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 607 uint32_t i; 608 609 if (!parse_flex_obj) { 610 DRV_LOG(ERR, "Failed to allocate flex parser data."); 611 rte_errno = ENOMEM; 612 return NULL; 613 } 614 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 615 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 616 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 617 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 618 MLX5_SET(parse_graph_flex, flex, header_length_mode, 619 data->header_length_mode); 620 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 621 data->header_length_base_value); 622 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 623 data->header_length_field_offset); 624 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 625 data->header_length_field_shift); 626 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 627 data->header_length_field_mask); 628 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 629 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 630 void *s_off = (void *)((char *)sample + i * 631 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 632 633 if (!s->flow_match_sample_en) 634 continue; 635 MLX5_SET(parse_graph_flow_match_sample, s_off, 636 flow_match_sample_en, !!s->flow_match_sample_en); 637 MLX5_SET(parse_graph_flow_match_sample, s_off, 638 flow_match_sample_field_offset, 639 s->flow_match_sample_field_offset); 640 MLX5_SET(parse_graph_flow_match_sample, s_off, 641 flow_match_sample_offset_mode, 642 s->flow_match_sample_offset_mode); 643 MLX5_SET(parse_graph_flow_match_sample, s_off, 644 flow_match_sample_field_offset_mask, 645 s->flow_match_sample_field_offset_mask); 646 MLX5_SET(parse_graph_flow_match_sample, s_off, 647 flow_match_sample_field_offset_shift, 648 s->flow_match_sample_field_offset_shift); 649 MLX5_SET(parse_graph_flow_match_sample, s_off, 650 flow_match_sample_field_base_offset, 651 s->flow_match_sample_field_base_offset); 652 MLX5_SET(parse_graph_flow_match_sample, s_off, 653 flow_match_sample_tunnel_mode, 654 s->flow_match_sample_tunnel_mode); 655 } 656 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 657 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 658 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 659 void *in_off = (void *)((char *)in_arc + i * 660 MLX5_ST_SZ_BYTES(parse_graph_arc)); 661 void *out_off = (void *)((char *)out_arc + i * 662 MLX5_ST_SZ_BYTES(parse_graph_arc)); 663 664 if (ia->arc_parse_graph_node != 0) { 665 MLX5_SET(parse_graph_arc, in_off, 666 compare_condition_value, 667 ia->compare_condition_value); 668 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 669 ia->start_inner_tunnel); 670 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 671 ia->arc_parse_graph_node); 672 MLX5_SET(parse_graph_arc, in_off, 673 parse_graph_node_handle, 674 ia->parse_graph_node_handle); 675 } 676 if (oa->arc_parse_graph_node != 0) { 677 MLX5_SET(parse_graph_arc, out_off, 678 compare_condition_value, 679 oa->compare_condition_value); 680 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 681 oa->start_inner_tunnel); 682 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 683 oa->arc_parse_graph_node); 684 MLX5_SET(parse_graph_arc, out_off, 685 parse_graph_node_handle, 686 oa->parse_graph_node_handle); 687 } 688 } 689 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 690 out, sizeof(out)); 691 if (!parse_flex_obj->obj) { 692 rte_errno = errno; 693 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 694 "by using DevX."); 695 mlx5_free(parse_flex_obj); 696 return NULL; 697 } 698 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 699 return parse_flex_obj; 700 } 701 702 static int 703 mlx5_devx_query_pkt_integrity_match(void *hcattr) 704 { 705 return MLX5_GET(flow_table_nic_cap, hcattr, 706 ft_field_support_2_nic_receive.inner_l3_ok) && 707 MLX5_GET(flow_table_nic_cap, hcattr, 708 ft_field_support_2_nic_receive.inner_l4_ok) && 709 MLX5_GET(flow_table_nic_cap, hcattr, 710 ft_field_support_2_nic_receive.outer_l3_ok) && 711 MLX5_GET(flow_table_nic_cap, hcattr, 712 ft_field_support_2_nic_receive.outer_l4_ok) && 713 MLX5_GET(flow_table_nic_cap, hcattr, 714 ft_field_support_2_nic_receive 715 .inner_ipv4_checksum_ok) && 716 MLX5_GET(flow_table_nic_cap, hcattr, 717 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 718 MLX5_GET(flow_table_nic_cap, hcattr, 719 ft_field_support_2_nic_receive 720 .outer_ipv4_checksum_ok) && 721 MLX5_GET(flow_table_nic_cap, hcattr, 722 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 723 } 724 725 /** 726 * Query HCA attributes. 727 * Using those attributes we can check on run time if the device 728 * is having the required capabilities. 729 * 730 * @param[in] ctx 731 * Context returned from mlx5 open_device() glue function. 732 * @param[out] attr 733 * Attributes device values. 734 * 735 * @return 736 * 0 on success, a negative value otherwise. 737 */ 738 int 739 mlx5_devx_cmd_query_hca_attr(void *ctx, 740 struct mlx5_hca_attr *attr) 741 { 742 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 743 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 744 void *hcattr; 745 int status, syndrome, rc, i; 746 uint64_t general_obj_types_supported = 0; 747 748 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 749 MLX5_SET(query_hca_cap_in, in, op_mod, 750 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 751 MLX5_HCA_CAP_OPMOD_GET_CUR); 752 753 rc = mlx5_glue->devx_general_cmd(ctx, 754 in, sizeof(in), out, sizeof(out)); 755 if (rc) 756 goto error; 757 status = MLX5_GET(query_hca_cap_out, out, status); 758 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 759 if (status) { 760 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 761 "status %x, syndrome = %x", status, syndrome); 762 return -1; 763 } 764 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 765 attr->flow_counter_bulk_alloc_bitmap = 766 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 767 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 768 flow_counters_dump); 769 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 770 log_max_rqt_size); 771 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 772 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 773 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 774 log_max_hairpin_queues); 775 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 776 log_max_hairpin_wq_data_sz); 777 attr->log_max_hairpin_num_packets = MLX5_GET 778 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 779 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 780 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 781 relaxed_ordering_write); 782 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 783 relaxed_ordering_read); 784 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 785 access_register_user); 786 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 787 eth_net_offloads); 788 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 789 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 790 flex_parser_protocols); 791 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 792 max_geneve_tlv_options); 793 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 794 max_geneve_tlv_option_data_len); 795 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 796 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 797 general_obj_types) & 798 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 799 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 800 general_obj_types) & 801 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 802 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 803 general_obj_types) & 804 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 805 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 806 general_obj_types) & 807 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 808 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 809 wqe_index_ignore_cap); 810 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 811 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 812 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 813 log_max_static_sq_wq); 814 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 815 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 816 device_frequency_khz); 817 attr->scatter_fcs_w_decap_disable = 818 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 819 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 820 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 821 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 822 attr->steering_format_version = 823 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 824 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp); 825 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 826 regexp_num_of_engines); 827 /* Read the general_obj_types bitmap and extract the relevant bits. */ 828 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 829 general_obj_types); 830 attr->vdpa.valid = !!(general_obj_types_supported & 831 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 832 attr->vdpa.queue_counters_valid = 833 !!(general_obj_types_supported & 834 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 835 attr->parse_graph_flex_node = 836 !!(general_obj_types_supported & 837 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 838 attr->flow_hit_aso = !!(general_obj_types_supported & 839 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 840 attr->geneve_tlv_opt = !!(general_obj_types_supported & 841 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 842 attr->dek = !!(general_obj_types_supported & 843 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 844 attr->import_kek = !!(general_obj_types_supported & 845 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 846 attr->credential = !!(general_obj_types_supported & 847 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 848 attr->crypto_login = !!(general_obj_types_supported & 849 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 850 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 851 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 852 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 853 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 854 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 855 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 856 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 857 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 858 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 859 attr->reg_c_preserve = 860 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 861 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 862 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 863 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 864 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 865 compress_mmo_sq); 866 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 867 decompress_mmo_sq); 868 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 869 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 870 compress_mmo_qp); 871 attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 872 decompress_mmo_qp); 873 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 874 compress_min_block_size); 875 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 876 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 877 log_compress_mmo_size); 878 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 879 log_decompress_mmo_size); 880 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 881 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 882 mini_cqe_resp_flow_tag); 883 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 884 mini_cqe_resp_l3_l4_tag); 885 attr->umr_indirect_mkey_disabled = 886 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 887 attr->umr_modify_entity_size_disabled = 888 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 889 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 890 if (attr->crypto) 891 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts); 892 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 893 general_obj_types) & 894 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 895 if (attr->qos.sup) { 896 MLX5_SET(query_hca_cap_in, in, op_mod, 897 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 898 MLX5_HCA_CAP_OPMOD_GET_CUR); 899 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 900 out, sizeof(out)); 901 if (rc) 902 goto error; 903 if (status) { 904 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities," 905 " status %x, syndrome = %x", status, syndrome); 906 return -1; 907 } 908 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 909 attr->qos.flow_meter_old = 910 MLX5_GET(qos_cap, hcattr, flow_meter_old); 911 attr->qos.log_max_flow_meter = 912 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 913 attr->qos.flow_meter_reg_c_ids = 914 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 915 attr->qos.flow_meter = 916 MLX5_GET(qos_cap, hcattr, flow_meter); 917 attr->qos.packet_pacing = 918 MLX5_GET(qos_cap, hcattr, packet_pacing); 919 attr->qos.wqe_rate_pp = 920 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 921 if (attr->qos.flow_meter_aso_sup) { 922 attr->qos.log_meter_aso_granularity = 923 MLX5_GET(qos_cap, hcattr, 924 log_meter_aso_granularity); 925 attr->qos.log_meter_aso_max_alloc = 926 MLX5_GET(qos_cap, hcattr, 927 log_meter_aso_max_alloc); 928 attr->qos.log_max_num_meter_aso = 929 MLX5_GET(qos_cap, hcattr, 930 log_max_num_meter_aso); 931 } 932 } 933 if (attr->vdpa.valid) 934 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 935 if (!attr->eth_net_offloads) 936 return 0; 937 938 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 939 memset(in, 0, sizeof(in)); 940 memset(out, 0, sizeof(out)); 941 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 942 MLX5_SET(query_hca_cap_in, in, op_mod, 943 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 944 MLX5_HCA_CAP_OPMOD_GET_CUR); 945 946 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 947 if (rc) 948 goto error; 949 status = MLX5_GET(query_hca_cap_out, out, status); 950 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 951 if (status) { 952 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 953 "status %x, syndrome = %x", status, syndrome); 954 attr->log_max_ft_sampler_num = 0; 955 return -1; 956 } 957 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 958 attr->log_max_ft_sampler_num = MLX5_GET 959 (flow_table_nic_cap, hcattr, 960 flow_table_properties_nic_receive.log_max_ft_sampler_num); 961 attr->flow.tunnel_header_0_1 = MLX5_GET 962 (flow_table_nic_cap, hcattr, 963 ft_field_support_2_nic_receive.tunnel_header_0_1); 964 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 965 attr->inner_ipv4_ihl = MLX5_GET 966 (flow_table_nic_cap, hcattr, 967 ft_field_support_2_nic_receive.inner_ipv4_ihl); 968 attr->outer_ipv4_ihl = MLX5_GET 969 (flow_table_nic_cap, hcattr, 970 ft_field_support_2_nic_receive.outer_ipv4_ihl); 971 /* Query HCA offloads for Ethernet protocol. */ 972 memset(in, 0, sizeof(in)); 973 memset(out, 0, sizeof(out)); 974 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 975 MLX5_SET(query_hca_cap_in, in, op_mod, 976 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 977 MLX5_HCA_CAP_OPMOD_GET_CUR); 978 979 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 980 if (rc) { 981 attr->eth_net_offloads = 0; 982 goto error; 983 } 984 status = MLX5_GET(query_hca_cap_out, out, status); 985 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 986 if (status) { 987 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 988 "status %x, syndrome = %x", status, syndrome); 989 attr->eth_net_offloads = 0; 990 return -1; 991 } 992 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 993 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 994 hcattr, wqe_vlan_insert); 995 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 996 hcattr, csum_cap); 997 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 998 lro_cap); 999 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1000 hcattr, tunnel_lro_gre); 1001 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1002 hcattr, tunnel_lro_vxlan); 1003 attr->lro_max_msg_sz_mode = MLX5_GET 1004 (per_protocol_networking_offload_caps, 1005 hcattr, lro_max_msg_sz_mode); 1006 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1007 attr->lro_timer_supported_periods[i] = 1008 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1009 lro_timer_supported_periods[i]); 1010 } 1011 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1012 hcattr, lro_min_mss_size); 1013 attr->tunnel_stateless_geneve_rx = 1014 MLX5_GET(per_protocol_networking_offload_caps, 1015 hcattr, tunnel_stateless_geneve_rx); 1016 attr->geneve_max_opt_len = 1017 MLX5_GET(per_protocol_networking_offload_caps, 1018 hcattr, max_geneve_opt_len); 1019 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1020 hcattr, wqe_inline_mode); 1021 attr->tunnel_stateless_gtp = MLX5_GET 1022 (per_protocol_networking_offload_caps, 1023 hcattr, tunnel_stateless_gtp); 1024 attr->rss_ind_tbl_cap = MLX5_GET 1025 (per_protocol_networking_offload_caps, 1026 hcattr, rss_ind_tbl_cap); 1027 /* Query HCA attribute for ROCE. */ 1028 if (attr->roce) { 1029 memset(in, 0, sizeof(in)); 1030 memset(out, 0, sizeof(out)); 1031 MLX5_SET(query_hca_cap_in, in, opcode, 1032 MLX5_CMD_OP_QUERY_HCA_CAP); 1033 MLX5_SET(query_hca_cap_in, in, op_mod, 1034 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1035 MLX5_HCA_CAP_OPMOD_GET_CUR); 1036 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 1037 out, sizeof(out)); 1038 if (rc) 1039 goto error; 1040 status = MLX5_GET(query_hca_cap_out, out, status); 1041 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 1042 if (status) { 1043 DRV_LOG(DEBUG, 1044 "Failed to query devx HCA ROCE capabilities, " 1045 "status %x, syndrome = %x", status, syndrome); 1046 return -1; 1047 } 1048 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 1049 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1050 } 1051 if (attr->eth_virt && 1052 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1053 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1054 if (rc) { 1055 attr->eth_virt = 0; 1056 goto error; 1057 } 1058 } 1059 return 0; 1060 error: 1061 rc = (rc > 0) ? -rc : rc; 1062 return rc; 1063 } 1064 1065 /** 1066 * Query TIS transport domain from QP verbs object using DevX API. 1067 * 1068 * @param[in] qp 1069 * Pointer to verbs QP returned by ibv_create_qp . 1070 * @param[in] tis_num 1071 * TIS number of TIS to query. 1072 * @param[out] tis_td 1073 * Pointer to TIS transport domain variable, to be set by the routine. 1074 * 1075 * @return 1076 * 0 on success, a negative value otherwise. 1077 */ 1078 int 1079 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1080 uint32_t *tis_td) 1081 { 1082 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1083 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1084 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1085 int rc; 1086 void *tis_ctx; 1087 1088 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1089 MLX5_SET(query_tis_in, in, tisn, tis_num); 1090 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1091 if (rc) { 1092 DRV_LOG(ERR, "Failed to query QP using DevX"); 1093 return -rc; 1094 }; 1095 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1096 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1097 return 0; 1098 #else 1099 (void)qp; 1100 (void)tis_num; 1101 (void)tis_td; 1102 return -ENOTSUP; 1103 #endif 1104 } 1105 1106 /** 1107 * Fill WQ data for DevX API command. 1108 * Utility function for use when creating DevX objects containing a WQ. 1109 * 1110 * @param[in] wq_ctx 1111 * Pointer to WQ context to fill with data. 1112 * @param [in] wq_attr 1113 * Pointer to WQ attributes structure to fill in WQ context. 1114 */ 1115 static void 1116 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1117 { 1118 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1119 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1120 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1121 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1122 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1123 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1124 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1125 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1126 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1127 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1128 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1129 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1130 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1131 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1132 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1133 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1134 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1135 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1136 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1137 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1138 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1139 wq_attr->log_hairpin_num_packets); 1140 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1141 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1142 wq_attr->single_wqe_log_num_of_strides); 1143 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1144 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1145 wq_attr->single_stride_log_num_of_bytes); 1146 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1147 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1148 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1149 } 1150 1151 /** 1152 * Create RQ using DevX API. 1153 * 1154 * @param[in] ctx 1155 * Context returned from mlx5 open_device() glue function. 1156 * @param [in] rq_attr 1157 * Pointer to create RQ attributes structure. 1158 * @param [in] socket 1159 * CPU socket ID for allocations. 1160 * 1161 * @return 1162 * The DevX object created, NULL otherwise and rte_errno is set. 1163 */ 1164 struct mlx5_devx_obj * 1165 mlx5_devx_cmd_create_rq(void *ctx, 1166 struct mlx5_devx_create_rq_attr *rq_attr, 1167 int socket) 1168 { 1169 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1170 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1171 void *rq_ctx, *wq_ctx; 1172 struct mlx5_devx_wq_attr *wq_attr; 1173 struct mlx5_devx_obj *rq = NULL; 1174 1175 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1176 if (!rq) { 1177 DRV_LOG(ERR, "Failed to allocate RQ data"); 1178 rte_errno = ENOMEM; 1179 return NULL; 1180 } 1181 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1182 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1183 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1184 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1185 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1186 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1187 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1188 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1189 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1190 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1191 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1192 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1193 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1194 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1195 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1196 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1197 wq_attr = &rq_attr->wq_attr; 1198 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1199 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1200 out, sizeof(out)); 1201 if (!rq->obj) { 1202 DRV_LOG(ERR, "Failed to create RQ using DevX"); 1203 rte_errno = errno; 1204 mlx5_free(rq); 1205 return NULL; 1206 } 1207 rq->id = MLX5_GET(create_rq_out, out, rqn); 1208 return rq; 1209 } 1210 1211 /** 1212 * Modify RQ using DevX API. 1213 * 1214 * @param[in] rq 1215 * Pointer to RQ object structure. 1216 * @param [in] rq_attr 1217 * Pointer to modify RQ attributes structure. 1218 * 1219 * @return 1220 * 0 on success, a negative errno value otherwise and rte_errno is set. 1221 */ 1222 int 1223 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1224 struct mlx5_devx_modify_rq_attr *rq_attr) 1225 { 1226 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1227 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1228 void *rq_ctx, *wq_ctx; 1229 int ret; 1230 1231 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1232 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1233 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1234 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1235 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1236 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1237 if (rq_attr->modify_bitmask & 1238 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1239 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1240 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1241 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1242 if (rq_attr->modify_bitmask & 1243 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1244 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1245 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1246 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1247 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1248 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1249 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1250 } 1251 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1252 out, sizeof(out)); 1253 if (ret) { 1254 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1255 rte_errno = errno; 1256 return -errno; 1257 } 1258 return ret; 1259 } 1260 1261 /** 1262 * Create TIR using DevX API. 1263 * 1264 * @param[in] ctx 1265 * Context returned from mlx5 open_device() glue function. 1266 * @param [in] tir_attr 1267 * Pointer to TIR attributes structure. 1268 * 1269 * @return 1270 * The DevX object created, NULL otherwise and rte_errno is set. 1271 */ 1272 struct mlx5_devx_obj * 1273 mlx5_devx_cmd_create_tir(void *ctx, 1274 struct mlx5_devx_tir_attr *tir_attr) 1275 { 1276 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1277 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1278 void *tir_ctx, *outer, *inner, *rss_key; 1279 struct mlx5_devx_obj *tir = NULL; 1280 1281 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1282 if (!tir) { 1283 DRV_LOG(ERR, "Failed to allocate TIR data"); 1284 rte_errno = ENOMEM; 1285 return NULL; 1286 } 1287 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1288 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1289 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1290 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1291 tir_attr->lro_timeout_period_usecs); 1292 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1293 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1294 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1295 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1296 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1297 tir_attr->tunneled_offload_en); 1298 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1299 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1300 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1301 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1302 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1303 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1304 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1305 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1306 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1307 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1308 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1309 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1310 tir_attr->rx_hash_field_selector_outer.selected_fields); 1311 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1312 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1313 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1314 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1315 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1316 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1317 tir_attr->rx_hash_field_selector_inner.selected_fields); 1318 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1319 out, sizeof(out)); 1320 if (!tir->obj) { 1321 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1322 rte_errno = errno; 1323 mlx5_free(tir); 1324 return NULL; 1325 } 1326 tir->id = MLX5_GET(create_tir_out, out, tirn); 1327 return tir; 1328 } 1329 1330 /** 1331 * Modify TIR using DevX API. 1332 * 1333 * @param[in] tir 1334 * Pointer to TIR DevX object structure. 1335 * @param [in] modify_tir_attr 1336 * Pointer to TIR modification attributes structure. 1337 * 1338 * @return 1339 * 0 on success, a negative errno value otherwise and rte_errno is set. 1340 */ 1341 int 1342 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1343 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1344 { 1345 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1346 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1347 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1348 void *tir_ctx; 1349 int ret; 1350 1351 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1352 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1353 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1354 modify_tir_attr->modify_bitmask); 1355 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1356 if (modify_tir_attr->modify_bitmask & 1357 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1358 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1359 tir_attr->lro_timeout_period_usecs); 1360 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1361 tir_attr->lro_enable_mask); 1362 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1363 tir_attr->lro_max_msg_sz); 1364 } 1365 if (modify_tir_attr->modify_bitmask & 1366 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1367 MLX5_SET(tirc, tir_ctx, indirect_table, 1368 tir_attr->indirect_table); 1369 if (modify_tir_attr->modify_bitmask & 1370 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1371 int i; 1372 void *outer, *inner; 1373 1374 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1375 tir_attr->rx_hash_symmetric); 1376 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1377 for (i = 0; i < 10; i++) { 1378 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1379 tir_attr->rx_hash_toeplitz_key[i]); 1380 } 1381 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1382 rx_hash_field_selector_outer); 1383 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1384 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1385 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1386 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1387 MLX5_SET 1388 (rx_hash_field_select, outer, selected_fields, 1389 tir_attr->rx_hash_field_selector_outer.selected_fields); 1390 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1391 rx_hash_field_selector_inner); 1392 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1393 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1394 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1395 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1396 MLX5_SET 1397 (rx_hash_field_select, inner, selected_fields, 1398 tir_attr->rx_hash_field_selector_inner.selected_fields); 1399 } 1400 if (modify_tir_attr->modify_bitmask & 1401 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1402 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1403 } 1404 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1405 out, sizeof(out)); 1406 if (ret) { 1407 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1408 rte_errno = errno; 1409 return -errno; 1410 } 1411 return ret; 1412 } 1413 1414 /** 1415 * Create RQT using DevX API. 1416 * 1417 * @param[in] ctx 1418 * Context returned from mlx5 open_device() glue function. 1419 * @param [in] rqt_attr 1420 * Pointer to RQT attributes structure. 1421 * 1422 * @return 1423 * The DevX object created, NULL otherwise and rte_errno is set. 1424 */ 1425 struct mlx5_devx_obj * 1426 mlx5_devx_cmd_create_rqt(void *ctx, 1427 struct mlx5_devx_rqt_attr *rqt_attr) 1428 { 1429 uint32_t *in = NULL; 1430 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1431 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1432 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1433 void *rqt_ctx; 1434 struct mlx5_devx_obj *rqt = NULL; 1435 int i; 1436 1437 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1438 if (!in) { 1439 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1440 rte_errno = ENOMEM; 1441 return NULL; 1442 } 1443 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1444 if (!rqt) { 1445 DRV_LOG(ERR, "Failed to allocate RQT data"); 1446 rte_errno = ENOMEM; 1447 mlx5_free(in); 1448 return NULL; 1449 } 1450 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1451 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1452 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1453 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1454 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1455 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1456 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1457 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1458 mlx5_free(in); 1459 if (!rqt->obj) { 1460 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1461 rte_errno = errno; 1462 mlx5_free(rqt); 1463 return NULL; 1464 } 1465 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1466 return rqt; 1467 } 1468 1469 /** 1470 * Modify RQT using DevX API. 1471 * 1472 * @param[in] rqt 1473 * Pointer to RQT DevX object structure. 1474 * @param [in] rqt_attr 1475 * Pointer to RQT attributes structure. 1476 * 1477 * @return 1478 * 0 on success, a negative errno value otherwise and rte_errno is set. 1479 */ 1480 int 1481 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1482 struct mlx5_devx_rqt_attr *rqt_attr) 1483 { 1484 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1485 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1486 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1487 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1488 void *rqt_ctx; 1489 int i; 1490 int ret; 1491 1492 if (!in) { 1493 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1494 rte_errno = ENOMEM; 1495 return -ENOMEM; 1496 } 1497 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1498 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1499 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1500 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1501 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1502 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1503 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1504 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1505 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1506 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1507 mlx5_free(in); 1508 if (ret) { 1509 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1510 rte_errno = errno; 1511 return -rte_errno; 1512 } 1513 return ret; 1514 } 1515 1516 /** 1517 * Create SQ using DevX API. 1518 * 1519 * @param[in] ctx 1520 * Context returned from mlx5 open_device() glue function. 1521 * @param [in] sq_attr 1522 * Pointer to SQ attributes structure. 1523 * @param [in] socket 1524 * CPU socket ID for allocations. 1525 * 1526 * @return 1527 * The DevX object created, NULL otherwise and rte_errno is set. 1528 **/ 1529 struct mlx5_devx_obj * 1530 mlx5_devx_cmd_create_sq(void *ctx, 1531 struct mlx5_devx_create_sq_attr *sq_attr) 1532 { 1533 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1534 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1535 void *sq_ctx; 1536 void *wq_ctx; 1537 struct mlx5_devx_wq_attr *wq_attr; 1538 struct mlx5_devx_obj *sq = NULL; 1539 1540 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1541 if (!sq) { 1542 DRV_LOG(ERR, "Failed to allocate SQ data"); 1543 rte_errno = ENOMEM; 1544 return NULL; 1545 } 1546 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1547 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1548 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1549 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1550 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1551 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1552 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1553 sq_attr->allow_multi_pkt_send_wqe); 1554 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1555 sq_attr->min_wqe_inline_mode); 1556 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1557 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1558 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1559 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1560 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1561 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1562 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1563 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1564 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1565 sq_attr->packet_pacing_rate_limit_index); 1566 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1567 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1568 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1569 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1570 wq_attr = &sq_attr->wq_attr; 1571 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1572 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1573 out, sizeof(out)); 1574 if (!sq->obj) { 1575 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1576 rte_errno = errno; 1577 mlx5_free(sq); 1578 return NULL; 1579 } 1580 sq->id = MLX5_GET(create_sq_out, out, sqn); 1581 return sq; 1582 } 1583 1584 /** 1585 * Modify SQ using DevX API. 1586 * 1587 * @param[in] sq 1588 * Pointer to SQ object structure. 1589 * @param [in] sq_attr 1590 * Pointer to SQ attributes structure. 1591 * 1592 * @return 1593 * 0 on success, a negative errno value otherwise and rte_errno is set. 1594 */ 1595 int 1596 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1597 struct mlx5_devx_modify_sq_attr *sq_attr) 1598 { 1599 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1600 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1601 void *sq_ctx; 1602 int ret; 1603 1604 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1605 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1606 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1607 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1608 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1609 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1610 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1611 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1612 out, sizeof(out)); 1613 if (ret) { 1614 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1615 rte_errno = errno; 1616 return -rte_errno; 1617 } 1618 return ret; 1619 } 1620 1621 /** 1622 * Create TIS using DevX API. 1623 * 1624 * @param[in] ctx 1625 * Context returned from mlx5 open_device() glue function. 1626 * @param [in] tis_attr 1627 * Pointer to TIS attributes structure. 1628 * 1629 * @return 1630 * The DevX object created, NULL otherwise and rte_errno is set. 1631 */ 1632 struct mlx5_devx_obj * 1633 mlx5_devx_cmd_create_tis(void *ctx, 1634 struct mlx5_devx_tis_attr *tis_attr) 1635 { 1636 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1637 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1638 struct mlx5_devx_obj *tis = NULL; 1639 void *tis_ctx; 1640 1641 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1642 if (!tis) { 1643 DRV_LOG(ERR, "Failed to allocate TIS object"); 1644 rte_errno = ENOMEM; 1645 return NULL; 1646 } 1647 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1648 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1649 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1650 tis_attr->strict_lag_tx_port_affinity); 1651 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1652 tis_attr->lag_tx_port_affinity); 1653 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1654 MLX5_SET(tisc, tis_ctx, transport_domain, 1655 tis_attr->transport_domain); 1656 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1657 out, sizeof(out)); 1658 if (!tis->obj) { 1659 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1660 rte_errno = errno; 1661 mlx5_free(tis); 1662 return NULL; 1663 } 1664 tis->id = MLX5_GET(create_tis_out, out, tisn); 1665 return tis; 1666 } 1667 1668 /** 1669 * Create transport domain using DevX API. 1670 * 1671 * @param[in] ctx 1672 * Context returned from mlx5 open_device() glue function. 1673 * @return 1674 * The DevX object created, NULL otherwise and rte_errno is set. 1675 */ 1676 struct mlx5_devx_obj * 1677 mlx5_devx_cmd_create_td(void *ctx) 1678 { 1679 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1680 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1681 struct mlx5_devx_obj *td = NULL; 1682 1683 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1684 if (!td) { 1685 DRV_LOG(ERR, "Failed to allocate TD object"); 1686 rte_errno = ENOMEM; 1687 return NULL; 1688 } 1689 MLX5_SET(alloc_transport_domain_in, in, opcode, 1690 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1691 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1692 out, sizeof(out)); 1693 if (!td->obj) { 1694 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1695 rte_errno = errno; 1696 mlx5_free(td); 1697 return NULL; 1698 } 1699 td->id = MLX5_GET(alloc_transport_domain_out, out, 1700 transport_domain); 1701 return td; 1702 } 1703 1704 /** 1705 * Dump all flows to file. 1706 * 1707 * @param[in] fdb_domain 1708 * FDB domain. 1709 * @param[in] rx_domain 1710 * RX domain. 1711 * @param[in] tx_domain 1712 * TX domain. 1713 * @param[out] file 1714 * Pointer to file stream. 1715 * 1716 * @return 1717 * 0 on success, a nagative value otherwise. 1718 */ 1719 int 1720 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1721 void *rx_domain __rte_unused, 1722 void *tx_domain __rte_unused, FILE *file __rte_unused) 1723 { 1724 int ret = 0; 1725 1726 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1727 if (fdb_domain) { 1728 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1729 if (ret) 1730 return ret; 1731 } 1732 MLX5_ASSERT(rx_domain); 1733 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1734 if (ret) 1735 return ret; 1736 MLX5_ASSERT(tx_domain); 1737 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1738 #else 1739 ret = ENOTSUP; 1740 #endif 1741 return -ret; 1742 } 1743 1744 int 1745 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 1746 FILE *file __rte_unused) 1747 { 1748 int ret = 0; 1749 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 1750 if (rule_info) 1751 ret = mlx5_glue->dr_dump_rule(file, rule_info); 1752 #else 1753 ret = ENOTSUP; 1754 #endif 1755 return -ret; 1756 } 1757 1758 /* 1759 * Create CQ using DevX API. 1760 * 1761 * @param[in] ctx 1762 * Context returned from mlx5 open_device() glue function. 1763 * @param [in] attr 1764 * Pointer to CQ attributes structure. 1765 * 1766 * @return 1767 * The DevX object created, NULL otherwise and rte_errno is set. 1768 */ 1769 struct mlx5_devx_obj * 1770 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1771 { 1772 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1773 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1774 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1775 sizeof(*cq_obj), 1776 0, SOCKET_ID_ANY); 1777 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1778 1779 if (!cq_obj) { 1780 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1781 rte_errno = ENOMEM; 1782 return NULL; 1783 } 1784 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1785 if (attr->db_umem_valid) { 1786 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1787 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1788 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1789 } else { 1790 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1791 } 1792 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1793 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1794 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1795 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1796 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1797 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1798 MLX5_SET(cqc, cqctx, log_page_size, 1799 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1800 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1801 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1802 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1803 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1804 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1805 attr->mini_cqe_res_format_ext); 1806 if (attr->q_umem_valid) { 1807 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1808 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1809 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1810 attr->q_umem_offset); 1811 } 1812 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1813 sizeof(out)); 1814 if (!cq_obj->obj) { 1815 rte_errno = errno; 1816 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1817 mlx5_free(cq_obj); 1818 return NULL; 1819 } 1820 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1821 return cq_obj; 1822 } 1823 1824 /** 1825 * Create VIRTQ using DevX API. 1826 * 1827 * @param[in] ctx 1828 * Context returned from mlx5 open_device() glue function. 1829 * @param [in] attr 1830 * Pointer to VIRTQ attributes structure. 1831 * 1832 * @return 1833 * The DevX object created, NULL otherwise and rte_errno is set. 1834 */ 1835 struct mlx5_devx_obj * 1836 mlx5_devx_cmd_create_virtq(void *ctx, 1837 struct mlx5_devx_virtq_attr *attr) 1838 { 1839 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1840 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1841 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1842 sizeof(*virtq_obj), 1843 0, SOCKET_ID_ANY); 1844 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1845 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1846 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1847 1848 if (!virtq_obj) { 1849 DRV_LOG(ERR, "Failed to allocate virtq data."); 1850 rte_errno = ENOMEM; 1851 return NULL; 1852 } 1853 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1854 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1855 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1856 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1857 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1858 attr->hw_available_index); 1859 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1860 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1861 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1862 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1863 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1864 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1865 attr->virtio_version_1_0); 1866 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1867 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1868 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1869 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1870 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1871 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1872 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1873 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1874 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1875 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 1876 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 1877 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 1878 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 1879 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 1880 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 1881 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 1882 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 1883 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 1884 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 1885 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 1886 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 1887 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 1888 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 1889 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1890 sizeof(out)); 1891 if (!virtq_obj->obj) { 1892 rte_errno = errno; 1893 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 1894 mlx5_free(virtq_obj); 1895 return NULL; 1896 } 1897 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1898 return virtq_obj; 1899 } 1900 1901 /** 1902 * Modify VIRTQ using DevX API. 1903 * 1904 * @param[in] virtq_obj 1905 * Pointer to virtq object structure. 1906 * @param [in] attr 1907 * Pointer to modify virtq attributes structure. 1908 * 1909 * @return 1910 * 0 on success, a negative errno value otherwise and rte_errno is set. 1911 */ 1912 int 1913 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 1914 struct mlx5_devx_virtq_attr *attr) 1915 { 1916 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1917 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1918 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1919 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1920 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1921 int ret; 1922 1923 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1924 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 1925 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1926 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1927 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1928 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 1929 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1930 switch (attr->type) { 1931 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 1932 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 1933 break; 1934 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 1935 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 1936 attr->dirty_bitmap_mkey); 1937 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 1938 attr->dirty_bitmap_addr); 1939 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 1940 attr->dirty_bitmap_size); 1941 break; 1942 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 1943 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 1944 attr->dirty_bitmap_dump_enable); 1945 break; 1946 default: 1947 rte_errno = EINVAL; 1948 return -rte_errno; 1949 } 1950 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 1951 out, sizeof(out)); 1952 if (ret) { 1953 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1954 rte_errno = errno; 1955 return -rte_errno; 1956 } 1957 return ret; 1958 } 1959 1960 /** 1961 * Query VIRTQ using DevX API. 1962 * 1963 * @param[in] virtq_obj 1964 * Pointer to virtq object structure. 1965 * @param [in/out] attr 1966 * Pointer to virtq attributes structure. 1967 * 1968 * @return 1969 * 0 on success, a negative errno value otherwise and rte_errno is set. 1970 */ 1971 int 1972 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 1973 struct mlx5_devx_virtq_attr *attr) 1974 { 1975 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1976 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 1977 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 1978 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 1979 int ret; 1980 1981 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1982 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1983 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1984 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1985 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1986 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 1987 out, sizeof(out)); 1988 if (ret) { 1989 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1990 rte_errno = errno; 1991 return -errno; 1992 } 1993 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 1994 hw_available_index); 1995 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 1996 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 1997 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 1998 virtio_q_context.error_type); 1999 return ret; 2000 } 2001 2002 /** 2003 * Create QP using DevX API. 2004 * 2005 * @param[in] ctx 2006 * Context returned from mlx5 open_device() glue function. 2007 * @param [in] attr 2008 * Pointer to QP attributes structure. 2009 * 2010 * @return 2011 * The DevX object created, NULL otherwise and rte_errno is set. 2012 */ 2013 struct mlx5_devx_obj * 2014 mlx5_devx_cmd_create_qp(void *ctx, 2015 struct mlx5_devx_qp_attr *attr) 2016 { 2017 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2018 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2019 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2020 sizeof(*qp_obj), 2021 0, SOCKET_ID_ANY); 2022 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2023 2024 if (!qp_obj) { 2025 DRV_LOG(ERR, "Failed to allocate QP data."); 2026 rte_errno = ENOMEM; 2027 return NULL; 2028 } 2029 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2030 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2031 MLX5_SET(qpc, qpc, pd, attr->pd); 2032 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2033 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2034 if (attr->uar_index) { 2035 if (attr->mmo) { 2036 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2037 in, qpc_extension_and_pas_list); 2038 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2039 qpc_ext_and_pas_list, qpc_data_extension); 2040 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2041 } 2042 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2043 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2044 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2045 MLX5_SET(qpc, qpc, log_page_size, 2046 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2047 if (attr->sq_size) { 2048 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); 2049 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2050 MLX5_SET(qpc, qpc, log_sq_size, 2051 rte_log2_u32(attr->sq_size)); 2052 } else { 2053 MLX5_SET(qpc, qpc, no_sq, 1); 2054 } 2055 if (attr->rq_size) { 2056 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); 2057 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2058 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2059 MLX5_LOG_RQ_STRIDE_SHIFT); 2060 MLX5_SET(qpc, qpc, log_rq_size, 2061 rte_log2_u32(attr->rq_size)); 2062 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2063 } else { 2064 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2065 } 2066 if (attr->dbr_umem_valid) { 2067 MLX5_SET(qpc, qpc, dbr_umem_valid, 2068 attr->dbr_umem_valid); 2069 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2070 } 2071 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2072 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2073 attr->wq_umem_offset); 2074 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2075 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2076 } else { 2077 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2078 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2079 MLX5_SET(qpc, qpc, no_sq, 1); 2080 } 2081 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2082 sizeof(out)); 2083 if (!qp_obj->obj) { 2084 rte_errno = errno; 2085 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 2086 mlx5_free(qp_obj); 2087 return NULL; 2088 } 2089 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2090 return qp_obj; 2091 } 2092 2093 /** 2094 * Modify QP using DevX API. 2095 * Currently supports only force loop-back QP. 2096 * 2097 * @param[in] qp 2098 * Pointer to QP object structure. 2099 * @param [in] qp_st_mod_op 2100 * The QP state modification operation. 2101 * @param [in] remote_qp_id 2102 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2103 * 2104 * @return 2105 * 0 on success, a negative errno value otherwise and rte_errno is set. 2106 */ 2107 int 2108 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2109 uint32_t remote_qp_id) 2110 { 2111 union { 2112 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2113 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2114 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2115 } in; 2116 union { 2117 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2118 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2119 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2120 } out; 2121 void *qpc; 2122 int ret; 2123 unsigned int inlen; 2124 unsigned int outlen; 2125 2126 memset(&in, 0, sizeof(in)); 2127 memset(&out, 0, sizeof(out)); 2128 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2129 switch (qp_st_mod_op) { 2130 case MLX5_CMD_OP_RST2INIT_QP: 2131 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2132 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2133 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2134 MLX5_SET(qpc, qpc, rre, 1); 2135 MLX5_SET(qpc, qpc, rwe, 1); 2136 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2137 inlen = sizeof(in.rst2init); 2138 outlen = sizeof(out.rst2init); 2139 break; 2140 case MLX5_CMD_OP_INIT2RTR_QP: 2141 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2142 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2143 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2144 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2145 MLX5_SET(qpc, qpc, mtu, 1); 2146 MLX5_SET(qpc, qpc, log_msg_max, 30); 2147 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2148 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2149 inlen = sizeof(in.init2rtr); 2150 outlen = sizeof(out.init2rtr); 2151 break; 2152 case MLX5_CMD_OP_RTR2RTS_QP: 2153 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2154 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2155 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 2156 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2157 MLX5_SET(qpc, qpc, retry_count, 7); 2158 MLX5_SET(qpc, qpc, rnr_retry, 7); 2159 inlen = sizeof(in.rtr2rts); 2160 outlen = sizeof(out.rtr2rts); 2161 break; 2162 default: 2163 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2164 qp_st_mod_op); 2165 rte_errno = EINVAL; 2166 return -rte_errno; 2167 } 2168 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2169 if (ret) { 2170 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2171 rte_errno = errno; 2172 return -rte_errno; 2173 } 2174 return ret; 2175 } 2176 2177 struct mlx5_devx_obj * 2178 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2179 { 2180 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2181 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2182 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2183 sizeof(*couners_obj), 0, 2184 SOCKET_ID_ANY); 2185 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2186 2187 if (!couners_obj) { 2188 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2189 rte_errno = ENOMEM; 2190 return NULL; 2191 } 2192 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2193 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2194 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2195 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2196 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2197 sizeof(out)); 2198 if (!couners_obj->obj) { 2199 rte_errno = errno; 2200 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 2201 " DevX."); 2202 mlx5_free(couners_obj); 2203 return NULL; 2204 } 2205 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2206 return couners_obj; 2207 } 2208 2209 int 2210 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2211 struct mlx5_devx_virtio_q_couners_attr *attr) 2212 { 2213 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2214 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2215 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2216 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2217 virtio_q_counters); 2218 int ret; 2219 2220 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2221 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2222 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2223 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2224 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2225 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2226 sizeof(out)); 2227 if (ret) { 2228 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2229 rte_errno = errno; 2230 return -errno; 2231 } 2232 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2233 received_desc); 2234 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2235 completed_desc); 2236 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2237 error_cqes); 2238 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2239 bad_desc_errors); 2240 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2241 exceed_max_chain); 2242 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2243 invalid_buffer); 2244 return ret; 2245 } 2246 2247 /** 2248 * Create general object of type FLOW_HIT_ASO using DevX API. 2249 * 2250 * @param[in] ctx 2251 * Context returned from mlx5 open_device() glue function. 2252 * @param [in] pd 2253 * PD value to associate the FLOW_HIT_ASO object with. 2254 * 2255 * @return 2256 * The DevX object created, NULL otherwise and rte_errno is set. 2257 */ 2258 struct mlx5_devx_obj * 2259 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2260 { 2261 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2262 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2263 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2264 void *ptr = NULL; 2265 2266 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2267 0, SOCKET_ID_ANY); 2268 if (!flow_hit_aso_obj) { 2269 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2270 rte_errno = ENOMEM; 2271 return NULL; 2272 } 2273 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2274 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2275 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2276 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2277 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2278 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2279 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2280 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2281 out, sizeof(out)); 2282 if (!flow_hit_aso_obj->obj) { 2283 rte_errno = errno; 2284 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX."); 2285 mlx5_free(flow_hit_aso_obj); 2286 return NULL; 2287 } 2288 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2289 return flow_hit_aso_obj; 2290 } 2291 2292 /* 2293 * Create PD using DevX API. 2294 * 2295 * @param[in] ctx 2296 * Context returned from mlx5 open_device() glue function. 2297 * 2298 * @return 2299 * The DevX object created, NULL otherwise and rte_errno is set. 2300 */ 2301 struct mlx5_devx_obj * 2302 mlx5_devx_cmd_alloc_pd(void *ctx) 2303 { 2304 struct mlx5_devx_obj *ppd = 2305 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2306 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2307 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2308 2309 if (!ppd) { 2310 DRV_LOG(ERR, "Failed to allocate PD data."); 2311 rte_errno = ENOMEM; 2312 return NULL; 2313 } 2314 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2315 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2316 out, sizeof(out)); 2317 if (!ppd->obj) { 2318 mlx5_free(ppd); 2319 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2320 rte_errno = errno; 2321 return NULL; 2322 } 2323 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2324 return ppd; 2325 } 2326 2327 /** 2328 * Create general object of type FLOW_METER_ASO using DevX API. 2329 * 2330 * @param[in] ctx 2331 * Context returned from mlx5 open_device() glue function. 2332 * @param [in] pd 2333 * PD value to associate the FLOW_METER_ASO object with. 2334 * @param [in] log_obj_size 2335 * log_obj_size define to allocate number of 2 * meters 2336 * in one FLOW_METER_ASO object. 2337 * 2338 * @return 2339 * The DevX object created, NULL otherwise and rte_errno is set. 2340 */ 2341 struct mlx5_devx_obj * 2342 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2343 uint32_t log_obj_size) 2344 { 2345 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2346 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2347 struct mlx5_devx_obj *flow_meter_aso_obj; 2348 void *ptr; 2349 2350 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2351 sizeof(*flow_meter_aso_obj), 2352 0, SOCKET_ID_ANY); 2353 if (!flow_meter_aso_obj) { 2354 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2355 rte_errno = ENOMEM; 2356 return NULL; 2357 } 2358 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2359 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2360 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2361 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2362 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2363 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2364 log_obj_size); 2365 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2366 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2367 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2368 ctx, in, sizeof(in), 2369 out, sizeof(out)); 2370 if (!flow_meter_aso_obj->obj) { 2371 rte_errno = errno; 2372 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX."); 2373 mlx5_free(flow_meter_aso_obj); 2374 return NULL; 2375 } 2376 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2377 out, obj_id); 2378 return flow_meter_aso_obj; 2379 } 2380 2381 /* 2382 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2383 * 2384 * @param[in] ctx 2385 * Context returned from mlx5 open_device() glue function. 2386 * @param [in] pd 2387 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2388 * @param [in] log_obj_size 2389 * log_obj_size to allocate its power of 2 * objects 2390 * in one CONN_TRACK_OFFLOAD bulk allocation. 2391 * 2392 * @return 2393 * The DevX object created, NULL otherwise and rte_errno is set. 2394 */ 2395 struct mlx5_devx_obj * 2396 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2397 uint32_t log_obj_size) 2398 { 2399 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2400 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2401 struct mlx5_devx_obj *ct_aso_obj; 2402 void *ptr; 2403 2404 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2405 0, SOCKET_ID_ANY); 2406 if (!ct_aso_obj) { 2407 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2408 rte_errno = ENOMEM; 2409 return NULL; 2410 } 2411 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2412 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2413 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2414 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2415 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2416 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2417 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2418 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2419 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2420 out, sizeof(out)); 2421 if (!ct_aso_obj->obj) { 2422 rte_errno = errno; 2423 DRV_LOG(ERR, "Failed to create CONN_TRACK_OFFLOAD obj by using DevX."); 2424 mlx5_free(ct_aso_obj); 2425 return NULL; 2426 } 2427 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2428 return ct_aso_obj; 2429 } 2430 2431 /** 2432 * Create general object of type GENEVE TLV option using DevX API. 2433 * 2434 * @param[in] ctx 2435 * Context returned from mlx5 open_device() glue function. 2436 * @param [in] class 2437 * TLV option variable value of class 2438 * @param [in] type 2439 * TLV option variable value of type 2440 * @param [in] len 2441 * TLV option variable value of len 2442 * 2443 * @return 2444 * The DevX object created, NULL otherwise and rte_errno is set. 2445 */ 2446 struct mlx5_devx_obj * 2447 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2448 uint16_t class, uint8_t type, uint8_t len) 2449 { 2450 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2451 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2452 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2453 sizeof(*geneve_tlv_opt_obj), 2454 0, SOCKET_ID_ANY); 2455 2456 if (!geneve_tlv_opt_obj) { 2457 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2458 rte_errno = ENOMEM; 2459 return NULL; 2460 } 2461 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2462 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2463 geneve_tlv_opt); 2464 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2465 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2466 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2467 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2468 MLX5_SET(geneve_tlv_option, opt, option_class, 2469 rte_be_to_cpu_16(class)); 2470 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2471 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2472 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2473 sizeof(in), out, sizeof(out)); 2474 if (!geneve_tlv_opt_obj->obj) { 2475 rte_errno = errno; 2476 DRV_LOG(ERR, "Failed to create Geneve tlv option " 2477 "Obj using DevX."); 2478 mlx5_free(geneve_tlv_opt_obj); 2479 return NULL; 2480 } 2481 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2482 return geneve_tlv_opt_obj; 2483 } 2484 2485 int 2486 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2487 { 2488 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2489 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2490 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2491 int rc; 2492 void *rq_ctx; 2493 2494 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2495 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2496 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2497 if (rc) { 2498 rte_errno = errno; 2499 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2500 "rc = %d, errno = %d.", rc, errno); 2501 return -rc; 2502 }; 2503 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2504 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2505 return 0; 2506 #else 2507 (void)wq; 2508 (void)counter_set_id; 2509 return -ENOTSUP; 2510 #endif 2511 } 2512 2513 /* 2514 * Allocate queue counters via devx interface. 2515 * 2516 * @param[in] ctx 2517 * Context returned from mlx5 open_device() glue function. 2518 * 2519 * @return 2520 * Pointer to counter object on success, a NULL value otherwise and 2521 * rte_errno is set. 2522 */ 2523 struct mlx5_devx_obj * 2524 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2525 { 2526 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2527 SOCKET_ID_ANY); 2528 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2529 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2530 2531 if (!dcs) { 2532 rte_errno = ENOMEM; 2533 return NULL; 2534 } 2535 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2536 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2537 sizeof(out)); 2538 if (!dcs->obj) { 2539 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error " 2540 "%d.", errno); 2541 rte_errno = errno; 2542 mlx5_free(dcs); 2543 return NULL; 2544 } 2545 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2546 return dcs; 2547 } 2548 2549 /** 2550 * Query queue counters values. 2551 * 2552 * @param[in] dcs 2553 * devx object of the queue counter set. 2554 * @param[in] clear 2555 * Whether hardware should clear the counters after the query or not. 2556 * @param[out] out_of_buffers 2557 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2558 * 2559 * @return 2560 * 0 on success, a negative value otherwise. 2561 */ 2562 int 2563 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2564 uint32_t *out_of_buffers) 2565 { 2566 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2567 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2568 int rc; 2569 2570 MLX5_SET(query_q_counter_in, in, opcode, 2571 MLX5_CMD_OP_QUERY_Q_COUNTER); 2572 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2573 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2574 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2575 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2576 sizeof(out)); 2577 if (rc) { 2578 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2579 rte_errno = rc; 2580 return -rc; 2581 } 2582 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2583 return 0; 2584 } 2585 2586 /** 2587 * Create general object of type DEK using DevX API. 2588 * 2589 * @param[in] ctx 2590 * Context returned from mlx5 open_device() glue function. 2591 * @param [in] attr 2592 * Pointer to DEK attributes structure. 2593 * 2594 * @return 2595 * The DevX object created, NULL otherwise and rte_errno is set. 2596 */ 2597 struct mlx5_devx_obj * 2598 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2599 { 2600 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2601 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2602 struct mlx5_devx_obj *dek_obj = NULL; 2603 void *ptr = NULL, *key_addr = NULL; 2604 2605 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2606 0, SOCKET_ID_ANY); 2607 if (dek_obj == NULL) { 2608 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2609 rte_errno = ENOMEM; 2610 return NULL; 2611 } 2612 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2613 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2614 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2615 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2616 MLX5_GENERAL_OBJ_TYPE_DEK); 2617 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2618 MLX5_SET(dek, ptr, key_size, attr->key_size); 2619 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2620 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2621 MLX5_SET(dek, ptr, pd, attr->pd); 2622 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2623 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2624 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2625 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2626 out, sizeof(out)); 2627 if (dek_obj->obj == NULL) { 2628 rte_errno = errno; 2629 DRV_LOG(ERR, "Failed to create DEK obj using DevX."); 2630 mlx5_free(dek_obj); 2631 return NULL; 2632 } 2633 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2634 return dek_obj; 2635 } 2636 2637 /** 2638 * Create general object of type IMPORT_KEK using DevX API. 2639 * 2640 * @param[in] ctx 2641 * Context returned from mlx5 open_device() glue function. 2642 * @param [in] attr 2643 * Pointer to IMPORT_KEK attributes structure. 2644 * 2645 * @return 2646 * The DevX object created, NULL otherwise and rte_errno is set. 2647 */ 2648 struct mlx5_devx_obj * 2649 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 2650 struct mlx5_devx_import_kek_attr *attr) 2651 { 2652 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 2653 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2654 struct mlx5_devx_obj *import_kek_obj = NULL; 2655 void *ptr = NULL, *key_addr = NULL; 2656 2657 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 2658 0, SOCKET_ID_ANY); 2659 if (import_kek_obj == NULL) { 2660 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 2661 rte_errno = ENOMEM; 2662 return NULL; 2663 } 2664 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 2665 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2666 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2667 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2668 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 2669 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 2670 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 2671 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 2672 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2673 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2674 out, sizeof(out)); 2675 if (import_kek_obj->obj == NULL) { 2676 rte_errno = errno; 2677 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX."); 2678 mlx5_free(import_kek_obj); 2679 return NULL; 2680 } 2681 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2682 return import_kek_obj; 2683 } 2684 2685 /** 2686 * Create general object of type CREDENTIAL using DevX API. 2687 * 2688 * @param[in] ctx 2689 * Context returned from mlx5 open_device() glue function. 2690 * @param [in] attr 2691 * Pointer to CREDENTIAL attributes structure. 2692 * 2693 * @return 2694 * The DevX object created, NULL otherwise and rte_errno is set. 2695 */ 2696 struct mlx5_devx_obj * 2697 mlx5_devx_cmd_create_credential_obj(void *ctx, 2698 struct mlx5_devx_credential_attr *attr) 2699 { 2700 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 2701 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2702 struct mlx5_devx_obj *credential_obj = NULL; 2703 void *ptr = NULL, *credential_addr = NULL; 2704 2705 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 2706 0, SOCKET_ID_ANY); 2707 if (credential_obj == NULL) { 2708 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 2709 rte_errno = ENOMEM; 2710 return NULL; 2711 } 2712 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 2713 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2714 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2715 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2716 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 2717 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 2718 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 2719 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 2720 memcpy(credential_addr, (void *)(attr->credential), 2721 MLX5_CRYPTO_CREDENTIAL_SIZE); 2722 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2723 out, sizeof(out)); 2724 if (credential_obj->obj == NULL) { 2725 rte_errno = errno; 2726 DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX."); 2727 mlx5_free(credential_obj); 2728 return NULL; 2729 } 2730 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2731 return credential_obj; 2732 } 2733 2734 /** 2735 * Create general object of type CRYPTO_LOGIN using DevX API. 2736 * 2737 * @param[in] ctx 2738 * Context returned from mlx5 open_device() glue function. 2739 * @param [in] attr 2740 * Pointer to CRYPTO_LOGIN attributes structure. 2741 * 2742 * @return 2743 * The DevX object created, NULL otherwise and rte_errno is set. 2744 */ 2745 struct mlx5_devx_obj * 2746 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 2747 struct mlx5_devx_crypto_login_attr *attr) 2748 { 2749 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 2750 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2751 struct mlx5_devx_obj *crypto_login_obj = NULL; 2752 void *ptr = NULL, *credential_addr = NULL; 2753 2754 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 2755 0, SOCKET_ID_ANY); 2756 if (crypto_login_obj == NULL) { 2757 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 2758 rte_errno = ENOMEM; 2759 return NULL; 2760 } 2761 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 2762 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2763 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2764 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2765 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 2766 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 2767 MLX5_SET(crypto_login, ptr, credential_pointer, 2768 attr->credential_pointer); 2769 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 2770 attr->session_import_kek_ptr); 2771 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 2772 memcpy(credential_addr, (void *)(attr->credential), 2773 MLX5_CRYPTO_CREDENTIAL_SIZE); 2774 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2775 out, sizeof(out)); 2776 if (crypto_login_obj->obj == NULL) { 2777 rte_errno = errno; 2778 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX."); 2779 mlx5_free(crypto_login_obj); 2780 return NULL; 2781 } 2782 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2783 return crypto_login_obj; 2784 } 2785