1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_COMMON_H_ 6 #define RTE_PMD_MLX5_COMMON_H_ 7 8 #include <stdio.h> 9 10 #include <rte_pci.h> 11 #include <rte_debug.h> 12 #include <rte_atomic.h> 13 #include <rte_log.h> 14 #include <rte_kvargs.h> 15 #include <rte_devargs.h> 16 #include <rte_bitops.h> 17 #include <rte_lcore.h> 18 #include <rte_spinlock.h> 19 #include <rte_os_shim.h> 20 21 #include "mlx5_prm.h" 22 #include "mlx5_devx_cmds.h" 23 #include "mlx5_common_os.h" 24 25 /* Reported driver name. */ 26 #define MLX5_PCI_DRIVER_NAME "mlx5_pci" 27 #define MLX5_AUXILIARY_DRIVER_NAME "mlx5_auxiliary" 28 29 /* Bit-field manipulation. */ 30 #define BITFIELD_DECLARE(bf, type, size) \ 31 type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \ 32 !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))] 33 #define BITFIELD_DEFINE(bf, type, size) \ 34 BITFIELD_DECLARE((bf), type, (size)) = { 0 } 35 #define BITFIELD_SET(bf, b) \ 36 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \ 37 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 38 #define BITFIELD_RESET(bf, b) \ 39 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \ 40 ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 41 #define BITFIELD_ISSET(bf, b) \ 42 !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \ 43 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))) 44 45 /* 46 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant 47 * manner. 48 */ 49 #define PMD_DRV_LOG_STRIP(a, b) a 50 #define PMD_DRV_LOG_OPAREN ( 51 #define PMD_DRV_LOG_CPAREN ) 52 #define PMD_DRV_LOG_COMMA , 53 54 /* Return the file name part of a path. */ 55 static inline const char * 56 pmd_drv_log_basename(const char *s) 57 { 58 const char *n = s; 59 60 while (*n) 61 if (*(n++) == '/') 62 s = n; 63 return s; 64 } 65 66 #define PMD_DRV_LOG___(level, type, name, ...) \ 67 rte_log(RTE_LOG_ ## level, \ 68 type, \ 69 RTE_FMT(name ": " \ 70 RTE_FMT_HEAD(__VA_ARGS__,), \ 71 RTE_FMT_TAIL(__VA_ARGS__,))) 72 73 #ifdef RTE_LIBRTE_MLX5_DEBUG 74 75 #define PMD_DRV_LOG__(level, type, name, ...) \ 76 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__) 77 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 78 PMD_DRV_LOG__(level, type, name,\ 79 s "\n" PMD_DRV_LOG_COMMA \ 80 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \ 81 __LINE__ PMD_DRV_LOG_COMMA \ 82 __func__, \ 83 __VA_ARGS__) 84 85 #else /* RTE_LIBRTE_MLX5_DEBUG */ 86 #define PMD_DRV_LOG__(level, type, name, ...) \ 87 PMD_DRV_LOG___(level, type, name, __VA_ARGS__) 88 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 89 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__) 90 91 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 92 93 /* claim_zero() does not perform any check when debugging is disabled. */ 94 #ifdef RTE_LIBRTE_MLX5_DEBUG 95 96 #define MLX5_ASSERT(exp) RTE_VERIFY(exp) 97 #define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0) 98 #define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0) 99 100 #else /* RTE_LIBRTE_MLX5_DEBUG */ 101 102 #define MLX5_ASSERT(exp) RTE_ASSERT(exp) 103 #define claim_zero(...) (__VA_ARGS__) 104 #define claim_nonzero(...) (__VA_ARGS__) 105 106 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 107 108 /* Allocate a buffer on the stack and fill it with a printf format string. */ 109 #define MKSTR(name, ...) \ 110 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \ 111 char name[mkstr_size_##name + 1]; \ 112 \ 113 memset(name, 0, mkstr_size_##name + 1); \ 114 snprintf(name, sizeof(name), "" __VA_ARGS__) 115 116 enum { 117 PCI_VENDOR_ID_MELLANOX = 0x15b3, 118 }; 119 120 enum { 121 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, 122 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, 123 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, 124 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, 125 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, 126 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, 127 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, 128 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, 129 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2, 130 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3, 131 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b, 132 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c, 133 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d, 134 PCI_DEVICE_ID_MELLANOX_CONNECTXVF = 0x101e, 135 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF = 0xa2d6, 136 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX = 0x101f, 137 PCI_DEVICE_ID_MELLANOX_CONNECTX7 = 0x1021, 138 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF = 0Xa2dc, 139 }; 140 141 /* Maximum number of simultaneous unicast MAC addresses. */ 142 #define MLX5_MAX_UC_MAC_ADDRESSES 128 143 /* Maximum number of simultaneous Multicast MAC addresses. */ 144 #define MLX5_MAX_MC_MAC_ADDRESSES 128 145 /* Maximum number of simultaneous MAC addresses. */ 146 #define MLX5_MAX_MAC_ADDRESSES \ 147 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES) 148 149 /* Recognized Infiniband device physical port name types. */ 150 enum mlx5_nl_phys_port_name_type { 151 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */ 152 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */ 153 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */ 154 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */ 155 MLX5_PHYS_PORT_NAME_TYPE_PFHPF, /* pf0, kernel ver >= 5.7, HPF rep */ 156 MLX5_PHYS_PORT_NAME_TYPE_PFSF, /* pf0sf0, kernel ver >= 5.0 */ 157 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */ 158 }; 159 160 /** Switch information returned by mlx5_nl_switch_info(). */ 161 struct mlx5_switch_info { 162 uint32_t master:1; /**< Master device. */ 163 uint32_t representor:1; /**< Representor device. */ 164 enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */ 165 int32_t ctrl_num; /**< Controller number (valid for c#pf#vf# format). */ 166 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */ 167 int32_t port_name; /**< Representor port name. */ 168 uint64_t switch_id; /**< Switch identifier. */ 169 }; 170 171 /* CQE status. */ 172 enum mlx5_cqe_status { 173 MLX5_CQE_STATUS_SW_OWN = -1, 174 MLX5_CQE_STATUS_HW_OWN = -2, 175 MLX5_CQE_STATUS_ERR = -3, 176 }; 177 178 /** 179 * Check whether CQE is valid. 180 * 181 * @param cqe 182 * Pointer to CQE. 183 * @param cqes_n 184 * Size of completion queue. 185 * @param ci 186 * Consumer index. 187 * 188 * @return 189 * The CQE status. 190 */ 191 static __rte_always_inline enum mlx5_cqe_status 192 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, 193 const uint16_t ci) 194 { 195 const uint16_t idx = ci & cqes_n; 196 const uint8_t op_own = cqe->op_own; 197 const uint8_t op_owner = MLX5_CQE_OWNER(op_own); 198 const uint8_t op_code = MLX5_CQE_OPCODE(op_own); 199 200 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID))) 201 return MLX5_CQE_STATUS_HW_OWN; 202 rte_io_rmb(); 203 if (unlikely(op_code == MLX5_CQE_RESP_ERR || 204 op_code == MLX5_CQE_REQ_ERR)) 205 return MLX5_CQE_STATUS_ERR; 206 return MLX5_CQE_STATUS_SW_OWN; 207 } 208 209 /* 210 * Get PCI address <DBDF> string from EAL device. 211 * 212 * @param[out] addr 213 * The output address buffer string 214 * @param[in] size 215 * The output buffer size 216 * @return 217 * - 0 on success. 218 * - Negative value and rte_errno is set otherwise. 219 */ 220 __rte_internal 221 int mlx5_dev_to_pci_str(const struct rte_device *dev, char *addr, size_t size); 222 223 /* 224 * Get PCI address from sysfs of a PCI-related device. 225 * 226 * @param[in] dev_path 227 * The sysfs path should not point to the direct plain PCI device. 228 * Instead, the node "/device/" is used to access the real device. 229 * @param[out] pci_addr 230 * Parsed PCI address. 231 * 232 * @return 233 * - 0 on success. 234 * - Negative value and rte_errno is set otherwise. 235 */ 236 __rte_internal 237 int mlx5_get_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr); 238 239 /* 240 * Get kernel network interface name from sysfs IB device path. 241 * 242 * @param[in] ibdev_path 243 * The sysfs path to IB device. 244 * @param[out] ifname 245 * Interface name output of size IF_NAMESIZE. 246 * 247 * @return 248 * - 0 on success. 249 * - Negative value and rte_errno is set otherwise. 250 */ 251 __rte_internal 252 int mlx5_get_ifname_sysfs(const char *ibdev_path, char *ifname); 253 254 __rte_internal 255 int mlx5_auxiliary_get_child_name(const char *dev, const char *node, 256 char *child, size_t size); 257 258 enum mlx5_class { 259 MLX5_CLASS_INVALID, 260 MLX5_CLASS_ETH = RTE_BIT64(0), 261 MLX5_CLASS_VDPA = RTE_BIT64(1), 262 MLX5_CLASS_REGEX = RTE_BIT64(2), 263 MLX5_CLASS_COMPRESS = RTE_BIT64(3), 264 MLX5_CLASS_CRYPTO = RTE_BIT64(4), 265 }; 266 267 #define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE 268 269 /* devX creation object */ 270 struct mlx5_devx_obj { 271 void *obj; /* The DV object. */ 272 int id; /* The object ID. */ 273 }; 274 275 /* UMR memory buffer used to define 1 entry in indirect mkey. */ 276 struct mlx5_klm { 277 uint32_t byte_count; 278 uint32_t mkey; 279 uint64_t address; 280 }; 281 282 __rte_internal 283 void mlx5_translate_port_name(const char *port_name_in, 284 struct mlx5_switch_info *port_info_out); 285 void mlx5_glue_constructor(void); 286 __rte_internal 287 void *mlx5_devx_alloc_uar(void *ctx, int mapping); 288 extern uint8_t haswell_broadwell_cpu; 289 290 __rte_internal 291 void mlx5_common_init(void); 292 293 /* 294 * Common Driver Interface 295 * 296 * ConnectX common driver supports multiple classes: net, vDPA, regex, crypto 297 * and compress devices. This layer enables creating such multiple classes 298 * on a single device by allowing to bind multiple class-specific device 299 * drivers to attach to the common driver. 300 * 301 * ------------ ------------- -------------- ----------------- ------------ 302 * | mlx5 net | | mlx5 vdpa | | mlx5 regex | | mlx5 compress | | mlx5 ... | 303 * | driver | | driver | | driver | | driver | | drivers | 304 * ------------ ------------- -------------- ----------------- ------------ 305 * || 306 * ----------------- 307 * | mlx5 | 308 * | common driver | 309 * ----------------- 310 * | | 311 * ----------- ----------------- 312 * | mlx5 | | mlx5 | 313 * | pci dev | | auxiliary dev | 314 * ----------- ----------------- 315 * 316 * - mlx5 PCI bus driver binds to mlx5 PCI devices defined by PCI ID table 317 * of all related devices. 318 * - mlx5 class driver such as net, vDPA, regex defines its specific 319 * PCI ID table and mlx5 bus driver probes matching class drivers. 320 * - mlx5 common driver is central place that validates supported 321 * class combinations. 322 * - mlx5 common driver hides bus difference by resolving device address 323 * from devargs, locating target RDMA device and probing with it. 324 */ 325 326 /** 327 * Initialization function for the driver called during device probing. 328 */ 329 typedef int (mlx5_class_driver_probe_t)(struct rte_device *dev); 330 331 /** 332 * Uninitialization function for the driver called during hot-unplugging. 333 */ 334 typedef int (mlx5_class_driver_remove_t)(struct rte_device *dev); 335 336 /** 337 * Driver-specific DMA mapping. After a successful call the device 338 * will be able to read/write from/to this segment. 339 * 340 * @param dev 341 * Pointer to the device. 342 * @param addr 343 * Starting virtual address of memory to be mapped. 344 * @param iova 345 * Starting IOVA address of memory to be mapped. 346 * @param len 347 * Length of memory segment being mapped. 348 * @return 349 * - 0 On success. 350 * - Negative value and rte_errno is set otherwise. 351 */ 352 typedef int (mlx5_class_driver_dma_map_t)(struct rte_device *dev, void *addr, 353 uint64_t iova, size_t len); 354 355 /** 356 * Driver-specific DMA un-mapping. After a successful call the device 357 * will not be able to read/write from/to this segment. 358 * 359 * @param dev 360 * Pointer to the device. 361 * @param addr 362 * Starting virtual address of memory to be unmapped. 363 * @param iova 364 * Starting IOVA address of memory to be unmapped. 365 * @param len 366 * Length of memory segment being unmapped. 367 * @return 368 * - 0 On success. 369 * - Negative value and rte_errno is set otherwise. 370 */ 371 typedef int (mlx5_class_driver_dma_unmap_t)(struct rte_device *dev, void *addr, 372 uint64_t iova, size_t len); 373 374 /** Device already probed can be probed again to check for new ports. */ 375 #define MLX5_DRV_PROBE_AGAIN 0x0004 376 377 /** 378 * A structure describing a mlx5 common class driver. 379 */ 380 struct mlx5_class_driver { 381 TAILQ_ENTRY(mlx5_class_driver) next; 382 enum mlx5_class drv_class; /**< Class of this driver. */ 383 const char *name; /**< Driver name. */ 384 mlx5_class_driver_probe_t *probe; /**< Device probe function. */ 385 mlx5_class_driver_remove_t *remove; /**< Device remove function. */ 386 mlx5_class_driver_dma_map_t *dma_map; /**< Device DMA map function. */ 387 mlx5_class_driver_dma_unmap_t *dma_unmap; 388 /**< Device DMA unmap function. */ 389 const struct rte_pci_id *id_table; /**< ID table, NULL terminated. */ 390 uint32_t probe_again:1; 391 /**< Device already probed can be probed again to check new device. */ 392 uint32_t intr_lsc:1; /**< Supports link state interrupt. */ 393 uint32_t intr_rmv:1; /**< Supports device remove interrupt. */ 394 }; 395 396 /** 397 * Register a mlx5 device driver. 398 * 399 * @param driver 400 * A pointer to a mlx5_driver structure describing the driver 401 * to be registered. 402 */ 403 __rte_internal 404 void 405 mlx5_class_driver_register(struct mlx5_class_driver *driver); 406 407 /** 408 * Test device is a PCI bus device. 409 * 410 * @param dev 411 * Pointer to device. 412 * 413 * @return 414 * - True on device devargs is a PCI bus device. 415 * - False otherwise. 416 */ 417 __rte_internal 418 bool 419 mlx5_dev_is_pci(const struct rte_device *dev); 420 421 #endif /* RTE_PMD_MLX5_COMMON_H_ */ 422