1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_COMMON_H_ 6 #define RTE_PMD_MLX5_COMMON_H_ 7 8 #include <stdio.h> 9 10 #include <rte_pci.h> 11 #include <rte_debug.h> 12 #include <rte_atomic.h> 13 #include <rte_log.h> 14 #include <rte_kvargs.h> 15 #include <rte_devargs.h> 16 17 #include "mlx5_prm.h" 18 #include "mlx5_devx_cmds.h" 19 20 21 /* Bit-field manipulation. */ 22 #define BITFIELD_DECLARE(bf, type, size) \ 23 type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \ 24 !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))] 25 #define BITFIELD_DEFINE(bf, type, size) \ 26 BITFIELD_DECLARE((bf), type, (size)) = { 0 } 27 #define BITFIELD_SET(bf, b) \ 28 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \ 29 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 30 #define BITFIELD_RESET(bf, b) \ 31 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \ 32 ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 33 #define BITFIELD_ISSET(bf, b) \ 34 !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \ 35 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))) 36 37 /* 38 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant 39 * manner. 40 */ 41 #define PMD_DRV_LOG_STRIP(a, b) a 42 #define PMD_DRV_LOG_OPAREN ( 43 #define PMD_DRV_LOG_CPAREN ) 44 #define PMD_DRV_LOG_COMMA , 45 46 /* Return the file name part of a path. */ 47 static inline const char * 48 pmd_drv_log_basename(const char *s) 49 { 50 const char *n = s; 51 52 while (*n) 53 if (*(n++) == '/') 54 s = n; 55 return s; 56 } 57 58 #define PMD_DRV_LOG___(level, type, name, ...) \ 59 rte_log(RTE_LOG_ ## level, \ 60 type, \ 61 RTE_FMT(name ": " \ 62 RTE_FMT_HEAD(__VA_ARGS__,), \ 63 RTE_FMT_TAIL(__VA_ARGS__,))) 64 65 /* 66 * When debugging is enabled (MLX5_DEBUG not defined), file, line and function 67 * information replace the driver name (MLX5_DRIVER_NAME) in log messages. 68 */ 69 #ifdef RTE_LIBRTE_MLX5_DEBUG 70 71 #define PMD_DRV_LOG__(level, type, name, ...) \ 72 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__) 73 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 74 PMD_DRV_LOG__(level, type, name,\ 75 s "\n" PMD_DRV_LOG_COMMA \ 76 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \ 77 __LINE__ PMD_DRV_LOG_COMMA \ 78 __func__, \ 79 __VA_ARGS__) 80 81 #else /* RTE_LIBRTE_MLX5_DEBUG */ 82 #define PMD_DRV_LOG__(level, type, name, ...) \ 83 PMD_DRV_LOG___(level, type, name, __VA_ARGS__) 84 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 85 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__) 86 87 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 88 89 /* claim_zero() does not perform any check when debugging is disabled. */ 90 #ifdef RTE_LIBRTE_MLX5_DEBUG 91 92 #define DEBUG(...) DRV_LOG(DEBUG, __VA_ARGS__) 93 #define MLX5_ASSERT(exp) RTE_VERIFY(exp) 94 #define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0) 95 #define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0) 96 97 #else /* RTE_LIBRTE_MLX5_DEBUG */ 98 99 #define DEBUG(...) (void)0 100 #define MLX5_ASSERT(exp) RTE_ASSERT(exp) 101 #define claim_zero(...) (__VA_ARGS__) 102 #define claim_nonzero(...) (__VA_ARGS__) 103 104 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 105 106 /* Allocate a buffer on the stack and fill it with a printf format string. */ 107 #define MKSTR(name, ...) \ 108 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \ 109 char name[mkstr_size_##name + 1]; \ 110 \ 111 snprintf(name, sizeof(name), "" __VA_ARGS__) 112 113 enum { 114 PCI_VENDOR_ID_MELLANOX = 0x15b3, 115 }; 116 117 enum { 118 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, 119 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, 120 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, 121 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, 122 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, 123 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, 124 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, 125 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, 126 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2, 127 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3, 128 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b, 129 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c, 130 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d, 131 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e, 132 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF = 0xa2d6, 133 }; 134 135 /* Maximum number of simultaneous unicast MAC addresses. */ 136 #define MLX5_MAX_UC_MAC_ADDRESSES 128 137 /* Maximum number of simultaneous Multicast MAC addresses. */ 138 #define MLX5_MAX_MC_MAC_ADDRESSES 128 139 /* Maximum number of simultaneous MAC addresses. */ 140 #define MLX5_MAX_MAC_ADDRESSES \ 141 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES) 142 143 /* Recognized Infiniband device physical port name types. */ 144 enum mlx5_nl_phys_port_name_type { 145 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */ 146 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */ 147 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */ 148 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */ 149 MLX5_PHYS_PORT_NAME_TYPE_PFHPF, /* pf0, kernel ver >= 5.7, HPF rep */ 150 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */ 151 }; 152 153 /** Switch information returned by mlx5_nl_switch_info(). */ 154 struct mlx5_switch_info { 155 uint32_t master:1; /**< Master device. */ 156 uint32_t representor:1; /**< Representor device. */ 157 enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */ 158 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */ 159 int32_t port_name; /**< Representor port name. */ 160 uint64_t switch_id; /**< Switch identifier. */ 161 }; 162 163 /* CQE status. */ 164 enum mlx5_cqe_status { 165 MLX5_CQE_STATUS_SW_OWN = -1, 166 MLX5_CQE_STATUS_HW_OWN = -2, 167 MLX5_CQE_STATUS_ERR = -3, 168 }; 169 170 /** 171 * Check whether CQE is valid. 172 * 173 * @param cqe 174 * Pointer to CQE. 175 * @param cqes_n 176 * Size of completion queue. 177 * @param ci 178 * Consumer index. 179 * 180 * @return 181 * The CQE status. 182 */ 183 static __rte_always_inline enum mlx5_cqe_status 184 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, 185 const uint16_t ci) 186 { 187 const uint16_t idx = ci & cqes_n; 188 const uint8_t op_own = cqe->op_own; 189 const uint8_t op_owner = MLX5_CQE_OWNER(op_own); 190 const uint8_t op_code = MLX5_CQE_OPCODE(op_own); 191 192 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID))) 193 return MLX5_CQE_STATUS_HW_OWN; 194 rte_cio_rmb(); 195 if (unlikely(op_code == MLX5_CQE_RESP_ERR || 196 op_code == MLX5_CQE_REQ_ERR)) 197 return MLX5_CQE_STATUS_ERR; 198 return MLX5_CQE_STATUS_SW_OWN; 199 } 200 201 __rte_internal 202 int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr); 203 __rte_internal 204 int mlx5_get_ifname_sysfs(const char *ibdev_path, char *ifname); 205 206 207 #define MLX5_CLASS_ARG_NAME "class" 208 209 enum mlx5_class { 210 MLX5_CLASS_NET, 211 MLX5_CLASS_VDPA, 212 MLX5_CLASS_INVALID, 213 }; 214 215 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */ 216 #define MLX5_DBR_SIZE 8 217 #define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE) 218 #define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64) 219 220 struct mlx5_devx_dbr_page { 221 /* Door-bell records, must be first member in structure. */ 222 uint8_t dbrs[MLX5_DBR_PAGE_SIZE]; 223 LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */ 224 void *umem; 225 uint32_t dbr_count; /* Number of door-bell records in use. */ 226 /* 1 bit marks matching door-bell is in use. */ 227 uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE]; 228 }; 229 230 /* devX creation object */ 231 struct mlx5_devx_obj { 232 void *obj; /* The DV object. */ 233 int id; /* The object ID. */ 234 }; 235 236 /* UMR memory buffer used to define 1 entry in indirect mkey. */ 237 struct mlx5_klm { 238 uint32_t byte_count; 239 uint32_t mkey; 240 uint64_t address; 241 }; 242 243 LIST_HEAD(mlx5_dbr_page_list, mlx5_devx_dbr_page); 244 245 __rte_internal 246 enum mlx5_class mlx5_class_get(struct rte_devargs *devargs); 247 __rte_internal 248 void mlx5_translate_port_name(const char *port_name_in, 249 struct mlx5_switch_info *port_info_out); 250 void mlx5_glue_constructor(void); 251 __rte_internal 252 int64_t mlx5_get_dbr(void *ctx, struct mlx5_dbr_page_list *head, 253 struct mlx5_devx_dbr_page **dbr_page); 254 __rte_internal 255 int32_t mlx5_release_dbr(struct mlx5_dbr_page_list *head, uint32_t umem_id, 256 uint64_t offset); 257 extern uint8_t haswell_broadwell_cpu; 258 259 #endif /* RTE_PMD_MLX5_COMMON_H_ */ 260