1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_COMMON_H_ 6 #define RTE_PMD_MLX5_COMMON_H_ 7 8 #include <stdio.h> 9 10 #include <rte_compat.h> 11 #include <rte_pci.h> 12 #include <bus_pci_driver.h> 13 #include <rte_debug.h> 14 #include <rte_atomic.h> 15 #include <rte_rwlock.h> 16 #include <rte_log.h> 17 #include <rte_kvargs.h> 18 #include <rte_devargs.h> 19 #include <rte_bitops.h> 20 #include <rte_lcore.h> 21 #include <rte_spinlock.h> 22 #include <rte_os_shim.h> 23 24 #include "mlx5_prm.h" 25 #include "mlx5_devx_cmds.h" 26 #include "mlx5_common_os.h" 27 #include "mlx5_common_mr.h" 28 29 /* Reported driver name. */ 30 #define MLX5_PCI_DRIVER_NAME "mlx5_pci" 31 #define MLX5_AUXILIARY_DRIVER_NAME "mlx5_auxiliary" 32 33 /* Bit-field manipulation. */ 34 #define BITFIELD_DECLARE(bf, type, size) \ 35 type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \ 36 !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))] 37 #define BITFIELD_DEFINE(bf, type, size) \ 38 BITFIELD_DECLARE((bf), type, (size)) = { 0 } 39 #define BITFIELD_SET(bf, b) \ 40 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \ 41 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 42 #define BITFIELD_RESET(bf, b) \ 43 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \ 44 ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 45 #define BITFIELD_ISSET(bf, b) \ 46 !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \ 47 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))) 48 49 /* 50 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant 51 * manner. 52 */ 53 #define PMD_DRV_LOG_STRIP(a, b) a 54 #define PMD_DRV_LOG_OPAREN ( 55 #define PMD_DRV_LOG_CPAREN ) 56 #define PMD_DRV_LOG_COMMA , 57 58 /* Return the file name part of a path. */ 59 static inline const char * 60 pmd_drv_log_basename(const char *s) 61 { 62 const char *n = s; 63 64 while (*n) 65 if (*(n++) == '/') 66 s = n; 67 return s; 68 } 69 70 #define PMD_DRV_LOG___(level, type, name, ...) \ 71 rte_log(RTE_LOG_ ## level, \ 72 type, \ 73 RTE_FMT(name ": " \ 74 RTE_FMT_HEAD(__VA_ARGS__,), \ 75 RTE_FMT_TAIL(__VA_ARGS__,))) 76 77 #ifdef RTE_LIBRTE_MLX5_DEBUG 78 79 #define PMD_DRV_LOG__(level, type, name, ...) \ 80 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__) 81 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 82 PMD_DRV_LOG__(level, type, name,\ 83 s "\n" PMD_DRV_LOG_COMMA \ 84 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \ 85 __LINE__ PMD_DRV_LOG_COMMA \ 86 __func__, \ 87 __VA_ARGS__) 88 89 #else /* RTE_LIBRTE_MLX5_DEBUG */ 90 #define PMD_DRV_LOG__(level, type, name, ...) \ 91 PMD_DRV_LOG___(level, type, name, __VA_ARGS__) 92 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 93 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__) 94 95 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 96 97 /* claim_zero() does not perform any check when debugging is disabled. */ 98 #ifdef RTE_LIBRTE_MLX5_DEBUG 99 100 #define MLX5_ASSERT(exp) RTE_VERIFY(exp) 101 #define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0) 102 #define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0) 103 104 #else /* RTE_LIBRTE_MLX5_DEBUG */ 105 106 #define MLX5_ASSERT(exp) RTE_ASSERT(exp) 107 #define claim_zero(...) (__VA_ARGS__) 108 #define claim_nonzero(...) (__VA_ARGS__) 109 110 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 111 112 /* Allocate a buffer on the stack and fill it with a printf format string. */ 113 #define MKSTR(name, ...) \ 114 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \ 115 char name[mkstr_size_##name + 1]; \ 116 \ 117 memset(name, 0, mkstr_size_##name + 1); \ 118 snprintf(name, sizeof(name), "" __VA_ARGS__) 119 120 enum { 121 PCI_VENDOR_ID_MELLANOX = 0x15b3, 122 }; 123 124 enum { 125 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, 126 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, 127 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, 128 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, 129 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, 130 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, 131 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, 132 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, 133 PCI_DEVICE_ID_MELLANOX_BLUEFIELD = 0xa2d2, 134 PCI_DEVICE_ID_MELLANOX_BLUEFIELDVF = 0xa2d3, 135 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b, 136 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c, 137 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d, 138 PCI_DEVICE_ID_MELLANOX_CONNECTXVF = 0x101e, 139 PCI_DEVICE_ID_MELLANOX_BLUEFIELD2 = 0xa2d6, 140 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX = 0x101f, 141 PCI_DEVICE_ID_MELLANOX_CONNECTX7 = 0x1021, 142 PCI_DEVICE_ID_MELLANOX_BLUEFIELD3 = 0Xa2dc, 143 }; 144 145 /* Maximum number of simultaneous unicast MAC addresses. */ 146 #define MLX5_MAX_UC_MAC_ADDRESSES 128 147 /* Maximum number of simultaneous Multicast MAC addresses. */ 148 #define MLX5_MAX_MC_MAC_ADDRESSES 128 149 /* Maximum number of simultaneous MAC addresses. */ 150 #define MLX5_MAX_MAC_ADDRESSES \ 151 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES) 152 153 /* Recognized Infiniband device physical port name types. */ 154 enum mlx5_nl_phys_port_name_type { 155 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */ 156 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */ 157 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */ 158 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */ 159 MLX5_PHYS_PORT_NAME_TYPE_PFHPF, /* pf0, kernel ver >= 5.7, HPF rep */ 160 MLX5_PHYS_PORT_NAME_TYPE_PFSF, /* pf0sf0, kernel ver >= 5.0 */ 161 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */ 162 }; 163 164 /** Switch information returned by mlx5_nl_switch_info(). */ 165 struct mlx5_switch_info { 166 uint32_t master:1; /**< Master device. */ 167 uint32_t representor:1; /**< Representor device. */ 168 enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */ 169 int32_t ctrl_num; /**< Controller number (valid for c#pf#vf# format). */ 170 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */ 171 int32_t port_name; /**< Representor port name. */ 172 uint64_t switch_id; /**< Switch identifier. */ 173 }; 174 175 /* CQE status. */ 176 enum mlx5_cqe_status { 177 MLX5_CQE_STATUS_SW_OWN = -1, 178 MLX5_CQE_STATUS_HW_OWN = -2, 179 MLX5_CQE_STATUS_ERR = -3, 180 }; 181 182 /** 183 * Check whether CQE has an error opcode. 184 * 185 * @param op_code 186 * Opcode to check. 187 * 188 * @return 189 * The CQE status. 190 */ 191 static __rte_always_inline enum mlx5_cqe_status 192 check_cqe_error(const uint8_t op_code) 193 { 194 rte_io_rmb(); 195 if (unlikely(op_code == MLX5_CQE_RESP_ERR || 196 op_code == MLX5_CQE_REQ_ERR)) 197 return MLX5_CQE_STATUS_ERR; 198 return MLX5_CQE_STATUS_SW_OWN; 199 } 200 201 /** 202 * Check whether CQE is valid using owner bit. 203 * 204 * @param cqe 205 * Pointer to CQE. 206 * @param cqes_n 207 * Size of completion queue. 208 * @param ci 209 * Consumer index. 210 * 211 * @return 212 * The CQE status. 213 */ 214 static __rte_always_inline enum mlx5_cqe_status 215 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, 216 const uint16_t ci) 217 { 218 const uint16_t idx = ci & cqes_n; 219 const uint8_t op_own = cqe->op_own; 220 const uint8_t op_owner = MLX5_CQE_OWNER(op_own); 221 const uint8_t op_code = MLX5_CQE_OPCODE(op_own); 222 223 if (unlikely((op_owner != (!!(idx))) || 224 (op_code == MLX5_CQE_INVALID))) 225 return MLX5_CQE_STATUS_HW_OWN; 226 return check_cqe_error(op_code); 227 } 228 229 /** 230 * Check whether CQE is valid using validity iteration count. 231 * 232 * @param cqe 233 * Pointer to CQE. 234 * @param cqes_n 235 * Log 2 of completion queue size. 236 * @param ci 237 * Consumer index. 238 * 239 * @return 240 * The CQE status. 241 */ 242 static __rte_always_inline enum mlx5_cqe_status 243 check_cqe_iteration(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, 244 const uint32_t ci) 245 { 246 const uint8_t op_own = cqe->op_own; 247 const uint8_t op_code = MLX5_CQE_OPCODE(op_own); 248 const uint8_t vic = ci >> cqes_n; 249 250 if (unlikely((cqe->validity_iteration_count != vic) || 251 (op_code == MLX5_CQE_INVALID))) 252 return MLX5_CQE_STATUS_HW_OWN; 253 return check_cqe_error(op_code); 254 } 255 256 /* 257 * Get PCI address <DBDF> string from EAL device. 258 * 259 * @param[out] addr 260 * The output address buffer string 261 * @param[in] size 262 * The output buffer size 263 * @return 264 * - 0 on success. 265 * - Negative value and rte_errno is set otherwise. 266 */ 267 __rte_internal 268 int mlx5_dev_to_pci_str(const struct rte_device *dev, char *addr, size_t size); 269 270 /* 271 * Get PCI address from sysfs of a PCI-related device. 272 * 273 * @param[in] dev_path 274 * The sysfs path should not point to the direct plain PCI device. 275 * Instead, the node "/device/" is used to access the real device. 276 * @param[out] pci_addr 277 * Parsed PCI address. 278 * 279 * @return 280 * - 0 on success. 281 * - Negative value and rte_errno is set otherwise. 282 */ 283 __rte_internal 284 int mlx5_get_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr); 285 286 /* 287 * Get kernel network interface name from sysfs IB device path. 288 * 289 * @param[in] ibdev_path 290 * The sysfs path to IB device. 291 * @param[out] ifname 292 * Interface name output of size IF_NAMESIZE. 293 * 294 * @return 295 * - 0 on success. 296 * - Negative value and rte_errno is set otherwise. 297 */ 298 __rte_internal 299 int mlx5_get_ifname_sysfs(const char *ibdev_path, char *ifname); 300 301 __rte_internal 302 int mlx5_auxiliary_get_child_name(const char *dev, const char *node, 303 char *child, size_t size); 304 305 enum mlx5_class { 306 MLX5_CLASS_INVALID, 307 MLX5_CLASS_ETH = RTE_BIT64(0), 308 MLX5_CLASS_VDPA = RTE_BIT64(1), 309 MLX5_CLASS_REGEX = RTE_BIT64(2), 310 MLX5_CLASS_COMPRESS = RTE_BIT64(3), 311 MLX5_CLASS_CRYPTO = RTE_BIT64(4), 312 }; 313 314 #define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE 315 316 /* devX creation object */ 317 struct mlx5_devx_obj { 318 void *obj; /* The DV object. */ 319 int id; /* The object ID. */ 320 }; 321 322 /* UMR memory buffer used to define 1 entry in indirect mkey. */ 323 struct mlx5_klm { 324 uint32_t byte_count; 325 uint32_t mkey; 326 uint64_t address; 327 }; 328 329 /** Control for key/values list. */ 330 struct mlx5_kvargs_ctrl { 331 struct rte_kvargs *kvlist; /* Structure containing list of key/values.*/ 332 bool is_used[RTE_KVARGS_MAX]; /* Indicator which devargs were used. */ 333 }; 334 335 /** 336 * Call a handler function for each key/value in the list of keys. 337 * 338 * For each key/value association that matches the given key, calls the 339 * handler function with the for a given arg_name passing the value on the 340 * dictionary for that key and a given extra argument. 341 * 342 * @param mkvlist 343 * The mlx5_kvargs structure. 344 * @param keys 345 * A list of keys to process (table of const char *, the last must be NULL). 346 * @param handler 347 * The function to call for each matching key. 348 * @param opaque_arg 349 * A pointer passed unchanged to the handler. 350 * 351 * @return 352 * - 0 on success 353 * - Negative on error 354 */ 355 __rte_internal 356 int 357 mlx5_kvargs_process(struct mlx5_kvargs_ctrl *mkvlist, const char *const keys[], 358 arg_handler_t handler, void *opaque_arg); 359 360 /* All UAR arguments using doorbell register in datapath. */ 361 struct mlx5_uar_data { 362 uint64_t *db; 363 /* The doorbell's virtual address mapped to the relevant HW UAR space.*/ 364 #ifndef RTE_ARCH_64 365 rte_spinlock_t *sl_p; 366 /* Pointer to UAR access lock required for 32bit implementations. */ 367 #endif /* RTE_ARCH_64 */ 368 }; 369 370 /* DevX UAR control structure. */ 371 struct mlx5_uar { 372 struct mlx5_uar_data bf_db; /* UAR data for Blueflame register. */ 373 struct mlx5_uar_data cq_db; /* UAR data for CQ arm db register. */ 374 void *obj; /* DevX UAR object. */ 375 bool dbnc; /* Doorbell mapped to non-cached region. */ 376 #ifndef RTE_ARCH_64 377 rte_spinlock_t bf_sl; 378 rte_spinlock_t cq_sl; 379 /* UAR access locks required for 32bit implementations. */ 380 #endif /* RTE_ARCH_64 */ 381 }; 382 383 /** 384 * Ring a doorbell and flush the update if requested. 385 * 386 * @param uar 387 * Pointer to UAR data structure. 388 * @param val 389 * value to write in big endian format. 390 * @param index 391 * Index of doorbell record. 392 * @param db_rec 393 * Address of doorbell record. 394 * @param flash 395 * Decide whether to flush the DB writing using a memory barrier. 396 */ 397 static __rte_always_inline void 398 mlx5_doorbell_ring(struct mlx5_uar_data *uar, uint64_t val, uint32_t index, 399 volatile uint32_t *db_rec, bool flash) 400 { 401 rte_io_wmb(); 402 *db_rec = rte_cpu_to_be_32(index); 403 /* Ensure ordering between DB record actual update and UAR access. */ 404 rte_wmb(); 405 #ifdef RTE_ARCH_64 406 *uar->db = val; 407 #else /* !RTE_ARCH_64 */ 408 rte_spinlock_lock(uar->sl_p); 409 *(volatile uint32_t *)uar->db = val; 410 rte_io_wmb(); 411 *((volatile uint32_t *)uar->db + 1) = val >> 32; 412 rte_spinlock_unlock(uar->sl_p); 413 #endif 414 if (flash) 415 rte_wmb(); 416 } 417 418 /** 419 * Get the doorbell register mapping type. 420 * 421 * @param uar_mmap_offset 422 * Mmap offset of Verbs/DevX UAR. 423 * @param page_size 424 * System page size 425 * 426 * @return 427 * 1 for non-cached, 0 otherwise. 428 */ 429 static inline uint16_t 430 mlx5_db_map_type_get(off_t uar_mmap_offset, size_t page_size) 431 { 432 off_t cmd = uar_mmap_offset / page_size; 433 434 cmd >>= MLX5_UAR_MMAP_CMD_SHIFT; 435 cmd &= MLX5_UAR_MMAP_CMD_MASK; 436 if (cmd == MLX5_MMAP_GET_NC_PAGES_CMD) 437 return 1; 438 return 0; 439 } 440 441 __rte_internal 442 void mlx5_translate_port_name(const char *port_name_in, 443 struct mlx5_switch_info *port_info_out); 444 void mlx5_glue_constructor(void); 445 extern uint8_t haswell_broadwell_cpu; 446 447 __rte_internal 448 void mlx5_common_init(void); 449 450 /* 451 * Common Driver Interface 452 * 453 * ConnectX common driver supports multiple classes: net, vDPA, regex, crypto 454 * and compress devices. This layer enables creating such multiple classes 455 * on a single device by allowing to bind multiple class-specific device 456 * drivers to attach to the common driver. 457 * 458 * ------------ ------------- -------------- ----------------- ------------ 459 * | mlx5 net | | mlx5 vdpa | | mlx5 regex | | mlx5 compress | | mlx5 ... | 460 * | driver | | driver | | driver | | driver | | drivers | 461 * ------------ ------------- -------------- ----------------- ------------ 462 * || 463 * ----------------- 464 * | mlx5 | 465 * | common driver | 466 * ----------------- 467 * | | 468 * ----------- ----------------- 469 * | mlx5 | | mlx5 | 470 * | pci dev | | auxiliary dev | 471 * ----------- ----------------- 472 * 473 * - mlx5 PCI bus driver binds to mlx5 PCI devices defined by PCI ID table 474 * of all related devices. 475 * - mlx5 class driver such as net, vDPA, regex defines its specific 476 * PCI ID table and mlx5 bus driver probes matching class drivers. 477 * - mlx5 common driver is central place that validates supported 478 * class combinations. 479 * - mlx5 common driver hides bus difference by resolving device address 480 * from devargs, locating target RDMA device and probing with it. 481 */ 482 483 /* 484 * Device configuration structure. 485 * 486 * Merged configuration from: 487 * 488 * - Device capabilities, 489 * - User device parameters disabled features. 490 */ 491 struct mlx5_common_dev_config { 492 struct mlx5_hca_attr hca_attr; /* HCA attributes. */ 493 int dbnc; /* Skip doorbell register write barrier. */ 494 int device_fd; /* Device file descriptor for importation. */ 495 int pd_handle; /* Protection Domain handle for importation. */ 496 unsigned int devx:1; /* Whether devx interface is available or not. */ 497 unsigned int sys_mem_en:1; /* The default memory allocator. */ 498 unsigned int mr_mempool_reg_en:1; 499 /* Allow/prevent implicit mempool memory registration. */ 500 unsigned int mr_ext_memseg_en:1; 501 /* Whether memseg should be extended for MR creation. */ 502 }; 503 504 struct mlx5_common_device { 505 struct rte_device *dev; 506 TAILQ_ENTRY(mlx5_common_device) next; 507 uint32_t classes_loaded; 508 void *ctx; /* Verbs/DV/DevX context. */ 509 void *pd; /* Protection Domain. */ 510 uint32_t pdn; /* Protection Domain Number. */ 511 struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ 512 struct mlx5_common_dev_config config; /* Device configuration. */ 513 }; 514 515 /** 516 * Indicates whether PD and CTX are imported from another process, 517 * or created by this process. 518 * 519 * @param cdev 520 * Pointer to common device. 521 * 522 * @return 523 * True if PD and CTX are imported from another process, False otherwise. 524 */ 525 static inline bool 526 mlx5_imported_pd_and_ctx(struct mlx5_common_device *cdev) 527 { 528 return cdev->config.device_fd != MLX5_ARG_UNSET && 529 cdev->config.pd_handle != MLX5_ARG_UNSET; 530 } 531 532 /** 533 * Initialization function for the driver called during device probing. 534 */ 535 typedef int (mlx5_class_driver_probe_t)(struct mlx5_common_device *cdev, 536 struct mlx5_kvargs_ctrl *mkvlist); 537 538 /** 539 * Uninitialization function for the driver called during hot-unplugging. 540 */ 541 typedef int (mlx5_class_driver_remove_t)(struct mlx5_common_device *cdev); 542 543 /** Device already probed can be probed again to check for new ports. */ 544 #define MLX5_DRV_PROBE_AGAIN 0x0004 545 546 /** 547 * A structure describing a mlx5 common class driver. 548 */ 549 struct mlx5_class_driver { 550 TAILQ_ENTRY(mlx5_class_driver) next; 551 enum mlx5_class drv_class; /**< Class of this driver. */ 552 const char *name; /**< Driver name. */ 553 mlx5_class_driver_probe_t *probe; /**< Device probe function. */ 554 mlx5_class_driver_remove_t *remove; /**< Device remove function. */ 555 const struct rte_pci_id *id_table; /**< ID table, NULL terminated. */ 556 uint32_t probe_again:1; 557 /**< Device already probed can be probed again to check new device. */ 558 uint32_t intr_lsc:1; /**< Supports link state interrupt. */ 559 uint32_t intr_rmv:1; /**< Supports device remove interrupt. */ 560 }; 561 562 /** 563 * Register a mlx5 device driver. 564 * 565 * @param driver 566 * A pointer to a mlx5_driver structure describing the driver 567 * to be registered. 568 */ 569 __rte_internal 570 void 571 mlx5_class_driver_register(struct mlx5_class_driver *driver); 572 573 /** 574 * Test device is a PCI bus device. 575 * 576 * @param dev 577 * Pointer to device. 578 * 579 * @return 580 * - True on device devargs is a PCI bus device. 581 * - False otherwise. 582 */ 583 __rte_internal 584 bool 585 mlx5_dev_is_pci(const struct rte_device *dev); 586 587 /** 588 * Test PCI device is a VF device. 589 * 590 * @param pci_dev 591 * Pointer to PCI device. 592 * 593 * @return 594 * - True on PCI device is a VF device. 595 * - False otherwise. 596 */ 597 __rte_internal 598 bool 599 mlx5_dev_is_vf_pci(struct rte_pci_device *pci_dev); 600 601 __rte_internal 602 int 603 mlx5_dev_mempool_subscribe(struct mlx5_common_device *cdev); 604 605 __rte_internal 606 void 607 mlx5_dev_mempool_unregister(struct mlx5_common_device *cdev, 608 struct rte_mempool *mp); 609 610 __rte_internal 611 int 612 mlx5_devx_uar_prepare(struct mlx5_common_device *cdev, struct mlx5_uar *uar); 613 614 __rte_internal 615 void 616 mlx5_devx_uar_release(struct mlx5_uar *uar); 617 618 /* mlx5_common_os.c */ 619 620 int mlx5_os_open_device(struct mlx5_common_device *cdev, uint32_t classes); 621 int mlx5_os_pd_prepare(struct mlx5_common_device *cdev); 622 int mlx5_os_pd_release(struct mlx5_common_device *cdev); 623 int mlx5_os_remote_pd_and_ctx_validate(struct mlx5_common_dev_config *config); 624 625 /* mlx5 PMD wrapped MR struct. */ 626 struct mlx5_pmd_wrapped_mr { 627 uint32_t lkey; 628 void *addr; 629 size_t len; 630 void *obj; /* verbs mr object or devx umem object. */ 631 void *imkey; /* DevX indirect mkey object. */ 632 }; 633 634 __rte_internal 635 int 636 mlx5_os_wrapped_mkey_create(void *ctx, void *pd, uint32_t pdn, void *addr, 637 size_t length, struct mlx5_pmd_wrapped_mr *pmd_mr); 638 639 __rte_internal 640 void 641 mlx5_os_wrapped_mkey_destroy(struct mlx5_pmd_wrapped_mr *pmd_mr); 642 643 #endif /* RTE_PMD_MLX5_COMMON_H_ */ 644