1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_COMMON_H_ 6 #define RTE_PMD_MLX5_COMMON_H_ 7 8 #include <stdio.h> 9 10 #include <rte_pci.h> 11 #include <rte_debug.h> 12 #include <rte_atomic.h> 13 #include <rte_log.h> 14 #include <rte_kvargs.h> 15 #include <rte_devargs.h> 16 #include <rte_bitops.h> 17 18 #include "mlx5_prm.h" 19 #include "mlx5_devx_cmds.h" 20 21 /* Reported driver name. */ 22 #define MLX5_PCI_DRIVER_NAME "mlx5_pci" 23 24 /* Bit-field manipulation. */ 25 #define BITFIELD_DECLARE(bf, type, size) \ 26 type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \ 27 !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))] 28 #define BITFIELD_DEFINE(bf, type, size) \ 29 BITFIELD_DECLARE((bf), type, (size)) = { 0 } 30 #define BITFIELD_SET(bf, b) \ 31 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \ 32 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 33 #define BITFIELD_RESET(bf, b) \ 34 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \ 35 ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 36 #define BITFIELD_ISSET(bf, b) \ 37 !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \ 38 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))) 39 40 /* 41 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant 42 * manner. 43 */ 44 #define PMD_DRV_LOG_STRIP(a, b) a 45 #define PMD_DRV_LOG_OPAREN ( 46 #define PMD_DRV_LOG_CPAREN ) 47 #define PMD_DRV_LOG_COMMA , 48 49 /* Return the file name part of a path. */ 50 static inline const char * 51 pmd_drv_log_basename(const char *s) 52 { 53 const char *n = s; 54 55 while (*n) 56 if (*(n++) == '/') 57 s = n; 58 return s; 59 } 60 61 #define PMD_DRV_LOG___(level, type, name, ...) \ 62 rte_log(RTE_LOG_ ## level, \ 63 type, \ 64 RTE_FMT(name ": " \ 65 RTE_FMT_HEAD(__VA_ARGS__,), \ 66 RTE_FMT_TAIL(__VA_ARGS__,))) 67 68 #ifdef RTE_LIBRTE_MLX5_DEBUG 69 70 #define PMD_DRV_LOG__(level, type, name, ...) \ 71 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__) 72 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 73 PMD_DRV_LOG__(level, type, name,\ 74 s "\n" PMD_DRV_LOG_COMMA \ 75 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \ 76 __LINE__ PMD_DRV_LOG_COMMA \ 77 __func__, \ 78 __VA_ARGS__) 79 80 #else /* RTE_LIBRTE_MLX5_DEBUG */ 81 #define PMD_DRV_LOG__(level, type, name, ...) \ 82 PMD_DRV_LOG___(level, type, name, __VA_ARGS__) 83 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 84 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__) 85 86 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 87 88 /* claim_zero() does not perform any check when debugging is disabled. */ 89 #ifdef RTE_LIBRTE_MLX5_DEBUG 90 91 #define MLX5_ASSERT(exp) RTE_VERIFY(exp) 92 #define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0) 93 #define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0) 94 95 #else /* RTE_LIBRTE_MLX5_DEBUG */ 96 97 #define MLX5_ASSERT(exp) RTE_ASSERT(exp) 98 #define claim_zero(...) (__VA_ARGS__) 99 #define claim_nonzero(...) (__VA_ARGS__) 100 101 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 102 103 /* Allocate a buffer on the stack and fill it with a printf format string. */ 104 #define MKSTR(name, ...) \ 105 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \ 106 char name[mkstr_size_##name + 1]; \ 107 \ 108 snprintf(name, sizeof(name), "" __VA_ARGS__) 109 110 enum { 111 PCI_VENDOR_ID_MELLANOX = 0x15b3, 112 }; 113 114 enum { 115 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, 116 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, 117 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, 118 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, 119 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, 120 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, 121 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, 122 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, 123 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2, 124 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3, 125 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b, 126 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c, 127 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d, 128 PCI_DEVICE_ID_MELLANOX_CONNECTXVF = 0x101e, 129 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF = 0xa2d6, 130 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX = 0x101f, 131 PCI_DEVICE_ID_MELLANOX_CONNECTX7 = 0x1021, 132 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF = 0Xa2dc, 133 }; 134 135 /* Maximum number of simultaneous unicast MAC addresses. */ 136 #define MLX5_MAX_UC_MAC_ADDRESSES 128 137 /* Maximum number of simultaneous Multicast MAC addresses. */ 138 #define MLX5_MAX_MC_MAC_ADDRESSES 128 139 /* Maximum number of simultaneous MAC addresses. */ 140 #define MLX5_MAX_MAC_ADDRESSES \ 141 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES) 142 143 /* Recognized Infiniband device physical port name types. */ 144 enum mlx5_nl_phys_port_name_type { 145 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */ 146 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */ 147 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */ 148 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */ 149 MLX5_PHYS_PORT_NAME_TYPE_PFHPF, /* pf0, kernel ver >= 5.7, HPF rep */ 150 MLX5_PHYS_PORT_NAME_TYPE_PFSF, /* pf0sf0, kernel ver >= 5.0 */ 151 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */ 152 }; 153 154 /** Switch information returned by mlx5_nl_switch_info(). */ 155 struct mlx5_switch_info { 156 uint32_t master:1; /**< Master device. */ 157 uint32_t representor:1; /**< Representor device. */ 158 enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */ 159 int32_t ctrl_num; /**< Controller number (valid for c#pf#vf# format). */ 160 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */ 161 int32_t port_name; /**< Representor port name. */ 162 uint64_t switch_id; /**< Switch identifier. */ 163 }; 164 165 /* CQE status. */ 166 enum mlx5_cqe_status { 167 MLX5_CQE_STATUS_SW_OWN = -1, 168 MLX5_CQE_STATUS_HW_OWN = -2, 169 MLX5_CQE_STATUS_ERR = -3, 170 }; 171 172 /** 173 * Check whether CQE is valid. 174 * 175 * @param cqe 176 * Pointer to CQE. 177 * @param cqes_n 178 * Size of completion queue. 179 * @param ci 180 * Consumer index. 181 * 182 * @return 183 * The CQE status. 184 */ 185 static __rte_always_inline enum mlx5_cqe_status 186 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, 187 const uint16_t ci) 188 { 189 const uint16_t idx = ci & cqes_n; 190 const uint8_t op_own = cqe->op_own; 191 const uint8_t op_owner = MLX5_CQE_OWNER(op_own); 192 const uint8_t op_code = MLX5_CQE_OPCODE(op_own); 193 194 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID))) 195 return MLX5_CQE_STATUS_HW_OWN; 196 rte_io_rmb(); 197 if (unlikely(op_code == MLX5_CQE_RESP_ERR || 198 op_code == MLX5_CQE_REQ_ERR)) 199 return MLX5_CQE_STATUS_ERR; 200 return MLX5_CQE_STATUS_SW_OWN; 201 } 202 203 __rte_internal 204 int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr); 205 __rte_internal 206 int mlx5_get_ifname_sysfs(const char *ibdev_path, char *ifname); 207 208 209 #define MLX5_CLASS_ARG_NAME "class" 210 211 enum mlx5_class { 212 MLX5_CLASS_INVALID, 213 MLX5_CLASS_NET = RTE_BIT64(0), 214 MLX5_CLASS_VDPA = RTE_BIT64(1), 215 MLX5_CLASS_REGEX = RTE_BIT64(2), 216 MLX5_CLASS_COMPRESS = RTE_BIT64(3), 217 }; 218 219 #define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE 220 221 /* devX creation object */ 222 struct mlx5_devx_obj { 223 void *obj; /* The DV object. */ 224 int id; /* The object ID. */ 225 }; 226 227 /* UMR memory buffer used to define 1 entry in indirect mkey. */ 228 struct mlx5_klm { 229 uint32_t byte_count; 230 uint32_t mkey; 231 uint64_t address; 232 }; 233 234 __rte_internal 235 void mlx5_translate_port_name(const char *port_name_in, 236 struct mlx5_switch_info *port_info_out); 237 void mlx5_glue_constructor(void); 238 __rte_internal 239 void *mlx5_devx_alloc_uar(void *ctx, int mapping); 240 extern uint8_t haswell_broadwell_cpu; 241 242 __rte_internal 243 void mlx5_common_init(void); 244 245 #endif /* RTE_PMD_MLX5_COMMON_H_ */ 246