1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_COMMON_H_ 6 #define RTE_PMD_MLX5_COMMON_H_ 7 8 #include <stdio.h> 9 10 #include <rte_pci.h> 11 #include <rte_debug.h> 12 #include <rte_atomic.h> 13 #include <rte_log.h> 14 #include <rte_kvargs.h> 15 #include <rte_devargs.h> 16 #include <rte_bitops.h> 17 18 #include "mlx5_prm.h" 19 #include "mlx5_devx_cmds.h" 20 21 /* Reported driver name. */ 22 #define MLX5_DRIVER_NAME "mlx5_pci" 23 24 /* Bit-field manipulation. */ 25 #define BITFIELD_DECLARE(bf, type, size) \ 26 type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \ 27 !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))] 28 #define BITFIELD_DEFINE(bf, type, size) \ 29 BITFIELD_DECLARE((bf), type, (size)) = { 0 } 30 #define BITFIELD_SET(bf, b) \ 31 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \ 32 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 33 #define BITFIELD_RESET(bf, b) \ 34 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \ 35 ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 36 #define BITFIELD_ISSET(bf, b) \ 37 !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \ 38 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))) 39 40 /* 41 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant 42 * manner. 43 */ 44 #define PMD_DRV_LOG_STRIP(a, b) a 45 #define PMD_DRV_LOG_OPAREN ( 46 #define PMD_DRV_LOG_CPAREN ) 47 #define PMD_DRV_LOG_COMMA , 48 49 /* Return the file name part of a path. */ 50 static inline const char * 51 pmd_drv_log_basename(const char *s) 52 { 53 const char *n = s; 54 55 while (*n) 56 if (*(n++) == '/') 57 s = n; 58 return s; 59 } 60 61 #define PMD_DRV_LOG___(level, type, name, ...) \ 62 rte_log(RTE_LOG_ ## level, \ 63 type, \ 64 RTE_FMT(name ": " \ 65 RTE_FMT_HEAD(__VA_ARGS__,), \ 66 RTE_FMT_TAIL(__VA_ARGS__,))) 67 68 /* 69 * When debugging is enabled (MLX5_DEBUG not defined), file, line and function 70 * information replace the driver name (MLX5_DRIVER_NAME) in log messages. 71 */ 72 #ifdef RTE_LIBRTE_MLX5_DEBUG 73 74 #define PMD_DRV_LOG__(level, type, name, ...) \ 75 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__) 76 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 77 PMD_DRV_LOG__(level, type, name,\ 78 s "\n" PMD_DRV_LOG_COMMA \ 79 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \ 80 __LINE__ PMD_DRV_LOG_COMMA \ 81 __func__, \ 82 __VA_ARGS__) 83 84 #else /* RTE_LIBRTE_MLX5_DEBUG */ 85 #define PMD_DRV_LOG__(level, type, name, ...) \ 86 PMD_DRV_LOG___(level, type, name, __VA_ARGS__) 87 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 88 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__) 89 90 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 91 92 /* claim_zero() does not perform any check when debugging is disabled. */ 93 #ifdef RTE_LIBRTE_MLX5_DEBUG 94 95 #define DEBUG(...) DRV_LOG(DEBUG, __VA_ARGS__) 96 #define MLX5_ASSERT(exp) RTE_VERIFY(exp) 97 #define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0) 98 #define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0) 99 100 #else /* RTE_LIBRTE_MLX5_DEBUG */ 101 102 #define DEBUG(...) (void)0 103 #define MLX5_ASSERT(exp) RTE_ASSERT(exp) 104 #define claim_zero(...) (__VA_ARGS__) 105 #define claim_nonzero(...) (__VA_ARGS__) 106 107 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 108 109 /* Allocate a buffer on the stack and fill it with a printf format string. */ 110 #define MKSTR(name, ...) \ 111 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \ 112 char name[mkstr_size_##name + 1]; \ 113 \ 114 snprintf(name, sizeof(name), "" __VA_ARGS__) 115 116 enum { 117 PCI_VENDOR_ID_MELLANOX = 0x15b3, 118 }; 119 120 enum { 121 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, 122 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, 123 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, 124 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, 125 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, 126 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, 127 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, 128 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, 129 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2, 130 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3, 131 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b, 132 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c, 133 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d, 134 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e, 135 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF = 0xa2d6, 136 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX = 0x101f, 137 PCI_DEVICE_ID_MELLANOX_CONNECTX7 = 0x1021, 138 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF = 0Xa2dc, 139 }; 140 141 /* Maximum number of simultaneous unicast MAC addresses. */ 142 #define MLX5_MAX_UC_MAC_ADDRESSES 128 143 /* Maximum number of simultaneous Multicast MAC addresses. */ 144 #define MLX5_MAX_MC_MAC_ADDRESSES 128 145 /* Maximum number of simultaneous MAC addresses. */ 146 #define MLX5_MAX_MAC_ADDRESSES \ 147 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES) 148 149 /* Recognized Infiniband device physical port name types. */ 150 enum mlx5_nl_phys_port_name_type { 151 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */ 152 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */ 153 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */ 154 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */ 155 MLX5_PHYS_PORT_NAME_TYPE_PFHPF, /* pf0, kernel ver >= 5.7, HPF rep */ 156 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */ 157 }; 158 159 /** Switch information returned by mlx5_nl_switch_info(). */ 160 struct mlx5_switch_info { 161 uint32_t master:1; /**< Master device. */ 162 uint32_t representor:1; /**< Representor device. */ 163 enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */ 164 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */ 165 int32_t port_name; /**< Representor port name. */ 166 uint64_t switch_id; /**< Switch identifier. */ 167 }; 168 169 /* CQE status. */ 170 enum mlx5_cqe_status { 171 MLX5_CQE_STATUS_SW_OWN = -1, 172 MLX5_CQE_STATUS_HW_OWN = -2, 173 MLX5_CQE_STATUS_ERR = -3, 174 }; 175 176 /** 177 * Check whether CQE is valid. 178 * 179 * @param cqe 180 * Pointer to CQE. 181 * @param cqes_n 182 * Size of completion queue. 183 * @param ci 184 * Consumer index. 185 * 186 * @return 187 * The CQE status. 188 */ 189 static __rte_always_inline enum mlx5_cqe_status 190 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, 191 const uint16_t ci) 192 { 193 const uint16_t idx = ci & cqes_n; 194 const uint8_t op_own = cqe->op_own; 195 const uint8_t op_owner = MLX5_CQE_OWNER(op_own); 196 const uint8_t op_code = MLX5_CQE_OPCODE(op_own); 197 198 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID))) 199 return MLX5_CQE_STATUS_HW_OWN; 200 rte_io_rmb(); 201 if (unlikely(op_code == MLX5_CQE_RESP_ERR || 202 op_code == MLX5_CQE_REQ_ERR)) 203 return MLX5_CQE_STATUS_ERR; 204 return MLX5_CQE_STATUS_SW_OWN; 205 } 206 207 __rte_internal 208 int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr); 209 __rte_internal 210 int mlx5_get_ifname_sysfs(const char *ibdev_path, char *ifname); 211 212 213 #define MLX5_CLASS_ARG_NAME "class" 214 215 enum mlx5_class { 216 MLX5_CLASS_INVALID, 217 MLX5_CLASS_NET = RTE_BIT64(0), 218 MLX5_CLASS_VDPA = RTE_BIT64(1), 219 MLX5_CLASS_REGEX = RTE_BIT64(2), 220 }; 221 222 #define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE 223 #define MLX5_DBR_PER_PAGE 64 224 /* Must be >= CHAR_BIT * sizeof(uint64_t) */ 225 #define MLX5_DBR_PAGE_SIZE (MLX5_DBR_PER_PAGE * MLX5_DBR_SIZE) 226 /* Page size must be >= 512. */ 227 #define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / (CHAR_BIT * sizeof(uint64_t))) 228 229 struct mlx5_devx_dbr_page { 230 /* Door-bell records, must be first member in structure. */ 231 uint8_t dbrs[MLX5_DBR_PAGE_SIZE]; 232 LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */ 233 void *umem; 234 uint32_t dbr_count; /* Number of door-bell records in use. */ 235 /* 1 bit marks matching door-bell is in use. */ 236 uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE]; 237 }; 238 239 /* devX creation object */ 240 struct mlx5_devx_obj { 241 void *obj; /* The DV object. */ 242 int id; /* The object ID. */ 243 }; 244 245 /* UMR memory buffer used to define 1 entry in indirect mkey. */ 246 struct mlx5_klm { 247 uint32_t byte_count; 248 uint32_t mkey; 249 uint64_t address; 250 }; 251 252 LIST_HEAD(mlx5_dbr_page_list, mlx5_devx_dbr_page); 253 254 __rte_internal 255 void mlx5_translate_port_name(const char *port_name_in, 256 struct mlx5_switch_info *port_info_out); 257 void mlx5_glue_constructor(void); 258 __rte_internal 259 int64_t mlx5_get_dbr(void *ctx, struct mlx5_dbr_page_list *head, 260 struct mlx5_devx_dbr_page **dbr_page); 261 __rte_internal 262 int32_t mlx5_release_dbr(struct mlx5_dbr_page_list *head, uint32_t umem_id, 263 uint64_t offset); 264 extern uint8_t haswell_broadwell_cpu; 265 266 __rte_internal 267 void mlx5_common_init(void); 268 269 #endif /* RTE_PMD_MLX5_COMMON_H_ */ 270