1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_COMMON_H_ 6 #define RTE_PMD_MLX5_COMMON_H_ 7 8 #include <stdio.h> 9 10 #include <rte_pci.h> 11 #include <rte_debug.h> 12 #include <rte_atomic.h> 13 #include <rte_log.h> 14 #include <rte_kvargs.h> 15 #include <rte_devargs.h> 16 17 #include "mlx5_prm.h" 18 19 20 /* 21 * Compilation workaround for PPC64 when AltiVec is fully enabled, e.g. std=c11. 22 * Otherwise there would be a type conflict between stdbool and altivec. 23 */ 24 #if defined(__PPC64__) && !defined(__APPLE_ALTIVEC__) 25 #undef bool 26 /* redefine as in stdbool.h */ 27 #define bool _Bool 28 #endif 29 30 /* Bit-field manipulation. */ 31 #define BITFIELD_DECLARE(bf, type, size) \ 32 type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \ 33 !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))] 34 #define BITFIELD_DEFINE(bf, type, size) \ 35 BITFIELD_DECLARE((bf), type, (size)) = { 0 } 36 #define BITFIELD_SET(bf, b) \ 37 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \ 38 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 39 #define BITFIELD_RESET(bf, b) \ 40 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \ 41 ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 42 #define BITFIELD_ISSET(bf, b) \ 43 !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \ 44 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))) 45 46 /* 47 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant 48 * manner. 49 */ 50 #define PMD_DRV_LOG_STRIP(a, b) a 51 #define PMD_DRV_LOG_OPAREN ( 52 #define PMD_DRV_LOG_CPAREN ) 53 #define PMD_DRV_LOG_COMMA , 54 55 /* Return the file name part of a path. */ 56 static inline const char * 57 pmd_drv_log_basename(const char *s) 58 { 59 const char *n = s; 60 61 while (*n) 62 if (*(n++) == '/') 63 s = n; 64 return s; 65 } 66 67 #define PMD_DRV_LOG___(level, type, name, ...) \ 68 rte_log(RTE_LOG_ ## level, \ 69 type, \ 70 RTE_FMT(name ": " \ 71 RTE_FMT_HEAD(__VA_ARGS__,), \ 72 RTE_FMT_TAIL(__VA_ARGS__,))) 73 74 /* 75 * When debugging is enabled (MLX5_DEBUG not defined), file, line and function 76 * information replace the driver name (MLX5_DRIVER_NAME) in log messages. 77 */ 78 #ifdef RTE_LIBRTE_MLX5_DEBUG 79 80 #define PMD_DRV_LOG__(level, type, name, ...) \ 81 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__) 82 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 83 PMD_DRV_LOG__(level, type, name,\ 84 s "\n" PMD_DRV_LOG_COMMA \ 85 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \ 86 __LINE__ PMD_DRV_LOG_COMMA \ 87 __func__, \ 88 __VA_ARGS__) 89 90 #else /* RTE_LIBRTE_MLX5_DEBUG */ 91 #define PMD_DRV_LOG__(level, type, name, ...) \ 92 PMD_DRV_LOG___(level, type, name, __VA_ARGS__) 93 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 94 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__) 95 96 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 97 98 /* claim_zero() does not perform any check when debugging is disabled. */ 99 #ifdef RTE_LIBRTE_MLX5_DEBUG 100 101 #define DEBUG(...) DRV_LOG(DEBUG, __VA_ARGS__) 102 #define MLX5_ASSERT(exp) RTE_VERIFY(exp) 103 #define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0) 104 #define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0) 105 106 #else /* RTE_LIBRTE_MLX5_DEBUG */ 107 108 #define DEBUG(...) (void)0 109 #define MLX5_ASSERT(exp) RTE_ASSERT(exp) 110 #define claim_zero(...) (__VA_ARGS__) 111 #define claim_nonzero(...) (__VA_ARGS__) 112 113 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 114 115 /* Allocate a buffer on the stack and fill it with a printf format string. */ 116 #define MKSTR(name, ...) \ 117 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \ 118 char name[mkstr_size_##name + 1]; \ 119 \ 120 snprintf(name, sizeof(name), "" __VA_ARGS__) 121 122 enum { 123 PCI_VENDOR_ID_MELLANOX = 0x15b3, 124 }; 125 126 enum { 127 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, 128 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, 129 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, 130 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, 131 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, 132 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, 133 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, 134 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, 135 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2, 136 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3, 137 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b, 138 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c, 139 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d, 140 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e, 141 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF = 0xa2d6, 142 }; 143 144 /* Maximum number of simultaneous unicast MAC addresses. */ 145 #define MLX5_MAX_UC_MAC_ADDRESSES 128 146 /* Maximum number of simultaneous Multicast MAC addresses. */ 147 #define MLX5_MAX_MC_MAC_ADDRESSES 128 148 /* Maximum number of simultaneous MAC addresses. */ 149 #define MLX5_MAX_MAC_ADDRESSES \ 150 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES) 151 152 /* Recognized Infiniband device physical port name types. */ 153 enum mlx5_nl_phys_port_name_type { 154 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */ 155 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */ 156 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */ 157 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */ 158 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */ 159 }; 160 161 /** Switch information returned by mlx5_nl_switch_info(). */ 162 struct mlx5_switch_info { 163 uint32_t master:1; /**< Master device. */ 164 uint32_t representor:1; /**< Representor device. */ 165 enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */ 166 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */ 167 int32_t port_name; /**< Representor port name. */ 168 uint64_t switch_id; /**< Switch identifier. */ 169 }; 170 171 /* CQE status. */ 172 enum mlx5_cqe_status { 173 MLX5_CQE_STATUS_SW_OWN = -1, 174 MLX5_CQE_STATUS_HW_OWN = -2, 175 MLX5_CQE_STATUS_ERR = -3, 176 }; 177 178 /** 179 * Check whether CQE is valid. 180 * 181 * @param cqe 182 * Pointer to CQE. 183 * @param cqes_n 184 * Size of completion queue. 185 * @param ci 186 * Consumer index. 187 * 188 * @return 189 * The CQE status. 190 */ 191 static __rte_always_inline enum mlx5_cqe_status 192 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, 193 const uint16_t ci) 194 { 195 const uint16_t idx = ci & cqes_n; 196 const uint8_t op_own = cqe->op_own; 197 const uint8_t op_owner = MLX5_CQE_OWNER(op_own); 198 const uint8_t op_code = MLX5_CQE_OPCODE(op_own); 199 200 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID))) 201 return MLX5_CQE_STATUS_HW_OWN; 202 rte_cio_rmb(); 203 if (unlikely(op_code == MLX5_CQE_RESP_ERR || 204 op_code == MLX5_CQE_REQ_ERR)) 205 return MLX5_CQE_STATUS_ERR; 206 return MLX5_CQE_STATUS_SW_OWN; 207 } 208 209 int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr); 210 211 #define MLX5_CLASS_ARG_NAME "class" 212 213 enum mlx5_class { 214 MLX5_CLASS_NET, 215 MLX5_CLASS_VDPA, 216 MLX5_CLASS_INVALID, 217 }; 218 219 enum mlx5_class mlx5_class_get(struct rte_devargs *devargs); 220 void mlx5_translate_port_name(const char *port_name_in, 221 struct mlx5_switch_info *port_info_out); 222 223 #endif /* RTE_PMD_MLX5_COMMON_H_ */ 224