1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_COMMON_H_ 6 #define RTE_PMD_MLX5_COMMON_H_ 7 8 #include <stdio.h> 9 10 #include <rte_compat.h> 11 #include <rte_pci.h> 12 #include <bus_pci_driver.h> 13 #include <rte_debug.h> 14 #include <rte_atomic.h> 15 #include <rte_rwlock.h> 16 #include <rte_log.h> 17 #include <rte_kvargs.h> 18 #include <rte_devargs.h> 19 #include <rte_bitops.h> 20 #include <rte_lcore.h> 21 #include <rte_spinlock.h> 22 #include <rte_os_shim.h> 23 24 #include "mlx5_prm.h" 25 #include "mlx5_devx_cmds.h" 26 #include "mlx5_common_os.h" 27 #include "mlx5_common_mr.h" 28 29 /* Reported driver name. */ 30 #define MLX5_PCI_DRIVER_NAME "mlx5_pci" 31 #define MLX5_AUXILIARY_DRIVER_NAME "mlx5_auxiliary" 32 33 /* Bit-field manipulation. */ 34 #define BITFIELD_DECLARE(bf, type, size) \ 35 type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \ 36 !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))] 37 #define BITFIELD_DEFINE(bf, type, size) \ 38 BITFIELD_DECLARE((bf), type, (size)) = { 0 } 39 #define BITFIELD_SET(bf, b) \ 40 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \ 41 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 42 #define BITFIELD_RESET(bf, b) \ 43 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \ 44 ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 45 #define BITFIELD_ISSET(bf, b) \ 46 !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \ 47 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))) 48 49 /* 50 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant 51 * manner. 52 */ 53 #define PMD_DRV_LOG_STRIP(a, b) a 54 #define PMD_DRV_LOG_OPAREN ( 55 #define PMD_DRV_LOG_CPAREN ) 56 #define PMD_DRV_LOG_COMMA , 57 58 /* Return the file name part of a path. */ 59 static inline const char * 60 pmd_drv_log_basename(const char *s) 61 { 62 const char *n = s; 63 64 while (*n) 65 if (*(n++) == '/') 66 s = n; 67 return s; 68 } 69 70 #define PMD_DRV_LOG___(level, type, name, ...) \ 71 rte_log(RTE_LOG_ ## level, \ 72 type, \ 73 RTE_FMT(name ": " \ 74 RTE_FMT_HEAD(__VA_ARGS__,), \ 75 RTE_FMT_TAIL(__VA_ARGS__,))) 76 77 #ifdef RTE_LIBRTE_MLX5_DEBUG 78 79 #define PMD_DRV_LOG__(level, type, name, ...) \ 80 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__) 81 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 82 PMD_DRV_LOG__(level, type, name,\ 83 s "\n" PMD_DRV_LOG_COMMA \ 84 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \ 85 __LINE__ PMD_DRV_LOG_COMMA \ 86 __func__, \ 87 __VA_ARGS__) 88 89 #else /* RTE_LIBRTE_MLX5_DEBUG */ 90 #define PMD_DRV_LOG__(level, type, name, ...) \ 91 PMD_DRV_LOG___(level, type, name, __VA_ARGS__) 92 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 93 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__) 94 95 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 96 97 /* claim_zero() does not perform any check when debugging is disabled. */ 98 #ifdef RTE_LIBRTE_MLX5_DEBUG 99 100 #define MLX5_ASSERT(exp) RTE_VERIFY(exp) 101 #define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0) 102 #define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0) 103 104 #else /* RTE_LIBRTE_MLX5_DEBUG */ 105 106 #define MLX5_ASSERT(exp) RTE_ASSERT(exp) 107 #define claim_zero(...) (__VA_ARGS__) 108 #define claim_nonzero(...) (__VA_ARGS__) 109 110 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 111 112 /* Allocate a buffer on the stack and fill it with a printf format string. */ 113 #define MKSTR(name, ...) \ 114 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \ 115 char name[mkstr_size_##name + 1]; \ 116 \ 117 memset(name, 0, mkstr_size_##name + 1); \ 118 snprintf(name, sizeof(name), "" __VA_ARGS__) 119 120 enum { 121 PCI_VENDOR_ID_MELLANOX = 0x15b3, 122 }; 123 124 enum { 125 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, 126 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, 127 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, 128 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, 129 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, 130 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, 131 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, 132 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, 133 PCI_DEVICE_ID_MELLANOX_BLUEFIELD = 0xa2d2, 134 PCI_DEVICE_ID_MELLANOX_BLUEFIELDVF = 0xa2d3, 135 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b, 136 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c, 137 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d, 138 PCI_DEVICE_ID_MELLANOX_CONNECTXVF = 0x101e, 139 PCI_DEVICE_ID_MELLANOX_BLUEFIELD2 = 0xa2d6, 140 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX = 0x101f, 141 PCI_DEVICE_ID_MELLANOX_CONNECTX7 = 0x1021, 142 PCI_DEVICE_ID_MELLANOX_BLUEFIELD3 = 0Xa2dc, 143 }; 144 145 /* Maximum number of simultaneous unicast MAC addresses. */ 146 #define MLX5_MAX_UC_MAC_ADDRESSES 128 147 /* Maximum number of simultaneous Multicast MAC addresses. */ 148 #define MLX5_MAX_MC_MAC_ADDRESSES 128 149 /* Maximum number of simultaneous MAC addresses. */ 150 #define MLX5_MAX_MAC_ADDRESSES \ 151 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES) 152 153 /* Recognized Infiniband device physical port name types. */ 154 enum mlx5_nl_phys_port_name_type { 155 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */ 156 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */ 157 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */ 158 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */ 159 MLX5_PHYS_PORT_NAME_TYPE_PFHPF, /* pf0, kernel ver >= 5.7, HPF rep */ 160 MLX5_PHYS_PORT_NAME_TYPE_PFSF, /* pf0sf0, kernel ver >= 5.0 */ 161 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */ 162 }; 163 164 /** Switch information returned by mlx5_nl_switch_info(). */ 165 struct mlx5_switch_info { 166 uint32_t master:1; /**< Master device. */ 167 uint32_t representor:1; /**< Representor device. */ 168 enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */ 169 int32_t ctrl_num; /**< Controller number (valid for c#pf#vf# format). */ 170 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */ 171 int32_t port_name; /**< Representor port name. */ 172 uint64_t switch_id; /**< Switch identifier. */ 173 }; 174 175 /* CQE status. */ 176 enum mlx5_cqe_status { 177 MLX5_CQE_STATUS_SW_OWN = -1, 178 MLX5_CQE_STATUS_HW_OWN = -2, 179 MLX5_CQE_STATUS_ERR = -3, 180 }; 181 182 /** 183 * Check whether CQE has an error opcode. 184 * 185 * @param op_code 186 * Opcode to check. 187 * 188 * @return 189 * The CQE status. 190 */ 191 static __rte_always_inline enum mlx5_cqe_status 192 check_cqe_error(const uint8_t op_code) 193 { 194 /* Prevent speculative reading of other fields in CQE until 195 * CQE is valid. 196 */ 197 rte_atomic_thread_fence(__ATOMIC_ACQUIRE); 198 199 if (unlikely(op_code == MLX5_CQE_RESP_ERR || 200 op_code == MLX5_CQE_REQ_ERR)) 201 return MLX5_CQE_STATUS_ERR; 202 return MLX5_CQE_STATUS_SW_OWN; 203 } 204 205 /** 206 * Check whether CQE is valid using owner bit. 207 * 208 * @param cqe 209 * Pointer to CQE. 210 * @param cqes_n 211 * Size of completion queue. 212 * @param ci 213 * Consumer index. 214 * 215 * @return 216 * The CQE status. 217 */ 218 static __rte_always_inline enum mlx5_cqe_status 219 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, 220 const uint16_t ci) 221 { 222 const uint16_t idx = ci & cqes_n; 223 const uint8_t op_own = cqe->op_own; 224 const uint8_t op_owner = MLX5_CQE_OWNER(op_own); 225 const uint8_t op_code = MLX5_CQE_OPCODE(op_own); 226 227 if (unlikely((op_owner != (!!(idx))) || 228 (op_code == MLX5_CQE_INVALID))) 229 return MLX5_CQE_STATUS_HW_OWN; 230 return check_cqe_error(op_code); 231 } 232 233 /** 234 * Check whether CQE is valid using validity iteration count. 235 * 236 * @param cqe 237 * Pointer to CQE. 238 * @param cqes_n 239 * Log 2 of completion queue size. 240 * @param ci 241 * Consumer index. 242 * 243 * @return 244 * The CQE status. 245 */ 246 static __rte_always_inline enum mlx5_cqe_status 247 check_cqe_iteration(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, 248 const uint32_t ci) 249 { 250 const uint8_t op_own = cqe->op_own; 251 const uint8_t op_code = MLX5_CQE_OPCODE(op_own); 252 const uint8_t vic = ci >> cqes_n; 253 254 if (unlikely((cqe->validity_iteration_count != vic) || 255 (op_code == MLX5_CQE_INVALID))) 256 return MLX5_CQE_STATUS_HW_OWN; 257 return check_cqe_error(op_code); 258 } 259 260 /* 261 * Get PCI address <DBDF> string from EAL device. 262 * 263 * @param[out] addr 264 * The output address buffer string 265 * @param[in] size 266 * The output buffer size 267 * @return 268 * - 0 on success. 269 * - Negative value and rte_errno is set otherwise. 270 */ 271 __rte_internal 272 int mlx5_dev_to_pci_str(const struct rte_device *dev, char *addr, size_t size); 273 274 /* 275 * Get PCI address from sysfs of a PCI-related device. 276 * 277 * @param[in] dev_path 278 * The sysfs path should not point to the direct plain PCI device. 279 * Instead, the node "/device/" is used to access the real device. 280 * @param[out] pci_addr 281 * Parsed PCI address. 282 * 283 * @return 284 * - 0 on success. 285 * - Negative value and rte_errno is set otherwise. 286 */ 287 __rte_internal 288 int mlx5_get_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr); 289 290 /* 291 * Get kernel network interface name from sysfs IB device path. 292 * 293 * @param[in] ibdev_path 294 * The sysfs path to IB device. 295 * @param[out] ifname 296 * Interface name output of size IF_NAMESIZE. 297 * 298 * @return 299 * - 0 on success. 300 * - Negative value and rte_errno is set otherwise. 301 */ 302 __rte_internal 303 int mlx5_get_ifname_sysfs(const char *ibdev_path, char *ifname); 304 305 __rte_internal 306 int mlx5_auxiliary_get_child_name(const char *dev, const char *node, 307 char *child, size_t size); 308 309 enum mlx5_class { 310 MLX5_CLASS_INVALID, 311 MLX5_CLASS_ETH = RTE_BIT64(0), 312 MLX5_CLASS_VDPA = RTE_BIT64(1), 313 MLX5_CLASS_REGEX = RTE_BIT64(2), 314 MLX5_CLASS_COMPRESS = RTE_BIT64(3), 315 MLX5_CLASS_CRYPTO = RTE_BIT64(4), 316 }; 317 318 #define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE 319 320 /* devX creation object */ 321 struct mlx5_devx_obj { 322 void *obj; /* The DV object. */ 323 int id; /* The object ID. */ 324 }; 325 326 /* UMR memory buffer used to define 1 entry in indirect mkey. */ 327 struct mlx5_klm { 328 uint32_t byte_count; 329 uint32_t mkey; 330 uint64_t address; 331 }; 332 333 /** Control for key/values list. */ 334 struct mlx5_kvargs_ctrl { 335 struct rte_kvargs *kvlist; /* Structure containing list of key/values.*/ 336 bool is_used[RTE_KVARGS_MAX]; /* Indicator which devargs were used. */ 337 }; 338 339 /** 340 * Call a handler function for each key/value in the list of keys. 341 * 342 * For each key/value association that matches the given key, calls the 343 * handler function with the for a given arg_name passing the value on the 344 * dictionary for that key and a given extra argument. 345 * 346 * @param mkvlist 347 * The mlx5_kvargs structure. 348 * @param keys 349 * A list of keys to process (table of const char *, the last must be NULL). 350 * @param handler 351 * The function to call for each matching key. 352 * @param opaque_arg 353 * A pointer passed unchanged to the handler. 354 * 355 * @return 356 * - 0 on success 357 * - Negative on error 358 */ 359 __rte_internal 360 int 361 mlx5_kvargs_process(struct mlx5_kvargs_ctrl *mkvlist, const char *const keys[], 362 arg_handler_t handler, void *opaque_arg); 363 364 /* All UAR arguments using doorbell register in datapath. */ 365 struct mlx5_uar_data { 366 uint64_t *db; 367 /* The doorbell's virtual address mapped to the relevant HW UAR space.*/ 368 #ifndef RTE_ARCH_64 369 rte_spinlock_t *sl_p; 370 /* Pointer to UAR access lock required for 32bit implementations. */ 371 #endif /* RTE_ARCH_64 */ 372 }; 373 374 /* DevX UAR control structure. */ 375 struct mlx5_uar { 376 struct mlx5_uar_data bf_db; /* UAR data for Blueflame register. */ 377 struct mlx5_uar_data cq_db; /* UAR data for CQ arm db register. */ 378 void *obj; /* DevX UAR object. */ 379 bool dbnc; /* Doorbell mapped to non-cached region. */ 380 #ifndef RTE_ARCH_64 381 rte_spinlock_t bf_sl; 382 rte_spinlock_t cq_sl; 383 /* UAR access locks required for 32bit implementations. */ 384 #endif /* RTE_ARCH_64 */ 385 }; 386 387 /** 388 * Ring a doorbell and flush the update if requested. 389 * 390 * @param uar 391 * Pointer to UAR data structure. 392 * @param val 393 * value to write in big endian format. 394 * @param index 395 * Index of doorbell record. 396 * @param db_rec 397 * Address of doorbell record. 398 * @param flash 399 * Decide whether to flush the DB writing using a memory barrier. 400 */ 401 static __rte_always_inline void 402 mlx5_doorbell_ring(struct mlx5_uar_data *uar, uint64_t val, uint32_t index, 403 volatile uint32_t *db_rec, bool flash) 404 { 405 rte_io_wmb(); 406 *db_rec = rte_cpu_to_be_32(index); 407 /* Ensure ordering between DB record actual update and UAR access. */ 408 rte_wmb(); 409 #ifdef RTE_ARCH_64 410 *uar->db = val; 411 #else /* !RTE_ARCH_64 */ 412 rte_spinlock_lock(uar->sl_p); 413 *(volatile uint32_t *)uar->db = val; 414 rte_io_wmb(); 415 *((volatile uint32_t *)uar->db + 1) = val >> 32; 416 rte_spinlock_unlock(uar->sl_p); 417 #endif 418 if (flash) 419 rte_wmb(); 420 } 421 422 /** 423 * Get the doorbell register mapping type. 424 * 425 * @param uar_mmap_offset 426 * Mmap offset of Verbs/DevX UAR. 427 * @param page_size 428 * System page size 429 * 430 * @return 431 * 1 for non-cached, 0 otherwise. 432 */ 433 static inline uint16_t 434 mlx5_db_map_type_get(off_t uar_mmap_offset, size_t page_size) 435 { 436 off_t cmd = uar_mmap_offset / page_size; 437 438 cmd >>= MLX5_UAR_MMAP_CMD_SHIFT; 439 cmd &= MLX5_UAR_MMAP_CMD_MASK; 440 if (cmd == MLX5_MMAP_GET_NC_PAGES_CMD) 441 return 1; 442 return 0; 443 } 444 445 __rte_internal 446 void mlx5_translate_port_name(const char *port_name_in, 447 struct mlx5_switch_info *port_info_out); 448 void mlx5_glue_constructor(void); 449 extern uint8_t haswell_broadwell_cpu; 450 451 __rte_internal 452 void mlx5_common_init(void); 453 454 /* 455 * Common Driver Interface 456 * 457 * ConnectX common driver supports multiple classes: net, vDPA, regex, crypto 458 * and compress devices. This layer enables creating such multiple classes 459 * on a single device by allowing to bind multiple class-specific device 460 * drivers to attach to the common driver. 461 * 462 * ------------ ------------- -------------- ----------------- ------------ 463 * | mlx5 net | | mlx5 vdpa | | mlx5 regex | | mlx5 compress | | mlx5 ... | 464 * | driver | | driver | | driver | | driver | | drivers | 465 * ------------ ------------- -------------- ----------------- ------------ 466 * || 467 * ----------------- 468 * | mlx5 | 469 * | common driver | 470 * ----------------- 471 * | | 472 * ----------- ----------------- 473 * | mlx5 | | mlx5 | 474 * | pci dev | | auxiliary dev | 475 * ----------- ----------------- 476 * 477 * - mlx5 PCI bus driver binds to mlx5 PCI devices defined by PCI ID table 478 * of all related devices. 479 * - mlx5 class driver such as net, vDPA, regex defines its specific 480 * PCI ID table and mlx5 bus driver probes matching class drivers. 481 * - mlx5 common driver is central place that validates supported 482 * class combinations. 483 * - mlx5 common driver hides bus difference by resolving device address 484 * from devargs, locating target RDMA device and probing with it. 485 */ 486 487 /* 488 * Device configuration structure. 489 * 490 * Merged configuration from: 491 * 492 * - Device capabilities, 493 * - User device parameters disabled features. 494 */ 495 struct mlx5_common_dev_config { 496 struct mlx5_hca_attr hca_attr; /* HCA attributes. */ 497 int dbnc; /* Skip doorbell register write barrier. */ 498 int device_fd; /* Device file descriptor for importation. */ 499 int pd_handle; /* Protection Domain handle for importation. */ 500 unsigned int devx:1; /* Whether devx interface is available or not. */ 501 unsigned int sys_mem_en:1; /* The default memory allocator. */ 502 unsigned int mr_mempool_reg_en:1; 503 /* Allow/prevent implicit mempool memory registration. */ 504 unsigned int mr_ext_memseg_en:1; 505 /* Whether memseg should be extended for MR creation. */ 506 }; 507 508 struct mlx5_common_device { 509 struct rte_device *dev; 510 TAILQ_ENTRY(mlx5_common_device) next; 511 uint32_t classes_loaded; 512 void *ctx; /* Verbs/DV/DevX context. */ 513 void *pd; /* Protection Domain. */ 514 uint32_t pdn; /* Protection Domain Number. */ 515 struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ 516 struct mlx5_common_dev_config config; /* Device configuration. */ 517 }; 518 519 /** 520 * Indicates whether PD and CTX are imported from another process, 521 * or created by this process. 522 * 523 * @param cdev 524 * Pointer to common device. 525 * 526 * @return 527 * True if PD and CTX are imported from another process, False otherwise. 528 */ 529 static inline bool 530 mlx5_imported_pd_and_ctx(struct mlx5_common_device *cdev) 531 { 532 return cdev->config.device_fd != MLX5_ARG_UNSET && 533 cdev->config.pd_handle != MLX5_ARG_UNSET; 534 } 535 536 /** 537 * Initialization function for the driver called during device probing. 538 */ 539 typedef int (mlx5_class_driver_probe_t)(struct mlx5_common_device *cdev, 540 struct mlx5_kvargs_ctrl *mkvlist); 541 542 /** 543 * Uninitialization function for the driver called during hot-unplugging. 544 */ 545 typedef int (mlx5_class_driver_remove_t)(struct mlx5_common_device *cdev); 546 547 /** Device already probed can be probed again to check for new ports. */ 548 #define MLX5_DRV_PROBE_AGAIN 0x0004 549 550 /** 551 * A structure describing a mlx5 common class driver. 552 */ 553 struct mlx5_class_driver { 554 TAILQ_ENTRY(mlx5_class_driver) next; 555 enum mlx5_class drv_class; /**< Class of this driver. */ 556 const char *name; /**< Driver name. */ 557 mlx5_class_driver_probe_t *probe; /**< Device probe function. */ 558 mlx5_class_driver_remove_t *remove; /**< Device remove function. */ 559 const struct rte_pci_id *id_table; /**< ID table, NULL terminated. */ 560 uint32_t probe_again:1; 561 /**< Device already probed can be probed again to check new device. */ 562 uint32_t intr_lsc:1; /**< Supports link state interrupt. */ 563 uint32_t intr_rmv:1; /**< Supports device remove interrupt. */ 564 }; 565 566 /** 567 * Register a mlx5 device driver. 568 * 569 * @param driver 570 * A pointer to a mlx5_driver structure describing the driver 571 * to be registered. 572 */ 573 __rte_internal 574 void 575 mlx5_class_driver_register(struct mlx5_class_driver *driver); 576 577 /** 578 * Test device is a PCI bus device. 579 * 580 * @param dev 581 * Pointer to device. 582 * 583 * @return 584 * - True on device devargs is a PCI bus device. 585 * - False otherwise. 586 */ 587 __rte_internal 588 bool 589 mlx5_dev_is_pci(const struct rte_device *dev); 590 591 /** 592 * Test PCI device is a VF device. 593 * 594 * @param pci_dev 595 * Pointer to PCI device. 596 * 597 * @return 598 * - True on PCI device is a VF device. 599 * - False otherwise. 600 */ 601 __rte_internal 602 bool 603 mlx5_dev_is_vf_pci(struct rte_pci_device *pci_dev); 604 605 __rte_internal 606 int 607 mlx5_dev_mempool_subscribe(struct mlx5_common_device *cdev); 608 609 __rte_internal 610 void 611 mlx5_dev_mempool_unregister(struct mlx5_common_device *cdev, 612 struct rte_mempool *mp); 613 614 __rte_internal 615 int 616 mlx5_devx_uar_prepare(struct mlx5_common_device *cdev, struct mlx5_uar *uar); 617 618 __rte_internal 619 void 620 mlx5_devx_uar_release(struct mlx5_uar *uar); 621 622 /* mlx5_common_os.c */ 623 624 int mlx5_os_open_device(struct mlx5_common_device *cdev, uint32_t classes); 625 int mlx5_os_pd_prepare(struct mlx5_common_device *cdev); 626 int mlx5_os_pd_release(struct mlx5_common_device *cdev); 627 int mlx5_os_remote_pd_and_ctx_validate(struct mlx5_common_dev_config *config); 628 629 /* mlx5 PMD wrapped MR struct. */ 630 struct mlx5_pmd_wrapped_mr { 631 uint32_t lkey; 632 void *addr; 633 size_t len; 634 void *obj; /* verbs mr object or devx umem object. */ 635 void *imkey; /* DevX indirect mkey object. */ 636 }; 637 638 __rte_internal 639 int 640 mlx5_os_wrapped_mkey_create(void *ctx, void *pd, uint32_t pdn, void *addr, 641 size_t length, struct mlx5_pmd_wrapped_mr *pmd_mr); 642 643 __rte_internal 644 void 645 mlx5_os_wrapped_mkey_destroy(struct mlx5_pmd_wrapped_mr *pmd_mr); 646 647 #endif /* RTE_PMD_MLX5_COMMON_H_ */ 648