1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_COMMON_H_ 6 #define RTE_PMD_MLX5_COMMON_H_ 7 8 #include <stdio.h> 9 10 #include <rte_pci.h> 11 #include <rte_atomic.h> 12 #include <rte_log.h> 13 #include <rte_kvargs.h> 14 #include <rte_devargs.h> 15 16 #include "mlx5_prm.h" 17 18 19 /* 20 * Compilation workaround for PPC64 when AltiVec is fully enabled, e.g. std=c11. 21 * Otherwise there would be a type conflict between stdbool and altivec. 22 */ 23 #if defined(__PPC64__) && !defined(__APPLE_ALTIVEC__) 24 #undef bool 25 /* redefine as in stdbool.h */ 26 #define bool _Bool 27 #endif 28 29 /* Bit-field manipulation. */ 30 #define BITFIELD_DECLARE(bf, type, size) \ 31 type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \ 32 !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))] 33 #define BITFIELD_DEFINE(bf, type, size) \ 34 BITFIELD_DECLARE((bf), type, (size)) = { 0 } 35 #define BITFIELD_SET(bf, b) \ 36 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \ 37 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 38 #define BITFIELD_RESET(bf, b) \ 39 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \ 40 ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 41 #define BITFIELD_ISSET(bf, b) \ 42 !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \ 43 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))) 44 45 /* 46 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant 47 * manner. 48 */ 49 #define PMD_DRV_LOG_STRIP(a, b) a 50 #define PMD_DRV_LOG_OPAREN ( 51 #define PMD_DRV_LOG_CPAREN ) 52 #define PMD_DRV_LOG_COMMA , 53 54 /* Return the file name part of a path. */ 55 static inline const char * 56 pmd_drv_log_basename(const char *s) 57 { 58 const char *n = s; 59 60 while (*n) 61 if (*(n++) == '/') 62 s = n; 63 return s; 64 } 65 66 #define PMD_DRV_LOG___(level, type, name, ...) \ 67 rte_log(RTE_LOG_ ## level, \ 68 type, \ 69 RTE_FMT(name ": " \ 70 RTE_FMT_HEAD(__VA_ARGS__,), \ 71 RTE_FMT_TAIL(__VA_ARGS__,))) 72 73 /* 74 * When debugging is enabled (MLX5_DEBUG not defined), file, line and function 75 * information replace the driver name (MLX5_DRIVER_NAME) in log messages. 76 */ 77 #ifdef RTE_LIBRTE_MLX5_DEBUG 78 79 #define PMD_DRV_LOG__(level, type, name, ...) \ 80 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__) 81 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 82 PMD_DRV_LOG__(level, type, name,\ 83 s "\n" PMD_DRV_LOG_COMMA \ 84 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \ 85 __LINE__ PMD_DRV_LOG_COMMA \ 86 __func__, \ 87 __VA_ARGS__) 88 89 #else /* RTE_LIBRTE_MLX5_DEBUG */ 90 #define PMD_DRV_LOG__(level, type, name, ...) \ 91 PMD_DRV_LOG___(level, type, name, __VA_ARGS__) 92 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 93 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__) 94 95 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 96 97 /* claim_zero() does not perform any check when debugging is disabled. */ 98 #ifdef RTE_LIBRTE_MLX5_DEBUG 99 100 #define DEBUG(...) DRV_LOG(DEBUG, __VA_ARGS__) 101 #define MLX5_ASSERT(exp) RTE_VERIFY(exp) 102 #define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0) 103 #define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0) 104 105 #else /* RTE_LIBRTE_MLX5_DEBUG */ 106 107 #define DEBUG(...) (void)0 108 #define MLX5_ASSERT(exp) RTE_ASSERT(exp) 109 #define claim_zero(...) (__VA_ARGS__) 110 #define claim_nonzero(...) (__VA_ARGS__) 111 112 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 113 114 /* Allocate a buffer on the stack and fill it with a printf format string. */ 115 #define MKSTR(name, ...) \ 116 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \ 117 char name[mkstr_size_##name + 1]; \ 118 \ 119 snprintf(name, sizeof(name), "" __VA_ARGS__) 120 121 enum { 122 PCI_VENDOR_ID_MELLANOX = 0x15b3, 123 }; 124 125 enum { 126 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, 127 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, 128 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, 129 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, 130 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, 131 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, 132 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, 133 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, 134 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2, 135 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3, 136 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b, 137 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c, 138 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d, 139 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e, 140 }; 141 142 /* Maximum number of simultaneous unicast MAC addresses. */ 143 #define MLX5_MAX_UC_MAC_ADDRESSES 128 144 /* Maximum number of simultaneous Multicast MAC addresses. */ 145 #define MLX5_MAX_MC_MAC_ADDRESSES 128 146 /* Maximum number of simultaneous MAC addresses. */ 147 #define MLX5_MAX_MAC_ADDRESSES \ 148 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES) 149 150 /* Recognized Infiniband device physical port name types. */ 151 enum mlx5_nl_phys_port_name_type { 152 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */ 153 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */ 154 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */ 155 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */ 156 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */ 157 }; 158 159 /** Switch information returned by mlx5_nl_switch_info(). */ 160 struct mlx5_switch_info { 161 uint32_t master:1; /**< Master device. */ 162 uint32_t representor:1; /**< Representor device. */ 163 enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */ 164 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */ 165 int32_t port_name; /**< Representor port name. */ 166 uint64_t switch_id; /**< Switch identifier. */ 167 }; 168 169 /* CQE status. */ 170 enum mlx5_cqe_status { 171 MLX5_CQE_STATUS_SW_OWN = -1, 172 MLX5_CQE_STATUS_HW_OWN = -2, 173 MLX5_CQE_STATUS_ERR = -3, 174 }; 175 176 /** 177 * Check whether CQE is valid. 178 * 179 * @param cqe 180 * Pointer to CQE. 181 * @param cqes_n 182 * Size of completion queue. 183 * @param ci 184 * Consumer index. 185 * 186 * @return 187 * The CQE status. 188 */ 189 static __rte_always_inline enum mlx5_cqe_status 190 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, 191 const uint16_t ci) 192 { 193 const uint16_t idx = ci & cqes_n; 194 const uint8_t op_own = cqe->op_own; 195 const uint8_t op_owner = MLX5_CQE_OWNER(op_own); 196 const uint8_t op_code = MLX5_CQE_OPCODE(op_own); 197 198 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID))) 199 return MLX5_CQE_STATUS_HW_OWN; 200 rte_cio_rmb(); 201 if (unlikely(op_code == MLX5_CQE_RESP_ERR || 202 op_code == MLX5_CQE_REQ_ERR)) 203 return MLX5_CQE_STATUS_ERR; 204 return MLX5_CQE_STATUS_SW_OWN; 205 } 206 207 int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr); 208 209 #define MLX5_CLASS_ARG_NAME "class" 210 211 enum mlx5_class { 212 MLX5_CLASS_NET, 213 MLX5_CLASS_VDPA, 214 MLX5_CLASS_INVALID, 215 }; 216 217 enum mlx5_class mlx5_class_get(struct rte_devargs *devargs); 218 void mlx5_translate_port_name(const char *port_name_in, 219 struct mlx5_switch_info *port_info_out); 220 221 #endif /* RTE_PMD_MLX5_COMMON_H_ */ 222