1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_COMMON_H_ 6 #define RTE_PMD_MLX5_COMMON_H_ 7 8 #include <stdio.h> 9 10 #include <rte_compat.h> 11 #include <rte_pci.h> 12 #include <bus_pci_driver.h> 13 #include <rte_debug.h> 14 #include <rte_atomic.h> 15 #include <rte_rwlock.h> 16 #include <rte_log.h> 17 #include <rte_kvargs.h> 18 #include <rte_devargs.h> 19 #include <rte_bitops.h> 20 #include <rte_lcore.h> 21 #include <rte_spinlock.h> 22 #include <rte_os_shim.h> 23 24 #include "mlx5_prm.h" 25 #include "mlx5_devx_cmds.h" 26 #include "mlx5_common_os.h" 27 #include "mlx5_common_mr.h" 28 29 /* Reported driver name. */ 30 #define MLX5_PCI_DRIVER_NAME "mlx5_pci" 31 #define MLX5_AUXILIARY_DRIVER_NAME "mlx5_auxiliary" 32 33 /* Bit-field manipulation. */ 34 #define BITFIELD_DECLARE(bf, type, size) \ 35 type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \ 36 !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))] 37 #define BITFIELD_DEFINE(bf, type, size) \ 38 BITFIELD_DECLARE((bf), type, (size)) = { 0 } 39 #define BITFIELD_SET(bf, b) \ 40 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \ 41 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 42 #define BITFIELD_RESET(bf, b) \ 43 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \ 44 ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 45 #define BITFIELD_ISSET(bf, b) \ 46 !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \ 47 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))) 48 49 /* 50 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant 51 * manner. 52 */ 53 #define PMD_DRV_LOG_STRIP(a, b) a 54 #define PMD_DRV_LOG_OPAREN ( 55 #define PMD_DRV_LOG_CPAREN ) 56 #define PMD_DRV_LOG_COMMA , 57 58 /* Return the file name part of a path. */ 59 static inline const char * 60 pmd_drv_log_basename(const char *s) 61 { 62 const char *n = s; 63 64 while (*n) 65 if (*(n++) == '/') 66 s = n; 67 return s; 68 } 69 70 #define PMD_DRV_LOG___(level, type, name, ...) \ 71 rte_log(RTE_LOG_ ## level, \ 72 type, \ 73 RTE_FMT(name ": " \ 74 RTE_FMT_HEAD(__VA_ARGS__,), \ 75 RTE_FMT_TAIL(__VA_ARGS__,))) 76 77 #ifdef RTE_LIBRTE_MLX5_DEBUG 78 79 #define PMD_DRV_LOG__(level, type, name, ...) \ 80 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__) 81 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 82 PMD_DRV_LOG__(level, type, name,\ 83 s "\n" PMD_DRV_LOG_COMMA \ 84 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \ 85 __LINE__ PMD_DRV_LOG_COMMA \ 86 __func__, \ 87 __VA_ARGS__) 88 89 #else /* RTE_LIBRTE_MLX5_DEBUG */ 90 #define PMD_DRV_LOG__(level, type, name, ...) \ 91 PMD_DRV_LOG___(level, type, name, __VA_ARGS__) 92 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 93 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__) 94 95 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 96 97 /* claim_zero() does not perform any check when debugging is disabled. */ 98 #ifdef RTE_LIBRTE_MLX5_DEBUG 99 100 #define MLX5_ASSERT(exp) RTE_VERIFY(exp) 101 #define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0) 102 #define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0) 103 104 #else /* RTE_LIBRTE_MLX5_DEBUG */ 105 106 #define MLX5_ASSERT(exp) RTE_ASSERT(exp) 107 #define claim_zero(...) (__VA_ARGS__) 108 #define claim_nonzero(...) (__VA_ARGS__) 109 110 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 111 112 /* Allocate a buffer on the stack and fill it with a printf format string. */ 113 #define MKSTR(name, ...) \ 114 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \ 115 char name[mkstr_size_##name + 1]; \ 116 \ 117 memset(name, 0, mkstr_size_##name + 1); \ 118 snprintf(name, sizeof(name), "" __VA_ARGS__) 119 120 enum { 121 PCI_VENDOR_ID_MELLANOX = 0x15b3, 122 }; 123 124 enum { 125 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, 126 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, 127 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, 128 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, 129 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, 130 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, 131 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, 132 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, 133 PCI_DEVICE_ID_MELLANOX_BLUEFIELD = 0xa2d2, 134 PCI_DEVICE_ID_MELLANOX_BLUEFIELDVF = 0xa2d3, 135 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b, 136 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c, 137 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d, 138 PCI_DEVICE_ID_MELLANOX_CONNECTXVF = 0x101e, 139 PCI_DEVICE_ID_MELLANOX_BLUEFIELD2 = 0xa2d6, 140 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX = 0x101f, 141 PCI_DEVICE_ID_MELLANOX_CONNECTX7 = 0x1021, 142 PCI_DEVICE_ID_MELLANOX_BLUEFIELD3 = 0Xa2dc, 143 }; 144 145 /* Maximum number of simultaneous unicast MAC addresses. */ 146 #define MLX5_MAX_UC_MAC_ADDRESSES 128 147 /* Maximum number of simultaneous Multicast MAC addresses. */ 148 #define MLX5_MAX_MC_MAC_ADDRESSES 128 149 /* Maximum number of simultaneous MAC addresses. */ 150 #define MLX5_MAX_MAC_ADDRESSES \ 151 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES) 152 153 /* Recognized Infiniband device physical port name types. */ 154 enum mlx5_nl_phys_port_name_type { 155 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */ 156 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */ 157 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */ 158 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */ 159 MLX5_PHYS_PORT_NAME_TYPE_PFHPF, /* pf0, kernel ver >= 5.7, HPF rep */ 160 MLX5_PHYS_PORT_NAME_TYPE_PFSF, /* pf0sf0, kernel ver >= 5.0 */ 161 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */ 162 }; 163 164 /** Switch information returned by mlx5_nl_switch_info(). */ 165 struct mlx5_switch_info { 166 uint32_t master:1; /**< Master device. */ 167 uint32_t representor:1; /**< Representor device. */ 168 enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */ 169 int32_t ctrl_num; /**< Controller number (valid for c#pf#vf# format). */ 170 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */ 171 int32_t port_name; /**< Representor port name. */ 172 uint64_t switch_id; /**< Switch identifier. */ 173 }; 174 175 /* CQE status. */ 176 enum mlx5_cqe_status { 177 MLX5_CQE_STATUS_SW_OWN = -1, 178 MLX5_CQE_STATUS_HW_OWN = -2, 179 MLX5_CQE_STATUS_ERR = -3, 180 }; 181 182 /** 183 * Check whether CQE is valid. 184 * 185 * @param cqe 186 * Pointer to CQE. 187 * @param cqes_n 188 * Size of completion queue. 189 * @param ci 190 * Consumer index. 191 * 192 * @return 193 * The CQE status. 194 */ 195 static __rte_always_inline enum mlx5_cqe_status 196 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, 197 const uint16_t ci) 198 { 199 const uint16_t idx = ci & cqes_n; 200 const uint8_t op_own = cqe->op_own; 201 const uint8_t op_owner = MLX5_CQE_OWNER(op_own); 202 const uint8_t op_code = MLX5_CQE_OPCODE(op_own); 203 204 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID))) 205 return MLX5_CQE_STATUS_HW_OWN; 206 rte_io_rmb(); 207 if (unlikely(op_code == MLX5_CQE_RESP_ERR || 208 op_code == MLX5_CQE_REQ_ERR)) 209 return MLX5_CQE_STATUS_ERR; 210 return MLX5_CQE_STATUS_SW_OWN; 211 } 212 213 /* 214 * Get PCI address <DBDF> string from EAL device. 215 * 216 * @param[out] addr 217 * The output address buffer string 218 * @param[in] size 219 * The output buffer size 220 * @return 221 * - 0 on success. 222 * - Negative value and rte_errno is set otherwise. 223 */ 224 __rte_internal 225 int mlx5_dev_to_pci_str(const struct rte_device *dev, char *addr, size_t size); 226 227 /* 228 * Get PCI address from sysfs of a PCI-related device. 229 * 230 * @param[in] dev_path 231 * The sysfs path should not point to the direct plain PCI device. 232 * Instead, the node "/device/" is used to access the real device. 233 * @param[out] pci_addr 234 * Parsed PCI address. 235 * 236 * @return 237 * - 0 on success. 238 * - Negative value and rte_errno is set otherwise. 239 */ 240 __rte_internal 241 int mlx5_get_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr); 242 243 /* 244 * Get kernel network interface name from sysfs IB device path. 245 * 246 * @param[in] ibdev_path 247 * The sysfs path to IB device. 248 * @param[out] ifname 249 * Interface name output of size IF_NAMESIZE. 250 * 251 * @return 252 * - 0 on success. 253 * - Negative value and rte_errno is set otherwise. 254 */ 255 __rte_internal 256 int mlx5_get_ifname_sysfs(const char *ibdev_path, char *ifname); 257 258 __rte_internal 259 int mlx5_auxiliary_get_child_name(const char *dev, const char *node, 260 char *child, size_t size); 261 262 enum mlx5_class { 263 MLX5_CLASS_INVALID, 264 MLX5_CLASS_ETH = RTE_BIT64(0), 265 MLX5_CLASS_VDPA = RTE_BIT64(1), 266 MLX5_CLASS_REGEX = RTE_BIT64(2), 267 MLX5_CLASS_COMPRESS = RTE_BIT64(3), 268 MLX5_CLASS_CRYPTO = RTE_BIT64(4), 269 }; 270 271 #define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE 272 273 /* devX creation object */ 274 struct mlx5_devx_obj { 275 void *obj; /* The DV object. */ 276 int id; /* The object ID. */ 277 }; 278 279 /* UMR memory buffer used to define 1 entry in indirect mkey. */ 280 struct mlx5_klm { 281 uint32_t byte_count; 282 uint32_t mkey; 283 uint64_t address; 284 }; 285 286 /** Control for key/values list. */ 287 struct mlx5_kvargs_ctrl { 288 struct rte_kvargs *kvlist; /* Structure containing list of key/values.*/ 289 bool is_used[RTE_KVARGS_MAX]; /* Indicator which devargs were used. */ 290 }; 291 292 /** 293 * Call a handler function for each key/value in the list of keys. 294 * 295 * For each key/value association that matches the given key, calls the 296 * handler function with the for a given arg_name passing the value on the 297 * dictionary for that key and a given extra argument. 298 * 299 * @param mkvlist 300 * The mlx5_kvargs structure. 301 * @param keys 302 * A list of keys to process (table of const char *, the last must be NULL). 303 * @param handler 304 * The function to call for each matching key. 305 * @param opaque_arg 306 * A pointer passed unchanged to the handler. 307 * 308 * @return 309 * - 0 on success 310 * - Negative on error 311 */ 312 __rte_internal 313 int 314 mlx5_kvargs_process(struct mlx5_kvargs_ctrl *mkvlist, const char *const keys[], 315 arg_handler_t handler, void *opaque_arg); 316 317 /* All UAR arguments using doorbell register in datapath. */ 318 struct mlx5_uar_data { 319 uint64_t *db; 320 /* The doorbell's virtual address mapped to the relevant HW UAR space.*/ 321 #ifndef RTE_ARCH_64 322 rte_spinlock_t *sl_p; 323 /* Pointer to UAR access lock required for 32bit implementations. */ 324 #endif /* RTE_ARCH_64 */ 325 }; 326 327 /* DevX UAR control structure. */ 328 struct mlx5_uar { 329 struct mlx5_uar_data bf_db; /* UAR data for Blueflame register. */ 330 struct mlx5_uar_data cq_db; /* UAR data for CQ arm db register. */ 331 void *obj; /* DevX UAR object. */ 332 bool dbnc; /* Doorbell mapped to non-cached region. */ 333 #ifndef RTE_ARCH_64 334 rte_spinlock_t bf_sl; 335 rte_spinlock_t cq_sl; 336 /* UAR access locks required for 32bit implementations. */ 337 #endif /* RTE_ARCH_64 */ 338 }; 339 340 /** 341 * Ring a doorbell and flush the update if requested. 342 * 343 * @param uar 344 * Pointer to UAR data structure. 345 * @param val 346 * value to write in big endian format. 347 * @param index 348 * Index of doorbell record. 349 * @param db_rec 350 * Address of doorbell record. 351 * @param flash 352 * Decide whether to flush the DB writing using a memory barrier. 353 */ 354 static __rte_always_inline void 355 mlx5_doorbell_ring(struct mlx5_uar_data *uar, uint64_t val, uint32_t index, 356 volatile uint32_t *db_rec, bool flash) 357 { 358 rte_io_wmb(); 359 *db_rec = rte_cpu_to_be_32(index); 360 /* Ensure ordering between DB record actual update and UAR access. */ 361 rte_wmb(); 362 #ifdef RTE_ARCH_64 363 *uar->db = val; 364 #else /* !RTE_ARCH_64 */ 365 rte_spinlock_lock(uar->sl_p); 366 *(volatile uint32_t *)uar->db = val; 367 rte_io_wmb(); 368 *((volatile uint32_t *)uar->db + 1) = val >> 32; 369 rte_spinlock_unlock(uar->sl_p); 370 #endif 371 if (flash) 372 rte_wmb(); 373 } 374 375 /** 376 * Get the doorbell register mapping type. 377 * 378 * @param uar_mmap_offset 379 * Mmap offset of Verbs/DevX UAR. 380 * @param page_size 381 * System page size 382 * 383 * @return 384 * 1 for non-cached, 0 otherwise. 385 */ 386 static inline uint16_t 387 mlx5_db_map_type_get(off_t uar_mmap_offset, size_t page_size) 388 { 389 off_t cmd = uar_mmap_offset / page_size; 390 391 cmd >>= MLX5_UAR_MMAP_CMD_SHIFT; 392 cmd &= MLX5_UAR_MMAP_CMD_MASK; 393 if (cmd == MLX5_MMAP_GET_NC_PAGES_CMD) 394 return 1; 395 return 0; 396 } 397 398 __rte_internal 399 void mlx5_translate_port_name(const char *port_name_in, 400 struct mlx5_switch_info *port_info_out); 401 void mlx5_glue_constructor(void); 402 extern uint8_t haswell_broadwell_cpu; 403 404 __rte_internal 405 void mlx5_common_init(void); 406 407 /* 408 * Common Driver Interface 409 * 410 * ConnectX common driver supports multiple classes: net, vDPA, regex, crypto 411 * and compress devices. This layer enables creating such multiple classes 412 * on a single device by allowing to bind multiple class-specific device 413 * drivers to attach to the common driver. 414 * 415 * ------------ ------------- -------------- ----------------- ------------ 416 * | mlx5 net | | mlx5 vdpa | | mlx5 regex | | mlx5 compress | | mlx5 ... | 417 * | driver | | driver | | driver | | driver | | drivers | 418 * ------------ ------------- -------------- ----------------- ------------ 419 * || 420 * ----------------- 421 * | mlx5 | 422 * | common driver | 423 * ----------------- 424 * | | 425 * ----------- ----------------- 426 * | mlx5 | | mlx5 | 427 * | pci dev | | auxiliary dev | 428 * ----------- ----------------- 429 * 430 * - mlx5 PCI bus driver binds to mlx5 PCI devices defined by PCI ID table 431 * of all related devices. 432 * - mlx5 class driver such as net, vDPA, regex defines its specific 433 * PCI ID table and mlx5 bus driver probes matching class drivers. 434 * - mlx5 common driver is central place that validates supported 435 * class combinations. 436 * - mlx5 common driver hides bus difference by resolving device address 437 * from devargs, locating target RDMA device and probing with it. 438 */ 439 440 /* 441 * Device configuration structure. 442 * 443 * Merged configuration from: 444 * 445 * - Device capabilities, 446 * - User device parameters disabled features. 447 */ 448 struct mlx5_common_dev_config { 449 struct mlx5_hca_attr hca_attr; /* HCA attributes. */ 450 int dbnc; /* Skip doorbell register write barrier. */ 451 int device_fd; /* Device file descriptor for importation. */ 452 int pd_handle; /* Protection Domain handle for importation. */ 453 unsigned int devx:1; /* Whether devx interface is available or not. */ 454 unsigned int sys_mem_en:1; /* The default memory allocator. */ 455 unsigned int mr_mempool_reg_en:1; 456 /* Allow/prevent implicit mempool memory registration. */ 457 unsigned int mr_ext_memseg_en:1; 458 /* Whether memseg should be extended for MR creation. */ 459 }; 460 461 struct mlx5_common_device { 462 struct rte_device *dev; 463 TAILQ_ENTRY(mlx5_common_device) next; 464 uint32_t classes_loaded; 465 void *ctx; /* Verbs/DV/DevX context. */ 466 void *pd; /* Protection Domain. */ 467 uint32_t pdn; /* Protection Domain Number. */ 468 struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ 469 struct mlx5_common_dev_config config; /* Device configuration. */ 470 }; 471 472 /** 473 * Indicates whether PD and CTX are imported from another process, 474 * or created by this process. 475 * 476 * @param cdev 477 * Pointer to common device. 478 * 479 * @return 480 * True if PD and CTX are imported from another process, False otherwise. 481 */ 482 static inline bool 483 mlx5_imported_pd_and_ctx(struct mlx5_common_device *cdev) 484 { 485 return cdev->config.device_fd != MLX5_ARG_UNSET && 486 cdev->config.pd_handle != MLX5_ARG_UNSET; 487 } 488 489 /** 490 * Initialization function for the driver called during device probing. 491 */ 492 typedef int (mlx5_class_driver_probe_t)(struct mlx5_common_device *cdev, 493 struct mlx5_kvargs_ctrl *mkvlist); 494 495 /** 496 * Uninitialization function for the driver called during hot-unplugging. 497 */ 498 typedef int (mlx5_class_driver_remove_t)(struct mlx5_common_device *cdev); 499 500 /** Device already probed can be probed again to check for new ports. */ 501 #define MLX5_DRV_PROBE_AGAIN 0x0004 502 503 /** 504 * A structure describing a mlx5 common class driver. 505 */ 506 struct mlx5_class_driver { 507 TAILQ_ENTRY(mlx5_class_driver) next; 508 enum mlx5_class drv_class; /**< Class of this driver. */ 509 const char *name; /**< Driver name. */ 510 mlx5_class_driver_probe_t *probe; /**< Device probe function. */ 511 mlx5_class_driver_remove_t *remove; /**< Device remove function. */ 512 const struct rte_pci_id *id_table; /**< ID table, NULL terminated. */ 513 uint32_t probe_again:1; 514 /**< Device already probed can be probed again to check new device. */ 515 uint32_t intr_lsc:1; /**< Supports link state interrupt. */ 516 uint32_t intr_rmv:1; /**< Supports device remove interrupt. */ 517 }; 518 519 /** 520 * Register a mlx5 device driver. 521 * 522 * @param driver 523 * A pointer to a mlx5_driver structure describing the driver 524 * to be registered. 525 */ 526 __rte_internal 527 void 528 mlx5_class_driver_register(struct mlx5_class_driver *driver); 529 530 /** 531 * Test device is a PCI bus device. 532 * 533 * @param dev 534 * Pointer to device. 535 * 536 * @return 537 * - True on device devargs is a PCI bus device. 538 * - False otherwise. 539 */ 540 __rte_internal 541 bool 542 mlx5_dev_is_pci(const struct rte_device *dev); 543 544 /** 545 * Test PCI device is a VF device. 546 * 547 * @param pci_dev 548 * Pointer to PCI device. 549 * 550 * @return 551 * - True on PCI device is a VF device. 552 * - False otherwise. 553 */ 554 __rte_internal 555 bool 556 mlx5_dev_is_vf_pci(struct rte_pci_device *pci_dev); 557 558 __rte_internal 559 int 560 mlx5_dev_mempool_subscribe(struct mlx5_common_device *cdev); 561 562 __rte_internal 563 void 564 mlx5_dev_mempool_unregister(struct mlx5_common_device *cdev, 565 struct rte_mempool *mp); 566 567 __rte_internal 568 int 569 mlx5_devx_uar_prepare(struct mlx5_common_device *cdev, struct mlx5_uar *uar); 570 571 __rte_internal 572 void 573 mlx5_devx_uar_release(struct mlx5_uar *uar); 574 575 /* mlx5_common_os.c */ 576 577 int mlx5_os_open_device(struct mlx5_common_device *cdev, uint32_t classes); 578 int mlx5_os_pd_prepare(struct mlx5_common_device *cdev); 579 int mlx5_os_pd_release(struct mlx5_common_device *cdev); 580 int mlx5_os_remote_pd_and_ctx_validate(struct mlx5_common_dev_config *config); 581 582 /* mlx5 PMD wrapped MR struct. */ 583 struct mlx5_pmd_wrapped_mr { 584 uint32_t lkey; 585 void *addr; 586 size_t len; 587 void *obj; /* verbs mr object or devx umem object. */ 588 void *imkey; /* DevX indirect mkey object. */ 589 }; 590 591 __rte_internal 592 int 593 mlx5_os_wrapped_mkey_create(void *ctx, void *pd, uint32_t pdn, void *addr, 594 size_t length, struct mlx5_pmd_wrapped_mr *pmd_mr); 595 596 __rte_internal 597 void 598 mlx5_os_wrapped_mkey_destroy(struct mlx5_pmd_wrapped_mr *pmd_mr); 599 600 #endif /* RTE_PMD_MLX5_COMMON_H_ */ 601