1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_COMMON_H_ 6 #define RTE_PMD_MLX5_COMMON_H_ 7 8 #include <stdio.h> 9 10 #include <rte_pci.h> 11 #include <rte_debug.h> 12 #include <rte_atomic.h> 13 #include <rte_log.h> 14 #include <rte_kvargs.h> 15 #include <rte_devargs.h> 16 #include <rte_bitops.h> 17 #include <rte_os_shim.h> 18 19 #include "mlx5_prm.h" 20 #include "mlx5_devx_cmds.h" 21 22 /* Reported driver name. */ 23 #define MLX5_PCI_DRIVER_NAME "mlx5_pci" 24 25 /* Bit-field manipulation. */ 26 #define BITFIELD_DECLARE(bf, type, size) \ 27 type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \ 28 !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))] 29 #define BITFIELD_DEFINE(bf, type, size) \ 30 BITFIELD_DECLARE((bf), type, (size)) = { 0 } 31 #define BITFIELD_SET(bf, b) \ 32 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \ 33 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 34 #define BITFIELD_RESET(bf, b) \ 35 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \ 36 ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 37 #define BITFIELD_ISSET(bf, b) \ 38 !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \ 39 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))) 40 41 /* 42 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant 43 * manner. 44 */ 45 #define PMD_DRV_LOG_STRIP(a, b) a 46 #define PMD_DRV_LOG_OPAREN ( 47 #define PMD_DRV_LOG_CPAREN ) 48 #define PMD_DRV_LOG_COMMA , 49 50 /* Return the file name part of a path. */ 51 static inline const char * 52 pmd_drv_log_basename(const char *s) 53 { 54 const char *n = s; 55 56 while (*n) 57 if (*(n++) == '/') 58 s = n; 59 return s; 60 } 61 62 #define PMD_DRV_LOG___(level, type, name, ...) \ 63 rte_log(RTE_LOG_ ## level, \ 64 type, \ 65 RTE_FMT(name ": " \ 66 RTE_FMT_HEAD(__VA_ARGS__,), \ 67 RTE_FMT_TAIL(__VA_ARGS__,))) 68 69 #ifdef RTE_LIBRTE_MLX5_DEBUG 70 71 #define PMD_DRV_LOG__(level, type, name, ...) \ 72 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__) 73 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 74 PMD_DRV_LOG__(level, type, name,\ 75 s "\n" PMD_DRV_LOG_COMMA \ 76 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \ 77 __LINE__ PMD_DRV_LOG_COMMA \ 78 __func__, \ 79 __VA_ARGS__) 80 81 #else /* RTE_LIBRTE_MLX5_DEBUG */ 82 #define PMD_DRV_LOG__(level, type, name, ...) \ 83 PMD_DRV_LOG___(level, type, name, __VA_ARGS__) 84 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 85 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__) 86 87 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 88 89 /* claim_zero() does not perform any check when debugging is disabled. */ 90 #ifdef RTE_LIBRTE_MLX5_DEBUG 91 92 #define MLX5_ASSERT(exp) RTE_VERIFY(exp) 93 #define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0) 94 #define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0) 95 96 #else /* RTE_LIBRTE_MLX5_DEBUG */ 97 98 #define MLX5_ASSERT(exp) RTE_ASSERT(exp) 99 #define claim_zero(...) (__VA_ARGS__) 100 #define claim_nonzero(...) (__VA_ARGS__) 101 102 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 103 104 /* Allocate a buffer on the stack and fill it with a printf format string. */ 105 #define MKSTR(name, ...) \ 106 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \ 107 char name[mkstr_size_##name + 1]; \ 108 \ 109 snprintf(name, sizeof(name), "" __VA_ARGS__) 110 111 enum { 112 PCI_VENDOR_ID_MELLANOX = 0x15b3, 113 }; 114 115 enum { 116 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, 117 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, 118 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, 119 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, 120 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, 121 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, 122 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, 123 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, 124 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2, 125 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3, 126 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b, 127 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c, 128 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d, 129 PCI_DEVICE_ID_MELLANOX_CONNECTXVF = 0x101e, 130 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF = 0xa2d6, 131 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX = 0x101f, 132 PCI_DEVICE_ID_MELLANOX_CONNECTX7 = 0x1021, 133 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF = 0Xa2dc, 134 }; 135 136 /* Maximum number of simultaneous unicast MAC addresses. */ 137 #define MLX5_MAX_UC_MAC_ADDRESSES 128 138 /* Maximum number of simultaneous Multicast MAC addresses. */ 139 #define MLX5_MAX_MC_MAC_ADDRESSES 128 140 /* Maximum number of simultaneous MAC addresses. */ 141 #define MLX5_MAX_MAC_ADDRESSES \ 142 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES) 143 144 /* Recognized Infiniband device physical port name types. */ 145 enum mlx5_nl_phys_port_name_type { 146 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */ 147 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */ 148 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */ 149 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */ 150 MLX5_PHYS_PORT_NAME_TYPE_PFHPF, /* pf0, kernel ver >= 5.7, HPF rep */ 151 MLX5_PHYS_PORT_NAME_TYPE_PFSF, /* pf0sf0, kernel ver >= 5.0 */ 152 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */ 153 }; 154 155 /** Switch information returned by mlx5_nl_switch_info(). */ 156 struct mlx5_switch_info { 157 uint32_t master:1; /**< Master device. */ 158 uint32_t representor:1; /**< Representor device. */ 159 enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */ 160 int32_t ctrl_num; /**< Controller number (valid for c#pf#vf# format). */ 161 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */ 162 int32_t port_name; /**< Representor port name. */ 163 uint64_t switch_id; /**< Switch identifier. */ 164 }; 165 166 /* CQE status. */ 167 enum mlx5_cqe_status { 168 MLX5_CQE_STATUS_SW_OWN = -1, 169 MLX5_CQE_STATUS_HW_OWN = -2, 170 MLX5_CQE_STATUS_ERR = -3, 171 }; 172 173 /** 174 * Check whether CQE is valid. 175 * 176 * @param cqe 177 * Pointer to CQE. 178 * @param cqes_n 179 * Size of completion queue. 180 * @param ci 181 * Consumer index. 182 * 183 * @return 184 * The CQE status. 185 */ 186 static __rte_always_inline enum mlx5_cqe_status 187 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, 188 const uint16_t ci) 189 { 190 const uint16_t idx = ci & cqes_n; 191 const uint8_t op_own = cqe->op_own; 192 const uint8_t op_owner = MLX5_CQE_OWNER(op_own); 193 const uint8_t op_code = MLX5_CQE_OPCODE(op_own); 194 195 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID))) 196 return MLX5_CQE_STATUS_HW_OWN; 197 rte_io_rmb(); 198 if (unlikely(op_code == MLX5_CQE_RESP_ERR || 199 op_code == MLX5_CQE_REQ_ERR)) 200 return MLX5_CQE_STATUS_ERR; 201 return MLX5_CQE_STATUS_SW_OWN; 202 } 203 204 __rte_internal 205 int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr); 206 __rte_internal 207 int mlx5_get_ifname_sysfs(const char *ibdev_path, char *ifname); 208 209 210 #define MLX5_CLASS_ARG_NAME "class" 211 212 enum mlx5_class { 213 MLX5_CLASS_INVALID, 214 MLX5_CLASS_NET = RTE_BIT64(0), 215 MLX5_CLASS_VDPA = RTE_BIT64(1), 216 MLX5_CLASS_REGEX = RTE_BIT64(2), 217 MLX5_CLASS_COMPRESS = RTE_BIT64(3), 218 }; 219 220 #define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE 221 222 /* devX creation object */ 223 struct mlx5_devx_obj { 224 void *obj; /* The DV object. */ 225 int id; /* The object ID. */ 226 }; 227 228 /* UMR memory buffer used to define 1 entry in indirect mkey. */ 229 struct mlx5_klm { 230 uint32_t byte_count; 231 uint32_t mkey; 232 uint64_t address; 233 }; 234 235 __rte_internal 236 void mlx5_translate_port_name(const char *port_name_in, 237 struct mlx5_switch_info *port_info_out); 238 void mlx5_glue_constructor(void); 239 __rte_internal 240 void *mlx5_devx_alloc_uar(void *ctx, int mapping); 241 extern uint8_t haswell_broadwell_cpu; 242 243 __rte_internal 244 void mlx5_common_init(void); 245 246 #endif /* RTE_PMD_MLX5_COMMON_H_ */ 247