1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_COMMON_H_ 6 #define RTE_PMD_MLX5_COMMON_H_ 7 8 #include <stdio.h> 9 10 #include <rte_compat.h> 11 #include <rte_pci.h> 12 #include <bus_pci_driver.h> 13 #include <rte_debug.h> 14 #include <rte_atomic.h> 15 #include <rte_rwlock.h> 16 #include <rte_log.h> 17 #include <rte_kvargs.h> 18 #include <rte_devargs.h> 19 #include <rte_bitops.h> 20 #include <rte_lcore.h> 21 #include <rte_spinlock.h> 22 #include <rte_os_shim.h> 23 24 #include "mlx5_prm.h" 25 #include "mlx5_devx_cmds.h" 26 #include "mlx5_common_os.h" 27 #include "mlx5_common_mr.h" 28 29 /* Reported driver name. */ 30 #define MLX5_PCI_DRIVER_NAME "mlx5_pci" 31 #define MLX5_AUXILIARY_DRIVER_NAME "mlx5_auxiliary" 32 33 /* Bit-field manipulation. */ 34 #define BITFIELD_DECLARE(bf, type, size) \ 35 type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \ 36 !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))] 37 #define BITFIELD_DEFINE(bf, type, size) \ 38 BITFIELD_DECLARE((bf), type, (size)) = { 0 } 39 #define BITFIELD_SET(bf, b) \ 40 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \ 41 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 42 #define BITFIELD_RESET(bf, b) \ 43 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \ 44 ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))) 45 #define BITFIELD_ISSET(bf, b) \ 46 !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \ 47 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))) 48 49 /* 50 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant 51 * manner. 52 */ 53 #define PMD_DRV_LOG_STRIP(a, b) a 54 #define PMD_DRV_LOG_OPAREN ( 55 #define PMD_DRV_LOG_CPAREN ) 56 #define PMD_DRV_LOG_COMMA , 57 58 /* Return the file name part of a path. */ 59 static inline const char * 60 pmd_drv_log_basename(const char *s) 61 { 62 const char *n = s; 63 64 while (*n) 65 if (*(n++) == '/') 66 s = n; 67 return s; 68 } 69 70 #define PMD_DRV_LOG___(level, type, name, ...) \ 71 rte_log(RTE_LOG_ ## level, \ 72 type, \ 73 RTE_FMT(name ": " \ 74 RTE_FMT_HEAD(__VA_ARGS__,), \ 75 RTE_FMT_TAIL(__VA_ARGS__,))) 76 77 #ifdef RTE_LIBRTE_MLX5_DEBUG 78 79 #define PMD_DRV_LOG__(level, type, name, ...) \ 80 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__) 81 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 82 PMD_DRV_LOG__(level, type, name,\ 83 s "\n" PMD_DRV_LOG_COMMA \ 84 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \ 85 __LINE__ PMD_DRV_LOG_COMMA \ 86 __func__, \ 87 __VA_ARGS__) 88 89 #else /* RTE_LIBRTE_MLX5_DEBUG */ 90 #define PMD_DRV_LOG__(level, type, name, ...) \ 91 PMD_DRV_LOG___(level, type, name, __VA_ARGS__) 92 #define PMD_DRV_LOG_(level, type, name, s, ...) \ 93 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__) 94 95 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 96 97 /* claim_zero() does not perform any check when debugging is disabled. */ 98 #ifdef RTE_LIBRTE_MLX5_DEBUG 99 100 #define MLX5_ASSERT(exp) RTE_VERIFY(exp) 101 #define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0) 102 #define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0) 103 104 #else /* RTE_LIBRTE_MLX5_DEBUG */ 105 106 #define MLX5_ASSERT(exp) RTE_ASSERT(exp) 107 #define claim_zero(...) (__VA_ARGS__) 108 #define claim_nonzero(...) (__VA_ARGS__) 109 110 #endif /* RTE_LIBRTE_MLX5_DEBUG */ 111 112 /* Allocate a buffer on the stack and fill it with a printf format string. */ 113 #define MKSTR(name, ...) \ 114 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \ 115 char name[mkstr_size_##name + 1]; \ 116 \ 117 memset(name, 0, mkstr_size_##name + 1); \ 118 snprintf(name, sizeof(name), "" __VA_ARGS__) 119 120 enum { 121 PCI_VENDOR_ID_MELLANOX = 0x15b3, 122 }; 123 124 enum { 125 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, 126 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, 127 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, 128 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, 129 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, 130 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, 131 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, 132 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, 133 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2, 134 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3, 135 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b, 136 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c, 137 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d, 138 PCI_DEVICE_ID_MELLANOX_CONNECTXVF = 0x101e, 139 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF = 0xa2d6, 140 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX = 0x101f, 141 PCI_DEVICE_ID_MELLANOX_CONNECTX7 = 0x1021, 142 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF = 0Xa2dc, 143 }; 144 145 /* Maximum number of simultaneous unicast MAC addresses. */ 146 #define MLX5_MAX_UC_MAC_ADDRESSES 128 147 /* Maximum number of simultaneous Multicast MAC addresses. */ 148 #define MLX5_MAX_MC_MAC_ADDRESSES 128 149 /* Maximum number of simultaneous MAC addresses. */ 150 #define MLX5_MAX_MAC_ADDRESSES \ 151 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES) 152 153 /* Recognized Infiniband device physical port name types. */ 154 enum mlx5_nl_phys_port_name_type { 155 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */ 156 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */ 157 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */ 158 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */ 159 MLX5_PHYS_PORT_NAME_TYPE_PFHPF, /* pf0, kernel ver >= 5.7, HPF rep */ 160 MLX5_PHYS_PORT_NAME_TYPE_PFSF, /* pf0sf0, kernel ver >= 5.0 */ 161 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */ 162 }; 163 164 /** Switch information returned by mlx5_nl_switch_info(). */ 165 struct mlx5_switch_info { 166 uint32_t master:1; /**< Master device. */ 167 uint32_t representor:1; /**< Representor device. */ 168 enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */ 169 int32_t ctrl_num; /**< Controller number (valid for c#pf#vf# format). */ 170 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */ 171 int32_t port_name; /**< Representor port name. */ 172 uint64_t switch_id; /**< Switch identifier. */ 173 }; 174 175 /* CQE status. */ 176 enum mlx5_cqe_status { 177 MLX5_CQE_STATUS_SW_OWN = -1, 178 MLX5_CQE_STATUS_HW_OWN = -2, 179 MLX5_CQE_STATUS_ERR = -3, 180 }; 181 182 /** 183 * Check whether CQE is valid. 184 * 185 * @param cqe 186 * Pointer to CQE. 187 * @param cqes_n 188 * Size of completion queue. 189 * @param ci 190 * Consumer index. 191 * 192 * @return 193 * The CQE status. 194 */ 195 static __rte_always_inline enum mlx5_cqe_status 196 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, 197 const uint16_t ci) 198 { 199 const uint16_t idx = ci & cqes_n; 200 const uint8_t op_own = cqe->op_own; 201 const uint8_t op_owner = MLX5_CQE_OWNER(op_own); 202 const uint8_t op_code = MLX5_CQE_OPCODE(op_own); 203 204 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID))) 205 return MLX5_CQE_STATUS_HW_OWN; 206 rte_io_rmb(); 207 if (unlikely(op_code == MLX5_CQE_RESP_ERR || 208 op_code == MLX5_CQE_REQ_ERR)) 209 return MLX5_CQE_STATUS_ERR; 210 return MLX5_CQE_STATUS_SW_OWN; 211 } 212 213 /* 214 * Get PCI address <DBDF> string from EAL device. 215 * 216 * @param[out] addr 217 * The output address buffer string 218 * @param[in] size 219 * The output buffer size 220 * @return 221 * - 0 on success. 222 * - Negative value and rte_errno is set otherwise. 223 */ 224 int mlx5_dev_to_pci_str(const struct rte_device *dev, char *addr, size_t size); 225 226 /* 227 * Get PCI address from sysfs of a PCI-related device. 228 * 229 * @param[in] dev_path 230 * The sysfs path should not point to the direct plain PCI device. 231 * Instead, the node "/device/" is used to access the real device. 232 * @param[out] pci_addr 233 * Parsed PCI address. 234 * 235 * @return 236 * - 0 on success. 237 * - Negative value and rte_errno is set otherwise. 238 */ 239 __rte_internal 240 int mlx5_get_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr); 241 242 /* 243 * Get kernel network interface name from sysfs IB device path. 244 * 245 * @param[in] ibdev_path 246 * The sysfs path to IB device. 247 * @param[out] ifname 248 * Interface name output of size IF_NAMESIZE. 249 * 250 * @return 251 * - 0 on success. 252 * - Negative value and rte_errno is set otherwise. 253 */ 254 __rte_internal 255 int mlx5_get_ifname_sysfs(const char *ibdev_path, char *ifname); 256 257 __rte_internal 258 int mlx5_auxiliary_get_child_name(const char *dev, const char *node, 259 char *child, size_t size); 260 261 enum mlx5_class { 262 MLX5_CLASS_INVALID, 263 MLX5_CLASS_ETH = RTE_BIT64(0), 264 MLX5_CLASS_VDPA = RTE_BIT64(1), 265 MLX5_CLASS_REGEX = RTE_BIT64(2), 266 MLX5_CLASS_COMPRESS = RTE_BIT64(3), 267 MLX5_CLASS_CRYPTO = RTE_BIT64(4), 268 }; 269 270 #define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE 271 272 /* devX creation object */ 273 struct mlx5_devx_obj { 274 void *obj; /* The DV object. */ 275 int id; /* The object ID. */ 276 }; 277 278 /* UMR memory buffer used to define 1 entry in indirect mkey. */ 279 struct mlx5_klm { 280 uint32_t byte_count; 281 uint32_t mkey; 282 uint64_t address; 283 }; 284 285 /** Control for key/values list. */ 286 struct mlx5_kvargs_ctrl { 287 struct rte_kvargs *kvlist; /* Structure containing list of key/values.*/ 288 bool is_used[RTE_KVARGS_MAX]; /* Indicator which devargs were used. */ 289 }; 290 291 /** 292 * Call a handler function for each key/value in the list of keys. 293 * 294 * For each key/value association that matches the given key, calls the 295 * handler function with the for a given arg_name passing the value on the 296 * dictionary for that key and a given extra argument. 297 * 298 * @param mkvlist 299 * The mlx5_kvargs structure. 300 * @param keys 301 * A list of keys to process (table of const char *, the last must be NULL). 302 * @param handler 303 * The function to call for each matching key. 304 * @param opaque_arg 305 * A pointer passed unchanged to the handler. 306 * 307 * @return 308 * - 0 on success 309 * - Negative on error 310 */ 311 __rte_internal 312 int 313 mlx5_kvargs_process(struct mlx5_kvargs_ctrl *mkvlist, const char *const keys[], 314 arg_handler_t handler, void *opaque_arg); 315 316 /* All UAR arguments using doorbell register in datapath. */ 317 struct mlx5_uar_data { 318 uint64_t *db; 319 /* The doorbell's virtual address mapped to the relevant HW UAR space.*/ 320 #ifndef RTE_ARCH_64 321 rte_spinlock_t *sl_p; 322 /* Pointer to UAR access lock required for 32bit implementations. */ 323 #endif /* RTE_ARCH_64 */ 324 }; 325 326 /* DevX UAR control structure. */ 327 struct mlx5_uar { 328 struct mlx5_uar_data bf_db; /* UAR data for Blueflame register. */ 329 struct mlx5_uar_data cq_db; /* UAR data for CQ arm db register. */ 330 void *obj; /* DevX UAR object. */ 331 bool dbnc; /* Doorbell mapped to non-cached region. */ 332 #ifndef RTE_ARCH_64 333 rte_spinlock_t bf_sl; 334 rte_spinlock_t cq_sl; 335 /* UAR access locks required for 32bit implementations. */ 336 #endif /* RTE_ARCH_64 */ 337 }; 338 339 /** 340 * Ring a doorbell and flush the update if requested. 341 * 342 * @param uar 343 * Pointer to UAR data structure. 344 * @param val 345 * value to write in big endian format. 346 * @param index 347 * Index of doorbell record. 348 * @param db_rec 349 * Address of doorbell record. 350 * @param flash 351 * Decide whether to flush the DB writing using a memory barrier. 352 */ 353 static __rte_always_inline void 354 mlx5_doorbell_ring(struct mlx5_uar_data *uar, uint64_t val, uint32_t index, 355 volatile uint32_t *db_rec, bool flash) 356 { 357 rte_io_wmb(); 358 *db_rec = rte_cpu_to_be_32(index); 359 /* Ensure ordering between DB record actual update and UAR access. */ 360 rte_wmb(); 361 #ifdef RTE_ARCH_64 362 *uar->db = val; 363 #else /* !RTE_ARCH_64 */ 364 rte_spinlock_lock(uar->sl_p); 365 *(volatile uint32_t *)uar->db = val; 366 rte_io_wmb(); 367 *((volatile uint32_t *)uar->db + 1) = val >> 32; 368 rte_spinlock_unlock(uar->sl_p); 369 #endif 370 if (flash) 371 rte_wmb(); 372 } 373 374 /** 375 * Get the doorbell register mapping type. 376 * 377 * @param uar_mmap_offset 378 * Mmap offset of Verbs/DevX UAR. 379 * @param page_size 380 * System page size 381 * 382 * @return 383 * 1 for non-cached, 0 otherwise. 384 */ 385 static inline uint16_t 386 mlx5_db_map_type_get(off_t uar_mmap_offset, size_t page_size) 387 { 388 off_t cmd = uar_mmap_offset / page_size; 389 390 cmd >>= MLX5_UAR_MMAP_CMD_SHIFT; 391 cmd &= MLX5_UAR_MMAP_CMD_MASK; 392 if (cmd == MLX5_MMAP_GET_NC_PAGES_CMD) 393 return 1; 394 return 0; 395 } 396 397 __rte_internal 398 void mlx5_translate_port_name(const char *port_name_in, 399 struct mlx5_switch_info *port_info_out); 400 void mlx5_glue_constructor(void); 401 extern uint8_t haswell_broadwell_cpu; 402 403 __rte_internal 404 void mlx5_common_init(void); 405 406 /* 407 * Common Driver Interface 408 * 409 * ConnectX common driver supports multiple classes: net, vDPA, regex, crypto 410 * and compress devices. This layer enables creating such multiple classes 411 * on a single device by allowing to bind multiple class-specific device 412 * drivers to attach to the common driver. 413 * 414 * ------------ ------------- -------------- ----------------- ------------ 415 * | mlx5 net | | mlx5 vdpa | | mlx5 regex | | mlx5 compress | | mlx5 ... | 416 * | driver | | driver | | driver | | driver | | drivers | 417 * ------------ ------------- -------------- ----------------- ------------ 418 * || 419 * ----------------- 420 * | mlx5 | 421 * | common driver | 422 * ----------------- 423 * | | 424 * ----------- ----------------- 425 * | mlx5 | | mlx5 | 426 * | pci dev | | auxiliary dev | 427 * ----------- ----------------- 428 * 429 * - mlx5 PCI bus driver binds to mlx5 PCI devices defined by PCI ID table 430 * of all related devices. 431 * - mlx5 class driver such as net, vDPA, regex defines its specific 432 * PCI ID table and mlx5 bus driver probes matching class drivers. 433 * - mlx5 common driver is central place that validates supported 434 * class combinations. 435 * - mlx5 common driver hides bus difference by resolving device address 436 * from devargs, locating target RDMA device and probing with it. 437 */ 438 439 /* 440 * Device configuration structure. 441 * 442 * Merged configuration from: 443 * 444 * - Device capabilities, 445 * - User device parameters disabled features. 446 */ 447 struct mlx5_common_dev_config { 448 struct mlx5_hca_attr hca_attr; /* HCA attributes. */ 449 int dbnc; /* Skip doorbell register write barrier. */ 450 int device_fd; /* Device file descriptor for importation. */ 451 int pd_handle; /* Protection Domain handle for importation. */ 452 unsigned int devx:1; /* Whether devx interface is available or not. */ 453 unsigned int sys_mem_en:1; /* The default memory allocator. */ 454 unsigned int mr_mempool_reg_en:1; 455 /* Allow/prevent implicit mempool memory registration. */ 456 unsigned int mr_ext_memseg_en:1; 457 /* Whether memseg should be extended for MR creation. */ 458 }; 459 460 struct mlx5_common_device { 461 struct rte_device *dev; 462 TAILQ_ENTRY(mlx5_common_device) next; 463 uint32_t classes_loaded; 464 void *ctx; /* Verbs/DV/DevX context. */ 465 void *pd; /* Protection Domain. */ 466 uint32_t pdn; /* Protection Domain Number. */ 467 struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ 468 struct mlx5_common_dev_config config; /* Device configuration. */ 469 }; 470 471 /** 472 * Indicates whether PD and CTX are imported from another process, 473 * or created by this process. 474 * 475 * @param cdev 476 * Pointer to common device. 477 * 478 * @return 479 * True if PD and CTX are imported from another process, False otherwise. 480 */ 481 static inline bool 482 mlx5_imported_pd_and_ctx(struct mlx5_common_device *cdev) 483 { 484 return cdev->config.device_fd != MLX5_ARG_UNSET && 485 cdev->config.pd_handle != MLX5_ARG_UNSET; 486 } 487 488 /** 489 * Initialization function for the driver called during device probing. 490 */ 491 typedef int (mlx5_class_driver_probe_t)(struct mlx5_common_device *cdev, 492 struct mlx5_kvargs_ctrl *mkvlist); 493 494 /** 495 * Uninitialization function for the driver called during hot-unplugging. 496 */ 497 typedef int (mlx5_class_driver_remove_t)(struct mlx5_common_device *cdev); 498 499 /** Device already probed can be probed again to check for new ports. */ 500 #define MLX5_DRV_PROBE_AGAIN 0x0004 501 502 /** 503 * A structure describing a mlx5 common class driver. 504 */ 505 struct mlx5_class_driver { 506 TAILQ_ENTRY(mlx5_class_driver) next; 507 enum mlx5_class drv_class; /**< Class of this driver. */ 508 const char *name; /**< Driver name. */ 509 mlx5_class_driver_probe_t *probe; /**< Device probe function. */ 510 mlx5_class_driver_remove_t *remove; /**< Device remove function. */ 511 const struct rte_pci_id *id_table; /**< ID table, NULL terminated. */ 512 uint32_t probe_again:1; 513 /**< Device already probed can be probed again to check new device. */ 514 uint32_t intr_lsc:1; /**< Supports link state interrupt. */ 515 uint32_t intr_rmv:1; /**< Supports device remove interrupt. */ 516 }; 517 518 /** 519 * Register a mlx5 device driver. 520 * 521 * @param driver 522 * A pointer to a mlx5_driver structure describing the driver 523 * to be registered. 524 */ 525 __rte_internal 526 void 527 mlx5_class_driver_register(struct mlx5_class_driver *driver); 528 529 /** 530 * Test device is a PCI bus device. 531 * 532 * @param dev 533 * Pointer to device. 534 * 535 * @return 536 * - True on device devargs is a PCI bus device. 537 * - False otherwise. 538 */ 539 __rte_internal 540 bool 541 mlx5_dev_is_pci(const struct rte_device *dev); 542 543 /** 544 * Test PCI device is a VF device. 545 * 546 * @param pci_dev 547 * Pointer to PCI device. 548 * 549 * @return 550 * - True on PCI device is a VF device. 551 * - False otherwise. 552 */ 553 __rte_internal 554 bool 555 mlx5_dev_is_vf_pci(struct rte_pci_device *pci_dev); 556 557 __rte_internal 558 int 559 mlx5_dev_mempool_subscribe(struct mlx5_common_device *cdev); 560 561 __rte_internal 562 void 563 mlx5_dev_mempool_unregister(struct mlx5_common_device *cdev, 564 struct rte_mempool *mp); 565 566 __rte_internal 567 int 568 mlx5_devx_uar_prepare(struct mlx5_common_device *cdev, struct mlx5_uar *uar); 569 570 __rte_internal 571 void 572 mlx5_devx_uar_release(struct mlx5_uar *uar); 573 574 /* mlx5_common_os.c */ 575 576 int mlx5_os_open_device(struct mlx5_common_device *cdev, uint32_t classes); 577 int mlx5_os_pd_prepare(struct mlx5_common_device *cdev); 578 int mlx5_os_pd_release(struct mlx5_common_device *cdev); 579 int mlx5_os_remote_pd_and_ctx_validate(struct mlx5_common_dev_config *config); 580 581 /* mlx5 PMD wrapped MR struct. */ 582 struct mlx5_pmd_wrapped_mr { 583 uint32_t lkey; 584 void *addr; 585 size_t len; 586 void *obj; /* verbs mr object or devx umem object. */ 587 void *imkey; /* DevX indirect mkey object. */ 588 }; 589 590 __rte_internal 591 int 592 mlx5_os_wrapped_mkey_create(void *ctx, void *pd, uint32_t pdn, void *addr, 593 size_t length, struct mlx5_pmd_wrapped_mr *pmd_mr); 594 595 __rte_internal 596 void 597 mlx5_os_wrapped_mkey_destroy(struct mlx5_pmd_wrapped_mr *pmd_mr); 598 599 #endif /* RTE_PMD_MLX5_COMMON_H_ */ 600