17b4f1e6bSMatan Azrad /* SPDX-License-Identifier: BSD-3-Clause 27b4f1e6bSMatan Azrad * Copyright 2019 Mellanox Technologies, Ltd 37b4f1e6bSMatan Azrad */ 47b4f1e6bSMatan Azrad 57b4f1e6bSMatan Azrad #ifndef RTE_PMD_MLX5_COMMON_H_ 67b4f1e6bSMatan Azrad #define RTE_PMD_MLX5_COMMON_H_ 77b4f1e6bSMatan Azrad 87b4f1e6bSMatan Azrad #include <assert.h> 993e30982SMatan Azrad #include <stdio.h> 107b4f1e6bSMatan Azrad 1193e30982SMatan Azrad #include <rte_pci.h> 12*8fc74217SMatan Azrad #include <rte_atomic.h> 137b4f1e6bSMatan Azrad #include <rte_log.h> 147b4f1e6bSMatan Azrad 15*8fc74217SMatan Azrad #include "mlx5_prm.h" 16*8fc74217SMatan Azrad 177b4f1e6bSMatan Azrad 187b4f1e6bSMatan Azrad /* 197b4f1e6bSMatan Azrad * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant 207b4f1e6bSMatan Azrad * manner. 217b4f1e6bSMatan Azrad */ 227b4f1e6bSMatan Azrad #define PMD_DRV_LOG_STRIP(a, b) a 237b4f1e6bSMatan Azrad #define PMD_DRV_LOG_OPAREN ( 247b4f1e6bSMatan Azrad #define PMD_DRV_LOG_CPAREN ) 257b4f1e6bSMatan Azrad #define PMD_DRV_LOG_COMMA , 267b4f1e6bSMatan Azrad 277b4f1e6bSMatan Azrad /* Return the file name part of a path. */ 287b4f1e6bSMatan Azrad static inline const char * 297b4f1e6bSMatan Azrad pmd_drv_log_basename(const char *s) 307b4f1e6bSMatan Azrad { 317b4f1e6bSMatan Azrad const char *n = s; 327b4f1e6bSMatan Azrad 337b4f1e6bSMatan Azrad while (*n) 347b4f1e6bSMatan Azrad if (*(n++) == '/') 357b4f1e6bSMatan Azrad s = n; 367b4f1e6bSMatan Azrad return s; 377b4f1e6bSMatan Azrad } 387b4f1e6bSMatan Azrad 397b4f1e6bSMatan Azrad #define PMD_DRV_LOG___(level, type, name, ...) \ 407b4f1e6bSMatan Azrad rte_log(RTE_LOG_ ## level, \ 417b4f1e6bSMatan Azrad type, \ 427b4f1e6bSMatan Azrad RTE_FMT(name ": " \ 437b4f1e6bSMatan Azrad RTE_FMT_HEAD(__VA_ARGS__,), \ 447b4f1e6bSMatan Azrad RTE_FMT_TAIL(__VA_ARGS__,))) 457b4f1e6bSMatan Azrad 467b4f1e6bSMatan Azrad /* 477b4f1e6bSMatan Azrad * When debugging is enabled (NDEBUG not defined), file, line and function 487b4f1e6bSMatan Azrad * information replace the driver name (MLX5_DRIVER_NAME) in log messages. 497b4f1e6bSMatan Azrad */ 507b4f1e6bSMatan Azrad #ifndef NDEBUG 517b4f1e6bSMatan Azrad 527b4f1e6bSMatan Azrad #define PMD_DRV_LOG__(level, type, name, ...) \ 537b4f1e6bSMatan Azrad PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__) 547b4f1e6bSMatan Azrad #define PMD_DRV_LOG_(level, type, name, s, ...) \ 557b4f1e6bSMatan Azrad PMD_DRV_LOG__(level, type, name,\ 567b4f1e6bSMatan Azrad s "\n" PMD_DRV_LOG_COMMA \ 577b4f1e6bSMatan Azrad pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \ 587b4f1e6bSMatan Azrad __LINE__ PMD_DRV_LOG_COMMA \ 597b4f1e6bSMatan Azrad __func__, \ 607b4f1e6bSMatan Azrad __VA_ARGS__) 617b4f1e6bSMatan Azrad 627b4f1e6bSMatan Azrad #else /* NDEBUG */ 637b4f1e6bSMatan Azrad #define PMD_DRV_LOG__(level, type, name, ...) \ 647b4f1e6bSMatan Azrad PMD_DRV_LOG___(level, type, name, __VA_ARGS__) 657b4f1e6bSMatan Azrad #define PMD_DRV_LOG_(level, type, name, s, ...) \ 667b4f1e6bSMatan Azrad PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__) 677b4f1e6bSMatan Azrad 687b4f1e6bSMatan Azrad #endif /* NDEBUG */ 697b4f1e6bSMatan Azrad 707b4f1e6bSMatan Azrad /* claim_zero() does not perform any check when debugging is disabled. */ 717b4f1e6bSMatan Azrad #ifndef NDEBUG 727b4f1e6bSMatan Azrad 737b4f1e6bSMatan Azrad #define DEBUG(...) DRV_LOG(DEBUG, __VA_ARGS__) 747b4f1e6bSMatan Azrad #define claim_zero(...) assert((__VA_ARGS__) == 0) 757b4f1e6bSMatan Azrad #define claim_nonzero(...) assert((__VA_ARGS__) != 0) 767b4f1e6bSMatan Azrad 777b4f1e6bSMatan Azrad #else /* NDEBUG */ 787b4f1e6bSMatan Azrad 797b4f1e6bSMatan Azrad #define DEBUG(...) (void)0 807b4f1e6bSMatan Azrad #define claim_zero(...) (__VA_ARGS__) 817b4f1e6bSMatan Azrad #define claim_nonzero(...) (__VA_ARGS__) 827b4f1e6bSMatan Azrad 837b4f1e6bSMatan Azrad #endif /* NDEBUG */ 847b4f1e6bSMatan Azrad 857b4f1e6bSMatan Azrad /* Allocate a buffer on the stack and fill it with a printf format string. */ 867b4f1e6bSMatan Azrad #define MKSTR(name, ...) \ 877b4f1e6bSMatan Azrad int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \ 887b4f1e6bSMatan Azrad char name[mkstr_size_##name + 1]; \ 897b4f1e6bSMatan Azrad \ 907b4f1e6bSMatan Azrad snprintf(name, sizeof(name), "" __VA_ARGS__) 917b4f1e6bSMatan Azrad 92e415f348SMatan Azrad enum { 93e415f348SMatan Azrad PCI_VENDOR_ID_MELLANOX = 0x15b3, 94e415f348SMatan Azrad }; 95e415f348SMatan Azrad 96e415f348SMatan Azrad enum { 97e415f348SMatan Azrad PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, 98e415f348SMatan Azrad PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, 99e415f348SMatan Azrad PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, 100e415f348SMatan Azrad PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, 101e415f348SMatan Azrad PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, 102e415f348SMatan Azrad PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, 103e415f348SMatan Azrad PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, 104e415f348SMatan Azrad PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, 105e415f348SMatan Azrad PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2, 106e415f348SMatan Azrad PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3, 107e415f348SMatan Azrad PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b, 108e415f348SMatan Azrad PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c, 109e415f348SMatan Azrad PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d, 110e415f348SMatan Azrad PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e, 111e415f348SMatan Azrad }; 112e415f348SMatan Azrad 113*8fc74217SMatan Azrad /* CQE status. */ 114*8fc74217SMatan Azrad enum mlx5_cqe_status { 115*8fc74217SMatan Azrad MLX5_CQE_STATUS_SW_OWN = -1, 116*8fc74217SMatan Azrad MLX5_CQE_STATUS_HW_OWN = -2, 117*8fc74217SMatan Azrad MLX5_CQE_STATUS_ERR = -3, 118*8fc74217SMatan Azrad }; 119*8fc74217SMatan Azrad 120*8fc74217SMatan Azrad /** 121*8fc74217SMatan Azrad * Check whether CQE is valid. 122*8fc74217SMatan Azrad * 123*8fc74217SMatan Azrad * @param cqe 124*8fc74217SMatan Azrad * Pointer to CQE. 125*8fc74217SMatan Azrad * @param cqes_n 126*8fc74217SMatan Azrad * Size of completion queue. 127*8fc74217SMatan Azrad * @param ci 128*8fc74217SMatan Azrad * Consumer index. 129*8fc74217SMatan Azrad * 130*8fc74217SMatan Azrad * @return 131*8fc74217SMatan Azrad * The CQE status. 132*8fc74217SMatan Azrad */ 133*8fc74217SMatan Azrad static __rte_always_inline enum mlx5_cqe_status 134*8fc74217SMatan Azrad check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, 135*8fc74217SMatan Azrad const uint16_t ci) 136*8fc74217SMatan Azrad { 137*8fc74217SMatan Azrad const uint16_t idx = ci & cqes_n; 138*8fc74217SMatan Azrad const uint8_t op_own = cqe->op_own; 139*8fc74217SMatan Azrad const uint8_t op_owner = MLX5_CQE_OWNER(op_own); 140*8fc74217SMatan Azrad const uint8_t op_code = MLX5_CQE_OPCODE(op_own); 141*8fc74217SMatan Azrad 142*8fc74217SMatan Azrad if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID))) 143*8fc74217SMatan Azrad return MLX5_CQE_STATUS_HW_OWN; 144*8fc74217SMatan Azrad rte_cio_rmb(); 145*8fc74217SMatan Azrad if (unlikely(op_code == MLX5_CQE_RESP_ERR || 146*8fc74217SMatan Azrad op_code == MLX5_CQE_REQ_ERR)) 147*8fc74217SMatan Azrad return MLX5_CQE_STATUS_ERR; 148*8fc74217SMatan Azrad return MLX5_CQE_STATUS_SW_OWN; 149*8fc74217SMatan Azrad } 150*8fc74217SMatan Azrad 15193e30982SMatan Azrad int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr); 15293e30982SMatan Azrad 1537b4f1e6bSMatan Azrad #endif /* RTE_PMD_MLX5_COMMON_H_ */ 154