1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018-2024 Advanced Micro Devices, Inc.
3 */
4
5 #ifndef _IONIC_REGS_H_
6 #define _IONIC_REGS_H_
7
8 /** struct ionic_intr - interrupt control register set.
9 * @coal_init: coalesce timer initial value.
10 * @mask: interrupt mask value.
11 * @credits: interrupt credit count and return.
12 * @mask_assert: interrupt mask value on assert.
13 * @coal: coalesce timer time remaining.
14 */
15 struct ionic_intr {
16 uint32_t coal_init;
17 uint32_t mask;
18 uint32_t credits;
19 uint32_t mask_assert;
20 uint32_t coal;
21 uint32_t rsvd[3];
22 };
23
24 /** enum ionic_intr_mask_vals - valid values for mask and mask_assert.
25 * @IONIC_INTR_MASK_CLEAR: unmask interrupt.
26 * @IONIC_INTR_MASK_SET: mask interrupt.
27 */
28 enum ionic_intr_mask_vals {
29 IONIC_INTR_MASK_CLEAR = 0,
30 IONIC_INTR_MASK_SET = 1,
31 };
32
33 /** enum ionic_intr_credits_bits - bitwise composition of credits values.
34 * @IONIC_INTR_CRED_COUNT: bit mask of credit count, no shift needed.
35 * @IONIC_INTR_CRED_COUNT_SIGNED: bit mask of credit count, including sign bit.
36 * @IONIC_INTR_CRED_UNMASK: unmask the interrupt.
37 * @IONIC_INTR_CRED_RESET_COALESCE: reset the coalesce timer.
38 * @IONIC_INTR_CRED_REARM: unmask the and reset the timer.
39 */
40 enum ionic_intr_credits_bits {
41 IONIC_INTR_CRED_COUNT = 0x7fffu,
42 IONIC_INTR_CRED_COUNT_SIGNED = 0xffffu,
43 IONIC_INTR_CRED_UNMASK = 0x10000u,
44 IONIC_INTR_CRED_RESET_COALESCE = 0x20000u,
45 IONIC_INTR_CRED_REARM = (IONIC_INTR_CRED_UNMASK |
46 IONIC_INTR_CRED_RESET_COALESCE),
47 };
48
49 #define IONIC_INTR_NONE (-1)
50 #define IONIC_INTR_CTRL_REGS_MAX 2048
51
52 struct ionic_intr_info {
53 int index;
54 uint32_t vector;
55 struct ionic_intr __iomem *ctrl;
56 };
57
58 struct ionic_intr_status {
59 uint32_t status[2];
60 };
61
62 static inline void
ionic_intr_coal_init(struct ionic_intr __iomem * intr_ctrl,int intr_idx,uint32_t coal)63 ionic_intr_coal_init(struct ionic_intr __iomem *intr_ctrl,
64 int intr_idx, uint32_t coal)
65 {
66 iowrite32(coal, &intr_ctrl[intr_idx].coal_init);
67 }
68
69 static inline void
ionic_intr_mask(struct ionic_intr __iomem * intr_ctrl,int intr_idx,uint32_t mask)70 ionic_intr_mask(struct ionic_intr __iomem *intr_ctrl,
71 int intr_idx, uint32_t mask)
72 {
73 iowrite32(mask, &intr_ctrl[intr_idx].mask);
74 }
75
76 static inline void
ionic_intr_credits(struct ionic_intr __iomem * intr_ctrl,int intr_idx,uint32_t cred,uint32_t flags)77 ionic_intr_credits(struct ionic_intr __iomem *intr_ctrl,
78 int intr_idx, uint32_t cred, uint32_t flags)
79 {
80 if (cred > IONIC_INTR_CRED_COUNT) {
81 cred = ioread32(&intr_ctrl[intr_idx].credits);
82 cred &= IONIC_INTR_CRED_COUNT_SIGNED;
83 }
84
85 iowrite32(cred | flags, &intr_ctrl[intr_idx].credits);
86 }
87
88 static inline void
ionic_intr_clean(struct ionic_intr __iomem * intr_ctrl,int intr_idx)89 ionic_intr_clean(struct ionic_intr __iomem *intr_ctrl,
90 int intr_idx)
91 {
92 uint32_t cred;
93
94 cred = ioread32(&intr_ctrl[intr_idx].credits);
95 cred &= IONIC_INTR_CRED_COUNT_SIGNED;
96 cred |= IONIC_INTR_CRED_RESET_COALESCE;
97 iowrite32(cred, &intr_ctrl[intr_idx].credits);
98 }
99
100 static inline void
ionic_intr_mask_assert(struct ionic_intr __iomem * intr_ctrl,int intr_idx,uint32_t mask)101 ionic_intr_mask_assert(struct ionic_intr __iomem *intr_ctrl,
102 int intr_idx, uint32_t mask)
103 {
104 iowrite32(mask, &intr_ctrl[intr_idx].mask_assert);
105 }
106
107 /** enum ionic_dbell_bits - bitwise composition of dbell values.
108 *
109 * @IONIC_DBELL_QID_MASK: unshifted mask of valid queue id bits.
110 * @IONIC_DBELL_QID_SHIFT: queue id shift amount in dbell value.
111 * @IONIC_DBELL_QID: macro to build QID component of dbell value.
112 *
113 * @IONIC_DBELL_RING_MASK: unshifted mask of valid ring bits.
114 * @IONIC_DBELL_RING_SHIFT: ring shift amount in dbell value.
115 * @IONIC_DBELL_RING: macro to build ring component of dbell value.
116 *
117 * @IONIC_DBELL_RING_0: ring zero dbell component value.
118 * @IONIC_DBELL_RING_1: ring one dbell component value.
119 * @IONIC_DBELL_RING_2: ring two dbell component value.
120 * @IONIC_DBELL_RING_3: ring three dbell component value.
121 *
122 * @IONIC_DBELL_INDEX_MASK: bit mask of valid index bits, no shift needed.
123 */
124 enum ionic_dbell_bits {
125 IONIC_DBELL_QID_MASK = 0xffffff,
126 IONIC_DBELL_QID_SHIFT = 24,
127
128 #define IONIC_DBELL_QID(n) \
129 (((u64)(n) & IONIC_DBELL_QID_MASK) << IONIC_DBELL_QID_SHIFT)
130
131 IONIC_DBELL_RING_MASK = 0x7,
132 IONIC_DBELL_RING_SHIFT = 16,
133
134 #define IONIC_DBELL_RING(n) \
135 (((u64)(n) & IONIC_DBELL_RING_MASK) << IONIC_DBELL_RING_SHIFT)
136
137 IONIC_DBELL_RING_0 = 0,
138 IONIC_DBELL_RING_1 = IONIC_DBELL_RING(1),
139 IONIC_DBELL_RING_2 = IONIC_DBELL_RING(2),
140 IONIC_DBELL_RING_3 = IONIC_DBELL_RING(3),
141
142 IONIC_DBELL_INDEX_MASK = 0xffff,
143 };
144
145 #define IONIC_BARS_MIN 2
146 #define IONIC_BARS_MAX 6
147 #define IONIC_PCI_BAR_DBELL 1
148
149 /* BAR0 */
150 #define IONIC_BAR0_SIZE 0x8000
151
152 #define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000
153 #define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800
154 #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00
155 #define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000
156 #define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000
157 #define IONIC_DEV_CMD_DONE 0x00000001
158
159 /**
160 * struct ionic_doorbell - Doorbell register layout
161 * @p_index: Producer index
162 * @ring: Selects the specific ring of the queue to update
163 * Type-specific meaning:
164 * ring=0: Default producer/consumer queue
165 * ring=1: (CQ, EQ) Re-Arm queue. CQs send events to EQs
166 * when armed. EQs send interrupts when armed.
167 * @qid_lo: Queue destination for the producer index and flags (low bits)
168 * @qid_hi: Queue destination for the producer index and flags (high bits)
169 */
170 struct ionic_doorbell {
171 __le16 p_index;
172 u8 ring;
173 u8 qid_lo;
174 __le16 qid_hi;
175 u16 rsvd2;
176 };
177
178 #endif /* _IONIC_REGS_H_ */
179