1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2023 Intel Corporation 3 */ 4 5 #ifndef _IDPF_LAN_VF_REGS_H_ 6 #define _IDPF_LAN_VF_REGS_H_ 7 8 9 /* Reset */ 10 #define VFGEN_RSTAT 0x00008800 11 #define VFGEN_RSTAT_VFR_STATE_S 0 12 #define VFGEN_RSTAT_VFR_STATE_M GENMASK(1, 0) 13 14 /* Control(VF Mailbox) Queue */ 15 #define VF_BASE 0x00006000 16 17 #define VF_ATQBAL (VF_BASE + 0x1C00) 18 #define VF_ATQBAH (VF_BASE + 0x1800) 19 #define VF_ATQLEN (VF_BASE + 0x0800) 20 #define VF_ATQLEN_ATQLEN_S 0 21 #define VF_ATQLEN_ATQLEN_M GENMASK(9, 0) 22 #define VF_ATQLEN_ATQVFE_S 28 23 #define VF_ATQLEN_ATQVFE_M BIT(VF_ATQLEN_ATQVFE_S) 24 #define VF_ATQLEN_ATQOVFL_S 29 25 #define VF_ATQLEN_ATQOVFL_M BIT(VF_ATQLEN_ATQOVFL_S) 26 #define VF_ATQLEN_ATQCRIT_S 30 27 #define VF_ATQLEN_ATQCRIT_M BIT(VF_ATQLEN_ATQCRIT_S) 28 #define VF_ATQLEN_ATQENABLE_S 31 29 #define VF_ATQLEN_ATQENABLE_M BIT(VF_ATQLEN_ATQENABLE_S) 30 #define VF_ATQH (VF_BASE + 0x0400) 31 #define VF_ATQH_ATQH_S 0 32 #define VF_ATQH_ATQH_M GENMASK(9, 0) 33 #define VF_ATQT (VF_BASE + 0x2400) 34 35 #define VF_ARQBAL (VF_BASE + 0x0C00) 36 #define VF_ARQBAH (VF_BASE) 37 #define VF_ARQLEN (VF_BASE + 0x2000) 38 #define VF_ARQLEN_ARQLEN_S 0 39 #define VF_ARQLEN_ARQLEN_M GENMASK(9, 0) 40 #define VF_ARQLEN_ARQVFE_S 28 41 #define VF_ARQLEN_ARQVFE_M BIT(VF_ARQLEN_ARQVFE_S) 42 #define VF_ARQLEN_ARQOVFL_S 29 43 #define VF_ARQLEN_ARQOVFL_M BIT(VF_ARQLEN_ARQOVFL_S) 44 #define VF_ARQLEN_ARQCRIT_S 30 45 #define VF_ARQLEN_ARQCRIT_M BIT(VF_ARQLEN_ARQCRIT_S) 46 #define VF_ARQLEN_ARQENABLE_S 31 47 #define VF_ARQLEN_ARQENABLE_M BIT(VF_ARQLEN_ARQENABLE_S) 48 #define VF_ARQH (VF_BASE + 0x1400) 49 #define VF_ARQH_ARQH_S 0 50 #define VF_ARQH_ARQH_M GENMASK(12, 0) 51 #define VF_ARQT (VF_BASE + 0x1000) 52 53 /* Transmit queues */ 54 #define VF_QTX_TAIL_BASE 0x00000000 55 #define VF_QTX_TAIL(_QTX) (VF_QTX_TAIL_BASE + (_QTX) * 0x4) 56 #define VF_QTX_TAIL_EXT_BASE 0x00040000 57 #define VF_QTX_TAIL_EXT(_QTX) (VF_QTX_TAIL_EXT_BASE + ((_QTX) * 4)) 58 59 /* Receive queues */ 60 #define VF_QRX_TAIL_BASE 0x00002000 61 #define VF_QRX_TAIL(_QRX) (VF_QRX_TAIL_BASE + ((_QRX) * 4)) 62 #define VF_QRX_TAIL_EXT_BASE 0x00050000 63 #define VF_QRX_TAIL_EXT(_QRX) (VF_QRX_TAIL_EXT_BASE + ((_QRX) * 4)) 64 #define VF_QRXB_TAIL_BASE 0x00060000 65 #define VF_QRXB_TAIL(_QRX) (VF_QRXB_TAIL_BASE + ((_QRX) * 4)) 66 67 /* Interrupts */ 68 #define VF_INT_DYN_CTL0 0x00005C00 69 #define VF_INT_DYN_CTL0_INTENA_S 0 70 #define VF_INT_DYN_CTL0_INTENA_M BIT(VF_INT_DYN_CTL0_INTENA_S) 71 #define VF_INT_DYN_CTL0_ITR_INDX_S 3 72 #define VF_INT_DYN_CTL0_ITR_INDX_M GENMASK(4, 3) 73 #define VF_INT_DYN_CTLN(_INT) (0x00003800 + ((_INT) * 4)) 74 #define VF_INT_DYN_CTLN_EXT(_INT) (0x00070000 + ((_INT) * 4)) 75 #define VF_INT_DYN_CTLN_INTENA_S 0 76 #define VF_INT_DYN_CTLN_INTENA_M BIT(VF_INT_DYN_CTLN_INTENA_S) 77 #define VF_INT_DYN_CTLN_CLEARPBA_S 1 78 #define VF_INT_DYN_CTLN_CLEARPBA_M BIT(VF_INT_DYN_CTLN_CLEARPBA_S) 79 #define VF_INT_DYN_CTLN_SWINT_TRIG_S 2 80 #define VF_INT_DYN_CTLN_SWINT_TRIG_M BIT(VF_INT_DYN_CTLN_SWINT_TRIG_S) 81 #define VF_INT_DYN_CTLN_ITR_INDX_S 3 82 #define VF_INT_DYN_CTLN_ITR_INDX_M GENMASK(4, 3) 83 #define VF_INT_DYN_CTLN_INTERVAL_S 5 84 #define VF_INT_DYN_CTLN_INTERVAL_M BIT(VF_INT_DYN_CTLN_INTERVAL_S) 85 #define VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_S 24 86 #define VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_M BIT(VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_S) 87 #define VF_INT_DYN_CTLN_SW_ITR_INDX_S 25 88 #define VF_INT_DYN_CTLN_SW_ITR_INDX_M BIT(VF_INT_DYN_CTLN_SW_ITR_INDX_S) 89 #define VF_INT_DYN_CTLN_WB_ON_ITR_S 30 90 #define VF_INT_DYN_CTLN_WB_ON_ITR_M BIT(VF_INT_DYN_CTLN_WB_ON_ITR_S) 91 #define VF_INT_DYN_CTLN_INTENA_MSK_S 31 92 #define VF_INT_DYN_CTLN_INTENA_MSK_M BIT(VF_INT_DYN_CTLN_INTENA_MSK_S) 93 /* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is spacing 94 * b/w itrn registers of the same vector 95 */ 96 #define VF_INT_ITR0(_ITR) (0x00004C00 + ((_ITR) * 4)) 97 #define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \ 98 ((_reg_start) + ((_ITR) * (_itrn_indx_spacing))) 99 /* For VF with 16 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing 100 * is 0x40 and base register offset is 0x00002800 101 */ 102 #define VF_INT_ITRN(_INT, _ITR) \ 103 (0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40)) 104 /* For VF with 64 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing 105 * is 0x100 and base register offset is 0x00002C00 106 */ 107 #define VF_INT_ITRN_64(_INT, _ITR) \ 108 (0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100)) 109 /* For VF with 2k vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing 110 * is 0x2000 and base register offset is 0x00072000 111 */ 112 #define VF_INT_ITRN_2K(_INT, _ITR) \ 113 (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000)) 114 #define VF_INT_ITRN_MAX_INDEX 2 115 #define VF_INT_ITRN_INTERVAL_S 0 116 #define VF_INT_ITRN_INTERVAL_M GENMASK(11, 0) 117 #define VF_INT_PBA_CLEAR 0x00008900 118 119 #define VF_INT_ICR0_ENA1 0x00005000 120 #define VF_INT_ICR0_ENA1_ADMINQ_S 30 121 #define VF_INT_ICR0_ENA1_ADMINQ_M BIT(VF_INT_ICR0_ENA1_ADMINQ_S) 122 #define VF_INT_ICR0_ENA1_RSVD_S 31 123 #define VF_INT_ICR01 0x00004800 124 #define VF_QF_HENA(_i) (0x0000C400 + ((_i) * 4)) 125 #define VF_QF_HENA_MAX_INDX 1 126 #define VF_QF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) 127 #define VF_QF_HKEY_MAX_INDX 12 128 #define VF_QF_HLUT(_i) (0x0000D000 + ((_i) * 4)) 129 #define VF_QF_HLUT_MAX_INDX 15 130 #endif 131