1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2021 Intel Corporation 3 */ 4 5 #ifndef _IAVF_TYPE_H_ 6 #define _IAVF_TYPE_H_ 7 8 #include "iavf_status.h" 9 #include "iavf_osdep.h" 10 #include "iavf_register.h" 11 #include "iavf_adminq.h" 12 #include "iavf_devids.h" 13 14 #define IAVF_RXQ_CTX_DBUFF_SHIFT 7 15 16 #define UNREFERENCED_XPARAMETER 17 #define UNREFERENCED_1PARAMETER(_p) (_p); 18 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q); 19 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r); 20 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s); 21 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t); 22 23 #define BIT(a) (1UL << (a)) 24 #define BIT_ULL(a) (1ULL << (a)) 25 26 /* IAVF_MASK is a macro used on 32 bit registers */ 27 #define IAVF_MASK(mask, shift) (mask << shift) 28 29 #define IAVF_MAX_PF 16 30 #define IAVF_MAX_PF_VSI 64 31 #define IAVF_MAX_PF_QP 128 32 #define IAVF_MAX_VSI_QP 16 33 #define IAVF_MAX_VF_VSI 4 34 #define IAVF_MAX_CHAINED_RX_BUFFERS 5 35 36 /* something less than 1 minute */ 37 #define IAVF_HEARTBEAT_TIMEOUT (HZ * 50) 38 39 40 /* Check whether address is multicast. */ 41 #define IAVF_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01)) 42 43 /* Check whether an address is broadcast. */ 44 #define IAVF_IS_BROADCAST(address) \ 45 ((((u8 *)(address))[0] == ((u8)0xff)) && \ 46 (((u8 *)(address))[1] == ((u8)0xff))) 47 48 49 /* forward declaration */ 50 struct iavf_hw; 51 typedef void (*IAVF_ADMINQ_CALLBACK)(struct iavf_hw *, struct iavf_aq_desc *); 52 53 #define ETH_ALEN 6 54 /* Data type manipulation macros. */ 55 #define IAVF_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 56 #define IAVF_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) 57 58 #define IAVF_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) 59 #define IAVF_LO_WORD(x) ((u16)((x) & 0xFFFF)) 60 61 #define IAVF_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF)) 62 #define IAVF_LO_BYTE(x) ((u8)((x) & 0xFF)) 63 64 /* Number of Transmit Descriptors must be a multiple of 8. */ 65 #define IAVF_REQ_TX_DESCRIPTOR_MULTIPLE 8 66 /* Number of Receive Descriptors must be a multiple of 32 if 67 * the number of descriptors is greater than 32. 68 */ 69 #define IAVF_REQ_RX_DESCRIPTOR_MULTIPLE 32 70 71 #define IAVF_DESC_UNUSED(R) \ 72 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 73 (R)->next_to_clean - (R)->next_to_use - 1) 74 75 /* bitfields for Tx queue mapping in QTX_CTL */ 76 #define IAVF_QTX_CTL_VF_QUEUE 0x0 77 #define IAVF_QTX_CTL_VM_QUEUE 0x1 78 #define IAVF_QTX_CTL_PF_QUEUE 0x2 79 80 /* debug masks - set these bits in hw->debug_mask to control output */ 81 enum iavf_debug_mask { 82 IAVF_DEBUG_INIT = 0x00000001, 83 IAVF_DEBUG_RELEASE = 0x00000002, 84 85 IAVF_DEBUG_LINK = 0x00000010, 86 IAVF_DEBUG_PHY = 0x00000020, 87 IAVF_DEBUG_HMC = 0x00000040, 88 IAVF_DEBUG_NVM = 0x00000080, 89 IAVF_DEBUG_LAN = 0x00000100, 90 IAVF_DEBUG_FLOW = 0x00000200, 91 IAVF_DEBUG_DCB = 0x00000400, 92 IAVF_DEBUG_DIAG = 0x00000800, 93 IAVF_DEBUG_FD = 0x00001000, 94 IAVF_DEBUG_PACKAGE = 0x00002000, 95 96 IAVF_DEBUG_AQ_MESSAGE = 0x01000000, 97 IAVF_DEBUG_AQ_DESCRIPTOR = 0x02000000, 98 IAVF_DEBUG_AQ_DESC_BUFFER = 0x04000000, 99 IAVF_DEBUG_AQ_COMMAND = 0x06000000, 100 IAVF_DEBUG_AQ = 0x0F000000, 101 102 IAVF_DEBUG_USER = 0xF0000000, 103 104 IAVF_DEBUG_ALL = 0xFFFFFFFF 105 }; 106 107 /* PCI Bus Info */ 108 #define IAVF_PCI_LINK_STATUS 0xB2 109 #define IAVF_PCI_LINK_WIDTH 0x3F0 110 #define IAVF_PCI_LINK_WIDTH_1 0x10 111 #define IAVF_PCI_LINK_WIDTH_2 0x20 112 #define IAVF_PCI_LINK_WIDTH_4 0x40 113 #define IAVF_PCI_LINK_WIDTH_8 0x80 114 #define IAVF_PCI_LINK_SPEED 0xF 115 #define IAVF_PCI_LINK_SPEED_2500 0x1 116 #define IAVF_PCI_LINK_SPEED_5000 0x2 117 #define IAVF_PCI_LINK_SPEED_8000 0x3 118 119 #define IAVF_MDIO_CLAUSE22_STCODE_MASK IAVF_MASK(1, \ 120 IAVF_GLGEN_MSCA_STCODE_SHIFT) 121 #define IAVF_MDIO_CLAUSE22_OPCODE_WRITE_MASK IAVF_MASK(1, \ 122 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 123 #define IAVF_MDIO_CLAUSE22_OPCODE_READ_MASK IAVF_MASK(2, \ 124 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 125 126 #define IAVF_MDIO_CLAUSE45_STCODE_MASK IAVF_MASK(0, \ 127 IAVF_GLGEN_MSCA_STCODE_SHIFT) 128 #define IAVF_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK IAVF_MASK(0, \ 129 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 130 #define IAVF_MDIO_CLAUSE45_OPCODE_WRITE_MASK IAVF_MASK(1, \ 131 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 132 #define IAVF_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK IAVF_MASK(2, \ 133 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 134 #define IAVF_MDIO_CLAUSE45_OPCODE_READ_MASK IAVF_MASK(3, \ 135 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 136 137 #define IAVF_PHY_COM_REG_PAGE 0x1E 138 #define IAVF_PHY_LED_LINK_MODE_MASK 0xF0 139 #define IAVF_PHY_LED_MANUAL_ON 0x100 140 #define IAVF_PHY_LED_PROV_REG_1 0xC430 141 #define IAVF_PHY_LED_MODE_MASK 0xFFFF 142 #define IAVF_PHY_LED_MODE_ORIG 0x80000000 143 144 #define IAVF_MAX_TRAFFIC_CLASS 8 145 146 /* Memory types */ 147 enum iavf_memset_type { 148 IAVF_NONDMA_MEM = 0, 149 IAVF_DMA_MEM 150 }; 151 152 /* Memcpy types */ 153 enum iavf_memcpy_type { 154 IAVF_NONDMA_TO_NONDMA = 0, 155 IAVF_NONDMA_TO_DMA, 156 IAVF_DMA_TO_DMA, 157 IAVF_DMA_TO_NONDMA 158 }; 159 160 /* These are structs for managing the hardware information and the operations. 161 * The structures of function pointers are filled out at init time when we 162 * know for sure exactly which hardware we're working with. This gives us the 163 * flexibility of using the same main driver code but adapting to slightly 164 * different hardware needs as new parts are developed. For this architecture, 165 * the Firmware and AdminQ are intended to insulate the driver from most of the 166 * future changes, but these structures will also do part of the job. 167 */ 168 enum iavf_mac_type { 169 IAVF_MAC_UNKNOWN = 0, 170 IAVF_MAC_XL710, 171 IAVF_MAC_VF, 172 IAVF_MAC_X722, 173 IAVF_MAC_X722_VF, 174 IAVF_MAC_GENERIC, 175 }; 176 177 enum iavf_vsi_type { 178 IAVF_VSI_MAIN = 0, 179 IAVF_VSI_VMDQ1 = 1, 180 IAVF_VSI_VMDQ2 = 2, 181 IAVF_VSI_CTRL = 3, 182 IAVF_VSI_FCOE = 4, 183 IAVF_VSI_MIRROR = 5, 184 IAVF_VSI_SRIOV = 6, 185 IAVF_VSI_FDIR = 7, 186 IAVF_VSI_TYPE_UNKNOWN 187 }; 188 189 enum iavf_queue_type { 190 IAVF_QUEUE_TYPE_RX = 0, 191 IAVF_QUEUE_TYPE_TX, 192 IAVF_QUEUE_TYPE_PE_CEQ, 193 IAVF_QUEUE_TYPE_UNKNOWN 194 }; 195 196 #define IAVF_HW_CAP_MAX_GPIO 30 197 #define IAVF_HW_CAP_MDIO_PORT_MODE_MDIO 0 198 #define IAVF_HW_CAP_MDIO_PORT_MODE_I2C 1 199 200 enum iavf_acpi_programming_method { 201 IAVF_ACPI_PROGRAMMING_METHOD_HW_FVL = 0, 202 IAVF_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1 203 }; 204 205 #define IAVF_WOL_SUPPORT_MASK 0x1 206 #define IAVF_ACPI_PROGRAMMING_METHOD_MASK 0x2 207 #define IAVF_PROXY_SUPPORT_MASK 0x4 208 209 /* Capabilities of a PF or a VF or the whole device */ 210 struct iavf_hw_capabilities { 211 /* Cloud filter modes: 212 * Mode1: Filter on L4 port only 213 * Mode2: Filter for non-tunneled traffic 214 * Mode3: Filter for tunnel traffic 215 */ 216 #define IAVF_CLOUD_FILTER_MODE1 0x6 217 #define IAVF_CLOUD_FILTER_MODE2 0x7 218 #define IAVF_CLOUD_FILTER_MODE3 0x8 219 #define IAVF_SWITCH_MODE_MASK 0xF 220 221 bool dcb; 222 bool fcoe; 223 bool iwarp; 224 u32 num_vsis; 225 u32 num_rx_qp; 226 u32 num_tx_qp; 227 u32 base_queue; 228 u32 num_msix_vectors_vf; 229 u32 max_mtu; 230 bool apm_wol_support; 231 enum iavf_acpi_programming_method acpi_prog_method; 232 bool proxy_support; 233 }; 234 235 struct iavf_mac_info { 236 enum iavf_mac_type type; 237 u8 addr[ETH_ALEN]; 238 u8 perm_addr[ETH_ALEN]; 239 u8 san_addr[ETH_ALEN]; 240 u8 port_addr[ETH_ALEN]; 241 u16 max_fcoeq; 242 }; 243 244 #define IAVF_NVM_EXEC_GET_AQ_RESULT 0x0 245 #define IAVF_NVM_EXEC_FEATURES 0xe 246 #define IAVF_NVM_EXEC_STATUS 0xf 247 248 /* NVMUpdate features API */ 249 #define IAVF_NVMUPD_FEATURES_API_VER_MAJOR 0 250 #define IAVF_NVMUPD_FEATURES_API_VER_MINOR 14 251 #define IAVF_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN 12 252 253 #define IAVF_NVMUPD_FEATURE_FLAT_NVM_SUPPORT BIT(0) 254 255 struct iavf_nvmupd_features { 256 u8 major; 257 u8 minor; 258 u16 size; 259 u8 features[IAVF_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN]; 260 }; 261 262 #define IAVF_MODULE_SFF_DIAG_CAPAB 0x40 263 /* PCI bus types */ 264 enum iavf_bus_type { 265 iavf_bus_type_unknown = 0, 266 iavf_bus_type_pci, 267 iavf_bus_type_pcix, 268 iavf_bus_type_pci_express, 269 iavf_bus_type_reserved 270 }; 271 272 /* PCI bus speeds */ 273 enum iavf_bus_speed { 274 iavf_bus_speed_unknown = 0, 275 iavf_bus_speed_33 = 33, 276 iavf_bus_speed_66 = 66, 277 iavf_bus_speed_100 = 100, 278 iavf_bus_speed_120 = 120, 279 iavf_bus_speed_133 = 133, 280 iavf_bus_speed_2500 = 2500, 281 iavf_bus_speed_5000 = 5000, 282 iavf_bus_speed_8000 = 8000, 283 iavf_bus_speed_reserved 284 }; 285 286 /* PCI bus widths */ 287 enum iavf_bus_width { 288 iavf_bus_width_unknown = 0, 289 iavf_bus_width_pcie_x1 = 1, 290 iavf_bus_width_pcie_x2 = 2, 291 iavf_bus_width_pcie_x4 = 4, 292 iavf_bus_width_pcie_x8 = 8, 293 iavf_bus_width_32 = 32, 294 iavf_bus_width_64 = 64, 295 iavf_bus_width_reserved 296 }; 297 298 /* Bus parameters */ 299 struct iavf_bus_info { 300 enum iavf_bus_speed speed; 301 enum iavf_bus_width width; 302 enum iavf_bus_type type; 303 304 u16 func; 305 u16 device; 306 u16 lan_id; 307 u16 bus_id; 308 }; 309 310 #define IAVF_MAX_USER_PRIORITY 8 311 #define IAVF_TLV_STATUS_OPER 0x1 312 #define IAVF_TLV_STATUS_SYNC 0x2 313 #define IAVF_TLV_STATUS_ERR 0x4 314 #define IAVF_CEE_OPER_MAX_APPS 3 315 #define IAVF_APP_PROTOID_FCOE 0x8906 316 #define IAVF_APP_PROTOID_ISCSI 0x0cbc 317 #define IAVF_APP_PROTOID_FIP 0x8914 318 #define IAVF_APP_SEL_ETHTYPE 0x1 319 #define IAVF_APP_SEL_TCPIP 0x2 320 #define IAVF_CEE_APP_SEL_ETHTYPE 0x0 321 #define IAVF_CEE_APP_SEL_TCPIP 0x1 322 323 /* Port hardware description */ 324 struct iavf_hw { 325 u8 *hw_addr; 326 void *back; 327 328 /* subsystem structs */ 329 struct iavf_mac_info mac; 330 struct iavf_bus_info bus; 331 332 /* pci info */ 333 u16 device_id; 334 u16 vendor_id; 335 u16 subsystem_device_id; 336 u16 subsystem_vendor_id; 337 u8 revision_id; 338 339 /* capabilities for entire device and PCI func */ 340 struct iavf_hw_capabilities dev_caps; 341 342 /* Admin Queue info */ 343 struct iavf_adminq_info aq; 344 345 /* WoL and proxy support */ 346 u16 num_wol_proxy_filters; 347 u16 wol_proxy_vsi_seid; 348 349 #define IAVF_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0) 350 #define IAVF_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1) 351 #define IAVF_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2) 352 #define IAVF_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3) 353 #define IAVF_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4) 354 u64 flags; 355 356 /* NVMUpdate features */ 357 struct iavf_nvmupd_features nvmupd_features; 358 359 /* debug mask */ 360 u32 debug_mask; 361 char err_str[16]; 362 }; 363 364 struct iavf_driver_version { 365 u8 major_version; 366 u8 minor_version; 367 u8 build_version; 368 u8 subbuild_version; 369 u8 driver_string[32]; 370 }; 371 372 /* RX Descriptors */ 373 union iavf_16byte_rx_desc { 374 struct { 375 __le64 pkt_addr; /* Packet buffer address */ 376 __le64 hdr_addr; /* Header buffer address */ 377 } read; 378 struct { 379 struct { 380 struct { 381 union { 382 __le16 mirroring_status; 383 __le16 fcoe_ctx_id; 384 } mirr_fcoe; 385 __le16 l2tag1; 386 } lo_dword; 387 union { 388 __le32 rss; /* RSS Hash */ 389 __le32 fd_id; /* Flow director filter id */ 390 __le32 fcoe_param; /* FCoE DDP Context id */ 391 } hi_dword; 392 } qword0; 393 struct { 394 /* ext status/error/pktype/length */ 395 __le64 status_error_len; 396 } qword1; 397 } wb; /* writeback */ 398 }; 399 400 union iavf_32byte_rx_desc { 401 struct { 402 __le64 pkt_addr; /* Packet buffer address */ 403 __le64 hdr_addr; /* Header buffer address */ 404 /* bit 0 of hdr_buffer_addr is DD bit */ 405 __le64 rsvd1; 406 __le64 rsvd2; 407 } read; 408 struct { 409 struct { 410 struct { 411 union { 412 __le16 mirroring_status; 413 __le16 fcoe_ctx_id; 414 } mirr_fcoe; 415 __le16 l2tag1; 416 } lo_dword; 417 union { 418 __le32 rss; /* RSS Hash */ 419 __le32 fcoe_param; /* FCoE DDP Context id */ 420 /* Flow director filter id in case of 421 * Programming status desc WB 422 */ 423 __le32 fd_id; 424 } hi_dword; 425 } qword0; 426 struct { 427 /* status/error/pktype/length */ 428 __le64 status_error_len; 429 } qword1; 430 struct { 431 __le16 ext_status; /* extended status */ 432 __le16 rsvd; 433 __le16 l2tag2_1; 434 __le16 l2tag2_2; 435 } qword2; 436 struct { 437 union { 438 __le32 flex_bytes_lo; 439 __le32 pe_status; 440 } lo_dword; 441 union { 442 __le32 flex_bytes_hi; 443 __le32 fd_id; 444 } hi_dword; 445 } qword3; 446 } wb; /* writeback */ 447 }; 448 449 #define IAVF_RXD_QW0_MIRROR_STATUS_SHIFT 8 450 #define IAVF_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \ 451 IAVF_RXD_QW0_MIRROR_STATUS_SHIFT) 452 #define IAVF_RXD_QW0_FCOEINDX_SHIFT 0 453 #define IAVF_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \ 454 IAVF_RXD_QW0_FCOEINDX_SHIFT) 455 456 enum iavf_rx_desc_status_bits { 457 /* Note: These are predefined bit offsets */ 458 IAVF_RX_DESC_STATUS_DD_SHIFT = 0, 459 IAVF_RX_DESC_STATUS_EOF_SHIFT = 1, 460 IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT = 2, 461 IAVF_RX_DESC_STATUS_L3L4P_SHIFT = 3, 462 IAVF_RX_DESC_STATUS_CRCP_SHIFT = 4, 463 IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */ 464 IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT = 7, 465 IAVF_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8, 466 467 IAVF_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */ 468 IAVF_RX_DESC_STATUS_FLM_SHIFT = 11, 469 IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */ 470 IAVF_RX_DESC_STATUS_LPBK_SHIFT = 14, 471 IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15, 472 IAVF_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */ 473 IAVF_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18, 474 IAVF_RX_DESC_STATUS_LAST /* this entry must be last!!! */ 475 }; 476 477 #define IAVF_RX_FLEX_DESC_STATUS_ERR0_DD_BIT BIT(0) 478 #define IAVF_RX_FLEX_DESC_STATUS_ERR0_EOP_BIT BIT(1) 479 #define IAVF_RX_FLEX_DESC_STATUS_ERR0_RXE_BIT BIT(10) 480 481 #define IAVF_RXD_QW1_STATUS_SHIFT 0 482 #define IAVF_RXD_QW1_STATUS_MASK ((BIT(IAVF_RX_DESC_STATUS_LAST) - 1) \ 483 << IAVF_RXD_QW1_STATUS_SHIFT) 484 485 #define IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT 486 #define IAVF_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \ 487 IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT) 488 489 #define IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT 490 #define IAVF_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT) 491 492 #define IAVF_RXD_QW1_STATUS_UMBCAST_SHIFT IAVF_RX_DESC_STATUS_UMBCAST 493 #define IAVF_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \ 494 IAVF_RXD_QW1_STATUS_UMBCAST_SHIFT) 495 496 enum iavf_rx_desc_fltstat_values { 497 IAVF_RX_DESC_FLTSTAT_NO_DATA = 0, 498 IAVF_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ 499 IAVF_RX_DESC_FLTSTAT_RSV = 2, 500 IAVF_RX_DESC_FLTSTAT_RSS_HASH = 3, 501 }; 502 503 #define IAVF_RXD_PACKET_TYPE_UNICAST 0 504 #define IAVF_RXD_PACKET_TYPE_MULTICAST 1 505 #define IAVF_RXD_PACKET_TYPE_BROADCAST 2 506 #define IAVF_RXD_PACKET_TYPE_MIRRORED 3 507 508 #define IAVF_RXD_QW1_ERROR_SHIFT 19 509 #define IAVF_RXD_QW1_ERROR_MASK (0xFFUL << IAVF_RXD_QW1_ERROR_SHIFT) 510 511 enum iavf_rx_desc_error_bits { 512 /* Note: These are predefined bit offsets */ 513 IAVF_RX_DESC_ERROR_RXE_SHIFT = 0, 514 IAVF_RX_DESC_ERROR_RECIPE_SHIFT = 1, 515 IAVF_RX_DESC_ERROR_HBO_SHIFT = 2, 516 IAVF_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */ 517 IAVF_RX_DESC_ERROR_IPE_SHIFT = 3, 518 IAVF_RX_DESC_ERROR_L4E_SHIFT = 4, 519 IAVF_RX_DESC_ERROR_EIPE_SHIFT = 5, 520 IAVF_RX_DESC_ERROR_OVERSIZE_SHIFT = 6, 521 IAVF_RX_DESC_ERROR_PPRS_SHIFT = 7 522 }; 523 524 enum iavf_rx_desc_error_l3l4e_fcoe_masks { 525 IAVF_RX_DESC_ERROR_L3L4E_NONE = 0, 526 IAVF_RX_DESC_ERROR_L3L4E_PROT = 1, 527 IAVF_RX_DESC_ERROR_L3L4E_FC = 2, 528 IAVF_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3, 529 IAVF_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4 530 }; 531 532 #define IAVF_RXD_QW1_PTYPE_SHIFT 30 533 #define IAVF_RXD_QW1_PTYPE_MASK (0xFFULL << IAVF_RXD_QW1_PTYPE_SHIFT) 534 535 /* Packet type non-ip values */ 536 enum iavf_rx_l2_ptype { 537 IAVF_RX_PTYPE_L2_RESERVED = 0, 538 IAVF_RX_PTYPE_L2_MAC_PAY2 = 1, 539 IAVF_RX_PTYPE_L2_TIMESYNC_PAY2 = 2, 540 IAVF_RX_PTYPE_L2_FIP_PAY2 = 3, 541 IAVF_RX_PTYPE_L2_OUI_PAY2 = 4, 542 IAVF_RX_PTYPE_L2_MACCNTRL_PAY2 = 5, 543 IAVF_RX_PTYPE_L2_LLDP_PAY2 = 6, 544 IAVF_RX_PTYPE_L2_ECP_PAY2 = 7, 545 IAVF_RX_PTYPE_L2_EVB_PAY2 = 8, 546 IAVF_RX_PTYPE_L2_QCN_PAY2 = 9, 547 IAVF_RX_PTYPE_L2_EAPOL_PAY2 = 10, 548 IAVF_RX_PTYPE_L2_ARP = 11, 549 IAVF_RX_PTYPE_L2_FCOE_PAY3 = 12, 550 IAVF_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13, 551 IAVF_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14, 552 IAVF_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15, 553 IAVF_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16, 554 IAVF_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17, 555 IAVF_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18, 556 IAVF_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19, 557 IAVF_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20, 558 IAVF_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21, 559 IAVF_RX_PTYPE_GRENAT4_MAC_PAY3 = 58, 560 IAVF_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87, 561 IAVF_RX_PTYPE_GRENAT6_MAC_PAY3 = 124, 562 IAVF_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153, 563 IAVF_RX_PTYPE_PARSER_ABORTED = 255 564 }; 565 566 struct iavf_rx_ptype_decoded { 567 u32 ptype:8; 568 u32 known:1; 569 u32 outer_ip:1; 570 u32 outer_ip_ver:1; 571 u32 outer_frag:1; 572 u32 tunnel_type:3; 573 u32 tunnel_end_prot:2; 574 u32 tunnel_end_frag:1; 575 u32 inner_prot:4; 576 u32 payload_layer:3; 577 }; 578 579 enum iavf_rx_ptype_outer_ip { 580 IAVF_RX_PTYPE_OUTER_L2 = 0, 581 IAVF_RX_PTYPE_OUTER_IP = 1 582 }; 583 584 enum iavf_rx_ptype_outer_ip_ver { 585 IAVF_RX_PTYPE_OUTER_NONE = 0, 586 IAVF_RX_PTYPE_OUTER_IPV4 = 0, 587 IAVF_RX_PTYPE_OUTER_IPV6 = 1 588 }; 589 590 enum iavf_rx_ptype_outer_fragmented { 591 IAVF_RX_PTYPE_NOT_FRAG = 0, 592 IAVF_RX_PTYPE_FRAG = 1 593 }; 594 595 enum iavf_rx_ptype_tunnel_type { 596 IAVF_RX_PTYPE_TUNNEL_NONE = 0, 597 IAVF_RX_PTYPE_TUNNEL_IP_IP = 1, 598 IAVF_RX_PTYPE_TUNNEL_IP_GRENAT = 2, 599 IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, 600 IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, 601 }; 602 603 enum iavf_rx_ptype_tunnel_end_prot { 604 IAVF_RX_PTYPE_TUNNEL_END_NONE = 0, 605 IAVF_RX_PTYPE_TUNNEL_END_IPV4 = 1, 606 IAVF_RX_PTYPE_TUNNEL_END_IPV6 = 2, 607 }; 608 609 enum iavf_rx_ptype_inner_prot { 610 IAVF_RX_PTYPE_INNER_PROT_NONE = 0, 611 IAVF_RX_PTYPE_INNER_PROT_UDP = 1, 612 IAVF_RX_PTYPE_INNER_PROT_TCP = 2, 613 IAVF_RX_PTYPE_INNER_PROT_SCTP = 3, 614 IAVF_RX_PTYPE_INNER_PROT_ICMP = 4, 615 IAVF_RX_PTYPE_INNER_PROT_TIMESYNC = 5 616 }; 617 618 enum iavf_rx_ptype_payload_layer { 619 IAVF_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, 620 IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, 621 IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, 622 IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, 623 }; 624 625 #define IAVF_RX_PTYPE_BIT_MASK 0x0FFFFFFF 626 #define IAVF_RX_PTYPE_SHIFT 56 627 628 #define IAVF_RXD_QW1_LENGTH_PBUF_SHIFT 38 629 #define IAVF_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \ 630 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) 631 632 #define IAVF_RXD_QW1_LENGTH_HBUF_SHIFT 52 633 #define IAVF_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \ 634 IAVF_RXD_QW1_LENGTH_HBUF_SHIFT) 635 636 #define IAVF_RXD_QW1_LENGTH_SPH_SHIFT 63 637 #define IAVF_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(IAVF_RXD_QW1_LENGTH_SPH_SHIFT) 638 639 #define IAVF_RXD_QW1_NEXTP_SHIFT 38 640 #define IAVF_RXD_QW1_NEXTP_MASK (0x1FFFULL << IAVF_RXD_QW1_NEXTP_SHIFT) 641 642 #define IAVF_RXD_QW2_EXT_STATUS_SHIFT 0 643 #define IAVF_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \ 644 IAVF_RXD_QW2_EXT_STATUS_SHIFT) 645 646 enum iavf_rx_desc_ext_status_bits { 647 /* Note: These are predefined bit offsets */ 648 IAVF_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0, 649 IAVF_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1, 650 IAVF_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */ 651 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */ 652 IAVF_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9, 653 IAVF_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10, 654 IAVF_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11, 655 }; 656 657 #define IAVF_RXD_QW2_L2TAG2_SHIFT 0 658 #define IAVF_RXD_QW2_L2TAG2_MASK (0xFFFFUL << IAVF_RXD_QW2_L2TAG2_SHIFT) 659 660 #define IAVF_RXD_QW2_L2TAG3_SHIFT 16 661 #define IAVF_RXD_QW2_L2TAG3_MASK (0xFFFFUL << IAVF_RXD_QW2_L2TAG3_SHIFT) 662 663 enum iavf_rx_desc_pe_status_bits { 664 /* Note: These are predefined bit offsets */ 665 IAVF_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */ 666 IAVF_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */ 667 IAVF_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */ 668 IAVF_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24, 669 IAVF_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25, 670 IAVF_RX_DESC_PE_STATUS_PORTV_SHIFT = 26, 671 IAVF_RX_DESC_PE_STATUS_URG_SHIFT = 27, 672 IAVF_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28, 673 IAVF_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29 674 }; 675 676 #define IAVF_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38 677 #define IAVF_RX_PROG_STATUS_DESC_LENGTH 0x2000000 678 679 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2 680 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \ 681 IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT) 682 683 #define IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0 684 #define IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \ 685 IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT) 686 687 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19 688 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \ 689 IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT) 690 691 enum iavf_rx_prog_status_desc_status_bits { 692 /* Note: These are predefined bit offsets */ 693 IAVF_RX_PROG_STATUS_DESC_DD_SHIFT = 0, 694 IAVF_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */ 695 }; 696 697 enum iavf_rx_prog_status_desc_prog_id_masks { 698 IAVF_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1, 699 IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2, 700 IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4, 701 }; 702 703 enum iavf_rx_prog_status_desc_error_bits { 704 /* Note: These are predefined bit offsets */ 705 IAVF_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0, 706 IAVF_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1, 707 IAVF_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2, 708 IAVF_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3 709 }; 710 711 #define IAVF_TWO_BIT_MASK 0x3 712 #define IAVF_THREE_BIT_MASK 0x7 713 #define IAVF_FOUR_BIT_MASK 0xF 714 #define IAVF_EIGHTEEN_BIT_MASK 0x3FFFF 715 716 /* TX Descriptor */ 717 struct iavf_tx_desc { 718 __le64 buffer_addr; /* Address of descriptor's data buf */ 719 __le64 cmd_type_offset_bsz; 720 }; 721 722 #define IAVF_TXD_QW1_DTYPE_SHIFT 0 723 #define IAVF_TXD_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT) 724 725 enum iavf_tx_desc_dtype_value { 726 IAVF_TX_DESC_DTYPE_DATA = 0x0, 727 IAVF_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */ 728 IAVF_TX_DESC_DTYPE_CONTEXT = 0x1, 729 IAVF_TX_DESC_DTYPE_FCOE_CTX = 0x2, 730 IAVF_TX_DESC_DTYPE_IPSEC = 0x3, 731 IAVF_TX_DESC_DTYPE_FILTER_PROG = 0x8, 732 IAVF_TX_DESC_DTYPE_DDP_CTX = 0x9, 733 IAVF_TX_DESC_DTYPE_FLEX_DATA = 0xB, 734 IAVF_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC, 735 IAVF_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD, 736 IAVF_TX_DESC_DTYPE_DESC_DONE = 0xF 737 }; 738 739 #define IAVF_TXD_QW1_CMD_SHIFT 4 740 #define IAVF_TXD_QW1_CMD_MASK (0x3FFUL << IAVF_TXD_QW1_CMD_SHIFT) 741 742 enum iavf_tx_desc_cmd_bits { 743 IAVF_TX_DESC_CMD_EOP = 0x0001, 744 IAVF_TX_DESC_CMD_RS = 0x0002, 745 IAVF_TX_DESC_CMD_ICRC = 0x0004, 746 IAVF_TX_DESC_CMD_IL2TAG1 = 0x0008, 747 IAVF_TX_DESC_CMD_DUMMY = 0x0010, 748 IAVF_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ 749 IAVF_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ 750 IAVF_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ 751 IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ 752 IAVF_TX_DESC_CMD_FCOET = 0x0080, 753 IAVF_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ 754 IAVF_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ 755 IAVF_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ 756 IAVF_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ 757 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */ 758 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */ 759 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */ 760 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */ 761 }; 762 763 #define IAVF_TXD_QW1_OFFSET_SHIFT 16 764 #define IAVF_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \ 765 IAVF_TXD_QW1_OFFSET_SHIFT) 766 767 enum iavf_tx_desc_length_fields { 768 /* Note: These are predefined bit offsets */ 769 IAVF_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */ 770 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */ 771 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */ 772 }; 773 774 #define IAVF_TXD_QW1_MACLEN_MASK (0x7FUL << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT) 775 #define IAVF_TXD_QW1_IPLEN_MASK (0x7FUL << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT) 776 #define IAVF_TXD_QW1_L4LEN_MASK (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 777 #define IAVF_TXD_QW1_FCLEN_MASK (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 778 779 #define IAVF_TXD_QW1_TX_BUF_SZ_SHIFT 34 780 #define IAVF_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \ 781 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) 782 783 #define IAVF_TXD_QW1_L2TAG1_SHIFT 48 784 #define IAVF_TXD_QW1_L2TAG1_MASK (0xFFFFULL << IAVF_TXD_QW1_L2TAG1_SHIFT) 785 786 /* Context descriptors */ 787 struct iavf_tx_context_desc { 788 __le32 tunneling_params; 789 __le16 l2tag2; 790 __le16 rsvd; 791 __le64 type_cmd_tso_mss; 792 }; 793 794 #define IAVF_TXD_CTX_QW1_DTYPE_SHIFT 0 795 #define IAVF_TXD_CTX_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_CTX_QW1_DTYPE_SHIFT) 796 797 #define IAVF_TXD_CTX_QW1_CMD_SHIFT 4 798 #define IAVF_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << IAVF_TXD_CTX_QW1_CMD_SHIFT) 799 800 enum iavf_tx_ctx_desc_cmd_bits { 801 IAVF_TX_CTX_DESC_TSO = 0x01, 802 IAVF_TX_CTX_DESC_TSYN = 0x02, 803 IAVF_TX_CTX_DESC_IL2TAG2 = 0x04, 804 IAVF_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 805 IAVF_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 806 IAVF_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 807 IAVF_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 808 IAVF_TX_CTX_DESC_SWTCH_VSI = 0x30, 809 IAVF_TX_CTX_DESC_SWPE = 0x40 810 }; 811 812 struct iavf_nop_desc { 813 __le64 rsvd; 814 __le64 dtype_cmd; 815 }; 816 817 #define IAVF_TXD_NOP_QW1_DTYPE_SHIFT 0 818 #define IAVF_TXD_NOP_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_NOP_QW1_DTYPE_SHIFT) 819 820 #define IAVF_TXD_NOP_QW1_CMD_SHIFT 4 821 #define IAVF_TXD_NOP_QW1_CMD_MASK (0x7FUL << IAVF_TXD_NOP_QW1_CMD_SHIFT) 822 823 enum iavf_tx_nop_desc_cmd_bits { 824 /* Note: These are predefined bit offsets */ 825 IAVF_TX_NOP_DESC_EOP_SHIFT = 0, 826 IAVF_TX_NOP_DESC_RS_SHIFT = 1, 827 IAVF_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */ 828 }; 829 830 /* Packet Classifier Types for filters */ 831 enum iavf_filter_pctype { 832 /* Note: Values 0-28 are reserved for future use. 833 * Value 29, 30, 32 are not supported on XL710 and X710. 834 */ 835 IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29, 836 IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30, 837 IAVF_FILTER_PCTYPE_NONF_IPV4_UDP = 31, 838 IAVF_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32, 839 IAVF_FILTER_PCTYPE_NONF_IPV4_TCP = 33, 840 IAVF_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, 841 IAVF_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, 842 IAVF_FILTER_PCTYPE_FRAG_IPV4 = 36, 843 /* Note: Values 37-38 are reserved for future use. 844 * Value 39, 40, 42 are not supported on XL710 and X710. 845 */ 846 IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39, 847 IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40, 848 IAVF_FILTER_PCTYPE_NONF_IPV6_UDP = 41, 849 IAVF_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42, 850 IAVF_FILTER_PCTYPE_NONF_IPV6_TCP = 43, 851 IAVF_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, 852 IAVF_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, 853 IAVF_FILTER_PCTYPE_FRAG_IPV6 = 46, 854 /* Note: Value 47 is reserved for future use */ 855 IAVF_FILTER_PCTYPE_FCOE_OX = 48, 856 IAVF_FILTER_PCTYPE_FCOE_RX = 49, 857 IAVF_FILTER_PCTYPE_FCOE_OTHER = 50, 858 /* Note: Values 51-62 are reserved for future use */ 859 IAVF_FILTER_PCTYPE_L2_PAYLOAD = 63, 860 }; 861 862 #define IAVF_TXD_FLTR_QW1_DTYPE_SHIFT 0 863 #define IAVF_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_FLTR_QW1_DTYPE_SHIFT) 864 865 #define IAVF_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \ 866 IAVF_TXD_FLTR_QW1_CMD_SHIFT) 867 #define IAVF_TXD_FLTR_QW1_ATR_MASK BIT_ULL(IAVF_TXD_FLTR_QW1_ATR_SHIFT) 868 869 870 #define IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT 30 871 #define IAVF_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \ 872 IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) 873 874 #define IAVF_TXD_CTX_QW1_MSS_SHIFT 50 875 #define IAVF_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \ 876 IAVF_TXD_CTX_QW1_MSS_SHIFT) 877 878 #define IAVF_TXD_CTX_QW1_VSI_SHIFT 50 879 #define IAVF_TXD_CTX_QW1_VSI_MASK (0x1FFULL << IAVF_TXD_CTX_QW1_VSI_SHIFT) 880 881 #define IAVF_TXD_CTX_QW0_EXT_IP_SHIFT 0 882 #define IAVF_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \ 883 IAVF_TXD_CTX_QW0_EXT_IP_SHIFT) 884 885 enum iavf_tx_ctx_desc_eipt_offload { 886 IAVF_TX_CTX_EXT_IP_NONE = 0x0, 887 IAVF_TX_CTX_EXT_IP_IPV6 = 0x1, 888 IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2, 889 IAVF_TX_CTX_EXT_IP_IPV4 = 0x3 890 }; 891 892 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2 893 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \ 894 IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT) 895 896 #define IAVF_TXD_CTX_QW0_NATT_SHIFT 9 897 #define IAVF_TXD_CTX_QW0_NATT_MASK (0x3ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT) 898 899 #define IAVF_TXD_CTX_UDP_TUNNELING BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT) 900 #define IAVF_TXD_CTX_GRE_TUNNELING (0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT) 901 902 #define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT 11 903 #define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK \ 904 BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT) 905 906 #define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST IAVF_TXD_CTX_QW0_EIP_NOINC_MASK 907 908 #define IAVF_TXD_CTX_QW0_NATLEN_SHIFT 12 909 #define IAVF_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \ 910 IAVF_TXD_CTX_QW0_NATLEN_SHIFT) 911 912 #define IAVF_TXD_CTX_QW0_DECTTL_SHIFT 19 913 #define IAVF_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \ 914 IAVF_TXD_CTX_QW0_DECTTL_SHIFT) 915 916 #define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT 23 917 #define IAVF_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT) 918 919 /* Statistics collected by each port, VSI, VEB, and S-channel */ 920 struct iavf_eth_stats { 921 u64 rx_bytes; /* gorc */ 922 u64 rx_unicast; /* uprc */ 923 u64 rx_multicast; /* mprc */ 924 u64 rx_broadcast; /* bprc */ 925 u64 rx_discards; /* rdpc */ 926 u64 rx_unknown_protocol; /* rupp */ 927 u64 tx_bytes; /* gotc */ 928 u64 tx_unicast; /* uptc */ 929 u64 tx_multicast; /* mptc */ 930 u64 tx_broadcast; /* bptc */ 931 u64 tx_discards; /* tdpc */ 932 u64 tx_errors; /* tepc */ 933 }; 934 #define IAVF_SR_PCIE_ANALOG_CONFIG_PTR 0x03 935 #define IAVF_SR_PHY_ANALOG_CONFIG_PTR 0x04 936 #define IAVF_SR_OPTION_ROM_PTR 0x05 937 #define IAVF_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 938 #define IAVF_SR_AUTO_GENERATED_POINTERS_PTR 0x07 939 #define IAVF_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 940 #define IAVF_SR_EMP_GLOBAL_MODULE_PTR 0x09 941 #define IAVF_SR_RO_PCIE_LCB_PTR 0x0A 942 #define IAVF_SR_EMP_IMAGE_PTR 0x0B 943 #define IAVF_SR_PE_IMAGE_PTR 0x0C 944 #define IAVF_SR_CSR_PROTECTED_LIST_PTR 0x0D 945 #define IAVF_SR_MNG_CONFIG_PTR 0x0E 946 #define IAVF_SR_PBA_FLAGS 0x15 947 #define IAVF_SR_PBA_BLOCK_PTR 0x16 948 #define IAVF_SR_BOOT_CONFIG_PTR 0x17 949 #define IAVF_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28 950 #define IAVF_SR_NVM_MAP_VERSION 0x29 951 #define IAVF_SR_NVM_IMAGE_VERSION 0x2A 952 #define IAVF_SR_NVM_STRUCTURE_VERSION 0x2B 953 #define IAVF_SR_PXE_SETUP_PTR 0x30 954 #define IAVF_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31 955 #define IAVF_SR_NVM_ORIGINAL_EETRACK_LO 0x34 956 #define IAVF_SR_NVM_ORIGINAL_EETRACK_HI 0x35 957 #define IAVF_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37 958 #define IAVF_SR_POR_REGS_AUTO_LOAD_PTR 0x38 959 #define IAVF_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A 960 #define IAVF_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B 961 #define IAVF_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C 962 #define IAVF_SR_PHY_ACTIVITY_LIST_PTR 0x3D 963 #define IAVF_SR_1ST_FREE_PROVISION_AREA_PTR 0x40 964 #define IAVF_SR_4TH_FREE_PROVISION_AREA_PTR 0x42 965 #define IAVF_SR_3RD_FREE_PROVISION_AREA_PTR 0x44 966 #define IAVF_SR_2ND_FREE_PROVISION_AREA_PTR 0x46 967 #define IAVF_SR_EMP_SR_SETTINGS_PTR 0x48 968 #define IAVF_SR_FEATURE_CONFIGURATION_PTR 0x49 969 #define IAVF_SR_CONFIGURATION_METADATA_PTR 0x4D 970 #define IAVF_SR_IMMEDIATE_VALUES_PTR 0x4E 971 #define IAVF_SR_OCP_CFG_WORD0 0x2B 972 #define IAVF_SR_OCP_ENABLED BIT(15) 973 #define IAVF_SR_BUF_ALIGNMENT 4096 974 975 976 struct iavf_lldp_variables { 977 u16 length; 978 u16 adminstatus; 979 u16 msgfasttx; 980 u16 msgtxinterval; 981 u16 txparams; 982 u16 timers; 983 u16 crc8; 984 }; 985 986 /* Offsets into Alternate Ram */ 987 #define IAVF_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */ 988 #define IAVF_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */ 989 #define IAVF_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */ 990 #define IAVF_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */ 991 #define IAVF_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */ 992 #define IAVF_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */ 993 994 /* Alternate Ram Bandwidth Masks */ 995 #define IAVF_ALT_BW_VALUE_MASK 0xFF 996 #define IAVF_ALT_BW_RELATIVE_MASK 0x40000000 997 #define IAVF_ALT_BW_VALID_MASK 0x80000000 998 999 #define IAVF_DDP_TRACKID_RDONLY 0 1000 #define IAVF_DDP_TRACKID_INVALID 0xFFFFFFFF 1001 #define SECTION_TYPE_RB_MMIO 0x00001800 1002 #define SECTION_TYPE_RB_AQ 0x00001801 1003 #define SECTION_TYPE_PROTO 0x80000002 1004 #define SECTION_TYPE_PCTYPE 0x80000003 1005 #define SECTION_TYPE_PTYPE 0x80000004 1006 struct iavf_profile_tlv_section_record { 1007 u8 rtype; 1008 u8 type; 1009 u16 len; 1010 u8 data[12]; 1011 }; 1012 1013 /* Generic AQ section in profile */ 1014 struct iavf_profile_aq_section { 1015 u16 opcode; 1016 u16 flags; 1017 u8 param[16]; 1018 u16 datalen; 1019 u8 data[1]; 1020 }; 1021 1022 #endif /* _IAVF_TYPE_H_ */ 1023