1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #ifndef _ROC_PLATFORM_H_ 6 #define _ROC_PLATFORM_H_ 7 8 #include <rte_compat.h> 9 #include <rte_alarm.h> 10 #include <rte_bitmap.h> 11 #include <bus_pci_driver.h> 12 #include <rte_byteorder.h> 13 #include <rte_common.h> 14 #include <rte_cycles.h> 15 #include <rte_ether.h> 16 #include <rte_interrupts.h> 17 #include <rte_io.h> 18 #include <rte_lcore.h> 19 #include <rte_log.h> 20 #include <rte_malloc.h> 21 #include <rte_memzone.h> 22 #include <rte_pci.h> 23 #include <rte_seqcount.h> 24 #include <rte_spinlock.h> 25 #include <rte_string_fns.h> 26 #include <rte_tailq.h> 27 #include <rte_telemetry.h> 28 29 #include "eal_filesystem.h" 30 31 #include "roc_bits.h" 32 33 #if defined(__ARM_FEATURE_SVE) 34 #define PLT_CPU_FEATURE_PREAMBLE \ 35 ".arch_extension crc\n" \ 36 ".arch_extension lse\n" \ 37 ".arch_extension sve\n" 38 #else 39 #define PLT_CPU_FEATURE_PREAMBLE \ 40 ".arch_extension crc\n" \ 41 ".arch_extension lse\n" 42 #endif 43 44 #define PLT_ASSERT RTE_ASSERT 45 #define PLT_VERIFY RTE_VERIFY 46 #define PLT_MEMZONE_NAMESIZE RTE_MEMZONE_NAMESIZE 47 #define PLT_PTR_ADD RTE_PTR_ADD 48 #define PLT_PTR_SUB RTE_PTR_SUB 49 #define PLT_PTR_DIFF RTE_PTR_DIFF 50 #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID 51 #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET 52 #define PLT_MIN RTE_MIN 53 #define PLT_MAX RTE_MAX 54 #define PLT_DIM RTE_DIM 55 #define PLT_SET_USED RTE_SET_USED 56 #define PLT_SWAP RTE_SWAP 57 #define PLT_STATIC_ASSERT(s) _Static_assert(s, #s) 58 #define PLT_ALIGN RTE_ALIGN 59 #define PLT_ALIGN_MUL_CEIL RTE_ALIGN_MUL_CEIL 60 #define PLT_MODEL_MZ_NAME "roc_model_mz" 61 #define PLT_CACHE_LINE_SIZE RTE_CACHE_LINE_SIZE 62 #define BITMASK_ULL GENMASK_ULL 63 #define PLT_ALIGN_CEIL RTE_ALIGN_CEIL 64 #define PLT_ALIGN_FLOOR RTE_ALIGN_FLOOR 65 #define PLT_INIT RTE_INIT 66 #define PLT_MAX_ETHPORTS RTE_MAX_ETHPORTS 67 #define PLT_TAILQ_FOREACH_SAFE RTE_TAILQ_FOREACH_SAFE 68 69 #ifndef PLT_ETHER_ADDR_LEN 70 #define PLT_ETHER_ADDR_LEN RTE_ETHER_ADDR_LEN 71 #endif 72 73 #define PLT_DISABLE_TEMPLATE_FUNC 0 74 #if PLT_DISABLE_TEMPLATE_FUNC 75 #ifndef CNXK_DIS_TMPLT_FUNC 76 #define CNXK_DIS_TMPLT_FUNC 77 #endif 78 #endif 79 80 /* Cast to specific datatypes */ 81 #define PLT_PTR_CAST(val) ((void *)(val)) 82 #define PLT_U64_CAST(val) ((uint64_t)(val)) 83 #define PLT_U32_CAST(val) ((uint32_t)(val)) 84 #define PLT_U16_CAST(val) ((uint16_t)(val)) 85 86 /* Add / Sub pointer with scalar and cast to uint64_t */ 87 #define PLT_PTR_ADD_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_ADD(__ptr, __x)) 88 #define PLT_PTR_SUB_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_SUB(__ptr, __x)) 89 90 /** Divide ceil */ 91 #define PLT_DIV_CEIL(x, y) \ 92 __extension__ ({ \ 93 __typeof(x) __x = x; \ 94 __typeof(y) __y = y; \ 95 (__x + __y - 1) / __y; \ 96 }) 97 98 #define __plt_cache_aligned __rte_cache_aligned 99 #define __plt_always_inline __rte_always_inline 100 #define __plt_packed_begin __rte_packed_begin 101 #define __plt_packed_end __rte_packed_end 102 #define __plt_unused __rte_unused 103 #define __roc_api __rte_internal 104 #define plt_iova_t rte_iova_t 105 106 #define plt_pci_addr rte_pci_addr 107 #define plt_pci_device rte_pci_device 108 #define plt_pci_read_config rte_pci_read_config 109 #define plt_pci_find_ext_capability rte_pci_find_ext_capability 110 #define plt_sysfs_value_parse eal_parse_sysfs_value 111 112 #define plt_log2_u32 rte_log2_u32 113 #define plt_cpu_to_be_16 rte_cpu_to_be_16 114 #define plt_be_to_cpu_16 rte_be_to_cpu_16 115 #define plt_cpu_to_be_32 rte_cpu_to_be_32 116 #define plt_be_to_cpu_32 rte_be_to_cpu_32 117 #define plt_cpu_to_be_64 rte_cpu_to_be_64 118 #define plt_be_to_cpu_64 rte_be_to_cpu_64 119 120 #define __plt_aligned __rte_aligned 121 #define plt_align32pow2 rte_align32pow2 122 #define plt_align64pow2 rte_align64pow2 123 #define plt_align32prevpow2 rte_align32prevpow2 124 125 #define plt_bitmap rte_bitmap 126 #define plt_bitmap_init rte_bitmap_init 127 #define plt_bitmap_reset rte_bitmap_reset 128 #define plt_bitmap_free rte_bitmap_free 129 #define plt_bitmap_clear rte_bitmap_clear 130 #define plt_bitmap_set rte_bitmap_set 131 #define plt_bitmap_get rte_bitmap_get 132 #define plt_bitmap_scan_init __rte_bitmap_scan_init 133 #define plt_bitmap_scan rte_bitmap_scan 134 #define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint 135 136 #define plt_spinlock_t rte_spinlock_t 137 #define plt_spinlock_init rte_spinlock_init 138 #define plt_spinlock_lock rte_spinlock_lock 139 #define plt_spinlock_unlock rte_spinlock_unlock 140 #define plt_spinlock_trylock rte_spinlock_trylock 141 142 #define plt_seqcount_t rte_seqcount_t 143 #define plt_seqcount_init rte_seqcount_init 144 #define plt_seqcount_read_begin rte_seqcount_read_begin 145 #define plt_seqcount_read_retry rte_seqcount_read_retry 146 #define plt_seqcount_write_begin rte_seqcount_write_begin 147 #define plt_seqcount_write_end rte_seqcount_write_end 148 149 #define plt_thread_t rte_thread_t 150 #define plt_intr_callback_register rte_intr_callback_register 151 #define plt_intr_callback_unregister rte_intr_callback_unregister 152 #define plt_intr_disable rte_intr_disable 153 #define plt_thread_is_intr rte_thread_is_intr 154 #define plt_intr_callback_fn rte_intr_callback_fn 155 #define plt_thread_create_control rte_thread_create_internal_control 156 #define plt_thread_join rte_thread_join 157 158 static inline bool 159 plt_thread_is_valid(plt_thread_t thr) 160 { 161 return thr.opaque_id ? true : false; 162 } 163 164 #define plt_intr_efd_counter_size_get rte_intr_efd_counter_size_get 165 #define plt_intr_efd_counter_size_set rte_intr_efd_counter_size_set 166 #define plt_intr_vec_list_index_get rte_intr_vec_list_index_get 167 #define plt_intr_vec_list_index_set rte_intr_vec_list_index_set 168 #define plt_intr_vec_list_alloc rte_intr_vec_list_alloc 169 #define plt_intr_vec_list_free rte_intr_vec_list_free 170 #define plt_intr_fd_set rte_intr_fd_set 171 #define plt_intr_fd_get rte_intr_fd_get 172 #define plt_intr_dev_fd_get rte_intr_dev_fd_get 173 #define plt_intr_dev_fd_set rte_intr_dev_fd_set 174 #define plt_intr_type_get rte_intr_type_get 175 #define plt_intr_type_set rte_intr_type_set 176 #define plt_intr_instance_alloc rte_intr_instance_alloc 177 #define plt_intr_instance_dup rte_intr_instance_dup 178 #define plt_intr_instance_free rte_intr_instance_free 179 #define plt_intr_event_list_update rte_intr_event_list_update 180 #define plt_intr_max_intr_get rte_intr_max_intr_get 181 #define plt_intr_max_intr_set rte_intr_max_intr_set 182 #define plt_intr_nb_efd_get rte_intr_nb_efd_get 183 #define plt_intr_nb_efd_set rte_intr_nb_efd_set 184 #define plt_intr_nb_intr_get rte_intr_nb_intr_get 185 #define plt_intr_nb_intr_set rte_intr_nb_intr_set 186 #define plt_intr_efds_index_get rte_intr_efds_index_get 187 #define plt_intr_efds_index_set rte_intr_efds_index_set 188 #define plt_intr_elist_index_get rte_intr_elist_index_get 189 #define plt_intr_elist_index_set rte_intr_elist_index_set 190 #define plt_is_aligned rte_is_aligned 191 192 #define plt_alarm_set rte_eal_alarm_set 193 #define plt_alarm_cancel rte_eal_alarm_cancel 194 195 #define plt_intr_handle rte_intr_handle 196 197 #define plt_zmalloc(sz, align) rte_zmalloc("cnxk", sz, align) 198 #define plt_realloc rte_realloc 199 #define plt_free rte_free 200 201 #define plt_read64(addr) rte_read64_relaxed((volatile void *)(addr)) 202 #define plt_write64(val, addr) \ 203 rte_write64_relaxed((val), (volatile void *)(addr)) 204 205 #define plt_read32(addr) rte_read32_relaxed((volatile void *)(addr)) 206 #define plt_write32(val, addr) \ 207 rte_write32_relaxed((val), (volatile void *)(addr)) 208 209 #define plt_wmb() rte_wmb() 210 #define plt_rmb() rte_rmb() 211 #define plt_io_wmb() rte_io_wmb() 212 #define plt_io_rmb() rte_io_rmb() 213 #define plt_atomic_thread_fence rte_atomic_thread_fence 214 215 #define plt_bit_relaxed_get32 rte_bit_relaxed_get32 216 #define plt_bit_relaxed_set32 rte_bit_relaxed_set32 217 #define plt_bit_relaxed_clear32 rte_bit_relaxed_clear32 218 219 #define plt_bit_relaxed_get64 rte_bit_relaxed_get64 220 #define plt_bit_relaxed_set64 rte_bit_relaxed_set64 221 #define plt_bit_relaxed_clear64 rte_bit_relaxed_clear64 222 223 #define plt_popcount32 rte_popcount32 224 #define plt_popcount64 rte_popcount64 225 #define plt_clz32 rte_clz32 226 #define plt_ctz64 rte_ctz64 227 228 #define plt_mmap mmap 229 #define PLT_PROT_READ PROT_READ 230 #define PLT_PROT_WRITE PROT_WRITE 231 #define PLT_MAP_SHARED MAP_SHARED 232 233 #define plt_memzone rte_memzone 234 #define plt_memzone_lookup rte_memzone_lookup 235 #define plt_memzone_reserve_cache_align(name, sz) \ 236 rte_memzone_reserve_aligned(name, sz, 0, 0, RTE_CACHE_LINE_SIZE) 237 #define plt_memzone_free rte_memzone_free 238 #define plt_memzone_reserve_aligned(name, len, flags, align) \ 239 rte_memzone_reserve_aligned((name), (len), 0, (flags), (align)) 240 241 #define plt_tsc_hz rte_get_tsc_hz 242 #define plt_tsc_cycles rte_get_tsc_cycles 243 #define plt_delay_ms rte_delay_ms 244 #define plt_delay_us rte_delay_us 245 246 #define plt_lcore_id rte_lcore_id 247 248 #define plt_strlcpy rte_strlcpy 249 250 #define PLT_TEL_INT_VAL RTE_TEL_INT_VAL 251 #define PLT_TEL_STRING_VAL RTE_TEL_STRING_VAL 252 #define plt_tel_data rte_tel_data 253 #define plt_tel_data_start_array rte_tel_data_start_array 254 #define plt_tel_data_add_array_int rte_tel_data_add_array_int 255 #define plt_tel_data_add_array_string rte_tel_data_add_array_string 256 #define plt_tel_data_start_dict rte_tel_data_start_dict 257 #define plt_tel_data_add_dict_int rte_tel_data_add_dict_int 258 #define plt_tel_data_add_dict_ptr(d, n, v) \ 259 rte_tel_data_add_dict_uint(d, n, (uint64_t)v) 260 #define plt_tel_data_add_dict_string rte_tel_data_add_dict_string 261 #define plt_tel_data_add_dict_u64 rte_tel_data_add_dict_uint 262 #define plt_telemetry_register_cmd rte_telemetry_register_cmd 263 264 /* Log */ 265 extern int cnxk_logtype_base; 266 #define RTE_LOGTYPE_base cnxk_logtype_base 267 extern int cnxk_logtype_mbox; 268 #define RTE_LOGTYPE_mbox cnxk_logtype_mbox 269 extern int cnxk_logtype_cpt; 270 #define RTE_LOGTYPE_cpt cnxk_logtype_cpt 271 extern int cnxk_logtype_ml; 272 #define RTE_LOGTYPE_ml cnxk_logtype_ml 273 extern int cnxk_logtype_npa; 274 #define RTE_LOGTYPE_npa cnxk_logtype_npa 275 extern int cnxk_logtype_nix; 276 #define RTE_LOGTYPE_nix cnxk_logtype_nix 277 extern int cnxk_logtype_npc; 278 #define RTE_LOGTYPE_npc cnxk_logtype_npc 279 extern int cnxk_logtype_sso; 280 #define RTE_LOGTYPE_sso cnxk_logtype_sso 281 extern int cnxk_logtype_tim; 282 #define RTE_LOGTYPE_tim cnxk_logtype_tim 283 extern int cnxk_logtype_tm; 284 #define RTE_LOGTYPE_tm cnxk_logtype_tm 285 extern int cnxk_logtype_ree; 286 #define RTE_LOGTYPE_ree cnxk_logtype_ree 287 extern int cnxk_logtype_dpi; 288 #define RTE_LOGTYPE_dpi cnxk_logtype_dpi 289 extern int cnxk_logtype_rep; 290 #define RTE_LOGTYPE_rep cnxk_logtype_rep 291 extern int cnxk_logtype_esw; 292 #define RTE_LOGTYPE_esw cnxk_logtype_esw 293 294 #define RTE_LOGTYPE_CNXK cnxk_logtype_base 295 296 #define plt_err(...) \ 297 RTE_LOG_LINE_PREFIX(ERR, CNXK, "%s():%u ", __func__ RTE_LOG_COMMA __LINE__, __VA_ARGS__) 298 #define plt_info(...) RTE_LOG_LINE(INFO, CNXK, __VA_ARGS__) 299 #define plt_warn(...) RTE_LOG_LINE(WARNING, CNXK, __VA_ARGS__) 300 #define plt_print(...) RTE_LOG_LINE(INFO, CNXK, __VA_ARGS__) 301 #define plt_dump(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__) 302 #define plt_dump_no_nl(fmt, ...) fprintf(stderr, fmt, ##__VA_ARGS__) 303 304 /** 305 * Log debug message if given subsystem logging is enabled. 306 */ 307 #define plt_dbg(subsystem, ...) \ 308 RTE_LOG_LINE_PREFIX(DEBUG, subsystem, "%s():%u ", __func__ RTE_LOG_COMMA __LINE__, \ 309 __VA_ARGS__) 310 311 #define plt_base_dbg(fmt, ...) plt_dbg(base, fmt, ##__VA_ARGS__) 312 #define plt_cpt_dbg(fmt, ...) plt_dbg(cpt, fmt, ##__VA_ARGS__) 313 #define plt_mbox_dbg(fmt, ...) plt_dbg(mbox, fmt, ##__VA_ARGS__) 314 #define plt_ml_dbg(fmt, ...) plt_dbg(ml, fmt, ##__VA_ARGS__) 315 #define plt_npa_dbg(fmt, ...) plt_dbg(npa, fmt, ##__VA_ARGS__) 316 #define plt_nix_dbg(fmt, ...) plt_dbg(nix, fmt, ##__VA_ARGS__) 317 #define plt_npc_dbg(fmt, ...) plt_dbg(npc, fmt, ##__VA_ARGS__) 318 #define plt_sso_dbg(fmt, ...) plt_dbg(sso, fmt, ##__VA_ARGS__) 319 #define plt_tim_dbg(fmt, ...) plt_dbg(tim, fmt, ##__VA_ARGS__) 320 #define plt_tm_dbg(fmt, ...) plt_dbg(tm, fmt, ##__VA_ARGS__) 321 #define plt_ree_dbg(fmt, ...) plt_dbg(ree, fmt, ##__VA_ARGS__) 322 #define plt_dpi_dbg(fmt, ...) plt_dbg(dpi, fmt, ##__VA_ARGS__) 323 #define plt_rep_dbg(fmt, ...) plt_dbg(rep, fmt, ##__VA_ARGS__) 324 #define plt_esw_dbg(fmt, ...) plt_dbg(esw, fmt, ##__VA_ARGS__) 325 326 /* Datapath logs */ 327 #define plt_dp_err(...) \ 328 RTE_LOG_DP_LINE_PREFIX(ERR, CNXK, "%s():%u ", __func__ RTE_LOG_COMMA __LINE__, \ 329 __VA_ARGS__) 330 #define plt_dp_info(...) \ 331 RTE_LOG_DP_LINE_PREFIX(INFO, CNXK, "%s():%u ", __func__ RTE_LOG_COMMA __LINE__, \ 332 __VA_ARGS__) 333 #define plt_dp_dbg(...) \ 334 RTE_LOG_DP_LINE_PREFIX(DEBUG, CNXK, "%s():%u ", __func__ RTE_LOG_COMMA __LINE__, \ 335 __VA_ARGS__) 336 337 #ifdef __cplusplus 338 #define CNXK_PCI_ID(subsystem_dev, dev) \ 339 { \ 340 RTE_CLASS_ANY_ID, PCI_VENDOR_ID_CAVIUM, (dev), RTE_PCI_ANY_ID, \ 341 (subsystem_dev), \ 342 } 343 #else 344 #define CNXK_PCI_ID(subsystem_dev, dev) \ 345 { \ 346 .class_id = RTE_CLASS_ANY_ID, \ 347 .vendor_id = PCI_VENDOR_ID_CAVIUM, .device_id = (dev), \ 348 .subsystem_vendor_id = RTE_PCI_ANY_ID, \ 349 .subsystem_device_id = (subsystem_dev), \ 350 } 351 #endif 352 353 /* Device memory does not support unaligned access, instruct compiler to 354 * not optimize the memory access when working with mailbox memory. 355 */ 356 #ifndef __io 357 #define __io volatile 358 #endif 359 360 __rte_internal 361 int roc_plt_init(void); 362 363 __rte_internal 364 uint16_t roc_plt_control_lmt_id_get(void); 365 __rte_internal 366 uint16_t roc_plt_lmt_validate(void); 367 368 /* Init callbacks */ 369 typedef int (*roc_plt_init_cb_t)(void); 370 int __roc_api roc_plt_init_cb_register(roc_plt_init_cb_t cb); 371 372 static inline const void * 373 plt_lmt_region_reserve_aligned(const char *name, size_t len, uint32_t align) 374 { 375 /* To ensure returned memory is physically contiguous, bounding 376 * the start and end address in 2M range. 377 */ 378 return rte_memzone_reserve_bounded(name, len, SOCKET_ID_ANY, 379 RTE_MEMZONE_IOVA_CONTIG, 380 align, RTE_PGSIZE_2M); 381 } 382 383 #endif /* _ROC_PLATFORM_H_ */ 384