1cfb4f964SNithin Dabilpuram /* SPDX-License-Identifier: BSD-3-Clause 2cfb4f964SNithin Dabilpuram * Copyright(C) 2021 Marvell. 3cfb4f964SNithin Dabilpuram */ 4cfb4f964SNithin Dabilpuram #ifndef _ROC_NIX_INL_PRIV_H_ 5cfb4f964SNithin Dabilpuram #define _ROC_NIX_INL_PRIV_H_ 6bea5d990SVamsi Attunuru #include <pthread.h> 7bea5d990SVamsi Attunuru #include <sys/types.h> 8cfb4f964SNithin Dabilpuram 90f3f3ad8SNithin Dabilpuram #define NIX_INL_META_SIZE 384u 104b8eb5bdSRahul Bhansali #define NIX_INL_CPT_LF 2 110f3f3ad8SNithin Dabilpuram 123c100e0eSNithin Dabilpuram struct nix_inl_dev; 133c100e0eSNithin Dabilpuram struct nix_inl_qint { 143c100e0eSNithin Dabilpuram struct nix_inl_dev *inl_dev; 153c100e0eSNithin Dabilpuram uint16_t qint; 163c100e0eSNithin Dabilpuram }; 173c100e0eSNithin Dabilpuram 18cfb4f964SNithin Dabilpuram struct nix_inl_dev { 19cfb4f964SNithin Dabilpuram /* Base device object */ 20cfb4f964SNithin Dabilpuram struct dev dev; 21cfb4f964SNithin Dabilpuram 22cfb4f964SNithin Dabilpuram /* PCI device */ 23cfb4f964SNithin Dabilpuram struct plt_pci_device *pci_dev; 24cfb4f964SNithin Dabilpuram 25cfb4f964SNithin Dabilpuram /* LF specific BAR2 regions */ 26cfb4f964SNithin Dabilpuram uintptr_t nix_base; 27cfb4f964SNithin Dabilpuram uintptr_t ssow_base; 28cfb4f964SNithin Dabilpuram uintptr_t sso_base; 29bbcd191cSNithin Dabilpuram uintptr_t cpt_base; 30cfb4f964SNithin Dabilpuram 31cfb4f964SNithin Dabilpuram /* MSIX vector offsets */ 32cfb4f964SNithin Dabilpuram uint16_t nix_msixoff; 33cfb4f964SNithin Dabilpuram uint16_t ssow_msixoff; 34cfb4f964SNithin Dabilpuram uint16_t sso_msixoff; 354b8eb5bdSRahul Bhansali uint16_t cpt_msixoff[NIX_INL_CPT_LF]; 36cfb4f964SNithin Dabilpuram 37cfb4f964SNithin Dabilpuram /* SSO data */ 38cfb4f964SNithin Dabilpuram uint32_t xaq_buf_size; 39cfb4f964SNithin Dabilpuram uint32_t xae_waes; 40cfb4f964SNithin Dabilpuram uint32_t iue; 417e9a9490SNithin Dabilpuram uint32_t nb_xae; 426f30ac80SPavan Nikhilesh struct roc_sso_xaq_data xaq; 43cfb4f964SNithin Dabilpuram roc_nix_inl_sso_work_cb_t work_cb; 44cfb4f964SNithin Dabilpuram void *cb_args; 457e9a9490SNithin Dabilpuram uint64_t *pkt_pools; 467e9a9490SNithin Dabilpuram uint16_t pkt_pools_cnt; 47cfb4f964SNithin Dabilpuram 48cfb4f964SNithin Dabilpuram /* NIX data */ 49cfb4f964SNithin Dabilpuram uint8_t lf_tx_stats; 50cfb4f964SNithin Dabilpuram uint8_t lf_rx_stats; 51e9d33faaSPavan Nikhilesh uint16_t vwqe_interval; 52cfb4f964SNithin Dabilpuram uint16_t cints; 53cfb4f964SNithin Dabilpuram uint16_t qints; 543c100e0eSNithin Dabilpuram uint16_t configured_qints; 553c100e0eSNithin Dabilpuram struct roc_nix_rq *rqs; 563c100e0eSNithin Dabilpuram struct nix_inl_qint *qints_mem; 573c100e0eSNithin Dabilpuram uint16_t nb_rqs; 58cfb4f964SNithin Dabilpuram bool is_nix1; 59c8c967e1SNithin Dabilpuram uint8_t spb_drop_pc; 60c8c967e1SNithin Dabilpuram uint8_t lpb_drop_pc; 6142dab985SNithin Dabilpuram uint64_t sso_work_cnt; 62cfb4f964SNithin Dabilpuram 63cfb4f964SNithin Dabilpuram /* NIX/CPT data */ 64cfb4f964SNithin Dabilpuram void *inb_sa_base; 65cfb4f964SNithin Dabilpuram uint16_t inb_sa_sz; 664b8eb5bdSRahul Bhansali uint8_t nb_cptlf; 67cfb4f964SNithin Dabilpuram 68bbcd191cSNithin Dabilpuram /* CPT data */ 694b8eb5bdSRahul Bhansali struct roc_cpt_lf cpt_lf[NIX_INL_CPT_LF]; 70bbcd191cSNithin Dabilpuram 71bea5d990SVamsi Attunuru /* OUTB soft expiry poll thread */ 72354bf671SJerin Jacob plt_thread_t soft_exp_poll_thread; 73bea5d990SVamsi Attunuru uint32_t soft_exp_poll_freq; 74694e29eaSVamsi Attunuru uint64_t *sa_soft_exp_ring; 75f5a43270SNithin Dabilpuram bool set_soft_exp_poll; 76bea5d990SVamsi Attunuru 77bea5d990SVamsi Attunuru /* Soft expiry ring bitmap */ 78bea5d990SVamsi Attunuru struct plt_bitmap *soft_exp_ring_bmap; 79bea5d990SVamsi Attunuru 80bea5d990SVamsi Attunuru /* bitmap memory */ 81bea5d990SVamsi Attunuru void *soft_exp_ring_bmap_mem; 82bea5d990SVamsi Attunuru 83cfb4f964SNithin Dabilpuram /* Device arguments */ 84cfb4f964SNithin Dabilpuram uint8_t selftest; 8557f7b982SSatheesh Paul uint16_t channel; 8657f7b982SSatheesh Paul uint16_t chan_mask; 8757f7b982SSatheesh Paul bool is_multi_channel; 88fe5846bcSNithin Dabilpuram uint32_t ipsec_in_min_spi; 89fe5846bcSNithin Dabilpuram uint32_t ipsec_in_max_spi; 90fe5846bcSNithin Dabilpuram uint32_t inb_spi_mask; 91bbcd191cSNithin Dabilpuram bool attach_cptlf; 9275315881SNithin Dabilpuram uint16_t wqe_skip; 93064e7903SVidya Sagar Velumuri bool ts_ena; 940f3f3ad8SNithin Dabilpuram uint32_t nb_meta_bufs; 950f3f3ad8SNithin Dabilpuram uint32_t meta_buf_sz; 964b8eb5bdSRahul Bhansali uint8_t rx_inj_ena; /* Rx Inject Enable */ 97*03b15238SSrujana Challa uint8_t custom_inb_sa; 98df5cf15fSKiran Kumar K 99df5cf15fSKiran Kumar K /* NPC */ 100df5cf15fSKiran Kumar K int *ipsec_index; 101df5cf15fSKiran Kumar K uint32_t curr_ipsec_idx; 102df5cf15fSKiran Kumar K uint32_t max_ipsec_rules; 103df5cf15fSKiran Kumar K uint32_t alloc_ipsec_rules; 104de8c60d1SSrujana Challa 105de8c60d1SSrujana Challa struct roc_nix_inl_dev_q q_info[NIX_INL_CPT_LF]; 106cfb4f964SNithin Dabilpuram }; 107cfb4f964SNithin Dabilpuram 108cfb4f964SNithin Dabilpuram int nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev); 109cfb4f964SNithin Dabilpuram void nix_inl_sso_unregister_irqs(struct nix_inl_dev *inl_dev); 110cfb4f964SNithin Dabilpuram 111cfb4f964SNithin Dabilpuram int nix_inl_nix_register_irqs(struct nix_inl_dev *inl_dev); 112cfb4f964SNithin Dabilpuram void nix_inl_nix_unregister_irqs(struct nix_inl_dev *inl_dev); 113cfb4f964SNithin Dabilpuram 114bbcd191cSNithin Dabilpuram uint16_t nix_inl_dev_pffunc_get(void); 115bbcd191cSNithin Dabilpuram 116cfb4f964SNithin Dabilpuram #endif /* _ROC_NIX_INL_PRIV_H_ */ 117