1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #ifndef _ROC_DEV_PRIV_H 6 #define _ROC_DEV_PRIV_H 7 8 #define DEV_HWCAP_F_VF BIT_ULL(0) /* VF device */ 9 10 /* PF and VF bit encoding parameters in pcifunc */ 11 #define RVU_PFVF_PF_SHIFT_CN20K 9 12 #define RVU_PFVF_PF_MASK_CN20K 0x7F 13 #define RVU_PFVF_FUNC_SHIFT_CN20K 0 14 #define RVU_PFVF_FUNC_MASK_CN20K 0x1FF 15 16 #define RVU_PFVF_PF_SHIFT 10 17 #define RVU_PFVF_PF_MASK 0x3F 18 #define RVU_PFVF_FUNC_SHIFT 0 19 #define RVU_PFVF_FUNC_MASK 0x3FF 20 21 #define RVU_MAX_VF 64 /* RVU_PF_VFPF_MBOX_INT(0..1) */ 22 #define RVU_MAX_INT_RETRY 3 23 24 /* PF/VF message handling timer */ 25 #define VF_PF_MBOX_TIMER_MS (20 * 1000) 26 27 typedef struct { 28 /* 128 devices translate to two 64 bits dwords */ 29 #define MAX_VFPF_DWORD_BITS 2 30 uint64_t bits[MAX_VFPF_DWORD_BITS]; 31 } dev_intr_t; 32 33 /* Link status update callback */ 34 typedef void (*link_info_t)(void *roc_nix, 35 struct cgx_link_user_info *link); 36 37 /* PTP info callback */ 38 typedef int (*ptp_info_t)(void *roc_nix, bool enable); 39 40 /* Queue Error get callback */ 41 typedef void (*q_err_cb_t)(void *roc_nix, void *data); 42 43 /* Link status get callback */ 44 typedef void (*link_status_get_t)(void *roc_nix, 45 struct cgx_link_user_info *link); 46 /* Representee notification callback */ 47 typedef int (*repte_notify_t)(void *roc_nix, void *notify_msg); 48 49 /* RVU Message process callback */ 50 typedef int (*msg_process_cb_t)(uint16_t vf, uint16_t msg_id, 51 void *req, uint16_t req_len, 52 void **rsp, uint16_t *rsp_len); 53 54 struct dev_ops { 55 link_info_t link_status_update; 56 ptp_info_t ptp_info_update; 57 link_status_get_t link_status_get; 58 q_err_cb_t q_err_cb; 59 msg_process_cb_t msg_process_cb; 60 repte_notify_t repte_notify; 61 }; 62 63 #define dev_is_vf(dev) ((dev)->hwcap & DEV_HWCAP_F_VF) 64 65 static inline int 66 dev_get_vf(uint16_t pf_func) 67 { 68 if (roc_model_is_cn20k()) 69 return (((pf_func >> RVU_PFVF_FUNC_SHIFT_CN20K) & RVU_PFVF_FUNC_MASK_CN20K) - 1); 70 else 71 return (((pf_func >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK) - 1); 72 } 73 74 static inline int 75 dev_get_pf(uint16_t pf_func) 76 { 77 if (roc_model_is_cn20k()) 78 return (pf_func >> RVU_PFVF_PF_SHIFT_CN20K) & RVU_PFVF_PF_MASK_CN20K; 79 else 80 return (pf_func >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 81 } 82 83 static inline int 84 dev_pf_func(int pf, int vf) 85 { 86 if (roc_model_is_cn20k()) 87 return (pf << RVU_PFVF_PF_SHIFT_CN20K) | ((vf << RVU_PFVF_FUNC_SHIFT_CN20K) + 1); 88 else 89 return (pf << RVU_PFVF_PF_SHIFT) | ((vf << RVU_PFVF_FUNC_SHIFT) + 1); 90 } 91 92 static inline int 93 dev_is_afvf(uint16_t pf_func) 94 { 95 if (roc_model_is_cn20k()) 96 return !(pf_func & ~RVU_PFVF_FUNC_MASK_CN20K); 97 else 98 return !(pf_func & ~RVU_PFVF_FUNC_MASK); 99 } 100 101 struct mbox_sync { 102 bool start_thread; 103 uint8_t msg_avail; 104 plt_thread_t pfvf_msg_thread; 105 pthread_cond_t pfvf_msg_cond; 106 pthread_mutex_t mutex; 107 }; 108 109 struct mbox_platform { 110 uint8_t pfaf_vec; 111 uint8_t pfvf_mbox0_vec; 112 uint8_t pfvf_mbox1_vec; 113 uint8_t pfvf1_mbox0_vec; 114 uint8_t pfvf1_mbox1_vec; 115 uint64_t pfvf_mbox_intx[MAX_VFPF_DWORD_BITS]; 116 uint64_t pfvf_mbox_int_ena_w1s[MAX_VFPF_DWORD_BITS]; 117 uint64_t pfvf_mbox_int_ena_w1c[MAX_VFPF_DWORD_BITS]; 118 uint64_t pfvf1_mbox_intx[MAX_VFPF_DWORD_BITS]; 119 uint64_t pfvf1_mbox_int_ena_w1s[MAX_VFPF_DWORD_BITS]; 120 uint64_t pfvf1_mbox_int_ena_w1c[MAX_VFPF_DWORD_BITS]; 121 uintptr_t mbox_reg_base; 122 uintptr_t mbox_region_base; 123 }; 124 125 struct dev { 126 uint16_t pf; 127 int16_t vf; 128 uint16_t pf_func; 129 uint8_t mbox_active; 130 bool drv_inited; 131 uint64_t active_vfs[MAX_VFPF_DWORD_BITS]; 132 uintptr_t bar2; 133 uintptr_t bar4; 134 uintptr_t lmt_base; 135 struct mbox mbox_local; 136 struct mbox mbox_up; 137 struct mbox mbox_vfpf; 138 struct mbox mbox_vfpf_up; 139 dev_intr_t intr; 140 dev_intr_t flr; 141 uint64_t hwcap; 142 struct npa_lf npa; 143 struct mbox *mbox; 144 uint16_t maxvf; 145 struct dev_ops *ops; 146 void *roc_nix; 147 void *roc_cpt; 148 void *roc_tim; 149 void *roc_ml; 150 void *roc_rvu_lf; 151 bool disable_shared_lmt; /* false(default): shared lmt mode enabled */ 152 const struct plt_memzone *lmt_mz; 153 struct mbox_sync sync; 154 uintptr_t mbox_reg_base; 155 uintptr_t vf_mbox_base; 156 const struct plt_memzone *vf_mbox_mz; 157 struct mbox_platform *mbox_plat; 158 } __plt_cache_aligned; 159 160 struct npa { 161 struct plt_pci_device *pci_dev; 162 struct dev dev; 163 } __plt_cache_aligned; 164 165 extern uint16_t dev_rclk_freq; 166 extern uint16_t dev_sclk_freq; 167 168 int dev_init(struct dev *dev, struct plt_pci_device *pci_dev); 169 int dev_fini(struct dev *dev, struct plt_pci_device *pci_dev); 170 int dev_active_vfs(struct dev *dev); 171 172 int dev_irq_register(struct plt_intr_handle *intr_handle, 173 plt_intr_callback_fn cb, void *data, unsigned int vec); 174 void dev_irq_unregister(struct plt_intr_handle *intr_handle, 175 plt_intr_callback_fn cb, void *data, unsigned int vec); 176 int dev_irqs_disable(struct plt_intr_handle *intr_handle); 177 int dev_irq_reconfigure(struct plt_intr_handle *intr_handle, uint16_t max_intr); 178 179 int dev_mbox_register_irq(struct plt_pci_device *pci_dev, struct dev *dev); 180 void dev_mbox_unregister_irq(struct plt_pci_device *pci_dev, struct dev *dev); 181 int dev_vf_flr_register_irqs(struct plt_pci_device *pci_dev, struct dev *dev); 182 void dev_vf_flr_unregister_irqs(struct plt_pci_device *pci_dev, struct dev *dev); 183 184 #endif /* _ROC_DEV_PRIV_H */ 185