xref: /dpdk/drivers/common/cnxk/roc_cpt_debug.c (revision 665b49c51639a10c553433bc2bcd85c7331c631e)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(C) 2021 Marvell.
3  */
4 
5 #include "roc_api.h"
6 #include "roc_priv.h"
7 
8 void
9 roc_cpt_parse_hdr_dump(const struct cpt_parse_hdr_s *cpth)
10 {
11 	struct cpt_frag_info_s *frag_info;
12 	uint32_t offset;
13 	uint64_t *slot;
14 
15 	plt_print("CPT_PARSE \t0x%p:", cpth);
16 
17 	/* W0 */
18 	plt_print("W0: cookie \t0x%x\t\tmatch_id \t0x%04x\t\terr_sum \t%u \t",
19 		  cpth->w0.cookie, cpth->w0.match_id, cpth->w0.err_sum);
20 	plt_print("W0: reas_sts \t0x%x\t\tet_owr \t%u\t\tpkt_fmt \t%u \t",
21 		  cpth->w0.reas_sts, cpth->w0.et_owr, cpth->w0.pkt_fmt);
22 	plt_print("W0: pad_len \t%u\t\tnum_frags \t%u\t\tpkt_out \t%u \t",
23 		  cpth->w0.pad_len, cpth->w0.num_frags, cpth->w0.pkt_out);
24 
25 	/* W1 */
26 	plt_print("W1: wqe_ptr \t0x%016lx\t", plt_be_to_cpu_64(cpth->wqe_ptr));
27 
28 	/* W2 */
29 	plt_print("W2: frag_age \t0x%x\t\torig_pf_func \t0x%04x",
30 		  cpth->w2.frag_age, cpth->w2.orig_pf_func);
31 	plt_print("W2: il3_off \t0x%x\t\tfi_pad \t0x%x\t\tfi_offset \t0x%x \t",
32 		  cpth->w2.il3_off, cpth->w2.fi_pad, cpth->w2.fi_offset);
33 
34 	/* W3 */
35 	plt_print("W3: hw_ccode \t0x%x\t\tuc_ccode \t0x%x\t\tspi \t0x%08x",
36 		  cpth->w3.hw_ccode, cpth->w3.uc_ccode, cpth->w3.spi);
37 
38 	/* W4 */
39 	plt_print("W4: esn \t%" PRIx64 " \t OR frag1_wqe_ptr \t0x%" PRIx64,
40 		  cpth->esn, plt_be_to_cpu_64(cpth->frag1_wqe_ptr));
41 
42 	/* offset of 0 implies 256B, otherwise it implies offset*8B */
43 	offset = cpth->w2.fi_offset;
44 	offset = (((offset - 1) & 0x1f) + 1) * 8;
45 	frag_info = PLT_PTR_ADD(cpth, offset);
46 
47 	plt_print("CPT Fraginfo \t0x%p:", frag_info);
48 
49 	/* W0 */
50 	plt_print("W0: f0.info \t0x%x", frag_info->w0.f0.info);
51 	plt_print("W0: f1.info \t0x%x", frag_info->w0.f1.info);
52 	plt_print("W0: f2.info \t0x%x", frag_info->w0.f2.info);
53 	plt_print("W0: f3.info \t0x%x", frag_info->w0.f3.info);
54 
55 	/* W1 */
56 	plt_print("W1: frag_size0 \t0x%x", frag_info->w1.frag_size0);
57 	plt_print("W1: frag_size1 \t0x%x", frag_info->w1.frag_size1);
58 	plt_print("W1: frag_size2 \t0x%x", frag_info->w1.frag_size2);
59 	plt_print("W1: frag_size3 \t0x%x", frag_info->w1.frag_size3);
60 
61 	slot = (uint64_t *)(frag_info + 1);
62 	plt_print("Frag Slot2:  WQE ptr \t%p",
63 		  (void *)plt_be_to_cpu_64(slot[0]));
64 	plt_print("Frag Slot3:  WQE ptr \t%p",
65 		  (void *)plt_be_to_cpu_64(slot[1]));
66 }
67 
68 static int
69 cpt_af_reg_read(struct roc_cpt *roc_cpt, uint64_t reg, uint64_t *val)
70 {
71 	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
72 	struct cpt_rd_wr_reg_msg *msg;
73 	struct dev *dev = &cpt->dev;
74 	struct mbox *mbox = mbox_get(dev->mbox);
75 	int ret;
76 
77 	msg = mbox_alloc_msg_cpt_rd_wr_register(mbox);
78 	if (msg == NULL) {
79 		ret = -EIO;
80 		goto exit;
81 	}
82 
83 	msg->hdr.pcifunc = dev->pf_func;
84 
85 	msg->is_write = 0;
86 	msg->reg_offset = reg;
87 	msg->ret_val = val;
88 
89 	ret = mbox_process_msg(dev->mbox, (void *)&msg);
90 	if (ret) {
91 		ret =  -EIO;
92 		goto exit;
93 	}
94 
95 	*val = msg->val;
96 
97 	ret = 0;
98 exit:
99 	mbox_put(mbox);
100 	return ret;
101 }
102 
103 static int
104 cpt_sts_print(struct roc_cpt *roc_cpt)
105 {
106 	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
107 	struct dev *dev = &cpt->dev;
108 	struct cpt_sts_req *req;
109 	struct cpt_sts_rsp *rsp;
110 	struct mbox *mbox = mbox_get(dev->mbox);
111 	int ret;
112 
113 	req = mbox_alloc_msg_cpt_sts_get(mbox);
114 	if (req == NULL) {
115 		ret = -EIO;
116 		goto exit;
117 	}
118 
119 	req->blkaddr = 0;
120 	ret = mbox_process_msg(dev->mbox, (void *)&rsp);
121 	if (ret) {
122 		ret = -EIO;
123 		goto exit;
124 	}
125 
126 	plt_print("    %s:\t0x%016" PRIx64, "inst_req_pc", rsp->inst_req_pc);
127 	plt_print("    %s:\t0x%016" PRIx64, "inst_lat_pc", rsp->inst_lat_pc);
128 	plt_print("    %s:\t\t0x%016" PRIx64, "rd_req_pc", rsp->rd_req_pc);
129 	plt_print("    %s:\t\t0x%016" PRIx64, "rd_lat_pc", rsp->rd_lat_pc);
130 	plt_print("    %s:\t\t0x%016" PRIx64, "rd_uc_pc", rsp->rd_uc_pc);
131 	plt_print("    %s:\t0x%016" PRIx64, "active_cycles_pc",
132 		  rsp->active_cycles_pc);
133 	plt_print("    %s:\t\t0x%016" PRIx64, "ctx_mis_pc", rsp->ctx_mis_pc);
134 	plt_print("    %s:\t\t0x%016" PRIx64, "ctx_hit_pc", rsp->ctx_hit_pc);
135 	plt_print("    %s:\t\t0x%016" PRIx64, "ctx_aop_pc", rsp->ctx_aop_pc);
136 	plt_print("    %s:\t0x%016" PRIx64, "ctx_aop_lat_pc",
137 		  rsp->ctx_aop_lat_pc);
138 	plt_print("    %s:\t0x%016" PRIx64, "ctx_ifetch_pc",
139 		  rsp->ctx_ifetch_pc);
140 	plt_print("    %s:\t0x%016" PRIx64, "ctx_ifetch_lat_pc",
141 		  rsp->ctx_ifetch_lat_pc);
142 	plt_print("    %s:\t0x%016" PRIx64, "ctx_ffetch_pc",
143 		  rsp->ctx_ffetch_pc);
144 	plt_print("    %s:\t0x%016" PRIx64, "ctx_ffetch_lat_pc",
145 		  rsp->ctx_ffetch_lat_pc);
146 	plt_print("    %s:\t0x%016" PRIx64, "ctx_wback_pc", rsp->ctx_wback_pc);
147 	plt_print("    %s:\t0x%016" PRIx64, "ctx_wback_lat_pc",
148 		  rsp->ctx_wback_lat_pc);
149 	plt_print("    %s:\t\t0x%016" PRIx64, "ctx_psh_pc", rsp->ctx_psh_pc);
150 	plt_print("    %s:\t0x%016" PRIx64, "ctx_psh_lat_pc",
151 		  rsp->ctx_psh_lat_pc);
152 	plt_print("    %s:\t\t0x%016" PRIx64, "ctx_err", rsp->ctx_err);
153 	plt_print("    %s:\t\t0x%016" PRIx64, "ctx_enc_id", rsp->ctx_enc_id);
154 	plt_print("    %s:\t0x%016" PRIx64, "ctx_flush_timer",
155 		  rsp->ctx_flush_timer);
156 	plt_print("    %s:\t\t0x%016" PRIx64, "rxc_time", rsp->rxc_time);
157 	plt_print("    %s:\t0x%016" PRIx64, "rxc_time_cfg", rsp->rxc_time_cfg);
158 	plt_print("    %s:\t0x%016" PRIx64, "rxc_active_sts",
159 		  rsp->rxc_active_sts);
160 	plt_print("    %s:\t0x%016" PRIx64, "rxc_zombie_sts",
161 		  rsp->rxc_zombie_sts);
162 	plt_print("    %s:\t0x%016" PRIx64, "rxc_dfrg", rsp->rxc_dfrg);
163 	plt_print("    %s:\t0x%016" PRIx64, "x2p_link_cfg0",
164 		  rsp->x2p_link_cfg0);
165 	plt_print("    %s:\t0x%016" PRIx64, "x2p_link_cfg1",
166 		  rsp->x2p_link_cfg1);
167 	plt_print("    %s:\t0x%016" PRIx64, "busy_sts_ae", rsp->busy_sts_ae);
168 	plt_print("    %s:\t0x%016" PRIx64, "free_sts_ae", rsp->free_sts_ae);
169 	plt_print("    %s:\t0x%016" PRIx64, "busy_sts_se", rsp->busy_sts_se);
170 	plt_print("    %s:\t0x%016" PRIx64, "free_sts_se", rsp->free_sts_se);
171 	plt_print("    %s:\t0x%016" PRIx64, "busy_sts_ie", rsp->busy_sts_ie);
172 	plt_print("    %s:\t0x%016" PRIx64, "free_sts_ie", rsp->free_sts_ie);
173 	plt_print("    %s:\t0x%016" PRIx64, "exe_err_info", rsp->exe_err_info);
174 	plt_print("    %s:\t\t0x%016" PRIx64, "cptclk_cnt", rsp->cptclk_cnt);
175 	plt_print("    %s:\t\t0x%016" PRIx64, "diag", rsp->diag);
176 
177 	ret = 0;
178 exit:
179 	mbox_put(mbox);
180 	return ret;
181 }
182 
183 int
184 roc_cpt_afs_print(struct roc_cpt *roc_cpt)
185 {
186 	uint64_t reg_val;
187 
188 	plt_print("CPT AF registers:");
189 
190 	if (cpt_af_reg_read(roc_cpt, CPT_AF_LFX_CTL(0), &reg_val))
191 		return -EIO;
192 
193 	plt_print("    CPT_AF_LF0_CTL:\t0x%016" PRIx64, reg_val);
194 
195 	if (cpt_af_reg_read(roc_cpt, CPT_AF_LFX_CTL2(0), &reg_val))
196 		return -EIO;
197 
198 	plt_print("    CPT_AF_LF0_CTL2:\t0x%016" PRIx64, reg_val);
199 
200 	cpt_sts_print(roc_cpt);
201 
202 	return 0;
203 }
204 
205 void
206 cpt_lf_print(struct roc_cpt_lf *lf)
207 {
208 	uint64_t reg_val;
209 
210 	reg_val = plt_read64(lf->rbase + CPT_LF_Q_BASE);
211 	plt_print("    CPT_LF_Q_BASE:\t%016lx", reg_val);
212 
213 	reg_val = plt_read64(lf->rbase + CPT_LF_Q_SIZE);
214 	plt_print("    CPT_LF_Q_SIZE:\t%016lx", reg_val);
215 
216 	reg_val = plt_read64(lf->rbase + CPT_LF_Q_INST_PTR);
217 	plt_print("    CPT_LF_Q_INST_PTR:\t%016lx", reg_val);
218 
219 	reg_val = plt_read64(lf->rbase + CPT_LF_Q_GRP_PTR);
220 	plt_print("    CPT_LF_Q_GRP_PTR:\t%016lx", reg_val);
221 
222 	reg_val = plt_read64(lf->rbase + CPT_LF_CTL);
223 	plt_print("    CPT_LF_CTL:\t%016lx", reg_val);
224 
225 	reg_val = plt_read64(lf->rbase + CPT_LF_MISC_INT_ENA_W1S);
226 	plt_print("    CPT_LF_MISC_INT_ENA_W1S:\t%016lx", reg_val);
227 
228 	reg_val = plt_read64(lf->rbase + CPT_LF_MISC_INT);
229 	plt_print("    CPT_LF_MISC_INT:\t%016lx", reg_val);
230 
231 	reg_val = plt_read64(lf->rbase + CPT_LF_INPROG);
232 	plt_print("    CPT_LF_INPROG:\t%016lx", reg_val);
233 
234 	if (roc_model_is_cn9k())
235 		return;
236 
237 	plt_print("Count registers for CPT LF%d:", lf->lf_id);
238 
239 	reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_BYTE_CNT);
240 	plt_print("    Encrypted byte count:\t%" PRIu64, reg_val);
241 
242 	reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_PKT_CNT);
243 	plt_print("    Encrypted packet count:\t%" PRIu64, reg_val);
244 
245 	reg_val = plt_read64(lf->rbase + CPT_LF_CTX_DEC_BYTE_CNT);
246 	plt_print("    Decrypted byte count:\t%" PRIu64, reg_val);
247 
248 	reg_val = plt_read64(lf->rbase + CPT_LF_CTX_DEC_PKT_CNT);
249 	plt_print("    Decrypted packet count:\t%" PRIu64, reg_val);
250 }
251 
252 int
253 roc_cpt_lfs_print(struct roc_cpt *roc_cpt)
254 {
255 	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
256 	struct roc_cpt_lf *lf;
257 	int lf_id;
258 
259 	if (cpt == NULL)
260 		return -EINVAL;
261 
262 	for (lf_id = 0; lf_id < roc_cpt->nb_lf; lf_id++) {
263 		lf = roc_cpt->lf[lf_id];
264 		if (lf == NULL)
265 			continue;
266 
267 		cpt_lf_print(lf);
268 	}
269 
270 	return 0;
271 }
272