xref: /dpdk/drivers/common/cnxk/roc_cpt_debug.c (revision c758279fee3233d9b3663e18921eb3f62d6335ca)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(C) 2021 Marvell.
3  */
4 
5 #include "roc_api.h"
6 #include "roc_priv.h"
7 
8 #define cpt_dump(file, fmt, ...) do {                                           \
9 	if ((file) == NULL)							\
10 		plt_dump(fmt, ##__VA_ARGS__);					\
11 	else									\
12 		fprintf(file, fmt "\n", ##__VA_ARGS__);				\
13 } while (0)
14 
15 void
roc_cpt_parse_hdr_dump(FILE * file,const struct cpt_parse_hdr_s * cpth)16 roc_cpt_parse_hdr_dump(FILE *file, const struct cpt_parse_hdr_s *cpth)
17 {
18 	struct cpt_frag_info_s *frag_info;
19 	uint32_t offset;
20 	uint64_t *slot;
21 
22 	cpt_dump(file, "CPT_PARSE \t0x%p:", cpth);
23 
24 	/* W0 */
25 	cpt_dump(file, "W0: cookie \t0x%x\t\tmatch_id \t0x%04x \t",
26 		  cpth->w0.cookie, cpth->w0.match_id);
27 	cpt_dump(file, "W0: err_sum \t%u \t", cpth->w0.err_sum);
28 	cpt_dump(file, "W0: reas_sts \t0x%x\t\tet_owr \t%u\t\tpkt_fmt \t%u \t",
29 		  cpth->w0.reas_sts, cpth->w0.et_owr, cpth->w0.pkt_fmt);
30 	cpt_dump(file, "W0: pad_len \t%u\t\tnum_frags \t%u\t\tpkt_out \t%u \t",
31 		  cpth->w0.pad_len, cpth->w0.num_frags, cpth->w0.pkt_out);
32 
33 	/* W1 */
34 	cpt_dump(file, "W1: wqe_ptr \t0x%016lx\t",
35 			plt_be_to_cpu_64(cpth->wqe_ptr));
36 
37 	/* W2 */
38 	cpt_dump(file, "W2: frag_age \t0x%x\t\torig_pf_func \t0x%04x",
39 		  cpth->w2.frag_age, cpth->w2.orig_pf_func);
40 	cpt_dump(file, "W2: il3_off \t0x%x\t\tfi_pad \t0x%x \t",
41 		  cpth->w2.il3_off, cpth->w2.fi_pad);
42 	cpt_dump(file, "W2: fi_offset \t0x%x \t", cpth->w2.fi_offset);
43 
44 	/* W3 */
45 	cpt_dump(file, "W3: hw_ccode \t0x%x\t\tuc_ccode \t0x%x\t\tspi \t0x%08x",
46 		  cpth->w3.hw_ccode, cpth->w3.uc_ccode, cpth->w3.spi);
47 
48 	/* W4 */
49 	cpt_dump(file, "W4: esn \t%" PRIx64 " \t OR frag1_wqe_ptr \t0x%" PRIx64,
50 		  cpth->esn, plt_be_to_cpu_64(cpth->frag1_wqe_ptr));
51 
52 	/* offset of 0 implies 256B, otherwise it implies offset*8B */
53 	offset = cpth->w2.fi_offset;
54 	offset = (((offset - 1) & 0x1f) + 1) * 8;
55 	frag_info = PLT_PTR_ADD(cpth, offset);
56 
57 	cpt_dump(file, "CPT Fraginfo \t0x%p:", frag_info);
58 
59 	/* W0 */
60 	cpt_dump(file, "W0: f0.info \t0x%x", frag_info->w0.f0.info);
61 	cpt_dump(file, "W0: f1.info \t0x%x", frag_info->w0.f1.info);
62 	cpt_dump(file, "W0: f2.info \t0x%x", frag_info->w0.f2.info);
63 	cpt_dump(file, "W0: f3.info \t0x%x", frag_info->w0.f3.info);
64 
65 	/* W1 */
66 	cpt_dump(file, "W1: frag_size0 \t0x%x", frag_info->w1.frag_size0);
67 	cpt_dump(file, "W1: frag_size1 \t0x%x", frag_info->w1.frag_size1);
68 	cpt_dump(file, "W1: frag_size2 \t0x%x", frag_info->w1.frag_size2);
69 	cpt_dump(file, "W1: frag_size3 \t0x%x", frag_info->w1.frag_size3);
70 
71 	slot = (uint64_t *)(frag_info + 1);
72 	cpt_dump(file, "Frag Slot2:  WQE ptr \t%p",
73 		  (void *)plt_be_to_cpu_64(slot[0]));
74 	cpt_dump(file, "Frag Slot3:  WQE ptr \t%p",
75 		  (void *)plt_be_to_cpu_64(slot[1]));
76 }
77 
78 static int
cpt_af_reg_read(struct roc_cpt * roc_cpt,uint64_t reg,uint64_t * val)79 cpt_af_reg_read(struct roc_cpt *roc_cpt, uint64_t reg, uint64_t *val)
80 {
81 	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
82 	struct cpt_rd_wr_reg_msg *msg;
83 	struct dev *dev = &cpt->dev;
84 	struct mbox *mbox = mbox_get(dev->mbox);
85 	int ret;
86 
87 	msg = mbox_alloc_msg_cpt_rd_wr_register(mbox);
88 	if (msg == NULL) {
89 		ret = -EIO;
90 		goto exit;
91 	}
92 
93 	msg->hdr.pcifunc = dev->pf_func;
94 
95 	msg->is_write = 0;
96 	msg->reg_offset = reg;
97 	msg->ret_val = val;
98 
99 	ret = mbox_process_msg(dev->mbox, (void *)&msg);
100 	if (ret) {
101 		ret =  -EIO;
102 		goto exit;
103 	}
104 
105 	*val = msg->val;
106 
107 	ret = 0;
108 exit:
109 	mbox_put(mbox);
110 	return ret;
111 }
112 
113 static int
cpt_sts_print(struct roc_cpt * roc_cpt)114 cpt_sts_print(struct roc_cpt *roc_cpt)
115 {
116 	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
117 	struct dev *dev = &cpt->dev;
118 	struct cpt_sts_req *req;
119 	struct cpt_sts_rsp *rsp;
120 	struct mbox *mbox = mbox_get(dev->mbox);
121 	int ret;
122 
123 	req = mbox_alloc_msg_cpt_sts_get(mbox);
124 	if (req == NULL) {
125 		ret = -EIO;
126 		goto exit;
127 	}
128 
129 	req->blkaddr = 0;
130 	ret = mbox_process_msg(dev->mbox, (void *)&rsp);
131 	if (ret) {
132 		ret = -EIO;
133 		goto exit;
134 	}
135 
136 	plt_print("    %s:\t0x%016" PRIx64, "inst_req_pc", rsp->inst_req_pc);
137 	plt_print("    %s:\t0x%016" PRIx64, "inst_lat_pc", rsp->inst_lat_pc);
138 	plt_print("    %s:\t\t0x%016" PRIx64, "rd_req_pc", rsp->rd_req_pc);
139 	plt_print("    %s:\t\t0x%016" PRIx64, "rd_lat_pc", rsp->rd_lat_pc);
140 	plt_print("    %s:\t\t0x%016" PRIx64, "rd_uc_pc", rsp->rd_uc_pc);
141 	plt_print("    %s:\t0x%016" PRIx64, "active_cycles_pc",
142 		  rsp->active_cycles_pc);
143 	plt_print("    %s:\t\t0x%016" PRIx64, "ctx_mis_pc", rsp->ctx_mis_pc);
144 	plt_print("    %s:\t\t0x%016" PRIx64, "ctx_hit_pc", rsp->ctx_hit_pc);
145 	plt_print("    %s:\t\t0x%016" PRIx64, "ctx_aop_pc", rsp->ctx_aop_pc);
146 	plt_print("    %s:\t0x%016" PRIx64, "ctx_aop_lat_pc",
147 		  rsp->ctx_aop_lat_pc);
148 	plt_print("    %s:\t0x%016" PRIx64, "ctx_ifetch_pc",
149 		  rsp->ctx_ifetch_pc);
150 	plt_print("    %s:\t0x%016" PRIx64, "ctx_ifetch_lat_pc",
151 		  rsp->ctx_ifetch_lat_pc);
152 	plt_print("    %s:\t0x%016" PRIx64, "ctx_ffetch_pc",
153 		  rsp->ctx_ffetch_pc);
154 	plt_print("    %s:\t0x%016" PRIx64, "ctx_ffetch_lat_pc",
155 		  rsp->ctx_ffetch_lat_pc);
156 	plt_print("    %s:\t0x%016" PRIx64, "ctx_wback_pc", rsp->ctx_wback_pc);
157 	plt_print("    %s:\t0x%016" PRIx64, "ctx_wback_lat_pc",
158 		  rsp->ctx_wback_lat_pc);
159 	plt_print("    %s:\t\t0x%016" PRIx64, "ctx_psh_pc", rsp->ctx_psh_pc);
160 	plt_print("    %s:\t0x%016" PRIx64, "ctx_psh_lat_pc",
161 		  rsp->ctx_psh_lat_pc);
162 	plt_print("    %s:\t\t0x%016" PRIx64, "ctx_err", rsp->ctx_err);
163 	plt_print("    %s:\t\t0x%016" PRIx64, "ctx_enc_id", rsp->ctx_enc_id);
164 	plt_print("    %s:\t0x%016" PRIx64, "ctx_flush_timer",
165 		  rsp->ctx_flush_timer);
166 	plt_print("    %s:\t\t0x%016" PRIx64, "rxc_time", rsp->rxc_time);
167 	plt_print("    %s:\t0x%016" PRIx64, "rxc_time_cfg", rsp->rxc_time_cfg);
168 	plt_print("    %s:\t0x%016" PRIx64, "rxc_active_sts",
169 		  rsp->rxc_active_sts);
170 	plt_print("    %s:\t0x%016" PRIx64, "rxc_zombie_sts",
171 		  rsp->rxc_zombie_sts);
172 	plt_print("    %s:\t0x%016" PRIx64, "rxc_dfrg", rsp->rxc_dfrg);
173 	plt_print("    %s:\t0x%016" PRIx64, "x2p_link_cfg0",
174 		  rsp->x2p_link_cfg0);
175 	plt_print("    %s:\t0x%016" PRIx64, "x2p_link_cfg1",
176 		  rsp->x2p_link_cfg1);
177 	plt_print("    %s:\t0x%016" PRIx64, "busy_sts_ae", rsp->busy_sts_ae);
178 	plt_print("    %s:\t0x%016" PRIx64, "free_sts_ae", rsp->free_sts_ae);
179 	plt_print("    %s:\t0x%016" PRIx64, "busy_sts_se", rsp->busy_sts_se);
180 	plt_print("    %s:\t0x%016" PRIx64, "free_sts_se", rsp->free_sts_se);
181 	plt_print("    %s:\t0x%016" PRIx64, "busy_sts_ie", rsp->busy_sts_ie);
182 	plt_print("    %s:\t0x%016" PRIx64, "free_sts_ie", rsp->free_sts_ie);
183 	plt_print("    %s:\t0x%016" PRIx64, "exe_err_info", rsp->exe_err_info);
184 	plt_print("    %s:\t\t0x%016" PRIx64, "cptclk_cnt", rsp->cptclk_cnt);
185 	plt_print("    %s:\t\t0x%016" PRIx64, "diag", rsp->diag);
186 
187 	ret = 0;
188 exit:
189 	mbox_put(mbox);
190 	return ret;
191 }
192 
193 int
roc_cpt_afs_print(struct roc_cpt * roc_cpt)194 roc_cpt_afs_print(struct roc_cpt *roc_cpt)
195 {
196 	uint64_t reg_val;
197 
198 	plt_print("CPT AF registers:");
199 
200 	if (cpt_af_reg_read(roc_cpt, CPT_AF_LFX_CTL(0), &reg_val))
201 		return -EIO;
202 
203 	plt_print("    CPT_AF_LF0_CTL:\t0x%016" PRIx64, reg_val);
204 
205 	if (cpt_af_reg_read(roc_cpt, CPT_AF_LFX_CTL2(0), &reg_val))
206 		return -EIO;
207 
208 	plt_print("    CPT_AF_LF0_CTL2:\t0x%016" PRIx64, reg_val);
209 
210 	cpt_sts_print(roc_cpt);
211 
212 	return 0;
213 }
214 
215 void
cpt_lf_print(struct roc_cpt_lf * lf)216 cpt_lf_print(struct roc_cpt_lf *lf)
217 {
218 	uint64_t reg_val;
219 
220 	reg_val = plt_read64(lf->rbase + CPT_LF_Q_BASE);
221 	plt_print("    CPT_LF_Q_BASE:\t%016lx", reg_val);
222 
223 	reg_val = plt_read64(lf->rbase + CPT_LF_Q_SIZE);
224 	plt_print("    CPT_LF_Q_SIZE:\t%016lx", reg_val);
225 
226 	reg_val = plt_read64(lf->rbase + CPT_LF_Q_INST_PTR);
227 	plt_print("    CPT_LF_Q_INST_PTR:\t%016lx", reg_val);
228 
229 	reg_val = plt_read64(lf->rbase + CPT_LF_Q_GRP_PTR);
230 	plt_print("    CPT_LF_Q_GRP_PTR:\t%016lx", reg_val);
231 
232 	reg_val = plt_read64(lf->rbase + CPT_LF_CTL);
233 	plt_print("    CPT_LF_CTL:\t%016lx", reg_val);
234 
235 	reg_val = plt_read64(lf->rbase + CPT_LF_MISC_INT_ENA_W1S);
236 	plt_print("    CPT_LF_MISC_INT_ENA_W1S:\t%016lx", reg_val);
237 
238 	reg_val = plt_read64(lf->rbase + CPT_LF_MISC_INT);
239 	plt_print("    CPT_LF_MISC_INT:\t%016lx", reg_val);
240 
241 	reg_val = plt_read64(lf->rbase + CPT_LF_INPROG);
242 	plt_print("    CPT_LF_INPROG:\t%016lx", reg_val);
243 
244 	if (roc_model_is_cn9k())
245 		return;
246 
247 	plt_print("Count registers for CPT LF%d:", lf->lf_id);
248 
249 	reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_BYTE_CNT);
250 	plt_print("    Encrypted byte count:\t%" PRIu64, reg_val);
251 
252 	reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_PKT_CNT);
253 	plt_print("    Encrypted packet count:\t%" PRIu64, reg_val);
254 
255 	reg_val = plt_read64(lf->rbase + CPT_LF_CTX_DEC_BYTE_CNT);
256 	plt_print("    Decrypted byte count:\t%" PRIu64, reg_val);
257 
258 	reg_val = plt_read64(lf->rbase + CPT_LF_CTX_DEC_PKT_CNT);
259 	plt_print("    Decrypted packet count:\t%" PRIu64, reg_val);
260 }
261 
262 int
roc_cpt_lfs_print(struct roc_cpt * roc_cpt)263 roc_cpt_lfs_print(struct roc_cpt *roc_cpt)
264 {
265 	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
266 	struct roc_cpt_lf *lf;
267 	int lf_id;
268 
269 	if (cpt == NULL)
270 		return -EINVAL;
271 
272 	for (lf_id = 0; lf_id < roc_cpt->nb_lf; lf_id++) {
273 		lf = roc_cpt->lf[lf_id];
274 		if (lf == NULL)
275 			continue;
276 
277 		cpt_lf_print(lf);
278 	}
279 
280 	return 0;
281 }
282