1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 #ifndef _ROC_CONSTANTS_H_ 5 #define _ROC_CONSTANTS_H_ 6 7 #define ROC_IPV6_ADDR_LEN 16 8 9 /* ROC Cache */ 10 #define ROC_CACHE_LINE_SZ 128 11 #define ROC_ALIGN ROC_CACHE_LINE_SZ 12 13 /* LMTST constants */ 14 /* [CN10K, .) */ 15 #define ROC_LMT_LINE_SZ 128 16 #define ROC_NUM_LMT_LINES 2048 17 #define ROC_LMT_LINES_PER_STR_LOG2 4 18 #define ROC_LMT_LINES_PER_CORE_LOG2 5 19 #define ROC_LMT_LINE_SIZE_LOG2 7 20 #define ROC_LMT_BASE_PER_CORE_LOG2 \ 21 (ROC_LMT_LINES_PER_CORE_LOG2 + ROC_LMT_LINE_SIZE_LOG2) 22 #define ROC_LMT_MAX_THREADS 42UL 23 #define ROC_LMT_CPT_LINES_PER_CORE_LOG2 4 24 #define ROC_LMT_CPT_BASE_ID_OFF \ 25 (ROC_LMT_MAX_THREADS << ROC_LMT_LINES_PER_CORE_LOG2) 26 27 /* PCI IDs */ 28 #define PCI_VENDOR_ID_CAVIUM 0x177D 29 #define PCI_DEVID_CNXK_RVU_PF 0xA063 30 #define PCI_DEVID_CNXK_RVU_VF 0xA064 31 #define PCI_DEVID_CNXK_RVU_AF 0xA065 32 #define PCI_DEVID_CNXK_RVU_SSO_TIM_PF 0xA0F9 33 #define PCI_DEVID_CNXK_RVU_SSO_TIM_VF 0xA0FA 34 #define PCI_DEVID_CNXK_RVU_NPA_PF 0xA0FB 35 #define PCI_DEVID_CNXK_RVU_NPA_VF 0xA0FC 36 #define PCI_DEVID_CNXK_RVU_AF_VF 0xA0f8 37 #define PCI_DEVID_CNXK_DPI_VF 0xA081 38 #define PCI_DEVID_CNXK_EP_VF 0xB203 39 #define PCI_DEVID_CNXK_RVU_SDP_PF 0xA0f6 40 #define PCI_DEVID_CNXK_RVU_SDP_VF 0xA0f7 41 #define PCI_DEVID_CNXK_BPHY 0xA089 42 #define PCI_DEVID_CNXK_RVU_NIX_INL_PF 0xA0F0 43 #define PCI_DEVID_CNXK_RVU_NIX_INL_VF 0xA0F1 44 #define PCI_DEVID_CNXK_RVU_REE_PF 0xA0f4 45 #define PCI_DEVID_CNXK_RVU_REE_VF 0xA0f5 46 #define PCI_DEVID_CNXK_RVU_ESWITCH_PF 0xA0E0 47 #define PCI_DEVID_CNXK_RVU_ESWITCH_VF 0xA0E1 48 #define PCI_DEVID_CNXK_RVU_BPHY_PF 0xA0E4 49 #define PCI_DEVID_CNXK_RVU_BPHY_VF 0xA0E5 50 51 #define PCI_DEVID_CN9K_CGX 0xA059 52 #define PCI_DEVID_CN10K_RPM 0xA060 53 54 #define PCI_DEVID_CN9K_RVU_CPT_PF 0xA0FD 55 #define PCI_DEVID_CN9K_RVU_CPT_VF 0xA0FE 56 #define PCI_DEVID_CN10K_RVU_CPT_PF 0xA0F2 57 #define PCI_DEVID_CN10K_RVU_CPT_VF 0xA0F3 58 59 #define PCI_DEVID_CN10K_ML_PF 0xA092 60 61 #define PCI_SUBSYSTEM_DEVID_CN10KA 0xB900 62 #define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900 63 #define PCI_SUBSYSTEM_DEVID_CNF10KA 0xBA00 64 #define PCI_SUBSYSTEM_DEVID_CN10KB 0xBD00 65 #define PCI_SUBSYSTEM_DEVID_CNF10KB 0xBC00 66 67 #define PCI_SUBSYSTEM_DEVID_CN20KA 0xA020 68 #define PCI_SUBSYSTEM_DEVID_CNF20KA 0xA000 69 70 #define PCI_SUBSYSTEM_DEVID_CN9KA 0x0000 71 #define PCI_SUBSYSTEM_DEVID_CN9KB 0xb400 72 #define PCI_SUBSYSTEM_DEVID_CN9KC 0x0200 73 #define PCI_SUBSYSTEM_DEVID_CN9KD 0xB200 74 #define PCI_SUBSYSTEM_DEVID_CN9KE 0xB100 75 #define PCI_SUBSYSTEM_DEVID_CNF9KA 0xB600 76 77 #endif /* _ROC_CONSTANTS_H_ */ 78