xref: /dpdk/drivers/common/cnxk/roc_bphy_cgx.h (revision 6576ef656a6b736a7ea4fc695e490f1f1372602a)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(C) 2021 Marvell.
3  */
4 
5 #ifndef _ROC_BPHY_CGX_H_
6 #define _ROC_BPHY_CGX_H_
7 
8 #include <pthread.h>
9 
10 #include "roc_api.h"
11 
12 #define MAX_LMACS_PER_CGX 4
13 
14 struct roc_bphy_cgx {
15 	uint64_t bar0_pa;
16 	void *bar0_va;
17 	uint64_t lmac_bmap;
18 	unsigned int id;
19 	/* serialize access to the whole structure */
20 	pthread_mutex_t lock;
21 } __plt_cache_aligned;
22 
23 enum roc_bphy_cgx_eth_link_speed {
24 	ROC_BPHY_CGX_ETH_LINK_SPEED_NONE,
25 	ROC_BPHY_CGX_ETH_LINK_SPEED_10M,
26 	ROC_BPHY_CGX_ETH_LINK_SPEED_100M,
27 	ROC_BPHY_CGX_ETH_LINK_SPEED_1G,
28 	ROC_BPHY_CGX_ETH_LINK_SPEED_2HG,
29 	ROC_BPHY_CGX_ETH_LINK_SPEED_5G,
30 	ROC_BPHY_CGX_ETH_LINK_SPEED_10G,
31 	ROC_BPHY_CGX_ETH_LINK_SPEED_20G,
32 	ROC_BPHY_CGX_ETH_LINK_SPEED_25G,
33 	ROC_BPHY_CGX_ETH_LINK_SPEED_40G,
34 	ROC_BPHY_CGX_ETH_LINK_SPEED_50G,
35 	ROC_BPHY_CGX_ETH_LINK_SPEED_80G,
36 	ROC_BPHY_CGX_ETH_LINK_SPEED_100G,
37 	__ROC_BPHY_CGX_ETH_LINK_SPEED_MAX
38 };
39 
40 enum roc_bphy_cgx_eth_link_fec {
41 	ROC_BPHY_CGX_ETH_LINK_FEC_NONE,
42 	ROC_BPHY_CGX_ETH_LINK_FEC_BASE_R,
43 	ROC_BPHY_CGX_ETH_LINK_FEC_RS,
44 	__ROC_BPHY_CGX_ETH_LINK_FEC_MAX
45 };
46 
47 enum roc_bphy_cgx_eth_link_mode {
48 	ROC_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
49 	ROC_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
50 	ROC_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
51 	ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
52 	ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
53 	ROC_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
54 	ROC_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
55 	ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
56 	ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
57 	ROC_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
58 	ROC_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
59 	ROC_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
60 	ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
61 	ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
62 	ROC_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
63 	ROC_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
64 	ROC_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
65 	ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
66 	ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
67 	ROC_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
68 	ROC_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
69 	ROC_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
70 	ROC_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
71 	ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
72 	ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
73 	ROC_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
74 	ROC_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
75 	ROC_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2C_BIT,
76 	ROC_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2M_BIT,
77 	ROC_BPHY_CGX_ETH_LINK_MODE_50GBASE_CR2_C_BIT,
78 	ROC_BPHY_CGX_ETH_LINK_MODE_50GBASE_KR2_C_BIT,
79 	ROC_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2C_BIT,
80 	ROC_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2M_BIT,
81 	ROC_BPHY_CGX_ETH_LINK_MODE_100GBASE_CR2_BIT,
82 	ROC_BPHY_CGX_ETH_LINK_MODE_100GBASE_KR2_BIT,
83 	ROC_BPHY_CGX_ETH_LINK_MODE_SFI_1G_BIT,
84 	ROC_BPHY_CGX_ETH_LINK_MODE_25GBASE_CR_C_BIT,
85 	ROC_BPHY_CGX_ETH_LINK_MODE_25GBASE_KR_C_BIT,
86 	__ROC_BPHY_CGX_ETH_LINK_MODE_MAX
87 };
88 
89 /* Supported CPRI modes */
90 enum roc_bphy_cgx_eth_mode_cpri {
91 	ROC_BPHY_CGX_ETH_MODE_CPRI_2_4G_BIT,
92 	ROC_BPHY_CGX_ETH_MODE_CPRI_3_1G_BIT,
93 	ROC_BPHY_CGX_ETH_MODE_CPRI_4_9G_BIT,
94 	ROC_BPHY_CGX_ETH_MODE_CPRI_6_1G_BIT,
95 	ROC_BPHY_CGX_ETH_MODE_CPRI_9_8G_BIT,
96 	ROC_BPHY_CGX_ETH_MODE_CPRI_10_1_BIT,
97 	ROC_BPHY_CGX_ETH_MODE_CPRI_24_3G_BIT,
98 };
99 
100 enum roc_bphy_cgx_mode_group {
101 	ROC_BPHY_CGX_MODE_GROUP_ETH,
102 	ROC_BPHY_CGX_MODE_GROUP_CPRI = 2,
103 };
104 
105 struct roc_bphy_cgx_link_mode {
106 	bool full_duplex;
107 	bool an;
108 	bool use_portm_idx;
109 	unsigned int portm_idx;
110 	enum roc_bphy_cgx_mode_group mode_group_idx;
111 	enum roc_bphy_cgx_eth_link_speed speed;
112 	union {
113 		enum roc_bphy_cgx_eth_link_mode mode;
114 		enum roc_bphy_cgx_eth_mode_cpri mode_cpri;
115 	};
116 };
117 
118 struct roc_bphy_cgx_link_info {
119 	bool link_up;
120 	bool full_duplex;
121 	enum roc_bphy_cgx_eth_link_speed speed;
122 	bool an;
123 	enum roc_bphy_cgx_eth_link_fec fec;
124 	enum roc_bphy_cgx_eth_link_mode mode;
125 };
126 
127 struct roc_bphy_cgx_cpri_mode_change {
128 	int gserc_idx;
129 	int lane_idx;
130 	int rate;
131 	bool disable_leq;
132 	bool disable_dfe;
133 };
134 
135 struct roc_bphy_cgx_cpri_mode_tx_ctrl {
136 	int gserc_idx;
137 	int lane_idx;
138 	bool enable;
139 };
140 
141 struct roc_bphy_cgx_cpri_mode_misc {
142 	int gserc_idx;
143 	int lane_idx;
144 	int flags;
145 };
146 
147 struct roc_bphy_cgx_link_state {
148 	bool state;
149 	int timeout;
150 	bool rx_tx_dis;
151 };
152 
153 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
154 __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
155 
156 __roc_api int roc_bphy_cgx_start_rxtx(struct roc_bphy_cgx *roc_cgx,
157 				      unsigned int lmac);
158 __roc_api int roc_bphy_cgx_stop_rxtx(struct roc_bphy_cgx *roc_cgx,
159 				     unsigned int lmac);
160 __roc_api int roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx,
161 					  unsigned int lmac, struct roc_bphy_cgx_link_state *state);
162 __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
163 					unsigned int lmac,
164 					struct roc_bphy_cgx_link_info *info);
165 __roc_api int roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx,
166 					 unsigned int lmac,
167 					 struct roc_bphy_cgx_link_mode *mode);
168 __roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx,
169 					 unsigned int lmac);
170 __roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
171 					  unsigned int lmac);
172 __roc_api int roc_bphy_cgx_ptp_rx_enable(struct roc_bphy_cgx *roc_cgx,
173 					 unsigned int lmac);
174 __roc_api int roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx,
175 					  unsigned int lmac);
176 __roc_api int roc_bphy_cgx_fec_set(struct roc_bphy_cgx *roc_cgx,
177 				   unsigned int lmac,
178 				   enum roc_bphy_cgx_eth_link_fec fec);
179 __roc_api int roc_bphy_cgx_fec_supported_get(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
180 					     enum roc_bphy_cgx_eth_link_fec *fec);
181 __roc_api int roc_bphy_cgx_cpri_mode_change(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
182 					    struct roc_bphy_cgx_cpri_mode_change *mode);
183 __roc_api int roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
184 						struct roc_bphy_cgx_cpri_mode_tx_ctrl *mode);
185 __roc_api int roc_bphy_cgx_cpri_mode_misc(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
186 					  struct roc_bphy_cgx_cpri_mode_misc *mode);
187 
188 #endif /* _ROC_BPHY_CGX_H_ */
189