1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2022 Marvell. 3 */ 4 5 #ifndef __ML_HW_H__ 6 #define __ML_HW_H__ 7 8 #include <stdint.h> 9 10 /* Constants */ 11 #define ML_ANBX_NR 0x3 12 13 /* Base offsets */ 14 #define ML_MLAB_BLK_OFFSET 0x20000000 /* CNF10KB */ 15 #define ML_AXI_START_ADDR 0x800000000 16 17 /* MLW register offsets / ML_PF_BAR0 */ 18 #define ML_CFG 0x10000 19 #define ML_MLR_BASE 0x10008 20 #define ML_AXI_BRIDGE_CTRL(a) (0x10020 | (uint64_t)(a) << 3) 21 #define ML_JOB_MGR_CTRL 0x10060 22 #define ML_CORE_INT_LO 0x10140 23 #define ML_CORE_INT_HI 0x10160 24 #define ML_JCMDQ_IN(a) (0x11000 | (uint64_t)(a) << 3) /* CN10KA */ 25 #define ML_JCMDQ_STATUS 0x11010 /* CN10KA */ 26 #define ML_STGX_STATUS(a) (0x11020 | (uint64_t)(a) << 3) /* CNF10KB */ 27 #define ML_STG_CONTROL 0x11100 /* CNF10KB */ 28 #define ML_PNB_CMD_TYPE 0x113a0 /* CNF10KB */ 29 #define ML_SCRATCH(a) (0x14000 | (uint64_t)(a) << 3) 30 #define ML_ANBX_BACKP_DISABLE(a) (0x18000 | (uint64_t)(a) << 12) /* CN10KA */ 31 #define ML_ANBX_NCBI_P_OVR(a) (0x18010 | (uint64_t)(a) << 12) /* CN10KA */ 32 #define ML_ANBX_NCBI_NP_OVR(a) (0x18020 | (uint64_t)(a) << 12) /* CN10KA */ 33 34 /* MLIP configuration register offsets / ML_PF_BAR0 */ 35 #define ML_SW_RST_CTRL 0x12084000 36 #define ML_A35_0_RST_VECTOR_BASE_W(a) (0x12084014 + (a) * (0x04)) 37 #define ML_A35_1_RST_VECTOR_BASE_W(a) (0x1208401c + (a) * (0x04)) 38 39 /* MLW scratch register offsets */ 40 #define ML_SCRATCH_WORK_PTR (ML_SCRATCH(0)) 41 #define ML_SCRATCH_FW_CTRL (ML_SCRATCH(1)) 42 #define ML_SCRATCH_DBG_BUFFER_HEAD_C0 (ML_SCRATCH(2)) 43 #define ML_SCRATCH_DBG_BUFFER_TAIL_C0 (ML_SCRATCH(3)) 44 #define ML_SCRATCH_DBG_BUFFER_HEAD_C1 (ML_SCRATCH(4)) 45 #define ML_SCRATCH_DBG_BUFFER_TAIL_C1 (ML_SCRATCH(5)) 46 #define ML_SCRATCH_EXCEPTION_SP_C0 (ML_SCRATCH(6)) 47 #define ML_SCRATCH_EXCEPTION_SP_C1 (ML_SCRATCH(7)) 48 49 /* ML job completion structure */ 50 struct ml_jce_s { 51 /* WORD 0 */ 52 union ml_jce_w0 { 53 struct { 54 uint64_t rsvd_0_3 : 4; 55 56 /* Reserved for future architecture */ 57 uint64_t ggrp_h : 2; 58 59 /* Tag type */ 60 uint64_t ttype : 2; 61 62 /* Physical function number */ 63 uint64_t pf_func : 16; 64 65 /* Unused [7] + Guest Group [6:0] */ 66 uint64_t ggrp : 8; 67 68 /* Tag */ 69 uint64_t tag : 32; 70 } s; 71 uint64_t u64; 72 } w0; 73 74 /* WORD 1 */ 75 union ml_jce_w1 { 76 struct { 77 /* Work queue pointer */ 78 uint64_t wqp : 53; 79 uint64_t rsvd_53_63 : 11; 80 81 } s; 82 uint64_t u64; 83 } w1; 84 }; 85 86 /* ML job command structure */ 87 struct ml_job_cmd_s { 88 /* WORD 0 */ 89 union ml_job_cmd_w0 { 90 struct { 91 uint64_t rsvd_0_63; 92 } s; 93 uint64_t u64; 94 } w0; 95 96 /* WORD 1 */ 97 union ml_job_cmd_w1 { 98 struct { 99 /* Job pointer */ 100 uint64_t jobptr : 53; 101 uint64_t rsvd_53_63 : 11; 102 } s; 103 uint64_t u64; 104 } w1; 105 }; 106 107 /* ML A35 0 RST vector base structure */ 108 union ml_a35_0_rst_vector_base_s { 109 struct { 110 /* Base address */ 111 uint64_t addr : 37; 112 uint64_t rsvd_37_63 : 27; 113 } s; 114 115 struct { 116 /* WORD 0 */ 117 uint32_t w0; 118 119 /* WORD 1 */ 120 uint32_t w1; 121 } w; 122 123 uint64_t u64; 124 }; 125 126 /* ML A35 1 RST vector base structure */ 127 union ml_a35_1_rst_vector_base_s { 128 struct { 129 /* Base address */ 130 uint64_t addr : 37; 131 uint64_t rsvd_37_63 : 27; 132 } s; 133 134 struct { 135 /* WORD 0 */ 136 uint32_t w0; 137 138 /* WORD 1 */ 139 uint32_t w1; 140 } w; 141 142 uint64_t u64; 143 }; 144 145 /* Work pointer scratch register */ 146 union ml_scratch_work_ptr_s { 147 struct { 148 /* Work pointer */ 149 uint64_t work_ptr : 37; 150 uint64_t rsvd_37_63 : 27; 151 } s; 152 uint64_t u64; 153 }; 154 155 /* Firmware control scratch register */ 156 union ml_scratch_fw_ctrl_s { 157 struct { 158 uint64_t rsvd_0_15 : 16; 159 160 /* Valid job bit */ 161 uint64_t valid : 1; 162 163 /* Done status bit */ 164 uint64_t done : 1; 165 uint64_t rsvd_18_63 : 46; 166 } s; 167 uint64_t u64; 168 }; 169 170 #endif /* __ML_HW_H__ */ 171